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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <linux/list.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
771fe6b9 JG |
34 | #include <drm/drmP.h> |
35 | #include "radeon_drm.h" | |
36 | #include "radeon.h" | |
37 | ||
771fe6b9 JG |
38 | |
39 | int radeon_ttm_init(struct radeon_device *rdev); | |
40 | void radeon_ttm_fini(struct radeon_device *rdev); | |
4c788679 | 41 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
771fe6b9 JG |
42 | |
43 | /* | |
44 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all | |
45 | * function are calling it. | |
46 | */ | |
47 | ||
4c788679 | 48 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
771fe6b9 | 49 | { |
4c788679 | 50 | struct radeon_bo *bo; |
771fe6b9 | 51 | |
4c788679 JG |
52 | bo = container_of(tbo, struct radeon_bo, tbo); |
53 | mutex_lock(&bo->rdev->gem.mutex); | |
54 | list_del_init(&bo->list); | |
55 | mutex_unlock(&bo->rdev->gem.mutex); | |
56 | radeon_bo_clear_surface_reg(bo); | |
57 | kfree(bo); | |
771fe6b9 JG |
58 | } |
59 | ||
d03d8589 JG |
60 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
61 | { | |
62 | if (bo->destroy == &radeon_ttm_bo_destroy) | |
63 | return true; | |
64 | return false; | |
65 | } | |
66 | ||
312ea8da JG |
67 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
68 | { | |
69 | u32 c = 0; | |
70 | ||
71 | rbo->placement.fpfn = 0; | |
72 | rbo->placement.lpfn = 0; | |
73 | rbo->placement.placement = rbo->placements; | |
74 | rbo->placement.busy_placement = rbo->placements; | |
75 | if (domain & RADEON_GEM_DOMAIN_VRAM) | |
76 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | | |
77 | TTM_PL_FLAG_VRAM; | |
78 | if (domain & RADEON_GEM_DOMAIN_GTT) | |
79 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
80 | if (domain & RADEON_GEM_DOMAIN_CPU) | |
81 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
9fb03e63 JG |
82 | if (!c) |
83 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
312ea8da JG |
84 | rbo->placement.num_placement = c; |
85 | rbo->placement.num_busy_placement = c; | |
86 | } | |
87 | ||
4c788679 JG |
88 | int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, |
89 | unsigned long size, bool kernel, u32 domain, | |
90 | struct radeon_bo **bo_ptr) | |
771fe6b9 | 91 | { |
4c788679 | 92 | struct radeon_bo *bo; |
771fe6b9 | 93 | enum ttm_bo_type type; |
771fe6b9 JG |
94 | int r; |
95 | ||
96 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { | |
97 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; | |
98 | } | |
99 | if (kernel) { | |
100 | type = ttm_bo_type_kernel; | |
101 | } else { | |
102 | type = ttm_bo_type_device; | |
103 | } | |
4c788679 JG |
104 | *bo_ptr = NULL; |
105 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); | |
106 | if (bo == NULL) | |
771fe6b9 | 107 | return -ENOMEM; |
4c788679 JG |
108 | bo->rdev = rdev; |
109 | bo->gobj = gobj; | |
110 | bo->surface_reg = -1; | |
111 | INIT_LIST_HEAD(&bo->list); | |
112 | ||
1fb107fc | 113 | radeon_ttm_placement_from_domain(bo, domain); |
5cc6fbab | 114 | /* Kernel allocation are uninterruptible */ |
5876dd24 | 115 | mutex_lock(&rdev->vram_mutex); |
1fb107fc JG |
116 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
117 | &bo->placement, 0, 0, !kernel, NULL, size, | |
118 | &radeon_ttm_bo_destroy); | |
5876dd24 | 119 | mutex_unlock(&rdev->vram_mutex); |
771fe6b9 | 120 | if (unlikely(r != 0)) { |
5cc6fbab TH |
121 | if (r != -ERESTARTSYS) |
122 | dev_err(rdev->dev, | |
1fb107fc JG |
123 | "object_init failed for (%lu, 0x%08X)\n", |
124 | size, domain); | |
771fe6b9 JG |
125 | return r; |
126 | } | |
4c788679 | 127 | *bo_ptr = bo; |
771fe6b9 | 128 | if (gobj) { |
4c788679 JG |
129 | mutex_lock(&bo->rdev->gem.mutex); |
130 | list_add_tail(&bo->list, &rdev->gem.objects); | |
131 | mutex_unlock(&bo->rdev->gem.mutex); | |
771fe6b9 JG |
132 | } |
133 | return 0; | |
134 | } | |
135 | ||
4c788679 | 136 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
771fe6b9 | 137 | { |
4c788679 | 138 | bool is_iomem; |
771fe6b9 JG |
139 | int r; |
140 | ||
4c788679 | 141 | if (bo->kptr) { |
771fe6b9 | 142 | if (ptr) { |
4c788679 | 143 | *ptr = bo->kptr; |
771fe6b9 | 144 | } |
771fe6b9 JG |
145 | return 0; |
146 | } | |
4c788679 | 147 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
771fe6b9 JG |
148 | if (r) { |
149 | return r; | |
150 | } | |
4c788679 | 151 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
771fe6b9 | 152 | if (ptr) { |
4c788679 | 153 | *ptr = bo->kptr; |
771fe6b9 | 154 | } |
4c788679 | 155 | radeon_bo_check_tiling(bo, 0, 0); |
771fe6b9 JG |
156 | return 0; |
157 | } | |
158 | ||
4c788679 | 159 | void radeon_bo_kunmap(struct radeon_bo *bo) |
771fe6b9 | 160 | { |
4c788679 | 161 | if (bo->kptr == NULL) |
771fe6b9 | 162 | return; |
4c788679 JG |
163 | bo->kptr = NULL; |
164 | radeon_bo_check_tiling(bo, 0, 0); | |
165 | ttm_bo_kunmap(&bo->kmap); | |
771fe6b9 JG |
166 | } |
167 | ||
4c788679 | 168 | void radeon_bo_unref(struct radeon_bo **bo) |
771fe6b9 | 169 | { |
4c788679 | 170 | struct ttm_buffer_object *tbo; |
f4b7fb94 | 171 | struct radeon_device *rdev; |
771fe6b9 | 172 | |
4c788679 | 173 | if ((*bo) == NULL) |
771fe6b9 | 174 | return; |
f4b7fb94 | 175 | rdev = (*bo)->rdev; |
4c788679 | 176 | tbo = &((*bo)->tbo); |
f4b7fb94 | 177 | mutex_lock(&rdev->vram_mutex); |
4c788679 | 178 | ttm_bo_unref(&tbo); |
f4b7fb94 | 179 | mutex_unlock(&rdev->vram_mutex); |
4c788679 JG |
180 | if (tbo == NULL) |
181 | *bo = NULL; | |
771fe6b9 JG |
182 | } |
183 | ||
4c788679 | 184 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
771fe6b9 | 185 | { |
312ea8da | 186 | int r, i; |
771fe6b9 | 187 | |
4c788679 JG |
188 | if (bo->pin_count) { |
189 | bo->pin_count++; | |
190 | if (gpu_addr) | |
191 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 JG |
192 | return 0; |
193 | } | |
312ea8da | 194 | radeon_ttm_placement_from_domain(bo, domain); |
3ca82da3 MD |
195 | if (domain == RADEON_GEM_DOMAIN_VRAM) { |
196 | /* force to pin into visible video ram */ | |
197 | bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
198 | } | |
312ea8da JG |
199 | for (i = 0; i < bo->placement.num_placement; i++) |
200 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; | |
9d87fa21 | 201 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); |
4c788679 JG |
202 | if (likely(r == 0)) { |
203 | bo->pin_count = 1; | |
204 | if (gpu_addr != NULL) | |
205 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 | 206 | } |
5cc6fbab | 207 | if (unlikely(r != 0)) |
4c788679 | 208 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
771fe6b9 JG |
209 | return r; |
210 | } | |
211 | ||
4c788679 | 212 | int radeon_bo_unpin(struct radeon_bo *bo) |
771fe6b9 | 213 | { |
312ea8da | 214 | int r, i; |
771fe6b9 | 215 | |
4c788679 JG |
216 | if (!bo->pin_count) { |
217 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); | |
218 | return 0; | |
771fe6b9 | 219 | } |
4c788679 JG |
220 | bo->pin_count--; |
221 | if (bo->pin_count) | |
222 | return 0; | |
312ea8da JG |
223 | for (i = 0; i < bo->placement.num_placement; i++) |
224 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; | |
9d87fa21 | 225 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); |
5cc6fbab | 226 | if (unlikely(r != 0)) |
4c788679 | 227 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
5cc6fbab | 228 | return r; |
cefb87ef DA |
229 | } |
230 | ||
4c788679 | 231 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
771fe6b9 | 232 | { |
d796d844 DA |
233 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
234 | if (0 && (rdev->flags & RADEON_IS_IGP)) { | |
06b6476d AD |
235 | if (rdev->mc.igp_sideport_enabled == false) |
236 | /* Useless to evict on IGP chips */ | |
237 | return 0; | |
771fe6b9 JG |
238 | } |
239 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
240 | } | |
241 | ||
4c788679 | 242 | void radeon_bo_force_delete(struct radeon_device *rdev) |
771fe6b9 | 243 | { |
4c788679 | 244 | struct radeon_bo *bo, *n; |
771fe6b9 JG |
245 | struct drm_gem_object *gobj; |
246 | ||
247 | if (list_empty(&rdev->gem.objects)) { | |
248 | return; | |
249 | } | |
4c788679 JG |
250 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
251 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
771fe6b9 | 252 | mutex_lock(&rdev->ddev->struct_mutex); |
4c788679 JG |
253 | gobj = bo->gobj; |
254 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", | |
255 | gobj, bo, (unsigned long)gobj->size, | |
256 | *((unsigned long *)&gobj->refcount)); | |
257 | mutex_lock(&bo->rdev->gem.mutex); | |
258 | list_del_init(&bo->list); | |
259 | mutex_unlock(&bo->rdev->gem.mutex); | |
260 | radeon_bo_unref(&bo); | |
771fe6b9 JG |
261 | gobj->driver_private = NULL; |
262 | drm_gem_object_unreference(gobj); | |
263 | mutex_unlock(&rdev->ddev->struct_mutex); | |
264 | } | |
265 | } | |
266 | ||
4c788679 | 267 | int radeon_bo_init(struct radeon_device *rdev) |
771fe6b9 | 268 | { |
a4d68279 JG |
269 | /* Add an MTRR for the VRAM */ |
270 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, | |
271 | MTRR_TYPE_WRCOMB, 1); | |
272 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", | |
273 | rdev->mc.mc_vram_size >> 20, | |
274 | (unsigned long long)rdev->mc.aper_size >> 20); | |
275 | DRM_INFO("RAM width %dbits %cDR\n", | |
276 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | |
771fe6b9 JG |
277 | return radeon_ttm_init(rdev); |
278 | } | |
279 | ||
4c788679 | 280 | void radeon_bo_fini(struct radeon_device *rdev) |
771fe6b9 JG |
281 | { |
282 | radeon_ttm_fini(rdev); | |
283 | } | |
284 | ||
4c788679 JG |
285 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
286 | struct list_head *head) | |
771fe6b9 JG |
287 | { |
288 | if (lobj->wdomain) { | |
289 | list_add(&lobj->list, head); | |
290 | } else { | |
291 | list_add_tail(&lobj->list, head); | |
292 | } | |
293 | } | |
294 | ||
4c788679 | 295 | int radeon_bo_list_reserve(struct list_head *head) |
771fe6b9 | 296 | { |
4c788679 | 297 | struct radeon_bo_list *lobj; |
771fe6b9 JG |
298 | int r; |
299 | ||
9d8401fc | 300 | list_for_each_entry(lobj, head, list){ |
4c788679 JG |
301 | r = radeon_bo_reserve(lobj->bo, false); |
302 | if (unlikely(r != 0)) | |
303 | return r; | |
e8652753 | 304 | lobj->reserved = true; |
771fe6b9 JG |
305 | } |
306 | return 0; | |
307 | } | |
308 | ||
4c788679 | 309 | void radeon_bo_list_unreserve(struct list_head *head) |
771fe6b9 | 310 | { |
4c788679 | 311 | struct radeon_bo_list *lobj; |
771fe6b9 | 312 | |
9d8401fc | 313 | list_for_each_entry(lobj, head, list) { |
4c788679 | 314 | /* only unreserve object we successfully reserved */ |
e8652753 | 315 | if (lobj->reserved && radeon_bo_is_reserved(lobj->bo)) |
4c788679 | 316 | radeon_bo_unreserve(lobj->bo); |
771fe6b9 JG |
317 | } |
318 | } | |
319 | ||
6cb8e1f7 | 320 | int radeon_bo_list_validate(struct list_head *head) |
771fe6b9 | 321 | { |
4c788679 JG |
322 | struct radeon_bo_list *lobj; |
323 | struct radeon_bo *bo; | |
771fe6b9 JG |
324 | int r; |
325 | ||
e8652753 JG |
326 | list_for_each_entry(lobj, head, list) { |
327 | lobj->reserved = false; | |
328 | } | |
4c788679 | 329 | r = radeon_bo_list_reserve(head); |
771fe6b9 | 330 | if (unlikely(r != 0)) { |
771fe6b9 JG |
331 | return r; |
332 | } | |
9d8401fc | 333 | list_for_each_entry(lobj, head, list) { |
4c788679 JG |
334 | bo = lobj->bo; |
335 | if (!bo->pin_count) { | |
664f8659 | 336 | if (lobj->wdomain) { |
312ea8da JG |
337 | radeon_ttm_placement_from_domain(bo, |
338 | lobj->wdomain); | |
664f8659 | 339 | } else { |
312ea8da JG |
340 | radeon_ttm_placement_from_domain(bo, |
341 | lobj->rdomain); | |
664f8659 | 342 | } |
1fb107fc | 343 | r = ttm_bo_validate(&bo->tbo, &bo->placement, |
9d87fa21 | 344 | true, false, false); |
5cc6fbab | 345 | if (unlikely(r)) |
771fe6b9 | 346 | return r; |
771fe6b9 | 347 | } |
4c788679 JG |
348 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
349 | lobj->tiling_flags = bo->tiling_flags; | |
771fe6b9 JG |
350 | } |
351 | return 0; | |
352 | } | |
353 | ||
6cb8e1f7 | 354 | void radeon_bo_list_fence(struct list_head *head, void *fence) |
771fe6b9 | 355 | { |
4c788679 | 356 | struct radeon_bo_list *lobj; |
6cb8e1f7 JG |
357 | struct radeon_bo *bo; |
358 | struct radeon_fence *old_fence = NULL; | |
359 | ||
360 | list_for_each_entry(lobj, head, list) { | |
361 | bo = lobj->bo; | |
362 | spin_lock(&bo->tbo.lock); | |
363 | old_fence = (struct radeon_fence *)bo->tbo.sync_obj; | |
364 | bo->tbo.sync_obj = radeon_fence_ref(fence); | |
365 | bo->tbo.sync_obj_arg = NULL; | |
366 | spin_unlock(&bo->tbo.lock); | |
367 | if (old_fence) { | |
368 | radeon_fence_unref(&old_fence); | |
771fe6b9 | 369 | } |
6cb8e1f7 | 370 | } |
771fe6b9 JG |
371 | } |
372 | ||
4c788679 | 373 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
771fe6b9 JG |
374 | struct vm_area_struct *vma) |
375 | { | |
4c788679 | 376 | return ttm_fbdev_mmap(vma, &bo->tbo); |
771fe6b9 JG |
377 | } |
378 | ||
550e2d92 | 379 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
771fe6b9 | 380 | { |
4c788679 | 381 | struct radeon_device *rdev = bo->rdev; |
e024e110 | 382 | struct radeon_surface_reg *reg; |
4c788679 | 383 | struct radeon_bo *old_object; |
e024e110 DA |
384 | int steal; |
385 | int i; | |
386 | ||
4c788679 JG |
387 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
388 | ||
389 | if (!bo->tiling_flags) | |
e024e110 DA |
390 | return 0; |
391 | ||
4c788679 JG |
392 | if (bo->surface_reg >= 0) { |
393 | reg = &rdev->surface_regs[bo->surface_reg]; | |
394 | i = bo->surface_reg; | |
e024e110 DA |
395 | goto out; |
396 | } | |
397 | ||
398 | steal = -1; | |
399 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { | |
400 | ||
401 | reg = &rdev->surface_regs[i]; | |
4c788679 | 402 | if (!reg->bo) |
e024e110 DA |
403 | break; |
404 | ||
4c788679 | 405 | old_object = reg->bo; |
e024e110 DA |
406 | if (old_object->pin_count == 0) |
407 | steal = i; | |
408 | } | |
409 | ||
410 | /* if we are all out */ | |
411 | if (i == RADEON_GEM_MAX_SURFACES) { | |
412 | if (steal == -1) | |
413 | return -ENOMEM; | |
414 | /* find someone with a surface reg and nuke their BO */ | |
415 | reg = &rdev->surface_regs[steal]; | |
4c788679 | 416 | old_object = reg->bo; |
e024e110 DA |
417 | /* blow away the mapping */ |
418 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); | |
4c788679 | 419 | ttm_bo_unmap_virtual(&old_object->tbo); |
e024e110 DA |
420 | old_object->surface_reg = -1; |
421 | i = steal; | |
422 | } | |
423 | ||
4c788679 JG |
424 | bo->surface_reg = i; |
425 | reg->bo = bo; | |
e024e110 DA |
426 | |
427 | out: | |
4c788679 JG |
428 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
429 | bo->tbo.mem.mm_node->start << PAGE_SHIFT, | |
430 | bo->tbo.num_pages << PAGE_SHIFT); | |
e024e110 DA |
431 | return 0; |
432 | } | |
433 | ||
4c788679 | 434 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
e024e110 | 435 | { |
4c788679 | 436 | struct radeon_device *rdev = bo->rdev; |
e024e110 DA |
437 | struct radeon_surface_reg *reg; |
438 | ||
4c788679 | 439 | if (bo->surface_reg == -1) |
e024e110 DA |
440 | return; |
441 | ||
4c788679 JG |
442 | reg = &rdev->surface_regs[bo->surface_reg]; |
443 | radeon_clear_surface_reg(rdev, bo->surface_reg); | |
e024e110 | 444 | |
4c788679 JG |
445 | reg->bo = NULL; |
446 | bo->surface_reg = -1; | |
e024e110 DA |
447 | } |
448 | ||
4c788679 JG |
449 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
450 | uint32_t tiling_flags, uint32_t pitch) | |
e024e110 | 451 | { |
4c788679 JG |
452 | int r; |
453 | ||
454 | r = radeon_bo_reserve(bo, false); | |
455 | if (unlikely(r != 0)) | |
456 | return r; | |
457 | bo->tiling_flags = tiling_flags; | |
458 | bo->pitch = pitch; | |
459 | radeon_bo_unreserve(bo); | |
460 | return 0; | |
e024e110 DA |
461 | } |
462 | ||
4c788679 JG |
463 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
464 | uint32_t *tiling_flags, | |
465 | uint32_t *pitch) | |
e024e110 | 466 | { |
4c788679 | 467 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
e024e110 | 468 | if (tiling_flags) |
4c788679 | 469 | *tiling_flags = bo->tiling_flags; |
e024e110 | 470 | if (pitch) |
4c788679 | 471 | *pitch = bo->pitch; |
e024e110 DA |
472 | } |
473 | ||
4c788679 JG |
474 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
475 | bool force_drop) | |
e024e110 | 476 | { |
4c788679 JG |
477 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
478 | ||
479 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) | |
e024e110 DA |
480 | return 0; |
481 | ||
482 | if (force_drop) { | |
4c788679 | 483 | radeon_bo_clear_surface_reg(bo); |
e024e110 DA |
484 | return 0; |
485 | } | |
486 | ||
4c788679 | 487 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
e024e110 DA |
488 | if (!has_moved) |
489 | return 0; | |
490 | ||
4c788679 JG |
491 | if (bo->surface_reg >= 0) |
492 | radeon_bo_clear_surface_reg(bo); | |
e024e110 DA |
493 | return 0; |
494 | } | |
495 | ||
4c788679 | 496 | if ((bo->surface_reg >= 0) && !has_moved) |
e024e110 DA |
497 | return 0; |
498 | ||
4c788679 | 499 | return radeon_bo_get_surface_reg(bo); |
e024e110 DA |
500 | } |
501 | ||
502 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | |
d03d8589 | 503 | struct ttm_mem_reg *mem) |
e024e110 | 504 | { |
d03d8589 JG |
505 | struct radeon_bo *rbo; |
506 | if (!radeon_ttm_bo_is_radeon_bo(bo)) | |
507 | return; | |
508 | rbo = container_of(bo, struct radeon_bo, tbo); | |
4c788679 | 509 | radeon_bo_check_tiling(rbo, 0, 1); |
e024e110 DA |
510 | } |
511 | ||
0a2d50e3 | 512 | int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
e024e110 | 513 | { |
0a2d50e3 | 514 | struct radeon_device *rdev; |
d03d8589 | 515 | struct radeon_bo *rbo; |
0a2d50e3 JG |
516 | unsigned long offset, size; |
517 | int r; | |
518 | ||
d03d8589 | 519 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
0a2d50e3 | 520 | return 0; |
d03d8589 | 521 | rbo = container_of(bo, struct radeon_bo, tbo); |
4c788679 | 522 | radeon_bo_check_tiling(rbo, 0, 0); |
0a2d50e3 JG |
523 | rdev = rbo->rdev; |
524 | if (bo->mem.mem_type == TTM_PL_VRAM) { | |
525 | size = bo->mem.num_pages << PAGE_SHIFT; | |
526 | offset = bo->mem.mm_node->start << PAGE_SHIFT; | |
527 | if ((offset + size) > rdev->mc.visible_vram_size) { | |
528 | /* hurrah the memory is not visible ! */ | |
529 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); | |
530 | rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
531 | r = ttm_bo_validate(bo, &rbo->placement, false, true, false); | |
532 | if (unlikely(r != 0)) | |
533 | return r; | |
534 | offset = bo->mem.mm_node->start << PAGE_SHIFT; | |
535 | /* this should not happen */ | |
536 | if ((offset + size) > rdev->mc.visible_vram_size) | |
537 | return -EINVAL; | |
538 | } | |
539 | } | |
540 | return 0; | |
e024e110 | 541 | } |