[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / radeon / radeon_object.c

/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
#include <linux/list.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include "radeon_drm.h"
#include "radeon.h"
#include "radeon_trace.h"


int radeon_ttm_init(struct radeon_device *rdev);
void radeon_ttm_fini(struct radeon_device *rdev);
static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);

/*
 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
 * function are calling it.
 */

void radeon_bo_clear_va(struct radeon_bo *bo)
{
	struct radeon_bo_va *bo_va, *tmp;

	list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
		/* remove from all vm address space */
		mutex_lock(&bo_va->vm->mutex);
		list_del(&bo_va->vm_list);
		mutex_unlock(&bo_va->vm->mutex);
		list_del(&bo_va->bo_list);
		kfree(bo_va);
	}
}

static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
	struct radeon_bo *bo;

	bo = container_of(tbo, struct radeon_bo, tbo);
	mutex_lock(&bo->rdev->gem.mutex);
	list_del_init(&bo->list);
	mutex_unlock(&bo->rdev->gem.mutex);
	radeon_bo_clear_surface_reg(bo);
	radeon_bo_clear_va(bo);
	drm_gem_object_release(&bo->gem_base);
	kfree(bo);
}

bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
{
	if (bo->destroy == &radeon_ttm_bo_destroy)
		return true;
	return false;
}

void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
{
	u32 c = 0;

	rbo->placement.fpfn = 0;
	rbo->placement.lpfn = 0;
	rbo->placement.placement = rbo->placements;
	rbo->placement.busy_placement = rbo->placements;
	if (domain & RADEON_GEM_DOMAIN_VRAM)
		rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
					TTM_PL_FLAG_VRAM;
	if (domain & RADEON_GEM_DOMAIN_GTT)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
	if (domain & RADEON_GEM_DOMAIN_CPU)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	if (!c)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	rbo->placement.num_placement = c;
	rbo->placement.num_busy_placement = c;
}

int radeon_bo_create(struct radeon_device *rdev,
		     unsigned long size, int byte_align, bool kernel, u32 domain,
		     struct radeon_bo **bo_ptr)
{
	struct radeon_bo *bo;
	enum ttm_bo_type type;
	unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
	unsigned long max_size = 0;
	size_t acc_size;
	int r;

	size = ALIGN(size, PAGE_SIZE);

	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
		rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	}
	if (kernel) {
		type = ttm_bo_type_kernel;
	} else {
		type = ttm_bo_type_device;
	}
	*bo_ptr = NULL;

	/* maximun bo size is the minimun btw visible vram and gtt size */
	max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
	if ((page_align << PAGE_SHIFT) >= max_size) {
		printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
			__func__, __LINE__, page_align  >> (20 - PAGE_SHIFT), max_size >> 20);
		return -ENOMEM;
	}

	acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
				       sizeof(struct radeon_bo));

retry:
	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	if (bo == NULL)
		return -ENOMEM;
	r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
	if (unlikely(r)) {
		kfree(bo);
		return r;
	}
	bo->rdev = rdev;
	bo->gem_base.driver_private = NULL;
	bo->surface_reg = -1;
	INIT_LIST_HEAD(&bo->list);
	INIT_LIST_HEAD(&bo->va);
	radeon_ttm_placement_from_domain(bo, domain);
	/* Kernel allocation are uninterruptible */
	mutex_lock(&rdev->vram_mutex);
	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
			&bo->placement, page_align, 0, !kernel, NULL,
			acc_size, &radeon_ttm_bo_destroy);
	mutex_unlock(&rdev->vram_mutex);
	if (unlikely(r != 0)) {
		if (r != -ERESTARTSYS) {
			if (domain == RADEON_GEM_DOMAIN_VRAM) {
				domain |= RADEON_GEM_DOMAIN_GTT;
				goto retry;
			}
			dev_err(rdev->dev,
				"object_init failed for (%lu, 0x%08X)\n",
				size, domain);
		}
		return r;
	}
	*bo_ptr = bo;

	trace_radeon_bo_create(bo);

	return 0;
}

int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
{
	bool is_iomem;
	int r;

	if (bo->kptr) {
		if (ptr) {
			*ptr = bo->kptr;
		}
		return 0;
	}
	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
	if (r) {
		return r;
	}
	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
	if (ptr) {
		*ptr = bo->kptr;
	}
	radeon_bo_check_tiling(bo, 0, 0);
	return 0;
}

void radeon_bo_kunmap(struct radeon_bo *bo)
{
	if (bo->kptr == NULL)
		return;
	bo->kptr = NULL;
	radeon_bo_check_tiling(bo, 0, 0);
	ttm_bo_kunmap(&bo->kmap);
}

void radeon_bo_unref(struct radeon_bo **bo)
{
	struct ttm_buffer_object *tbo;
	struct radeon_device *rdev;

	if ((*bo) == NULL)
		return;
	rdev = (*bo)->rdev;
	tbo = &((*bo)->tbo);
	mutex_lock(&rdev->vram_mutex);
	ttm_bo_unref(&tbo);
	mutex_unlock(&rdev->vram_mutex);
	if (tbo == NULL)
		*bo = NULL;
}

int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
			     u64 *gpu_addr)
{
	int r, i;

	if (bo->pin_count) {
		bo->pin_count++;
		if (gpu_addr)
			*gpu_addr = radeon_bo_gpu_offset(bo);
		WARN_ON_ONCE(max_offset != 0);
		return 0;
	}
	radeon_ttm_placement_from_domain(bo, domain);
	if (domain == RADEON_GEM_DOMAIN_VRAM) {
		/* force to pin into visible video ram */
		bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	}
	if (max_offset) {
		u64 lpfn = max_offset >> PAGE_SHIFT;

		if (!bo->placement.lpfn)
			bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;

		if (lpfn < bo->placement.lpfn)
			bo->placement.lpfn = lpfn;
	}
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
	if (likely(r == 0)) {
		bo->pin_count = 1;
		if (gpu_addr != NULL)
			*gpu_addr = radeon_bo_gpu_offset(bo);
	}
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p pin failed\n", bo);
	return r;
}

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
{
	return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
}

int radeon_bo_unpin(struct radeon_bo *bo)
{
	int r, i;

	if (!bo->pin_count) {
		dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
		return 0;
	}
	bo->pin_count--;
	if (bo->pin_count)
		return 0;
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
	return r;
}

int radeon_bo_evict_vram(struct radeon_device *rdev)
{
	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
	if (0 && (rdev->flags & RADEON_IS_IGP)) {
		if (rdev->mc.igp_sideport_enabled == false)
			/* Useless to evict on IGP chips */
			return 0;
	}
	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
}

void radeon_bo_force_delete(struct radeon_device *rdev)
{
	struct radeon_bo *bo, *n;

	if (list_empty(&rdev->gem.objects)) {
		return;
	}
	dev_err(rdev->dev, "Userspace still has active objects !\n");
	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
		mutex_lock(&rdev->ddev->struct_mutex);
		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
			&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
			*((unsigned long *)&bo->gem_base.refcount));
		mutex_lock(&bo->rdev->gem.mutex);
		list_del_init(&bo->list);
		mutex_unlock(&bo->rdev->gem.mutex);
		/* this should unref the ttm bo */
		drm_gem_object_unreference(&bo->gem_base);
		mutex_unlock(&rdev->ddev->struct_mutex);
	}
}

int radeon_bo_init(struct radeon_device *rdev)
{
	/* Add an MTRR for the VRAM */
	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
			MTRR_TYPE_WRCOMB, 1);
	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
		rdev->mc.mc_vram_size >> 20,
		(unsigned long long)rdev->mc.aper_size >> 20);
	DRM_INFO("RAM width %dbits %cDR\n",
			rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
	return radeon_ttm_init(rdev);
}

void radeon_bo_fini(struct radeon_device *rdev)
{
	radeon_ttm_fini(rdev);
}

void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
				struct list_head *head)
{
	if (lobj->wdomain) {
		list_add(&lobj->tv.head, head);
	} else {
		list_add_tail(&lobj->tv.head, head);
	}
}

int radeon_bo_list_validate(struct list_head *head)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	u32 domain;
	int r;

	r = ttm_eu_reserve_buffers(head);
	if (unlikely(r != 0)) {
		return r;
	}
	list_for_each_entry(lobj, head, tv.head) {
		bo = lobj->bo;
		if (!bo->pin_count) {
			domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
			
		retry:
			radeon_ttm_placement_from_domain(bo, domain);
			r = ttm_bo_validate(&bo->tbo, &bo->placement,
						true, false, false);
			if (unlikely(r)) {
				if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
					domain |= RADEON_GEM_DOMAIN_GTT;
					goto retry;
				}
				return r;
			}
		}
		lobj->gpu_offset = radeon_bo_gpu_offset(bo);
		lobj->tiling_flags = bo->tiling_flags;
	}
	return 0;
}

int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
			     struct vm_area_struct *vma)
{
	return ttm_fbdev_mmap(vma, &bo->tbo);
}

int radeon_bo_get_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;
	struct radeon_bo *old_object;
	int steal;
	int i;

	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!bo->tiling_flags)
		return 0;

	if (bo->surface_reg >= 0) {
		reg = &rdev->surface_regs[bo->surface_reg];
		i = bo->surface_reg;
		goto out;
	}

	steal = -1;
	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {

		reg = &rdev->surface_regs[i];
		if (!reg->bo)
			break;

		old_object = reg->bo;
		if (old_object->pin_count == 0)
			steal = i;
	}

	/* if we are all out */
	if (i == RADEON_GEM_MAX_SURFACES) {
		if (steal == -1)
			return -ENOMEM;
		/* find someone with a surface reg and nuke their BO */
		reg = &rdev->surface_regs[steal];
		old_object = reg->bo;
		/* blow away the mapping */
		DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
		ttm_bo_unmap_virtual(&old_object->tbo);
		old_object->surface_reg = -1;
		i = steal;
	}

	bo->surface_reg = i;
	reg->bo = bo;

out:
	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
			       bo->tbo.mem.start << PAGE_SHIFT,
			       bo->tbo.num_pages << PAGE_SHIFT);
	return 0;
}

static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;

	if (bo->surface_reg == -1)
		return;

	reg = &rdev->surface_regs[bo->surface_reg];
	radeon_clear_surface_reg(rdev, bo->surface_reg);

	reg->bo = NULL;
	bo->surface_reg = -1;
}

int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
				uint32_t tiling_flags, uint32_t pitch)
{
	struct radeon_device *rdev = bo->rdev;
	int r;

	if (rdev->family >= CHIP_CEDAR) {
		unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;

		bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
		bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
		mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
		tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
		stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
		switch (bankw) {
		case 0:
		case 1:
		case 2:
		case 4:
		case 8:
			break;
		default:
			return -EINVAL;
		}
		switch (bankh) {
		case 0:
		case 1:
		case 2:
		case 4:
		case 8:
			break;
		default:
			return -EINVAL;
		}
		switch (mtaspect) {
		case 0:
		case 1:
		case 2:
		case 4:
		case 8:
			break;
		default:
			return -EINVAL;
		}
		if (tilesplit > 6) {
			return -EINVAL;
		}
		if (stilesplit > 6) {
			return -EINVAL;
		}
	}
	r = radeon_bo_reserve(bo, false);
	if (unlikely(r != 0))
		return r;
	bo->tiling_flags = tiling_flags;
	bo->pitch = pitch;
	radeon_bo_unreserve(bo);
	return 0;
}

void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
				uint32_t *tiling_flags,
				uint32_t *pitch)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));
	if (tiling_flags)
		*tiling_flags = bo->tiling_flags;
	if (pitch)
		*pitch = bo->pitch;
}

int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
				bool force_drop)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
		return 0;

	if (force_drop) {
		radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
		if (!has_moved)
			return 0;

		if (bo->surface_reg >= 0)
			radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if ((bo->surface_reg >= 0) && !has_moved)
		return 0;

	return radeon_bo_get_surface_reg(bo);
}

void radeon_bo_move_notify(struct ttm_buffer_object *bo,
			   struct ttm_mem_reg *mem)
{
	struct radeon_bo *rbo;
	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 1);
	radeon_vm_bo_invalidate(rbo->rdev, rbo);
}

int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
	struct radeon_device *rdev;
	struct radeon_bo *rbo;
	unsigned long offset, size;
	int r;

	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return 0;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 0);
	rdev = rbo->rdev;
	if (bo->mem.mem_type == TTM_PL_VRAM) {
		size = bo->mem.num_pages << PAGE_SHIFT;
		offset = bo->mem.start << PAGE_SHIFT;
		if ((offset + size) > rdev->mc.visible_vram_size) {
			/* hurrah the memory is not visible ! */
			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
			rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
			r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
			if (unlikely(r != 0))
				return r;
			offset = bo->mem.start << PAGE_SHIFT;
			/* this should not happen */
			if ((offset + size) > rdev->mc.visible_vram_size)
				return -EINVAL;
		}
	}
	return 0;
}

int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
{
	int r;

	r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
	if (unlikely(r != 0))
		return r;
	spin_lock(&bo->tbo.bdev->fence_lock);
	if (mem_type)
		*mem_type = bo->tbo.mem.mem_type;
	if (bo->tbo.sync_obj)
		r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
	spin_unlock(&bo->tbo.bdev->fence_lock);
	ttm_bo_unreserve(&bo->tbo);
	return r;
}


/**
 * radeon_bo_reserve - reserve bo
 * @bo:		bo structure
 * @no_wait:		don't sleep while trying to reserve (return -EBUSY)
 *
 * Returns:
 * -EBUSY: buffer is busy and @no_wait is true
 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 * a signal. Release all buffer reservations and return to user-space.
 */
int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
{
	int r;

	r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
	if (unlikely(r != 0)) {
		if (r != -ERESTARTSYS)
			dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
		return r;
	}
	return 0;
}

/* object have to be reserved */
struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo, struct radeon_vm *vm)
{
	struct radeon_bo_va *bo_va;

	list_for_each_entry(bo_va, &rbo->va, bo_list) {
		if (bo_va->vm == vm) {
			return bo_va;
		}
	}
	return NULL;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2009 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Jerome Glisse <glisse@freedesktop.org>
	29	* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
	30	* Dave Airlie
	31	*/
	32	#include <linux/list.h>
5a0e3ad6	33	#include <linux/slab.h>
771fe6b9 JG	34	#include <drm/drmP.h>
	35	#include "radeon_drm.h"
	36	#include "radeon.h"
99ee7fac	37	#include "radeon_trace.h"
771fe6b9	38
771fe6b9 JG	39
	40	int radeon_ttm_init(struct radeon_device *rdev);
	41	void radeon_ttm_fini(struct radeon_device *rdev);
4c788679	42	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
771fe6b9 JG	43
	44	/*
	45	* To exclude mutual BO access we rely on bo_reserve exclusion, as all
	46	* function are calling it.
	47	*/
	48
721604a1 JG	49	void radeon_bo_clear_va(struct radeon_bo *bo)
	50	{
	51	struct radeon_bo_va bo_va, tmp;
	52
	53	list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
	54	/* remove from all vm address space */
	55	mutex_lock(&bo_va->vm->mutex);
	56	list_del(&bo_va->vm_list);
	57	mutex_unlock(&bo_va->vm->mutex);
	58	list_del(&bo_va->bo_list);
	59	kfree(bo_va);
	60	}
	61	}
	62
4c788679	63	static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
771fe6b9	64	{
4c788679	65	struct radeon_bo *bo;
771fe6b9	66
4c788679 JG	67	bo = container_of(tbo, struct radeon_bo, tbo);
	68	mutex_lock(&bo->rdev->gem.mutex);
	69	list_del_init(&bo->list);
	70	mutex_unlock(&bo->rdev->gem.mutex);
	71	radeon_bo_clear_surface_reg(bo);
721604a1	72	radeon_bo_clear_va(bo);
441921d5	73	drm_gem_object_release(&bo->gem_base);
4c788679	74	kfree(bo);
771fe6b9 JG	75	}
771fe6b9 JG	76
d03d8589 JG	77	bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
	78	{
	79	if (bo->destroy == &radeon_ttm_bo_destroy)
	80	return true;
	81	return false;
	82	}
	83
312ea8da JG	84	void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
	85	{
	86	u32 c = 0;
	87
	88	rbo->placement.fpfn = 0;
93225b0d	89	rbo->placement.lpfn = 0;
312ea8da JG	90	rbo->placement.placement = rbo->placements;
	91	rbo->placement.busy_placement = rbo->placements;
	92	if (domain & RADEON_GEM_DOMAIN_VRAM)
	93	rbo->placements[c++] = TTM_PL_FLAG_WC \| TTM_PL_FLAG_UNCACHED \|
	94	TTM_PL_FLAG_VRAM;
	95	if (domain & RADEON_GEM_DOMAIN_GTT)
	96	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_TT;
	97	if (domain & RADEON_GEM_DOMAIN_CPU)
	98	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
9fb03e63 JG	99	if (!c)
9fb03e63 JG	100	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
312ea8da JG	101	rbo->placement.num_placement = c;
	102	rbo->placement.num_busy_placement = c;
	103	}
	104
441921d5	105	int radeon_bo_create(struct radeon_device *rdev,
268b2510 AD	106	unsigned long size, int byte_align, bool kernel, u32 domain,
268b2510 AD	107	struct radeon_bo **bo_ptr)
771fe6b9	108	{
4c788679	109	struct radeon_bo *bo;
771fe6b9	110	enum ttm_bo_type type;
93225b0d JG	111	unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
93225b0d JG	112	unsigned long max_size = 0;
57de4ba9	113	size_t acc_size;
771fe6b9 JG	114	int r;
771fe6b9 JG	115
441921d5 DV	116	size = ALIGN(size, PAGE_SIZE);
441921d5 DV	117
771fe6b9 JG	118	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
	119	rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	120	}
	121	if (kernel) {
	122	type = ttm_bo_type_kernel;
	123	} else {
	124	type = ttm_bo_type_device;
	125	}
4c788679	126	*bo_ptr = NULL;
2b66b50b	127
93225b0d JG	128	/* maximun bo size is the minimun btw visible vram and gtt size */
	129	max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
	130	if ((page_align << PAGE_SHIFT) >= max_size) {
	131	printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
	132	__func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20);
	133	return -ENOMEM;
	134	}
	135
57de4ba9 JG	136	acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
	137	sizeof(struct radeon_bo));
	138
2b66b50b	139	retry:
4c788679 JG	140	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
4c788679 JG	141	if (bo == NULL)
771fe6b9	142	return -ENOMEM;
441921d5 DV	143	r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
	144	if (unlikely(r)) {
	145	kfree(bo);
	146	return r;
	147	}
4c788679	148	bo->rdev = rdev;
7e4d15d9	149	bo->gem_base.driver_private = NULL;
4c788679 JG	150	bo->surface_reg = -1;
4c788679 JG	151	INIT_LIST_HEAD(&bo->list);
721604a1	152	INIT_LIST_HEAD(&bo->va);
1fb107fc	153	radeon_ttm_placement_from_domain(bo, domain);
5cc6fbab	154	/* Kernel allocation are uninterruptible */
5876dd24	155	mutex_lock(&rdev->vram_mutex);
1fb107fc	156	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
57de4ba9 JG	157	&bo->placement, page_align, 0, !kernel, NULL,
57de4ba9 JG	158	acc_size, &radeon_ttm_bo_destroy);
5876dd24	159	mutex_unlock(&rdev->vram_mutex);
771fe6b9	160	if (unlikely(r != 0)) {
e376573f MD	161	if (r != -ERESTARTSYS) {
	162	if (domain == RADEON_GEM_DOMAIN_VRAM) {
	163	domain \|= RADEON_GEM_DOMAIN_GTT;
	164	goto retry;
	165	}
5cc6fbab	166	dev_err(rdev->dev,
1fb107fc JG	167	"object_init failed for (%lu, 0x%08X)\n",
1fb107fc JG	168	size, domain);
e376573f	169	}
771fe6b9 JG	170	return r;
771fe6b9 JG	171	}
4c788679	172	*bo_ptr = bo;
441921d5	173
99ee7fac	174	trace_radeon_bo_create(bo);
441921d5	175
771fe6b9 JG	176	return 0;
	177	}
	178
4c788679	179	int radeon_bo_kmap(struct radeon_bo bo, void *ptr)
771fe6b9	180	{
4c788679	181	bool is_iomem;
771fe6b9 JG	182	int r;
771fe6b9 JG	183
4c788679	184	if (bo->kptr) {
771fe6b9	185	if (ptr) {
4c788679	186	*ptr = bo->kptr;
771fe6b9	187	}
771fe6b9 JG	188	return 0;
771fe6b9 JG	189	}
4c788679	190	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
771fe6b9 JG	191	if (r) {
	192	return r;
	193	}
4c788679	194	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
771fe6b9	195	if (ptr) {
4c788679	196	*ptr = bo->kptr;
771fe6b9	197	}
4c788679	198	radeon_bo_check_tiling(bo, 0, 0);
771fe6b9 JG	199	return 0;
	200	}
	201
4c788679	202	void radeon_bo_kunmap(struct radeon_bo *bo)
771fe6b9	203	{
4c788679	204	if (bo->kptr == NULL)
771fe6b9	205	return;
4c788679 JG	206	bo->kptr = NULL;
	207	radeon_bo_check_tiling(bo, 0, 0);
	208	ttm_bo_kunmap(&bo->kmap);
771fe6b9 JG	209	}
771fe6b9 JG	210
4c788679	211	void radeon_bo_unref(struct radeon_bo **bo)
771fe6b9	212	{
4c788679	213	struct ttm_buffer_object *tbo;
f4b7fb94	214	struct radeon_device *rdev;
771fe6b9	215
4c788679	216	if ((*bo) == NULL)
771fe6b9	217	return;
f4b7fb94	218	rdev = (*bo)->rdev;
4c788679	219	tbo = &((*bo)->tbo);
f4b7fb94	220	mutex_lock(&rdev->vram_mutex);
4c788679	221	ttm_bo_unref(&tbo);
f4b7fb94	222	mutex_unlock(&rdev->vram_mutex);
4c788679 JG	223	if (tbo == NULL)
4c788679 JG	224	*bo = NULL;
771fe6b9 JG	225	}
771fe6b9 JG	226
c4353016 MD	227	int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
c4353016 MD	228	u64 *gpu_addr)
771fe6b9	229	{
312ea8da	230	int r, i;
771fe6b9	231
4c788679 JG	232	if (bo->pin_count) {
	233	bo->pin_count++;
	234	if (gpu_addr)
	235	*gpu_addr = radeon_bo_gpu_offset(bo);
c4353016	236	WARN_ON_ONCE(max_offset != 0);
771fe6b9 JG	237	return 0;
771fe6b9 JG	238	}
312ea8da	239	radeon_ttm_placement_from_domain(bo, domain);
3ca82da3 MD	240	if (domain == RADEON_GEM_DOMAIN_VRAM) {
	241	/* force to pin into visible video ram */
	242	bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	243	}
c4353016 MD	244	if (max_offset) {
	245	u64 lpfn = max_offset >> PAGE_SHIFT;
	246
	247	if (!bo->placement.lpfn)
	248	bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
	249
	250	if (lpfn < bo->placement.lpfn)
	251	bo->placement.lpfn = lpfn;
	252	}
312ea8da JG	253	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	254	bo->placements[i] \|= TTM_PL_FLAG_NO_EVICT;
9d87fa21	255	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
4c788679 JG	256	if (likely(r == 0)) {
	257	bo->pin_count = 1;
	258	if (gpu_addr != NULL)
	259	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9	260	}
5cc6fbab	261	if (unlikely(r != 0))
4c788679	262	dev_err(bo->rdev->dev, "%p pin failed\n", bo);
771fe6b9 JG	263	return r;
771fe6b9 JG	264	}
c4353016 MD	265
	266	int radeon_bo_pin(struct radeon_bo bo, u32 domain, u64 gpu_addr)
	267	{
	268	return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
	269	}
771fe6b9	270
4c788679	271	int radeon_bo_unpin(struct radeon_bo *bo)
771fe6b9	272	{
312ea8da	273	int r, i;
771fe6b9	274
4c788679 JG	275	if (!bo->pin_count) {
	276	dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
	277	return 0;
771fe6b9	278	}
4c788679 JG	279	bo->pin_count--;
	280	if (bo->pin_count)
	281	return 0;
312ea8da JG	282	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	283	bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
9d87fa21	284	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
5cc6fbab	285	if (unlikely(r != 0))
4c788679	286	dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
5cc6fbab	287	return r;
cefb87ef DA	288	}
cefb87ef DA	289
4c788679	290	int radeon_bo_evict_vram(struct radeon_device *rdev)
771fe6b9	291	{
d796d844 DA	292	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
d796d844 DA	293	if (0 && (rdev->flags & RADEON_IS_IGP)) {
06b6476d AD	294	if (rdev->mc.igp_sideport_enabled == false)
	295	/* Useless to evict on IGP chips */
	296	return 0;
771fe6b9 JG	297	}
	298	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
	299	}
	300
4c788679	301	void radeon_bo_force_delete(struct radeon_device *rdev)
771fe6b9	302	{
4c788679	303	struct radeon_bo bo, n;
771fe6b9 JG	304
	305	if (list_empty(&rdev->gem.objects)) {
	306	return;
	307	}
4c788679 JG	308	dev_err(rdev->dev, "Userspace still has active objects !\n");
4c788679 JG	309	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
771fe6b9	310	mutex_lock(&rdev->ddev->struct_mutex);
4c788679	311	dev_err(rdev->dev, "%p %p %lu %lu force free\n",
31c3603d DV	312	&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
31c3603d DV	313	((unsigned long )&bo->gem_base.refcount));
4c788679 JG	314	mutex_lock(&bo->rdev->gem.mutex);
	315	list_del_init(&bo->list);
	316	mutex_unlock(&bo->rdev->gem.mutex);
91132d6b	317	/* this should unref the ttm bo */
31c3603d	318	drm_gem_object_unreference(&bo->gem_base);
771fe6b9 JG	319	mutex_unlock(&rdev->ddev->struct_mutex);
	320	}
	321	}
	322
4c788679	323	int radeon_bo_init(struct radeon_device *rdev)
771fe6b9	324	{
a4d68279 JG	325	/* Add an MTRR for the VRAM */
	326	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
	327	MTRR_TYPE_WRCOMB, 1);
	328	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
	329	rdev->mc.mc_vram_size >> 20,
	330	(unsigned long long)rdev->mc.aper_size >> 20);
	331	DRM_INFO("RAM width %dbits %cDR\n",
	332	rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
771fe6b9 JG	333	return radeon_ttm_init(rdev);
	334	}
	335
4c788679	336	void radeon_bo_fini(struct radeon_device *rdev)
771fe6b9 JG	337	{
	338	radeon_ttm_fini(rdev);
	339	}
	340
4c788679 JG	341	void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
4c788679 JG	342	struct list_head *head)
771fe6b9 JG	343	{
771fe6b9 JG	344	if (lobj->wdomain) {
147666fb	345	list_add(&lobj->tv.head, head);
771fe6b9	346	} else {
147666fb	347	list_add_tail(&lobj->tv.head, head);
771fe6b9 JG	348	}
	349	}
	350
6cb8e1f7	351	int radeon_bo_list_validate(struct list_head *head)
771fe6b9	352	{
4c788679 JG	353	struct radeon_bo_list *lobj;
4c788679 JG	354	struct radeon_bo *bo;
e376573f	355	u32 domain;
771fe6b9 JG	356	int r;
771fe6b9 JG	357
147666fb	358	r = ttm_eu_reserve_buffers(head);
771fe6b9	359	if (unlikely(r != 0)) {
771fe6b9 JG	360	return r;
771fe6b9 JG	361	}
147666fb	362	list_for_each_entry(lobj, head, tv.head) {
4c788679 JG	363	bo = lobj->bo;
4c788679 JG	364	if (!bo->pin_count) {
e376573f MD	365	domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
	366
	367	retry:
	368	radeon_ttm_placement_from_domain(bo, domain);
1fb107fc	369	r = ttm_bo_validate(&bo->tbo, &bo->placement,
9d87fa21	370	true, false, false);
e376573f MD	371	if (unlikely(r)) {
	372	if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
	373	domain \|= RADEON_GEM_DOMAIN_GTT;
	374	goto retry;
	375	}
771fe6b9	376	return r;
e376573f	377	}
771fe6b9	378	}
4c788679 JG	379	lobj->gpu_offset = radeon_bo_gpu_offset(bo);
4c788679 JG	380	lobj->tiling_flags = bo->tiling_flags;
771fe6b9 JG	381	}
	382	return 0;
	383	}
	384
4c788679	385	int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
771fe6b9 JG	386	struct vm_area_struct *vma)
771fe6b9 JG	387	{
4c788679	388	return ttm_fbdev_mmap(vma, &bo->tbo);
771fe6b9 JG	389	}
771fe6b9 JG	390
550e2d92	391	int radeon_bo_get_surface_reg(struct radeon_bo *bo)
771fe6b9	392	{
4c788679	393	struct radeon_device *rdev = bo->rdev;
e024e110	394	struct radeon_surface_reg *reg;
4c788679	395	struct radeon_bo *old_object;
e024e110 DA	396	int steal;
	397	int i;
	398
4c788679 JG	399	BUG_ON(!atomic_read(&bo->tbo.reserved));
	400
	401	if (!bo->tiling_flags)
e024e110 DA	402	return 0;
e024e110 DA	403
4c788679 JG	404	if (bo->surface_reg >= 0) {
	405	reg = &rdev->surface_regs[bo->surface_reg];
	406	i = bo->surface_reg;
e024e110 DA	407	goto out;
	408	}
	409
	410	steal = -1;
	411	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
	412
	413	reg = &rdev->surface_regs[i];
4c788679	414	if (!reg->bo)
e024e110 DA	415	break;
e024e110 DA	416
4c788679	417	old_object = reg->bo;
e024e110 DA	418	if (old_object->pin_count == 0)
	419	steal = i;
	420	}
	421
	422	/* if we are all out */
	423	if (i == RADEON_GEM_MAX_SURFACES) {
	424	if (steal == -1)
	425	return -ENOMEM;
	426	/* find someone with a surface reg and nuke their BO */
	427	reg = &rdev->surface_regs[steal];
4c788679	428	old_object = reg->bo;
e024e110 DA	429	/* blow away the mapping */
e024e110 DA	430	DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
4c788679	431	ttm_bo_unmap_virtual(&old_object->tbo);
e024e110 DA	432	old_object->surface_reg = -1;
	433	i = steal;
	434	}
	435
4c788679 JG	436	bo->surface_reg = i;
4c788679 JG	437	reg->bo = bo;
e024e110 DA	438
e024e110 DA	439	out:
4c788679	440	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
d961db75	441	bo->tbo.mem.start << PAGE_SHIFT,
4c788679	442	bo->tbo.num_pages << PAGE_SHIFT);
e024e110 DA	443	return 0;
	444	}
	445
4c788679	446	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
e024e110	447	{
4c788679	448	struct radeon_device *rdev = bo->rdev;
e024e110 DA	449	struct radeon_surface_reg *reg;
e024e110 DA	450
4c788679	451	if (bo->surface_reg == -1)
e024e110 DA	452	return;
e024e110 DA	453
4c788679 JG	454	reg = &rdev->surface_regs[bo->surface_reg];
4c788679 JG	455	radeon_clear_surface_reg(rdev, bo->surface_reg);
e024e110	456
4c788679 JG	457	reg->bo = NULL;
4c788679 JG	458	bo->surface_reg = -1;
e024e110 DA	459	}
e024e110 DA	460
4c788679 JG	461	int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
4c788679 JG	462	uint32_t tiling_flags, uint32_t pitch)
e024e110	463	{
285484e2	464	struct radeon_device *rdev = bo->rdev;
4c788679 JG	465	int r;
4c788679 JG	466
285484e2 JG	467	if (rdev->family >= CHIP_CEDAR) {
	468	unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
	469
	470	bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
	471	bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
	472	mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
	473	tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
	474	stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
	475	switch (bankw) {
	476	case 0:
	477	case 1:
	478	case 2:
	479	case 4:
	480	case 8:
	481	break;
	482	default:
	483	return -EINVAL;
	484	}
	485	switch (bankh) {
	486	case 0:
	487	case 1:
	488	case 2:
	489	case 4:
	490	case 8:
	491	break;
	492	default:
	493	return -EINVAL;
	494	}
	495	switch (mtaspect) {
	496	case 0:
	497	case 1:
	498	case 2:
	499	case 4:
	500	case 8:
	501	break;
	502	default:
	503	return -EINVAL;
	504	}
	505	if (tilesplit > 6) {
	506	return -EINVAL;
	507	}
	508	if (stilesplit > 6) {
	509	return -EINVAL;
	510	}
	511	}
4c788679 JG	512	r = radeon_bo_reserve(bo, false);
	513	if (unlikely(r != 0))
	514	return r;
	515	bo->tiling_flags = tiling_flags;
	516	bo->pitch = pitch;
	517	radeon_bo_unreserve(bo);
	518	return 0;
e024e110 DA	519	}
e024e110 DA	520
4c788679 JG	521	void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
	522	uint32_t *tiling_flags,
	523	uint32_t *pitch)
e024e110	524	{
4c788679	525	BUG_ON(!atomic_read(&bo->tbo.reserved));
e024e110	526	if (tiling_flags)
4c788679	527	*tiling_flags = bo->tiling_flags;
e024e110	528	if (pitch)
4c788679	529	*pitch = bo->pitch;
e024e110 DA	530	}
e024e110 DA	531
4c788679 JG	532	int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
4c788679 JG	533	bool force_drop)
e024e110	534	{
4c788679 JG	535	BUG_ON(!atomic_read(&bo->tbo.reserved));
	536
	537	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
e024e110 DA	538	return 0;
	539
	540	if (force_drop) {
4c788679	541	radeon_bo_clear_surface_reg(bo);
e024e110 DA	542	return 0;
	543	}
	544
4c788679	545	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
e024e110 DA	546	if (!has_moved)
	547	return 0;
	548
4c788679 JG	549	if (bo->surface_reg >= 0)
4c788679 JG	550	radeon_bo_clear_surface_reg(bo);
e024e110 DA	551	return 0;
	552	}
	553
4c788679	554	if ((bo->surface_reg >= 0) && !has_moved)
e024e110 DA	555	return 0;
e024e110 DA	556
4c788679	557	return radeon_bo_get_surface_reg(bo);
e024e110 DA	558	}
	559
	560	void radeon_bo_move_notify(struct ttm_buffer_object *bo,
d03d8589	561	struct ttm_mem_reg *mem)
e024e110	562	{
d03d8589 JG	563	struct radeon_bo *rbo;
	564	if (!radeon_ttm_bo_is_radeon_bo(bo))
	565	return;
	566	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	567	radeon_bo_check_tiling(rbo, 0, 1);
721604a1	568	radeon_vm_bo_invalidate(rbo->rdev, rbo);
e024e110 DA	569	}
e024e110 DA	570
0a2d50e3	571	int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
e024e110	572	{
0a2d50e3	573	struct radeon_device *rdev;
d03d8589	574	struct radeon_bo *rbo;
0a2d50e3 JG	575	unsigned long offset, size;
	576	int r;
	577
d03d8589	578	if (!radeon_ttm_bo_is_radeon_bo(bo))
0a2d50e3	579	return 0;
d03d8589	580	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	581	radeon_bo_check_tiling(rbo, 0, 0);
0a2d50e3 JG	582	rdev = rbo->rdev;
	583	if (bo->mem.mem_type == TTM_PL_VRAM) {
	584	size = bo->mem.num_pages << PAGE_SHIFT;
d961db75	585	offset = bo->mem.start << PAGE_SHIFT;
0a2d50e3 JG	586	if ((offset + size) > rdev->mc.visible_vram_size) {
	587	/* hurrah the memory is not visible ! */
	588	radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
	589	rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
	590	r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
	591	if (unlikely(r != 0))
	592	return r;
d961db75	593	offset = bo->mem.start << PAGE_SHIFT;
0a2d50e3 JG	594	/* this should not happen */
	595	if ((offset + size) > rdev->mc.visible_vram_size)
	596	return -EINVAL;
	597	}
	598	}
	599	return 0;
e024e110	600	}
ce580fab	601
83f30d0e	602	int radeon_bo_wait(struct radeon_bo bo, u32 mem_type, bool no_wait)
ce580fab AK	603	{
	604	int r;
	605
	606	r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
	607	if (unlikely(r != 0))
	608	return r;
	609	spin_lock(&bo->tbo.bdev->fence_lock);
	610	if (mem_type)
	611	*mem_type = bo->tbo.mem.mem_type;
	612	if (bo->tbo.sync_obj)
1717c0e2	613	r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
ce580fab AK	614	spin_unlock(&bo->tbo.bdev->fence_lock);
	615	ttm_bo_unreserve(&bo->tbo);
	616	return r;
	617	}
	618
	619
	620	/**
	621	* radeon_bo_reserve - reserve bo
	622	* @bo: bo structure
	623	* @no_wait: don't sleep while trying to reserve (return -EBUSY)
	624	*
	625	* Returns:
	626	* -EBUSY: buffer is busy and @no_wait is true
	627	* -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
	628	* a signal. Release all buffer reservations and return to user-space.
	629	*/
	630	int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
	631	{
	632	int r;
	633
	634	r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
	635	if (unlikely(r != 0)) {
	636	if (r != -ERESTARTSYS)
	637	dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
	638	return r;
	639	}
	640	return 0;
	641	}
721604a1 JG	642
	643	/* object have to be reserved */
	644	struct radeon_bo_va radeon_bo_va(struct radeon_bo rbo, struct radeon_vm *vm)
	645	{
	646	struct radeon_bo_va *bo_va;
	647
	648	list_for_each_entry(bo_va, &rbo->va, bo_list) {
	649	if (bo_va->vm == vm) {
	650	return bo_va;
	651	}
	652	}
	653	return NULL;
	654	}