[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / radeon / radeon_object.c

/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
#include <linux/list.h>
#include <drm/drmP.h>
#include "radeon_drm.h"
#include "radeon.h"


int radeon_ttm_init(struct radeon_device *rdev);
void radeon_ttm_fini(struct radeon_device *rdev);
static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);

/*
 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
 * function are calling it.
 */

static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
	struct radeon_bo *bo;

	bo = container_of(tbo, struct radeon_bo, tbo);
	mutex_lock(&bo->rdev->gem.mutex);
	list_del_init(&bo->list);
	mutex_unlock(&bo->rdev->gem.mutex);
	radeon_bo_clear_surface_reg(bo);
	kfree(bo);
}

static inline u32 radeon_ttm_flags_from_domain(u32 domain)
{
	u32 flags = 0;

	if (domain & RADEON_GEM_DOMAIN_VRAM) {
		flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
	}
	if (domain & RADEON_GEM_DOMAIN_GTT) {
		flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
	}
	if (domain & RADEON_GEM_DOMAIN_CPU) {
		flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
	}
	if (!flags) {
		flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
	}
	return flags;
}

void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
{
	u32 c = 0;

	rbo->placement.fpfn = 0;
	rbo->placement.lpfn = 0;
	rbo->placement.placement = rbo->placements;
	rbo->placement.busy_placement = rbo->placements;
	if (domain & RADEON_GEM_DOMAIN_VRAM)
		rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
					TTM_PL_FLAG_VRAM;
	if (domain & RADEON_GEM_DOMAIN_GTT)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
	if (domain & RADEON_GEM_DOMAIN_CPU)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	rbo->placement.num_placement = c;
	rbo->placement.num_busy_placement = c;
}

int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
			unsigned long size, bool kernel, u32 domain,
			struct radeon_bo **bo_ptr)
{
	struct radeon_bo *bo;
	enum ttm_bo_type type;
	u32 flags;
	int r;

	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
		rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	}
	if (kernel) {
		type = ttm_bo_type_kernel;
	} else {
		type = ttm_bo_type_device;
	}
	*bo_ptr = NULL;
	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	if (bo == NULL)
		return -ENOMEM;
	bo->rdev = rdev;
	bo->gobj = gobj;
	bo->surface_reg = -1;
	INIT_LIST_HEAD(&bo->list);

	flags = radeon_ttm_flags_from_domain(domain);
retry:
	r = ttm_buffer_object_init(&rdev->mman.bdev, &bo->tbo, size, type,
					flags, 0, 0, true, NULL, size,
					&radeon_ttm_bo_destroy);
	if (unlikely(r != 0)) {
		if (r == -ERESTART)
			goto retry;
		/* ttm call radeon_ttm_object_object_destroy if error happen */
		dev_err(rdev->dev, "object_init failed for (%ld, 0x%08X)\n",
			size, flags);
		return r;
	}
	*bo_ptr = bo;
	if (gobj) {
		mutex_lock(&bo->rdev->gem.mutex);
		list_add_tail(&bo->list, &rdev->gem.objects);
		mutex_unlock(&bo->rdev->gem.mutex);
	}
	return 0;
}

int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
{
	bool is_iomem;
	int r;

	if (bo->kptr) {
		if (ptr) {
			*ptr = bo->kptr;
		}
		return 0;
	}
	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
	if (r) {
		return r;
	}
	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
	if (ptr) {
		*ptr = bo->kptr;
	}
	radeon_bo_check_tiling(bo, 0, 0);
	return 0;
}

void radeon_bo_kunmap(struct radeon_bo *bo)
{
	if (bo->kptr == NULL)
		return;
	bo->kptr = NULL;
	radeon_bo_check_tiling(bo, 0, 0);
	ttm_bo_kunmap(&bo->kmap);
}

void radeon_bo_unref(struct radeon_bo **bo)
{
	struct ttm_buffer_object *tbo;

	if ((*bo) == NULL)
		return;
	tbo = &((*bo)->tbo);
	ttm_bo_unref(&tbo);
	if (tbo == NULL)
		*bo = NULL;
}

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
{
	int r, i;

	radeon_ttm_placement_from_domain(bo, domain);
	if (bo->pin_count) {
		bo->pin_count++;
		if (gpu_addr)
			*gpu_addr = radeon_bo_gpu_offset(bo);
		return 0;
	}
	radeon_ttm_placement_from_domain(bo, domain);
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
retry:
	r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, true, false);
	if (likely(r == 0)) {
		bo->pin_count = 1;
		if (gpu_addr != NULL)
			*gpu_addr = radeon_bo_gpu_offset(bo);
	}
	if (unlikely(r != 0)) {
		if (r == -ERESTART)
			goto retry;
		dev_err(bo->rdev->dev, "%p pin failed\n", bo);
	}
	return r;
}

int radeon_bo_unpin(struct radeon_bo *bo)
{
	int r, i;

	if (!bo->pin_count) {
		dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
		return 0;
	}
	bo->pin_count--;
	if (bo->pin_count)
		return 0;
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
retry:
	r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, true, false);
	if (unlikely(r != 0)) {
		if (r == -ERESTART)
			goto retry;
		dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
		return r;
	}
	return 0;
}

int radeon_bo_evict_vram(struct radeon_device *rdev)
{
	if (rdev->flags & RADEON_IS_IGP) {
		/* Useless to evict on IGP chips */
		return 0;
	}
	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
}

void radeon_bo_force_delete(struct radeon_device *rdev)
{
	struct radeon_bo *bo, *n;
	struct drm_gem_object *gobj;

	if (list_empty(&rdev->gem.objects)) {
		return;
	}
	dev_err(rdev->dev, "Userspace still has active objects !\n");
	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
		mutex_lock(&rdev->ddev->struct_mutex);
		gobj = bo->gobj;
		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
			gobj, bo, (unsigned long)gobj->size,
			*((unsigned long *)&gobj->refcount));
		mutex_lock(&bo->rdev->gem.mutex);
		list_del_init(&bo->list);
		mutex_unlock(&bo->rdev->gem.mutex);
		radeon_bo_unref(&bo);
		gobj->driver_private = NULL;
		drm_gem_object_unreference(gobj);
		mutex_unlock(&rdev->ddev->struct_mutex);
	}
}

int radeon_bo_init(struct radeon_device *rdev)
{
	/* Add an MTRR for the VRAM */
	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
			MTRR_TYPE_WRCOMB, 1);
	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
		rdev->mc.mc_vram_size >> 20,
		(unsigned long long)rdev->mc.aper_size >> 20);
	DRM_INFO("RAM width %dbits %cDR\n",
			rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
	return radeon_ttm_init(rdev);
}

void radeon_bo_fini(struct radeon_device *rdev)
{
	radeon_ttm_fini(rdev);
}

void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
				struct list_head *head)
{
	if (lobj->wdomain) {
		list_add(&lobj->list, head);
	} else {
		list_add_tail(&lobj->list, head);
	}
}

int radeon_bo_list_reserve(struct list_head *head)
{
	struct radeon_bo_list *lobj;
	int r;

	list_for_each_entry(lobj, head, list){
		r = radeon_bo_reserve(lobj->bo, false);
		if (unlikely(r != 0))
			return r;
	}
	return 0;
}

void radeon_bo_list_unreserve(struct list_head *head)
{
	struct radeon_bo_list *lobj;

	list_for_each_entry(lobj, head, list) {
		/* only unreserve object we successfully reserved */
		if (radeon_bo_is_reserved(lobj->bo))
			radeon_bo_unreserve(lobj->bo);
	}
}

int radeon_bo_list_validate(struct list_head *head, void *fence)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	struct radeon_fence *old_fence = NULL;
	int r;

	r = radeon_bo_list_reserve(head);
	if (unlikely(r != 0)) {
		return r;
	}
	list_for_each_entry(lobj, head, list) {
		bo = lobj->bo;
		if (!bo->pin_count) {
			if (lobj->wdomain) {
				radeon_ttm_placement_from_domain(bo,
								lobj->wdomain);
			} else {
				radeon_ttm_placement_from_domain(bo,
								lobj->rdomain);
			}
retry:
			r = ttm_buffer_object_validate(&bo->tbo,
						&bo->placement,
						true, false);
			if (unlikely(r)) {
				if (r == -ERESTART)
					goto retry;
				return r;
			}
		}
		lobj->gpu_offset = radeon_bo_gpu_offset(bo);
		lobj->tiling_flags = bo->tiling_flags;
		if (fence) {
			old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
			bo->tbo.sync_obj = radeon_fence_ref(fence);
			bo->tbo.sync_obj_arg = NULL;
		}
		if (old_fence) {
			radeon_fence_unref(&old_fence);
		}
	}
	return 0;
}

void radeon_bo_list_unvalidate(struct list_head *head, void *fence)
{
	struct radeon_bo_list *lobj;
	struct radeon_fence *old_fence;

	if (fence)
		list_for_each_entry(lobj, head, list) {
			old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
			if (old_fence == fence) {
				lobj->bo->tbo.sync_obj = NULL;
				radeon_fence_unref(&old_fence);
			}
		}
	radeon_bo_list_unreserve(head);
}

int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
			     struct vm_area_struct *vma)
{
	return ttm_fbdev_mmap(vma, &bo->tbo);
}

static int radeon_bo_get_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;
	struct radeon_bo *old_object;
	int steal;
	int i;

	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!bo->tiling_flags)
		return 0;

	if (bo->surface_reg >= 0) {
		reg = &rdev->surface_regs[bo->surface_reg];
		i = bo->surface_reg;
		goto out;
	}

	steal = -1;
	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {

		reg = &rdev->surface_regs[i];
		if (!reg->bo)
			break;

		old_object = reg->bo;
		if (old_object->pin_count == 0)
			steal = i;
	}

	/* if we are all out */
	if (i == RADEON_GEM_MAX_SURFACES) {
		if (steal == -1)
			return -ENOMEM;
		/* find someone with a surface reg and nuke their BO */
		reg = &rdev->surface_regs[steal];
		old_object = reg->bo;
		/* blow away the mapping */
		DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
		ttm_bo_unmap_virtual(&old_object->tbo);
		old_object->surface_reg = -1;
		i = steal;
	}

	bo->surface_reg = i;
	reg->bo = bo;

out:
	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
			       bo->tbo.mem.mm_node->start << PAGE_SHIFT,
			       bo->tbo.num_pages << PAGE_SHIFT);
	return 0;
}

static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;

	if (bo->surface_reg == -1)
		return;

	reg = &rdev->surface_regs[bo->surface_reg];
	radeon_clear_surface_reg(rdev, bo->surface_reg);

	reg->bo = NULL;
	bo->surface_reg = -1;
}

int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
				uint32_t tiling_flags, uint32_t pitch)
{
	int r;

	r = radeon_bo_reserve(bo, false);
	if (unlikely(r != 0))
		return r;
	bo->tiling_flags = tiling_flags;
	bo->pitch = pitch;
	radeon_bo_unreserve(bo);
	return 0;
}

void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
				uint32_t *tiling_flags,
				uint32_t *pitch)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));
	if (tiling_flags)
		*tiling_flags = bo->tiling_flags;
	if (pitch)
		*pitch = bo->pitch;
}

int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
				bool force_drop)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
		return 0;

	if (force_drop) {
		radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
		if (!has_moved)
			return 0;

		if (bo->surface_reg >= 0)
			radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if ((bo->surface_reg >= 0) && !has_moved)
		return 0;

	return radeon_bo_get_surface_reg(bo);
}

void radeon_bo_move_notify(struct ttm_buffer_object *bo,
				struct ttm_mem_reg *mem)
{
	struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 1);
}

void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
	struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 0);
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2009 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Jerome Glisse <glisse@freedesktop.org>
	29	* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
	30	* Dave Airlie
	31	*/
	32	#include <linux/list.h>
	33	#include <drm/drmP.h>
	34	#include "radeon_drm.h"
	35	#include "radeon.h"
	36
771fe6b9 JG	37
	38	int radeon_ttm_init(struct radeon_device *rdev);
	39	void radeon_ttm_fini(struct radeon_device *rdev);
4c788679	40	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
771fe6b9 JG	41
	42	/*
	43	* To exclude mutual BO access we rely on bo_reserve exclusion, as all
	44	* function are calling it.
	45	*/
	46
4c788679	47	static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
771fe6b9	48	{
4c788679	49	struct radeon_bo *bo;
771fe6b9	50
4c788679 JG	51	bo = container_of(tbo, struct radeon_bo, tbo);
	52	mutex_lock(&bo->rdev->gem.mutex);
	53	list_del_init(&bo->list);
	54	mutex_unlock(&bo->rdev->gem.mutex);
	55	radeon_bo_clear_surface_reg(bo);
	56	kfree(bo);
771fe6b9 JG	57	}
771fe6b9 JG	58
4c788679	59	static inline u32 radeon_ttm_flags_from_domain(u32 domain)
771fe6b9	60	{
4c788679	61	u32 flags = 0;
771fe6b9	62
771fe6b9	63	if (domain & RADEON_GEM_DOMAIN_VRAM) {
664f8659	64	flags \|= TTM_PL_FLAG_VRAM \| TTM_PL_FLAG_WC \| TTM_PL_FLAG_UNCACHED;
771fe6b9 JG	65	}
771fe6b9 JG	66	if (domain & RADEON_GEM_DOMAIN_GTT) {
985fe845	67	flags \|= TTM_PL_FLAG_TT \| TTM_PL_MASK_CACHING;
771fe6b9 JG	68	}
771fe6b9 JG	69	if (domain & RADEON_GEM_DOMAIN_CPU) {
664f8659	70	flags \|= TTM_PL_FLAG_SYSTEM \| TTM_PL_MASK_CACHING;
771fe6b9 JG	71	}
771fe6b9 JG	72	if (!flags) {
664f8659	73	flags \|= TTM_PL_FLAG_SYSTEM \| TTM_PL_MASK_CACHING;
771fe6b9 JG	74	}
	75	return flags;
	76	}
	77
312ea8da JG	78	void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
	79	{
	80	u32 c = 0;
	81
	82	rbo->placement.fpfn = 0;
	83	rbo->placement.lpfn = 0;
	84	rbo->placement.placement = rbo->placements;
	85	rbo->placement.busy_placement = rbo->placements;
	86	if (domain & RADEON_GEM_DOMAIN_VRAM)
	87	rbo->placements[c++] = TTM_PL_FLAG_WC \| TTM_PL_FLAG_UNCACHED \|
	88	TTM_PL_FLAG_VRAM;
	89	if (domain & RADEON_GEM_DOMAIN_GTT)
	90	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_TT;
	91	if (domain & RADEON_GEM_DOMAIN_CPU)
	92	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
	93	rbo->placement.num_placement = c;
	94	rbo->placement.num_busy_placement = c;
	95	}
	96
4c788679 JG	97	int radeon_bo_create(struct radeon_device rdev, struct drm_gem_object gobj,
	98	unsigned long size, bool kernel, u32 domain,
	99	struct radeon_bo **bo_ptr)
771fe6b9	100	{
4c788679	101	struct radeon_bo *bo;
771fe6b9	102	enum ttm_bo_type type;
4c788679	103	u32 flags;
771fe6b9 JG	104	int r;
	105
	106	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
	107	rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	108	}
	109	if (kernel) {
	110	type = ttm_bo_type_kernel;
	111	} else {
	112	type = ttm_bo_type_device;
	113	}
4c788679 JG	114	*bo_ptr = NULL;
	115	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	116	if (bo == NULL)
771fe6b9	117	return -ENOMEM;
4c788679 JG	118	bo->rdev = rdev;
	119	bo->gobj = gobj;
	120	bo->surface_reg = -1;
	121	INIT_LIST_HEAD(&bo->list);
	122
	123	flags = radeon_ttm_flags_from_domain(domain);
	124	retry:
	125	r = ttm_buffer_object_init(&rdev->mman.bdev, &bo->tbo, size, type,
	126	flags, 0, 0, true, NULL, size,
	127	&radeon_ttm_bo_destroy);
771fe6b9	128	if (unlikely(r != 0)) {
4c788679 JG	129	if (r == -ERESTART)
4c788679 JG	130	goto retry;
771fe6b9	131	/* ttm call radeon_ttm_object_object_destroy if error happen */
4c788679 JG	132	dev_err(rdev->dev, "object_init failed for (%ld, 0x%08X)\n",
4c788679 JG	133	size, flags);
771fe6b9 JG	134	return r;
771fe6b9 JG	135	}
4c788679	136	*bo_ptr = bo;
771fe6b9	137	if (gobj) {
4c788679 JG	138	mutex_lock(&bo->rdev->gem.mutex);
	139	list_add_tail(&bo->list, &rdev->gem.objects);
	140	mutex_unlock(&bo->rdev->gem.mutex);
771fe6b9 JG	141	}
	142	return 0;
	143	}
	144
4c788679	145	int radeon_bo_kmap(struct radeon_bo bo, void *ptr)
771fe6b9	146	{
4c788679	147	bool is_iomem;
771fe6b9 JG	148	int r;
771fe6b9 JG	149
4c788679	150	if (bo->kptr) {
771fe6b9	151	if (ptr) {
4c788679	152	*ptr = bo->kptr;
771fe6b9	153	}
771fe6b9 JG	154	return 0;
771fe6b9 JG	155	}
4c788679	156	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
771fe6b9 JG	157	if (r) {
	158	return r;
	159	}
4c788679	160	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
771fe6b9	161	if (ptr) {
4c788679	162	*ptr = bo->kptr;
771fe6b9	163	}
4c788679	164	radeon_bo_check_tiling(bo, 0, 0);
771fe6b9 JG	165	return 0;
	166	}
	167
4c788679	168	void radeon_bo_kunmap(struct radeon_bo *bo)
771fe6b9	169	{
4c788679	170	if (bo->kptr == NULL)
771fe6b9	171	return;
4c788679 JG	172	bo->kptr = NULL;
	173	radeon_bo_check_tiling(bo, 0, 0);
	174	ttm_bo_kunmap(&bo->kmap);
771fe6b9 JG	175	}
771fe6b9 JG	176
4c788679	177	void radeon_bo_unref(struct radeon_bo **bo)
771fe6b9	178	{
4c788679	179	struct ttm_buffer_object *tbo;
771fe6b9	180
4c788679	181	if ((*bo) == NULL)
771fe6b9	182	return;
4c788679 JG	183	tbo = &((*bo)->tbo);
	184	ttm_bo_unref(&tbo);
	185	if (tbo == NULL)
	186	*bo = NULL;
771fe6b9 JG	187	}
771fe6b9 JG	188
4c788679	189	int radeon_bo_pin(struct radeon_bo bo, u32 domain, u64 gpu_addr)
771fe6b9	190	{
312ea8da	191	int r, i;
771fe6b9	192
312ea8da	193	radeon_ttm_placement_from_domain(bo, domain);
4c788679 JG	194	if (bo->pin_count) {
	195	bo->pin_count++;
	196	if (gpu_addr)
	197	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9 JG	198	return 0;
771fe6b9 JG	199	}
312ea8da JG	200	radeon_ttm_placement_from_domain(bo, domain);
	201	for (i = 0; i < bo->placement.num_placement; i++)
	202	bo->placements[i] \|= TTM_PL_FLAG_NO_EVICT;
4c788679	203	retry:
312ea8da	204	r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, true, false);
4c788679 JG	205	if (likely(r == 0)) {
	206	bo->pin_count = 1;
	207	if (gpu_addr != NULL)
	208	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9	209	}
771fe6b9	210	if (unlikely(r != 0)) {
4c788679 JG	211	if (r == -ERESTART)
	212	goto retry;
	213	dev_err(bo->rdev->dev, "%p pin failed\n", bo);
771fe6b9	214	}
771fe6b9 JG	215	return r;
	216	}
	217
4c788679	218	int radeon_bo_unpin(struct radeon_bo *bo)
771fe6b9	219	{
312ea8da	220	int r, i;
771fe6b9	221
4c788679 JG	222	if (!bo->pin_count) {
	223	dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
	224	return 0;
771fe6b9	225	}
4c788679 JG	226	bo->pin_count--;
	227	if (bo->pin_count)
	228	return 0;
312ea8da JG	229	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	230	bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
4c788679	231	retry:
312ea8da	232	r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, true, false);
cefb87ef	233	if (unlikely(r != 0)) {
4c788679 JG	234	if (r == -ERESTART)
	235	goto retry;
	236	dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
cefb87ef DA	237	return r;
cefb87ef DA	238	}
4c788679	239	return 0;
cefb87ef DA	240	}
cefb87ef DA	241
4c788679	242	int radeon_bo_evict_vram(struct radeon_device *rdev)
771fe6b9 JG	243	{
	244	if (rdev->flags & RADEON_IS_IGP) {
	245	/* Useless to evict on IGP chips */
	246	return 0;
	247	}
	248	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
	249	}
	250
4c788679	251	void radeon_bo_force_delete(struct radeon_device *rdev)
771fe6b9	252	{
4c788679	253	struct radeon_bo bo, n;
771fe6b9 JG	254	struct drm_gem_object *gobj;
	255
	256	if (list_empty(&rdev->gem.objects)) {
	257	return;
	258	}
4c788679 JG	259	dev_err(rdev->dev, "Userspace still has active objects !\n");
4c788679 JG	260	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
771fe6b9	261	mutex_lock(&rdev->ddev->struct_mutex);
4c788679 JG	262	gobj = bo->gobj;
	263	dev_err(rdev->dev, "%p %p %lu %lu force free\n",
	264	gobj, bo, (unsigned long)gobj->size,
	265	((unsigned long )&gobj->refcount));
	266	mutex_lock(&bo->rdev->gem.mutex);
	267	list_del_init(&bo->list);
	268	mutex_unlock(&bo->rdev->gem.mutex);
	269	radeon_bo_unref(&bo);
771fe6b9 JG	270	gobj->driver_private = NULL;
	271	drm_gem_object_unreference(gobj);
	272	mutex_unlock(&rdev->ddev->struct_mutex);
	273	}
	274	}
	275
4c788679	276	int radeon_bo_init(struct radeon_device *rdev)
771fe6b9	277	{
a4d68279 JG	278	/* Add an MTRR for the VRAM */
	279	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
	280	MTRR_TYPE_WRCOMB, 1);
	281	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
	282	rdev->mc.mc_vram_size >> 20,
	283	(unsigned long long)rdev->mc.aper_size >> 20);
	284	DRM_INFO("RAM width %dbits %cDR\n",
	285	rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
771fe6b9 JG	286	return radeon_ttm_init(rdev);
	287	}
	288
4c788679	289	void radeon_bo_fini(struct radeon_device *rdev)
771fe6b9 JG	290	{
	291	radeon_ttm_fini(rdev);
	292	}
	293
4c788679 JG	294	void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
4c788679 JG	295	struct list_head *head)
771fe6b9 JG	296	{
	297	if (lobj->wdomain) {
	298	list_add(&lobj->list, head);
	299	} else {
	300	list_add_tail(&lobj->list, head);
	301	}
	302	}
	303
4c788679	304	int radeon_bo_list_reserve(struct list_head *head)
771fe6b9	305	{
4c788679	306	struct radeon_bo_list *lobj;
771fe6b9 JG	307	int r;
771fe6b9 JG	308
9d8401fc	309	list_for_each_entry(lobj, head, list){
4c788679 JG	310	r = radeon_bo_reserve(lobj->bo, false);
	311	if (unlikely(r != 0))
	312	return r;
771fe6b9 JG	313	}
	314	return 0;
	315	}
	316
4c788679	317	void radeon_bo_list_unreserve(struct list_head *head)
771fe6b9	318	{
4c788679	319	struct radeon_bo_list *lobj;
771fe6b9	320
9d8401fc	321	list_for_each_entry(lobj, head, list) {
4c788679 JG	322	/* only unreserve object we successfully reserved */
	323	if (radeon_bo_is_reserved(lobj->bo))
	324	radeon_bo_unreserve(lobj->bo);
771fe6b9 JG	325	}
	326	}
	327
4c788679	328	int radeon_bo_list_validate(struct list_head head, void fence)
771fe6b9	329	{
4c788679 JG	330	struct radeon_bo_list *lobj;
4c788679 JG	331	struct radeon_bo *bo;
771fe6b9	332	struct radeon_fence *old_fence = NULL;
771fe6b9 JG	333	int r;
771fe6b9 JG	334
4c788679	335	r = radeon_bo_list_reserve(head);
771fe6b9	336	if (unlikely(r != 0)) {
771fe6b9 JG	337	return r;
771fe6b9 JG	338	}
9d8401fc	339	list_for_each_entry(lobj, head, list) {
4c788679 JG	340	bo = lobj->bo;
4c788679 JG	341	if (!bo->pin_count) {
664f8659	342	if (lobj->wdomain) {
312ea8da JG	343	radeon_ttm_placement_from_domain(bo,
312ea8da JG	344	lobj->wdomain);
664f8659	345	} else {
312ea8da JG	346	radeon_ttm_placement_from_domain(bo,
312ea8da JG	347	lobj->rdomain);
664f8659	348	}
4c788679 JG	349	retry:
4c788679 JG	350	r = ttm_buffer_object_validate(&bo->tbo,
312ea8da	351	&bo->placement,
4c788679	352	true, false);
771fe6b9	353	if (unlikely(r)) {
4c788679 JG	354	if (r == -ERESTART)
4c788679 JG	355	goto retry;
771fe6b9 JG	356	return r;
771fe6b9 JG	357	}
771fe6b9	358	}
4c788679 JG	359	lobj->gpu_offset = radeon_bo_gpu_offset(bo);
4c788679 JG	360	lobj->tiling_flags = bo->tiling_flags;
771fe6b9	361	if (fence) {
4c788679 JG	362	old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
	363	bo->tbo.sync_obj = radeon_fence_ref(fence);
	364	bo->tbo.sync_obj_arg = NULL;
771fe6b9 JG	365	}
	366	if (old_fence) {
	367	radeon_fence_unref(&old_fence);
	368	}
	369	}
	370	return 0;
	371	}
	372
4c788679	373	void radeon_bo_list_unvalidate(struct list_head head, void fence)
771fe6b9	374	{
4c788679 JG	375	struct radeon_bo_list *lobj;
4c788679 JG	376	struct radeon_fence *old_fence;
771fe6b9	377
4c788679 JG	378	if (fence)
	379	list_for_each_entry(lobj, head, list) {
	380	old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
	381	if (old_fence == fence) {
	382	lobj->bo->tbo.sync_obj = NULL;
	383	radeon_fence_unref(&old_fence);
	384	}
771fe6b9	385	}
4c788679	386	radeon_bo_list_unreserve(head);
771fe6b9 JG	387	}
771fe6b9 JG	388
4c788679	389	int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
771fe6b9 JG	390	struct vm_area_struct *vma)
771fe6b9 JG	391	{
4c788679	392	return ttm_fbdev_mmap(vma, &bo->tbo);
771fe6b9 JG	393	}
771fe6b9 JG	394
4c788679	395	static int radeon_bo_get_surface_reg(struct radeon_bo *bo)
771fe6b9	396	{
4c788679	397	struct radeon_device *rdev = bo->rdev;
e024e110	398	struct radeon_surface_reg *reg;
4c788679	399	struct radeon_bo *old_object;
e024e110 DA	400	int steal;
	401	int i;
	402
4c788679 JG	403	BUG_ON(!atomic_read(&bo->tbo.reserved));
	404
	405	if (!bo->tiling_flags)
e024e110 DA	406	return 0;
e024e110 DA	407
4c788679 JG	408	if (bo->surface_reg >= 0) {
	409	reg = &rdev->surface_regs[bo->surface_reg];
	410	i = bo->surface_reg;
e024e110 DA	411	goto out;
	412	}
	413
	414	steal = -1;
	415	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
	416
	417	reg = &rdev->surface_regs[i];
4c788679	418	if (!reg->bo)
e024e110 DA	419	break;
e024e110 DA	420
4c788679	421	old_object = reg->bo;
e024e110 DA	422	if (old_object->pin_count == 0)
	423	steal = i;
	424	}
	425
	426	/* if we are all out */
	427	if (i == RADEON_GEM_MAX_SURFACES) {
	428	if (steal == -1)
	429	return -ENOMEM;
	430	/* find someone with a surface reg and nuke their BO */
	431	reg = &rdev->surface_regs[steal];
4c788679	432	old_object = reg->bo;
e024e110 DA	433	/* blow away the mapping */
e024e110 DA	434	DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
4c788679	435	ttm_bo_unmap_virtual(&old_object->tbo);
e024e110 DA	436	old_object->surface_reg = -1;
	437	i = steal;
	438	}
	439
4c788679 JG	440	bo->surface_reg = i;
4c788679 JG	441	reg->bo = bo;
e024e110 DA	442
e024e110 DA	443	out:
4c788679 JG	444	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
	445	bo->tbo.mem.mm_node->start << PAGE_SHIFT,
	446	bo->tbo.num_pages << PAGE_SHIFT);
e024e110 DA	447	return 0;
	448	}
	449
4c788679	450	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
e024e110	451	{
4c788679	452	struct radeon_device *rdev = bo->rdev;
e024e110 DA	453	struct radeon_surface_reg *reg;
e024e110 DA	454
4c788679	455	if (bo->surface_reg == -1)
e024e110 DA	456	return;
e024e110 DA	457
4c788679 JG	458	reg = &rdev->surface_regs[bo->surface_reg];
4c788679 JG	459	radeon_clear_surface_reg(rdev, bo->surface_reg);
e024e110	460
4c788679 JG	461	reg->bo = NULL;
4c788679 JG	462	bo->surface_reg = -1;
e024e110 DA	463	}
e024e110 DA	464
4c788679 JG	465	int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
4c788679 JG	466	uint32_t tiling_flags, uint32_t pitch)
e024e110	467	{
4c788679 JG	468	int r;
	469
	470	r = radeon_bo_reserve(bo, false);
	471	if (unlikely(r != 0))
	472	return r;
	473	bo->tiling_flags = tiling_flags;
	474	bo->pitch = pitch;
	475	radeon_bo_unreserve(bo);
	476	return 0;
e024e110 DA	477	}
e024e110 DA	478
4c788679 JG	479	void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
	480	uint32_t *tiling_flags,
	481	uint32_t *pitch)
e024e110	482	{
4c788679	483	BUG_ON(!atomic_read(&bo->tbo.reserved));
e024e110	484	if (tiling_flags)
4c788679	485	*tiling_flags = bo->tiling_flags;
e024e110	486	if (pitch)
4c788679	487	*pitch = bo->pitch;
e024e110 DA	488	}
e024e110 DA	489
4c788679 JG	490	int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
4c788679 JG	491	bool force_drop)
e024e110	492	{
4c788679 JG	493	BUG_ON(!atomic_read(&bo->tbo.reserved));
	494
	495	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
e024e110 DA	496	return 0;
	497
	498	if (force_drop) {
4c788679	499	radeon_bo_clear_surface_reg(bo);
e024e110 DA	500	return 0;
	501	}
	502
4c788679	503	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
e024e110 DA	504	if (!has_moved)
	505	return 0;
	506
4c788679 JG	507	if (bo->surface_reg >= 0)
4c788679 JG	508	radeon_bo_clear_surface_reg(bo);
e024e110 DA	509	return 0;
	510	}
	511
4c788679	512	if ((bo->surface_reg >= 0) && !has_moved)
e024e110 DA	513	return 0;
e024e110 DA	514
4c788679	515	return radeon_bo_get_surface_reg(bo);
e024e110 DA	516	}
	517
	518	void radeon_bo_move_notify(struct ttm_buffer_object *bo,
4c788679	519	struct ttm_mem_reg *mem)
e024e110	520	{
4c788679 JG	521	struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
4c788679 JG	522	radeon_bo_check_tiling(rbo, 0, 1);
e024e110 DA	523	}
	524
	525	void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
	526	{
4c788679 JG	527	struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
4c788679 JG	528	radeon_bo_check_tiling(rbo, 0, 0);
e024e110	529	}