]>
Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <linux/list.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
771fe6b9 | 34 | #include <drm/drmP.h> |
760285e7 | 35 | #include <drm/radeon_drm.h> |
c5244987 | 36 | #include <drm/drm_cache.h> |
771fe6b9 | 37 | #include "radeon.h" |
99ee7fac | 38 | #include "radeon_trace.h" |
771fe6b9 | 39 | |
771fe6b9 JG |
40 | |
41 | int radeon_ttm_init(struct radeon_device *rdev); | |
42 | void radeon_ttm_fini(struct radeon_device *rdev); | |
4c788679 | 43 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
771fe6b9 JG |
44 | |
45 | /* | |
46 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all | |
47 | * function are calling it. | |
48 | */ | |
49 | ||
67e8e3f9 MO |
50 | static void radeon_update_memory_usage(struct radeon_bo *bo, |
51 | unsigned mem_type, int sign) | |
52 | { | |
53 | struct radeon_device *rdev = bo->rdev; | |
54 | u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; | |
55 | ||
56 | switch (mem_type) { | |
57 | case TTM_PL_TT: | |
58 | if (sign > 0) | |
59 | atomic64_add(size, &rdev->gtt_usage); | |
60 | else | |
61 | atomic64_sub(size, &rdev->gtt_usage); | |
62 | break; | |
63 | case TTM_PL_VRAM: | |
64 | if (sign > 0) | |
65 | atomic64_add(size, &rdev->vram_usage); | |
66 | else | |
67 | atomic64_sub(size, &rdev->vram_usage); | |
68 | break; | |
69 | } | |
70 | } | |
71 | ||
4c788679 | 72 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
771fe6b9 | 73 | { |
4c788679 | 74 | struct radeon_bo *bo; |
771fe6b9 | 75 | |
4c788679 | 76 | bo = container_of(tbo, struct radeon_bo, tbo); |
67e8e3f9 MO |
77 | |
78 | radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); | |
79 | ||
4c788679 JG |
80 | mutex_lock(&bo->rdev->gem.mutex); |
81 | list_del_init(&bo->list); | |
82 | mutex_unlock(&bo->rdev->gem.mutex); | |
83 | radeon_bo_clear_surface_reg(bo); | |
c265f24d | 84 | WARN_ON(!list_empty(&bo->va)); |
441921d5 | 85 | drm_gem_object_release(&bo->gem_base); |
4c788679 | 86 | kfree(bo); |
771fe6b9 JG |
87 | } |
88 | ||
d03d8589 JG |
89 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
90 | { | |
91 | if (bo->destroy == &radeon_ttm_bo_destroy) | |
92 | return true; | |
93 | return false; | |
94 | } | |
95 | ||
312ea8da JG |
96 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
97 | { | |
deadcb36 | 98 | u32 c = 0, i; |
312ea8da | 99 | |
312ea8da | 100 | rbo->placement.placement = rbo->placements; |
20707874 | 101 | rbo->placement.busy_placement = rbo->placements; |
c9da4a4b MD |
102 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
103 | /* Try placing BOs which don't need CPU access outside of the | |
104 | * CPU accessible part of VRAM | |
105 | */ | |
106 | if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && | |
107 | rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { | |
108 | rbo->placements[c].fpfn = | |
109 | rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
110 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | | |
111 | TTM_PL_FLAG_UNCACHED | | |
112 | TTM_PL_FLAG_VRAM; | |
113 | } | |
114 | ||
115 | rbo->placements[c].fpfn = 0; | |
f1217ed0 CK |
116 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
117 | TTM_PL_FLAG_UNCACHED | | |
118 | TTM_PL_FLAG_VRAM; | |
c9da4a4b | 119 | } |
f1217ed0 | 120 | |
0d0b3e74 | 121 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
02376d82 | 122 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
c9da4a4b | 123 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
124 | rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | |
125 | TTM_PL_FLAG_TT; | |
126 | ||
02376d82 MD |
127 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
128 | (rbo->rdev->flags & RADEON_IS_AGP)) { | |
c9da4a4b | 129 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
130 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
131 | TTM_PL_FLAG_UNCACHED | | |
02376d82 | 132 | TTM_PL_FLAG_TT; |
0d0b3e74 | 133 | } else { |
c9da4a4b | 134 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
135 | rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | |
136 | TTM_PL_FLAG_TT; | |
0d0b3e74 JG |
137 | } |
138 | } | |
f1217ed0 | 139 | |
0d0b3e74 | 140 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
02376d82 | 141 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
c9da4a4b | 142 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
143 | rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | |
144 | TTM_PL_FLAG_SYSTEM; | |
145 | ||
02376d82 MD |
146 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
147 | rbo->rdev->flags & RADEON_IS_AGP) { | |
c9da4a4b | 148 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
149 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
150 | TTM_PL_FLAG_UNCACHED | | |
02376d82 | 151 | TTM_PL_FLAG_SYSTEM; |
0d0b3e74 | 152 | } else { |
c9da4a4b | 153 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
154 | rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | |
155 | TTM_PL_FLAG_SYSTEM; | |
0d0b3e74 JG |
156 | } |
157 | } | |
c9da4a4b MD |
158 | if (!c) { |
159 | rbo->placements[c].fpfn = 0; | |
f1217ed0 CK |
160 | rbo->placements[c++].flags = TTM_PL_MASK_CACHING | |
161 | TTM_PL_FLAG_SYSTEM; | |
c9da4a4b | 162 | } |
f1217ed0 | 163 | |
312ea8da JG |
164 | rbo->placement.num_placement = c; |
165 | rbo->placement.num_busy_placement = c; | |
deadcb36 | 166 | |
f1217ed0 | 167 | for (i = 0; i < c; ++i) { |
c8584039 | 168 | if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && |
c9da4a4b MD |
169 | (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && |
170 | !rbo->placements[i].fpfn) | |
c8584039 MD |
171 | rbo->placements[i].lpfn = |
172 | rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
173 | else | |
174 | rbo->placements[i].lpfn = 0; | |
f1217ed0 | 175 | } |
312ea8da JG |
176 | } |
177 | ||
441921d5 | 178 | int radeon_bo_create(struct radeon_device *rdev, |
831b6966 ML |
179 | unsigned long size, int byte_align, bool kernel, |
180 | u32 domain, u32 flags, struct sg_table *sg, | |
181 | struct reservation_object *resv, | |
182 | struct radeon_bo **bo_ptr) | |
771fe6b9 | 183 | { |
4c788679 | 184 | struct radeon_bo *bo; |
771fe6b9 | 185 | enum ttm_bo_type type; |
93225b0d | 186 | unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; |
57de4ba9 | 187 | size_t acc_size; |
771fe6b9 JG |
188 | int r; |
189 | ||
441921d5 DV |
190 | size = ALIGN(size, PAGE_SIZE); |
191 | ||
771fe6b9 JG |
192 | if (kernel) { |
193 | type = ttm_bo_type_kernel; | |
40f5cf99 AD |
194 | } else if (sg) { |
195 | type = ttm_bo_type_sg; | |
771fe6b9 JG |
196 | } else { |
197 | type = ttm_bo_type_device; | |
198 | } | |
4c788679 | 199 | *bo_ptr = NULL; |
2b66b50b | 200 | |
57de4ba9 JG |
201 | acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, |
202 | sizeof(struct radeon_bo)); | |
203 | ||
4c788679 JG |
204 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
205 | if (bo == NULL) | |
771fe6b9 | 206 | return -ENOMEM; |
441921d5 DV |
207 | r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); |
208 | if (unlikely(r)) { | |
209 | kfree(bo); | |
210 | return r; | |
211 | } | |
4c788679 | 212 | bo->rdev = rdev; |
4c788679 JG |
213 | bo->surface_reg = -1; |
214 | INIT_LIST_HEAD(&bo->list); | |
721604a1 | 215 | INIT_LIST_HEAD(&bo->va); |
bda72d58 | 216 | bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | |
3cf8bb1a JG |
217 | RADEON_GEM_DOMAIN_GTT | |
218 | RADEON_GEM_DOMAIN_CPU); | |
02376d82 MD |
219 | |
220 | bo->flags = flags; | |
221 | /* PCI GART is always snooped */ | |
222 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
223 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); | |
224 | ||
96ea47c0 MD |
225 | /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx |
226 | * See https://bugs.freedesktop.org/show_bug.cgi?id=91268 | |
227 | */ | |
228 | if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635) | |
229 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); | |
230 | ||
a08b588e MD |
231 | #ifdef CONFIG_X86_32 |
232 | /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit | |
233 | * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 | |
234 | */ | |
a28bbd58 | 235 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
a53fa438 MD |
236 | #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) |
237 | /* Don't try to enable write-combining when it can't work, or things | |
238 | * may be slow | |
239 | * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 | |
240 | */ | |
241 | ||
242 | #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ | |
243 | thanks to write-combining | |
244 | ||
93820498 MD |
245 | if (bo->flags & RADEON_GEM_GTT_WC) |
246 | DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " | |
247 | "better performance thanks to write-combining\n"); | |
a28bbd58 | 248 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
c5244987 OG |
249 | #else |
250 | /* For architectures that don't support WC memory, | |
251 | * mask out the WC flag from the BO | |
252 | */ | |
253 | if (!drm_arch_can_wc_memory()) | |
254 | bo->flags &= ~RADEON_GEM_GTT_WC; | |
a08b588e MD |
255 | #endif |
256 | ||
1fb107fc | 257 | radeon_ttm_placement_from_domain(bo, domain); |
5cc6fbab | 258 | /* Kernel allocation are uninterruptible */ |
db7fce39 | 259 | down_read(&rdev->pm.mclk_lock); |
1fb107fc | 260 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
0b91c4a1 | 261 | &bo->placement, page_align, !kernel, NULL, |
831b6966 | 262 | acc_size, sg, resv, &radeon_ttm_bo_destroy); |
db7fce39 | 263 | up_read(&rdev->pm.mclk_lock); |
771fe6b9 | 264 | if (unlikely(r != 0)) { |
771fe6b9 JG |
265 | return r; |
266 | } | |
4c788679 | 267 | *bo_ptr = bo; |
441921d5 | 268 | |
99ee7fac | 269 | trace_radeon_bo_create(bo); |
441921d5 | 270 | |
771fe6b9 JG |
271 | return 0; |
272 | } | |
273 | ||
4c788679 | 274 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
771fe6b9 | 275 | { |
4c788679 | 276 | bool is_iomem; |
771fe6b9 JG |
277 | int r; |
278 | ||
4c788679 | 279 | if (bo->kptr) { |
771fe6b9 | 280 | if (ptr) { |
4c788679 | 281 | *ptr = bo->kptr; |
771fe6b9 | 282 | } |
771fe6b9 JG |
283 | return 0; |
284 | } | |
4c788679 | 285 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
771fe6b9 JG |
286 | if (r) { |
287 | return r; | |
288 | } | |
4c788679 | 289 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
771fe6b9 | 290 | if (ptr) { |
4c788679 | 291 | *ptr = bo->kptr; |
771fe6b9 | 292 | } |
4c788679 | 293 | radeon_bo_check_tiling(bo, 0, 0); |
771fe6b9 JG |
294 | return 0; |
295 | } | |
296 | ||
4c788679 | 297 | void radeon_bo_kunmap(struct radeon_bo *bo) |
771fe6b9 | 298 | { |
4c788679 | 299 | if (bo->kptr == NULL) |
771fe6b9 | 300 | return; |
4c788679 JG |
301 | bo->kptr = NULL; |
302 | radeon_bo_check_tiling(bo, 0, 0); | |
303 | ttm_bo_kunmap(&bo->kmap); | |
771fe6b9 JG |
304 | } |
305 | ||
512d8afc CK |
306 | struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) |
307 | { | |
308 | if (bo == NULL) | |
309 | return NULL; | |
310 | ||
311 | ttm_bo_reference(&bo->tbo); | |
312 | return bo; | |
313 | } | |
314 | ||
4c788679 | 315 | void radeon_bo_unref(struct radeon_bo **bo) |
771fe6b9 | 316 | { |
4c788679 | 317 | struct ttm_buffer_object *tbo; |
f4b7fb94 | 318 | struct radeon_device *rdev; |
771fe6b9 | 319 | |
4c788679 | 320 | if ((*bo) == NULL) |
771fe6b9 | 321 | return; |
f4b7fb94 | 322 | rdev = (*bo)->rdev; |
4c788679 JG |
323 | tbo = &((*bo)->tbo); |
324 | ttm_bo_unref(&tbo); | |
325 | if (tbo == NULL) | |
326 | *bo = NULL; | |
771fe6b9 JG |
327 | } |
328 | ||
c4353016 MD |
329 | int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, |
330 | u64 *gpu_addr) | |
771fe6b9 | 331 | { |
312ea8da | 332 | int r, i; |
771fe6b9 | 333 | |
f72a113a CK |
334 | if (radeon_ttm_tt_has_userptr(bo->tbo.ttm)) |
335 | return -EPERM; | |
336 | ||
4c788679 JG |
337 | if (bo->pin_count) { |
338 | bo->pin_count++; | |
339 | if (gpu_addr) | |
340 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
d936622c MD |
341 | |
342 | if (max_offset != 0) { | |
343 | u64 domain_start; | |
344 | ||
345 | if (domain == RADEON_GEM_DOMAIN_VRAM) | |
346 | domain_start = bo->rdev->mc.vram_start; | |
347 | else | |
348 | domain_start = bo->rdev->mc.gtt_start; | |
e199fd42 MD |
349 | WARN_ON_ONCE(max_offset < |
350 | (radeon_bo_gpu_offset(bo) - domain_start)); | |
d936622c MD |
351 | } |
352 | ||
771fe6b9 JG |
353 | return 0; |
354 | } | |
312ea8da | 355 | radeon_ttm_placement_from_domain(bo, domain); |
f1217ed0 | 356 | for (i = 0; i < bo->placement.num_placement; i++) { |
3ca82da3 | 357 | /* force to pin into visible video ram */ |
b76ee67a | 358 | if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && |
f266f04d | 359 | !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && |
b76ee67a MD |
360 | (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) |
361 | bo->placements[i].lpfn = | |
362 | bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
f1217ed0 | 363 | else |
b76ee67a | 364 | bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; |
c4353016 | 365 | |
f1217ed0 | 366 | bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; |
c4353016 | 367 | } |
f1217ed0 | 368 | |
97a875cb | 369 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
4c788679 JG |
370 | if (likely(r == 0)) { |
371 | bo->pin_count = 1; | |
372 | if (gpu_addr != NULL) | |
373 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
71ecc97e AD |
374 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
375 | bo->rdev->vram_pin_size += radeon_bo_size(bo); | |
376 | else | |
377 | bo->rdev->gart_pin_size += radeon_bo_size(bo); | |
378 | } else { | |
4c788679 | 379 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
71ecc97e | 380 | } |
771fe6b9 JG |
381 | return r; |
382 | } | |
c4353016 MD |
383 | |
384 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) | |
385 | { | |
386 | return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); | |
387 | } | |
771fe6b9 | 388 | |
4c788679 | 389 | int radeon_bo_unpin(struct radeon_bo *bo) |
771fe6b9 | 390 | { |
312ea8da | 391 | int r, i; |
771fe6b9 | 392 | |
4c788679 JG |
393 | if (!bo->pin_count) { |
394 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); | |
395 | return 0; | |
771fe6b9 | 396 | } |
4c788679 JG |
397 | bo->pin_count--; |
398 | if (bo->pin_count) | |
399 | return 0; | |
f1217ed0 CK |
400 | for (i = 0; i < bo->placement.num_placement; i++) { |
401 | bo->placements[i].lpfn = 0; | |
402 | bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; | |
403 | } | |
97a875cb | 404 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
71ecc97e AD |
405 | if (likely(r == 0)) { |
406 | if (bo->tbo.mem.mem_type == TTM_PL_VRAM) | |
407 | bo->rdev->vram_pin_size -= radeon_bo_size(bo); | |
408 | else | |
409 | bo->rdev->gart_pin_size -= radeon_bo_size(bo); | |
410 | } else { | |
4c788679 | 411 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
71ecc97e | 412 | } |
5cc6fbab | 413 | return r; |
cefb87ef DA |
414 | } |
415 | ||
4c788679 | 416 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
771fe6b9 | 417 | { |
d796d844 DA |
418 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
419 | if (0 && (rdev->flags & RADEON_IS_IGP)) { | |
06b6476d AD |
420 | if (rdev->mc.igp_sideport_enabled == false) |
421 | /* Useless to evict on IGP chips */ | |
422 | return 0; | |
771fe6b9 JG |
423 | } |
424 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
425 | } | |
426 | ||
4c788679 | 427 | void radeon_bo_force_delete(struct radeon_device *rdev) |
771fe6b9 | 428 | { |
4c788679 | 429 | struct radeon_bo *bo, *n; |
771fe6b9 JG |
430 | |
431 | if (list_empty(&rdev->gem.objects)) { | |
432 | return; | |
433 | } | |
4c788679 JG |
434 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
435 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
4c788679 | 436 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", |
31c3603d DV |
437 | &bo->gem_base, bo, (unsigned long)bo->gem_base.size, |
438 | *((unsigned long *)&bo->gem_base.refcount)); | |
4c788679 JG |
439 | mutex_lock(&bo->rdev->gem.mutex); |
440 | list_del_init(&bo->list); | |
441 | mutex_unlock(&bo->rdev->gem.mutex); | |
91132d6b | 442 | /* this should unref the ttm bo */ |
42192a94 | 443 | drm_gem_object_unreference_unlocked(&bo->gem_base); |
771fe6b9 JG |
444 | } |
445 | } | |
446 | ||
4c788679 | 447 | int radeon_bo_init(struct radeon_device *rdev) |
771fe6b9 | 448 | { |
a4d68279 | 449 | /* Add an MTRR for the VRAM */ |
a0a53aa8 | 450 | if (!rdev->fastfb_working) { |
07ebea25 AL |
451 | rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, |
452 | rdev->mc.aper_size); | |
a0a53aa8 | 453 | } |
a4d68279 JG |
454 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
455 | rdev->mc.mc_vram_size >> 20, | |
456 | (unsigned long long)rdev->mc.aper_size >> 20); | |
457 | DRM_INFO("RAM width %dbits %cDR\n", | |
458 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | |
771fe6b9 JG |
459 | return radeon_ttm_init(rdev); |
460 | } | |
461 | ||
4c788679 | 462 | void radeon_bo_fini(struct radeon_device *rdev) |
771fe6b9 JG |
463 | { |
464 | radeon_ttm_fini(rdev); | |
07ebea25 | 465 | arch_phys_wc_del(rdev->mc.vram_mtrr); |
771fe6b9 JG |
466 | } |
467 | ||
19dff56a MO |
468 | /* Returns how many bytes TTM can move per IB. |
469 | */ | |
470 | static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) | |
471 | { | |
472 | u64 real_vram_size = rdev->mc.real_vram_size; | |
473 | u64 vram_usage = atomic64_read(&rdev->vram_usage); | |
474 | ||
475 | /* This function is based on the current VRAM usage. | |
476 | * | |
477 | * - If all of VRAM is free, allow relocating the number of bytes that | |
478 | * is equal to 1/4 of the size of VRAM for this IB. | |
479 | ||
480 | * - If more than one half of VRAM is occupied, only allow relocating | |
481 | * 1 MB of data for this IB. | |
482 | * | |
483 | * - From 0 to one half of used VRAM, the threshold decreases | |
484 | * linearly. | |
485 | * __________________ | |
486 | * 1/4 of -|\ | | |
487 | * VRAM | \ | | |
488 | * | \ | | |
489 | * | \ | | |
490 | * | \ | | |
491 | * | \ | | |
492 | * | \ | | |
493 | * | \________|1 MB | |
494 | * |----------------| | |
495 | * VRAM 0 % 100 % | |
496 | * used used | |
497 | * | |
498 | * Note: It's a threshold, not a limit. The threshold must be crossed | |
499 | * for buffer relocations to stop, so any buffer of an arbitrary size | |
500 | * can be moved as long as the threshold isn't crossed before | |
501 | * the relocation takes place. We don't want to disable buffer | |
502 | * relocations completely. | |
503 | * | |
504 | * The idea is that buffers should be placed in VRAM at creation time | |
505 | * and TTM should only do a minimum number of relocations during | |
506 | * command submission. In practice, you need to submit at least | |
507 | * a dozen IBs to move all buffers to VRAM if they are in GTT. | |
508 | * | |
509 | * Also, things can get pretty crazy under memory pressure and actual | |
510 | * VRAM usage can change a lot, so playing safe even at 50% does | |
511 | * consistently increase performance. | |
512 | */ | |
513 | ||
514 | u64 half_vram = real_vram_size >> 1; | |
515 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; | |
516 | u64 bytes_moved_threshold = half_free_vram >> 1; | |
517 | return max(bytes_moved_threshold, 1024*1024ull); | |
518 | } | |
519 | ||
520 | int radeon_bo_list_validate(struct radeon_device *rdev, | |
521 | struct ww_acquire_ctx *ticket, | |
ecff665f | 522 | struct list_head *head, int ring) |
771fe6b9 | 523 | { |
1d0c0942 | 524 | struct radeon_bo_list *lobj; |
466be338 | 525 | struct list_head duplicates; |
771fe6b9 | 526 | int r; |
19dff56a MO |
527 | u64 bytes_moved = 0, initial_bytes_moved; |
528 | u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); | |
771fe6b9 | 529 | |
466be338 CK |
530 | INIT_LIST_HEAD(&duplicates); |
531 | r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); | |
771fe6b9 | 532 | if (unlikely(r != 0)) { |
771fe6b9 JG |
533 | return r; |
534 | } | |
19dff56a | 535 | |
147666fb | 536 | list_for_each_entry(lobj, head, tv.head) { |
466be338 | 537 | struct radeon_bo *bo = lobj->robj; |
4c788679 | 538 | if (!bo->pin_count) { |
ce6758c8 | 539 | u32 domain = lobj->prefered_domains; |
3852752c | 540 | u32 allowed = lobj->allowed_domains; |
19dff56a MO |
541 | u32 current_domain = |
542 | radeon_mem_type_to_domain(bo->tbo.mem.mem_type); | |
543 | ||
544 | /* Check if this buffer will be moved and don't move it | |
545 | * if we have moved too many buffers for this IB already. | |
546 | * | |
547 | * Note that this allows moving at least one buffer of | |
548 | * any size, because it doesn't take the current "bo" | |
549 | * into account. We don't want to disallow buffer moves | |
550 | * completely. | |
551 | */ | |
3852752c | 552 | if ((allowed & current_domain) != 0 && |
19dff56a MO |
553 | (domain & current_domain) == 0 && /* will be moved */ |
554 | bytes_moved > bytes_moved_threshold) { | |
555 | /* don't move it */ | |
556 | domain = current_domain; | |
557 | } | |
558 | ||
20707874 AD |
559 | retry: |
560 | radeon_ttm_placement_from_domain(bo, domain); | |
f2ba57b5 | 561 | if (ring == R600_RING_TYPE_UVD_INDEX) |
3852752c | 562 | radeon_uvd_force_into_uvd_segment(bo, allowed); |
19dff56a MO |
563 | |
564 | initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); | |
565 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
566 | bytes_moved += atomic64_read(&rdev->num_bytes_moved) - | |
567 | initial_bytes_moved; | |
568 | ||
e376573f | 569 | if (unlikely(r)) { |
ce6758c8 CK |
570 | if (r != -ERESTARTSYS && |
571 | domain != lobj->allowed_domains) { | |
572 | domain = lobj->allowed_domains; | |
20707874 AD |
573 | goto retry; |
574 | } | |
1b6e5fd5 | 575 | ttm_eu_backoff_reservation(ticket, head); |
771fe6b9 | 576 | return r; |
e376573f | 577 | } |
771fe6b9 | 578 | } |
4c788679 JG |
579 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
580 | lobj->tiling_flags = bo->tiling_flags; | |
771fe6b9 | 581 | } |
466be338 CK |
582 | |
583 | list_for_each_entry(lobj, &duplicates, tv.head) { | |
584 | lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); | |
585 | lobj->tiling_flags = lobj->robj->tiling_flags; | |
586 | } | |
587 | ||
771fe6b9 JG |
588 | return 0; |
589 | } | |
590 | ||
550e2d92 | 591 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
771fe6b9 | 592 | { |
4c788679 | 593 | struct radeon_device *rdev = bo->rdev; |
e024e110 | 594 | struct radeon_surface_reg *reg; |
4c788679 | 595 | struct radeon_bo *old_object; |
e024e110 DA |
596 | int steal; |
597 | int i; | |
598 | ||
977c38d5 | 599 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
4c788679 JG |
600 | |
601 | if (!bo->tiling_flags) | |
e024e110 DA |
602 | return 0; |
603 | ||
4c788679 JG |
604 | if (bo->surface_reg >= 0) { |
605 | reg = &rdev->surface_regs[bo->surface_reg]; | |
606 | i = bo->surface_reg; | |
e024e110 DA |
607 | goto out; |
608 | } | |
609 | ||
610 | steal = -1; | |
611 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { | |
612 | ||
613 | reg = &rdev->surface_regs[i]; | |
4c788679 | 614 | if (!reg->bo) |
e024e110 DA |
615 | break; |
616 | ||
4c788679 | 617 | old_object = reg->bo; |
e024e110 DA |
618 | if (old_object->pin_count == 0) |
619 | steal = i; | |
620 | } | |
621 | ||
622 | /* if we are all out */ | |
623 | if (i == RADEON_GEM_MAX_SURFACES) { | |
624 | if (steal == -1) | |
625 | return -ENOMEM; | |
626 | /* find someone with a surface reg and nuke their BO */ | |
627 | reg = &rdev->surface_regs[steal]; | |
4c788679 | 628 | old_object = reg->bo; |
e024e110 DA |
629 | /* blow away the mapping */ |
630 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); | |
4c788679 | 631 | ttm_bo_unmap_virtual(&old_object->tbo); |
e024e110 DA |
632 | old_object->surface_reg = -1; |
633 | i = steal; | |
634 | } | |
635 | ||
4c788679 JG |
636 | bo->surface_reg = i; |
637 | reg->bo = bo; | |
e024e110 DA |
638 | |
639 | out: | |
4c788679 | 640 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
d961db75 | 641 | bo->tbo.mem.start << PAGE_SHIFT, |
4c788679 | 642 | bo->tbo.num_pages << PAGE_SHIFT); |
e024e110 DA |
643 | return 0; |
644 | } | |
645 | ||
4c788679 | 646 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
e024e110 | 647 | { |
4c788679 | 648 | struct radeon_device *rdev = bo->rdev; |
e024e110 DA |
649 | struct radeon_surface_reg *reg; |
650 | ||
4c788679 | 651 | if (bo->surface_reg == -1) |
e024e110 DA |
652 | return; |
653 | ||
4c788679 JG |
654 | reg = &rdev->surface_regs[bo->surface_reg]; |
655 | radeon_clear_surface_reg(rdev, bo->surface_reg); | |
e024e110 | 656 | |
4c788679 JG |
657 | reg->bo = NULL; |
658 | bo->surface_reg = -1; | |
e024e110 DA |
659 | } |
660 | ||
4c788679 JG |
661 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
662 | uint32_t tiling_flags, uint32_t pitch) | |
e024e110 | 663 | { |
285484e2 | 664 | struct radeon_device *rdev = bo->rdev; |
4c788679 JG |
665 | int r; |
666 | ||
285484e2 JG |
667 | if (rdev->family >= CHIP_CEDAR) { |
668 | unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; | |
669 | ||
670 | bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; | |
671 | bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; | |
672 | mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; | |
673 | tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; | |
674 | stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; | |
675 | switch (bankw) { | |
676 | case 0: | |
677 | case 1: | |
678 | case 2: | |
679 | case 4: | |
680 | case 8: | |
681 | break; | |
682 | default: | |
683 | return -EINVAL; | |
684 | } | |
685 | switch (bankh) { | |
686 | case 0: | |
687 | case 1: | |
688 | case 2: | |
689 | case 4: | |
690 | case 8: | |
691 | break; | |
692 | default: | |
693 | return -EINVAL; | |
694 | } | |
695 | switch (mtaspect) { | |
696 | case 0: | |
697 | case 1: | |
698 | case 2: | |
699 | case 4: | |
700 | case 8: | |
701 | break; | |
702 | default: | |
703 | return -EINVAL; | |
704 | } | |
705 | if (tilesplit > 6) { | |
706 | return -EINVAL; | |
707 | } | |
708 | if (stilesplit > 6) { | |
709 | return -EINVAL; | |
710 | } | |
711 | } | |
4c788679 JG |
712 | r = radeon_bo_reserve(bo, false); |
713 | if (unlikely(r != 0)) | |
714 | return r; | |
715 | bo->tiling_flags = tiling_flags; | |
716 | bo->pitch = pitch; | |
717 | radeon_bo_unreserve(bo); | |
718 | return 0; | |
e024e110 DA |
719 | } |
720 | ||
4c788679 JG |
721 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
722 | uint32_t *tiling_flags, | |
723 | uint32_t *pitch) | |
e024e110 | 724 | { |
977c38d5 ML |
725 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
726 | ||
e024e110 | 727 | if (tiling_flags) |
4c788679 | 728 | *tiling_flags = bo->tiling_flags; |
e024e110 | 729 | if (pitch) |
4c788679 | 730 | *pitch = bo->pitch; |
e024e110 DA |
731 | } |
732 | ||
4c788679 JG |
733 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
734 | bool force_drop) | |
e024e110 | 735 | { |
977c38d5 ML |
736 | if (!force_drop) |
737 | lockdep_assert_held(&bo->tbo.resv->lock.base); | |
4c788679 JG |
738 | |
739 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) | |
e024e110 DA |
740 | return 0; |
741 | ||
742 | if (force_drop) { | |
4c788679 | 743 | radeon_bo_clear_surface_reg(bo); |
e024e110 DA |
744 | return 0; |
745 | } | |
746 | ||
4c788679 | 747 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
e024e110 DA |
748 | if (!has_moved) |
749 | return 0; | |
750 | ||
4c788679 JG |
751 | if (bo->surface_reg >= 0) |
752 | radeon_bo_clear_surface_reg(bo); | |
e024e110 DA |
753 | return 0; |
754 | } | |
755 | ||
4c788679 | 756 | if ((bo->surface_reg >= 0) && !has_moved) |
e024e110 DA |
757 | return 0; |
758 | ||
4c788679 | 759 | return radeon_bo_get_surface_reg(bo); |
e024e110 DA |
760 | } |
761 | ||
762 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | |
67e8e3f9 | 763 | struct ttm_mem_reg *new_mem) |
e024e110 | 764 | { |
d03d8589 | 765 | struct radeon_bo *rbo; |
67e8e3f9 | 766 | |
d03d8589 JG |
767 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
768 | return; | |
67e8e3f9 | 769 | |
d03d8589 | 770 | rbo = container_of(bo, struct radeon_bo, tbo); |
4c788679 | 771 | radeon_bo_check_tiling(rbo, 0, 1); |
721604a1 | 772 | radeon_vm_bo_invalidate(rbo->rdev, rbo); |
67e8e3f9 MO |
773 | |
774 | /* update statistics */ | |
775 | if (!new_mem) | |
776 | return; | |
777 | ||
778 | radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); | |
779 | radeon_update_memory_usage(rbo, new_mem->mem_type, 1); | |
e024e110 DA |
780 | } |
781 | ||
0a2d50e3 | 782 | int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
e024e110 | 783 | { |
0a2d50e3 | 784 | struct radeon_device *rdev; |
d03d8589 | 785 | struct radeon_bo *rbo; |
c9da4a4b MD |
786 | unsigned long offset, size, lpfn; |
787 | int i, r; | |
0a2d50e3 | 788 | |
d03d8589 | 789 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
0a2d50e3 | 790 | return 0; |
d03d8589 | 791 | rbo = container_of(bo, struct radeon_bo, tbo); |
4c788679 | 792 | radeon_bo_check_tiling(rbo, 0, 0); |
0a2d50e3 | 793 | rdev = rbo->rdev; |
54409259 CK |
794 | if (bo->mem.mem_type != TTM_PL_VRAM) |
795 | return 0; | |
796 | ||
797 | size = bo->mem.num_pages << PAGE_SHIFT; | |
798 | offset = bo->mem.start << PAGE_SHIFT; | |
799 | if ((offset + size) <= rdev->mc.visible_vram_size) | |
800 | return 0; | |
801 | ||
e1a575ad MD |
802 | /* Can't move a pinned BO to visible VRAM */ |
803 | if (rbo->pin_count > 0) | |
804 | return -EINVAL; | |
805 | ||
54409259 CK |
806 | /* hurrah the memory is not visible ! */ |
807 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); | |
c9da4a4b MD |
808 | lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; |
809 | for (i = 0; i < rbo->placement.num_placement; i++) { | |
810 | /* Force into visible VRAM */ | |
811 | if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && | |
812 | (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) | |
813 | rbo->placements[i].lpfn = lpfn; | |
814 | } | |
54409259 CK |
815 | r = ttm_bo_validate(bo, &rbo->placement, false, false); |
816 | if (unlikely(r == -ENOMEM)) { | |
817 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); | |
818 | return ttm_bo_validate(bo, &rbo->placement, false, false); | |
819 | } else if (unlikely(r != 0)) { | |
820 | return r; | |
0a2d50e3 | 821 | } |
54409259 CK |
822 | |
823 | offset = bo->mem.start << PAGE_SHIFT; | |
824 | /* this should never happen */ | |
825 | if ((offset + size) > rdev->mc.visible_vram_size) | |
826 | return -EINVAL; | |
827 | ||
0a2d50e3 | 828 | return 0; |
e024e110 | 829 | } |
ce580fab | 830 | |
83f30d0e | 831 | int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) |
ce580fab AK |
832 | { |
833 | int r; | |
834 | ||
dfd5e50e | 835 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL); |
ce580fab AK |
836 | if (unlikely(r != 0)) |
837 | return r; | |
ce580fab AK |
838 | if (mem_type) |
839 | *mem_type = bo->tbo.mem.mem_type; | |
f2c24b83 ML |
840 | |
841 | r = ttm_bo_wait(&bo->tbo, true, true, no_wait); | |
ce580fab AK |
842 | ttm_bo_unreserve(&bo->tbo); |
843 | return r; | |
844 | } | |
587cdda8 CK |
845 | |
846 | /** | |
847 | * radeon_bo_fence - add fence to buffer object | |
848 | * | |
849 | * @bo: buffer object in question | |
850 | * @fence: fence to add | |
851 | * @shared: true if fence should be added shared | |
852 | * | |
853 | */ | |
854 | void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, | |
3cf8bb1a | 855 | bool shared) |
587cdda8 CK |
856 | { |
857 | struct reservation_object *resv = bo->tbo.resv; | |
858 | ||
859 | if (shared) | |
860 | reservation_object_add_shared_fence(resv, &fence->base); | |
861 | else | |
862 | reservation_object_add_excl_fence(resv, &fence->base); | |
863 | } |