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drm/radeon/kms: add common r600 dpm functions
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370 27#include <linux/power_supply.h>
21a8122a
AD		 28#include <linux/hwmon.h>
29#include <linux/hwmon-sysfs.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 34
f712d0c7 35static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 36 "",
f712d0c7
RM		 37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41};
42
ce8f5370 43static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 44static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 45static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47static void radeon_pm_update_profile(struct radeon_device *rdev);
48static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
a4c9e2ee
AD		 50int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53{
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66}
67
c4917074 68void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 69{
c4917074
AD		 70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71 if (rdev->pm.profile == PM_PROFILE_AUTO) {
72 mutex_lock(&rdev->pm.mutex);
73 radeon_pm_update_profile(rdev);
74 radeon_pm_set_clocks(rdev);
75 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 76 }
77 }
ce8f5370 78}
ce8f5370
AD		 79
80static void radeon_pm_update_profile(struct radeon_device *rdev)
81{
82 switch (rdev->pm.profile) {
83 case PM_PROFILE_DEFAULT:
84 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
85 break;
86 case PM_PROFILE_AUTO:
87 if (power_supply_is_system_supplied() > 0) {
88 if (rdev->pm.active_crtc_count > 1)
89 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
90 else
91 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
92 } else {
93 if (rdev->pm.active_crtc_count > 1)
c9e75b21 94 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 95 else
c9e75b21 96 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 97 }
98 break;
99 case PM_PROFILE_LOW:
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
104 break;
c9e75b21
AD		 105 case PM_PROFILE_MID:
106 if (rdev->pm.active_crtc_count > 1)
107 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
108 else
109 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
110 break;
ce8f5370
AD		 111 case PM_PROFILE_HIGH:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
116 break;
117 }
118
119 if (rdev->pm.active_crtc_count == 0) {
120 rdev->pm.requested_power_state_index =
121 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
122 rdev->pm.requested_clock_mode_index =
123 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
124 } else {
125 rdev->pm.requested_power_state_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
127 rdev->pm.requested_clock_mode_index =
128 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
129 }
130}
c913e23a 131
5876dd24
MG		 132static void radeon_unmap_vram_bos(struct radeon_device *rdev)
133{
134 struct radeon_bo *bo, *n;
135
136 if (list_empty(&rdev->gem.objects))
137 return;
138
139 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
140 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
141 ttm_bo_unmap_virtual(&bo->tbo);
142 }
5876dd24
MG		 143}
144
ce8f5370 145static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 146{
ce8f5370
AD		 147 if (rdev->pm.active_crtcs) {
148 rdev->pm.vblank_sync = false;
149 wait_event_timeout(
150 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
152 }
153}
154
155static void radeon_set_power_state(struct radeon_device *rdev)
156{
157 u32 sclk, mclk;
92645879 158 bool misc_after = false;
ce8f5370
AD		 159
160 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
161 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
162 return;
163
164 if (radeon_gui_idle(rdev)) {
165 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
166 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 167 if (sclk > rdev->pm.default_sclk)
168 sclk = rdev->pm.default_sclk;
ce8f5370 169
27810fb2
AD		 170 /* starting with BTC, there is one state that is used for both
171 * MH and SH. Difference is that we always use the high clock index for
7ae764b1 172 * mclk and vddci.
27810fb2
AD		 173 */
174 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
175 (rdev->family >= CHIP_BARTS) &&
176 rdev->pm.active_crtc_count &&
177 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
178 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
179 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
180 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
181 else
182 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].mclk;
184
9ace9f7b
AD		 185 if (mclk > rdev->pm.default_mclk)
186 mclk = rdev->pm.default_mclk;
ce8f5370 187
92645879
AD		 188 /* upvolt before raising clocks, downvolt after lowering clocks */
189 if (sclk < rdev->pm.current_sclk)
190 misc_after = true;
ce8f5370 191
92645879 192 radeon_sync_with_vblank(rdev);
ce8f5370 193
92645879 194 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 195 if (!radeon_pm_in_vbl(rdev))
196 return;
92645879 197 }
ce8f5370 198
92645879 199 radeon_pm_prepare(rdev);
ce8f5370 200
92645879
AD		 201 if (!misc_after)
202 /* voltage, pcie lanes, etc.*/
203 radeon_pm_misc(rdev);
204
205 /* set engine clock */
206 if (sclk != rdev->pm.current_sclk) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_set_engine_clock(rdev, sclk);
209 radeon_pm_debug_check_in_vbl(rdev, true);
210 rdev->pm.current_sclk = sclk;
d9fdaafb 211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 212 }
213
214 /* set memory clock */
798bcf73 215 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_memory_clock(rdev, mclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_mclk = mclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 221 }
2aba631c 222
92645879
AD		 223 if (misc_after)
224 /* voltage, pcie lanes, etc.*/
225 radeon_pm_misc(rdev);
226
227 radeon_pm_finish(rdev);
228
ce8f5370
AD		 229 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
230 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
231 } else
d9fdaafb 232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 233}
234
235static void radeon_pm_set_clocks(struct radeon_device *rdev)
236{
5f8f635e 237 int i, r;
c37d230a 238
4e186b2d
AD		 239 /* no need to take locks, etc. if nothing's going to change */
240 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
241 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
242 return;
243
612e06ce 244 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 245 down_write(&rdev->pm.mclk_lock);
d6999bc7 246 mutex_lock(&rdev->ring_lock);
4f3218cb 247
95f5a3ac
AD		 248 /* wait for the rings to drain */
249 for (i = 0; i < RADEON_NUM_RINGS; i++) {
250 struct radeon_ring *ring = &rdev->ring[i];
5f8f635e
JG		 251 if (!ring->ready) {
252 continue;
253 }
254 r = radeon_fence_wait_empty_locked(rdev, i);
255 if (r) {
256 /* needs a GPU reset dont reset here */
257 mutex_unlock(&rdev->ring_lock);
258 up_write(&rdev->pm.mclk_lock);
259 mutex_unlock(&rdev->ddev->struct_mutex);
260 return;
261 }
4f3218cb 262 }
95f5a3ac 263
5876dd24
MG		 264 radeon_unmap_vram_bos(rdev);
265
ce8f5370 266 if (rdev->irq.installed) {
2aba631c
MG		 267 for (i = 0; i < rdev->num_crtc; i++) {
268 if (rdev->pm.active_crtcs & (1 << i)) {
269 rdev->pm.req_vblank |= (1 << i);
270 drm_vblank_get(rdev->ddev, i);
271 }
272 }
273 }
539d2418 274
ce8f5370 275 radeon_set_power_state(rdev);
2aba631c 276
ce8f5370 277 if (rdev->irq.installed) {
2aba631c
MG		 278 for (i = 0; i < rdev->num_crtc; i++) {
279 if (rdev->pm.req_vblank & (1 << i)) {
280 rdev->pm.req_vblank &= ~(1 << i);
281 drm_vblank_put(rdev->ddev, i);
282 }
283 }
284 }
5876dd24 285
a424816f
AD		 286 /* update display watermarks based on new power state */
287 radeon_update_bandwidth_info(rdev);
288 if (rdev->pm.active_crtc_count)
289 radeon_bandwidth_update(rdev);
290
ce8f5370 291 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 292
d6999bc7 293 mutex_unlock(&rdev->ring_lock);
db7fce39 294 up_write(&rdev->pm.mclk_lock);
612e06ce 295 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 296}
297
f712d0c7
RM		 298static void radeon_pm_print_states(struct radeon_device *rdev)
299{
300 int i, j;
301 struct radeon_power_state *power_state;
302 struct radeon_pm_clock_info *clock_info;
303
d9fdaafb 304 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 305 for (i = 0; i < rdev->pm.num_power_states; i++) {
306 power_state = &rdev->pm.power_state[i];
d9fdaafb 307 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 308 radeon_pm_state_type_name[power_state->type]);
309 if (i == rdev->pm.default_power_state_index)
d9fdaafb 310 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 311 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 312 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 313 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 314 DRM_DEBUG_DRIVER("\tSingle display only\n");
315 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 316 for (j = 0; j < power_state->num_clock_modes; j++) {
317 clock_info = &(power_state->clock_info[j]);
318 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 319 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
320 j,
321 clock_info->sclk * 10);
f712d0c7 322 else
eb2c27a0
AD		 323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
324 j,
325 clock_info->sclk * 10,
326 clock_info->mclk * 10,
327 clock_info->voltage.voltage);
f712d0c7
RM		 328 }
329 }
330}
331
ce8f5370
AD		 332static ssize_t radeon_get_pm_profile(struct device *dev,
333 struct device_attribute *attr,
334 char *buf)
a424816f
AD		 335{
336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
337 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 338 int cp = rdev->pm.profile;
a424816f 339
ce8f5370
AD		 340 return snprintf(buf, PAGE_SIZE, "%s\n",
341 (cp == PM_PROFILE_AUTO) ? "auto" :
342 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 343 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 344 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 345}
346
ce8f5370
AD		 347static ssize_t radeon_set_pm_profile(struct device *dev,
348 struct device_attribute *attr,
349 const char *buf,
350 size_t count)
a424816f
AD		 351{
352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
353 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 354
355 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
357 if (strncmp("default", buf, strlen("default")) == 0)
358 rdev->pm.profile = PM_PROFILE_DEFAULT;
359 else if (strncmp("auto", buf, strlen("auto")) == 0)
360 rdev->pm.profile = PM_PROFILE_AUTO;
361 else if (strncmp("low", buf, strlen("low")) == 0)
362 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 363 else if (strncmp("mid", buf, strlen("mid")) == 0)
364 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 365 else if (strncmp("high", buf, strlen("high")) == 0)
366 rdev->pm.profile = PM_PROFILE_HIGH;
367 else {
1783e4bf 368 count = -EINVAL;
ce8f5370 369 goto fail;
a424816f 370 }
ce8f5370
AD		 371 radeon_pm_update_profile(rdev);
372 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 373 } else
374 count = -EINVAL;
375
ce8f5370 376fail:
a424816f
AD		 377 mutex_unlock(&rdev->pm.mutex);
378
379 return count;
380}
381
ce8f5370
AD		 382static ssize_t radeon_get_pm_method(struct device *dev,
383 struct device_attribute *attr,
384 char *buf)
a424816f
AD		 385{
386 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
387 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 388 int pm = rdev->pm.pm_method;
a424816f
AD		 389
390 return snprintf(buf, PAGE_SIZE, "%s\n",
da321c8a
AD		 391 (pm == PM_METHOD_DYNPM) ? "dynpm" :
392 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
a424816f
AD		 393}
394
ce8f5370
AD		 395static ssize_t radeon_set_pm_method(struct device *dev,
396 struct device_attribute *attr,
397 const char *buf,
398 size_t count)
a424816f
AD		 399{
400 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
401 struct radeon_device *rdev = ddev->dev_private;
a424816f 402
da321c8a
AD		 403 /* we don't support the legacy modes with dpm */
404 if (rdev->pm.pm_method == PM_METHOD_DPM) {
405 count = -EINVAL;
406 goto fail;
407 }
ce8f5370
AD		 408
409 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 410 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 411 rdev->pm.pm_method = PM_METHOD_DYNPM;
412 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
413 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 414 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 415 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
416 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 417 /* disable dynpm */
418 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
419 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 420 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 421 mutex_unlock(&rdev->pm.mutex);
32c87fca 422 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 423 } else {
1783e4bf 424 count = -EINVAL;
ce8f5370
AD		 425 goto fail;
426 }
427 radeon_pm_compute_clocks(rdev);
428fail:
a424816f
AD		 429 return count;
430}
431
da321c8a
AD		 432static ssize_t radeon_get_dpm_state(struct device *dev,
433 struct device_attribute *attr,
434 char *buf)
435{
436 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
437 struct radeon_device *rdev = ddev->dev_private;
438 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
439
440 return snprintf(buf, PAGE_SIZE, "%s\n",
441 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
442 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
443}
444
445static ssize_t radeon_set_dpm_state(struct device *dev,
446 struct device_attribute *attr,
447 const char *buf,
448 size_t count)
449{
450 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
451 struct radeon_device *rdev = ddev->dev_private;
452
453 mutex_lock(&rdev->pm.mutex);
454 if (strncmp("battery", buf, strlen("battery")) == 0)
455 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
456 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
457 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
458 else if (strncmp("performance", buf, strlen("performance")) == 0)
459 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
460 else {
461 mutex_unlock(&rdev->pm.mutex);
462 count = -EINVAL;
463 goto fail;
464 }
465 mutex_unlock(&rdev->pm.mutex);
466 radeon_pm_compute_clocks(rdev);
467fail:
468 return count;
469}
470
ce8f5370
AD		 471static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
472static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
da321c8a 473static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
a424816f 474
21a8122a
AD		 475static ssize_t radeon_hwmon_show_temp(struct device *dev,
476 struct device_attribute *attr,
477 char *buf)
478{
479 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
480 struct radeon_device *rdev = ddev->dev_private;
20d391d7 481 int temp;
21a8122a 482
6bd1c385
AD		 483 if (rdev->asic->pm.get_temperature)
484 temp = radeon_get_temperature(rdev);
485 else
21a8122a 486 temp = 0;
21a8122a
AD		 487
488 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
489}
490
491static ssize_t radeon_hwmon_show_name(struct device *dev,
492 struct device_attribute *attr,
493 char *buf)
494{
495 return sprintf(buf, "radeon\n");
496}
497
498static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
499static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
500
501static struct attribute *hwmon_attributes[] = {
502 &sensor_dev_attr_temp1_input.dev_attr.attr,
503 &sensor_dev_attr_name.dev_attr.attr,
504 NULL
505};
506
507static const struct attribute_group hwmon_attrgroup = {
508 .attrs = hwmon_attributes,
509};
510
0d18abed 511static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 512{
0d18abed 513 int err = 0;
21a8122a
AD		 514
515 rdev->pm.int_hwmon_dev = NULL;
516
517 switch (rdev->pm.int_thermal_type) {
518 case THERMAL_TYPE_RV6XX:
519 case THERMAL_TYPE_RV770:
520 case THERMAL_TYPE_EVERGREEN:
457558ed 521 case THERMAL_TYPE_NI:
e33df25f 522 case THERMAL_TYPE_SUMO:
1bd47d2e 523 case THERMAL_TYPE_SI:
6bd1c385 524 if (rdev->asic->pm.get_temperature == NULL)
5d7486c7 525 return err;
21a8122a 526 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 527 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
528 err = PTR_ERR(rdev->pm.int_hwmon_dev);
529 dev_err(rdev->dev,
530 "Unable to register hwmon device: %d\n", err);
531 break;
532 }
21a8122a
AD		 533 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
534 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
535 &hwmon_attrgroup);
0d18abed
DC		 536 if (err) {
537 dev_err(rdev->dev,
538 "Unable to create hwmon sysfs file: %d\n", err);
539 hwmon_device_unregister(rdev->dev);
540 }
21a8122a
AD		 541 break;
542 default:
543 break;
544 }
0d18abed
DC		 545
546 return err;
21a8122a
AD		 547}
548
549static void radeon_hwmon_fini(struct radeon_device *rdev)
550{
551 if (rdev->pm.int_hwmon_dev) {
552 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
553 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
554 }
555}
556
da321c8a
AD		 557static void radeon_dpm_thermal_work_handler(struct work_struct *work)
558{
559 struct radeon_device *rdev =
560 container_of(work, struct radeon_device,
561 pm.dpm.thermal.work);
562 /* switch to the thermal state */
563 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
564
565 if (!rdev->pm.dpm_enabled)
566 return;
567
568 if (rdev->asic->pm.get_temperature) {
569 int temp = radeon_get_temperature(rdev);
570
571 if (temp < rdev->pm.dpm.thermal.min_temp)
572 /* switch back the user state */
573 dpm_state = rdev->pm.dpm.user_state;
574 } else {
575 if (rdev->pm.dpm.thermal.high_to_low)
576 /* switch back the user state */
577 dpm_state = rdev->pm.dpm.user_state;
578 }
579 radeon_dpm_enable_power_state(rdev, dpm_state);
580}
581
582static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
583 enum radeon_pm_state_type dpm_state)
584{
585 int i;
586 struct radeon_ps *ps;
587 u32 ui_class;
588
589restart_search:
590 /* balanced states don't exist at the moment */
591 if (dpm_state == POWER_STATE_TYPE_BALANCED)
592 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
593
594 /* Pick the best power state based on current conditions */
595 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
596 ps = &rdev->pm.dpm.ps[i];
597 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
598 switch (dpm_state) {
599 /* user states */
600 case POWER_STATE_TYPE_BATTERY:
601 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
602 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
603 if (rdev->pm.dpm.new_active_crtc_count < 2)
604 return ps;
605 } else
606 return ps;
607 }
608 break;
609 case POWER_STATE_TYPE_BALANCED:
610 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
611 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
612 if (rdev->pm.dpm.new_active_crtc_count < 2)
613 return ps;
614 } else
615 return ps;
616 }
617 break;
618 case POWER_STATE_TYPE_PERFORMANCE:
619 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
620 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
621 if (rdev->pm.dpm.new_active_crtc_count < 2)
622 return ps;
623 } else
624 return ps;
625 }
626 break;
627 /* internal states */
628 case POWER_STATE_TYPE_INTERNAL_UVD:
629 return rdev->pm.dpm.uvd_ps;
630 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
631 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
632 return ps;
633 break;
634 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
635 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
636 return ps;
637 break;
638 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
639 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
640 return ps;
641 break;
642 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
643 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
644 return ps;
645 break;
646 case POWER_STATE_TYPE_INTERNAL_BOOT:
647 return rdev->pm.dpm.boot_ps;
648 case POWER_STATE_TYPE_INTERNAL_THERMAL:
649 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
650 return ps;
651 break;
652 case POWER_STATE_TYPE_INTERNAL_ACPI:
653 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
654 return ps;
655 break;
656 case POWER_STATE_TYPE_INTERNAL_ULV:
657 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
658 return ps;
659 break;
660 default:
661 break;
662 }
663 }
664 /* use a fallback state if we didn't match */
665 switch (dpm_state) {
666 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
667 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
668 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
669 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
670 return rdev->pm.dpm.uvd_ps;
671 case POWER_STATE_TYPE_INTERNAL_THERMAL:
672 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
673 goto restart_search;
674 case POWER_STATE_TYPE_INTERNAL_ACPI:
675 dpm_state = POWER_STATE_TYPE_BATTERY;
676 goto restart_search;
677 case POWER_STATE_TYPE_BATTERY:
678 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
679 goto restart_search;
680 default:
681 break;
682 }
683
684 return NULL;
685}
686
687static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
688{
689 int i;
690 struct radeon_ps *ps;
691 enum radeon_pm_state_type dpm_state;
692
693 /* if dpm init failed */
694 if (!rdev->pm.dpm_enabled)
695 return;
696
697 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
698 /* add other state override checks here */
699 if (!rdev->pm.dpm.thermal_active)
700 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
701 }
702 dpm_state = rdev->pm.dpm.state;
703
704 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
705 if (ps)
706 rdev->pm.dpm.requested_ps = ps;
707 else
708 return;
709
710 /* no need to reprogram if nothing changed */
711 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
712 /* update display watermarks based on new power state */
713 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
714 radeon_bandwidth_update(rdev);
715 /* update displays */
716 radeon_dpm_display_configuration_changed(rdev);
717 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
718 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
719 }
720 return;
721 }
722
723 printk("switching from power state:\n");
724 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
725 printk("switching to power state:\n");
726 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
727
728 mutex_lock(&rdev->ddev->struct_mutex);
729 down_write(&rdev->pm.mclk_lock);
730 mutex_lock(&rdev->ring_lock);
731
732 /* update display watermarks based on new power state */
733 radeon_bandwidth_update(rdev);
734 /* update displays */
735 radeon_dpm_display_configuration_changed(rdev);
736
737 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
738 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
739
740 /* wait for the rings to drain */
741 for (i = 0; i < RADEON_NUM_RINGS; i++) {
742 struct radeon_ring *ring = &rdev->ring[i];
743 if (ring->ready)
744 radeon_fence_wait_empty_locked(rdev, i);
745 }
746
747 /* program the new power state */
748 radeon_dpm_set_power_state(rdev);
749
750 /* update current power state */
751 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
752
753 mutex_unlock(&rdev->ring_lock);
754 up_write(&rdev->pm.mclk_lock);
755 mutex_unlock(&rdev->ddev->struct_mutex);
756}
757
758void radeon_dpm_enable_power_state(struct radeon_device *rdev,
759 enum radeon_pm_state_type dpm_state)
760{
761 if (!rdev->pm.dpm_enabled)
762 return;
763
764 mutex_lock(&rdev->pm.mutex);
765 switch (dpm_state) {
766 case POWER_STATE_TYPE_INTERNAL_THERMAL:
767 rdev->pm.dpm.thermal_active = true;
768 break;
769 default:
770 rdev->pm.dpm.thermal_active = false;
771 break;
772 }
773 rdev->pm.dpm.state = dpm_state;
774 mutex_unlock(&rdev->pm.mutex);
775 radeon_pm_compute_clocks(rdev);
776}
777
778static void radeon_pm_suspend_old(struct radeon_device *rdev)
56278a8e 779{
ce8f5370 780 mutex_lock(&rdev->pm.mutex);
3f53eb6f 781 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 782 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
783 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 784 }
ce8f5370 785 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 786
787 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 788}
789
da321c8a
AD		 790static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
791{
792 mutex_lock(&rdev->pm.mutex);
793 /* disable dpm */
794 radeon_dpm_disable(rdev);
795 /* reset the power state */
796 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
797 rdev->pm.dpm_enabled = false;
798 mutex_unlock(&rdev->pm.mutex);
799}
800
801void radeon_pm_suspend(struct radeon_device *rdev)
802{
803 if (rdev->pm.pm_method == PM_METHOD_DPM)
804 radeon_pm_suspend_dpm(rdev);
805 else
806 radeon_pm_suspend_old(rdev);
807}
808
809static void radeon_pm_resume_old(struct radeon_device *rdev)
d0d6cb81 810{
ed18a360 811 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10
AD		 812 if ((rdev->family >= CHIP_BARTS) &&
813 (rdev->family <= CHIP_CAYMAN) &&
814 rdev->mc_fw) {
ed18a360 815 if (rdev->pm.default_vddc)
8a83ec5e
AD		 816 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
817 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 818 if (rdev->pm.default_vddci)
819 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
820 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 821 if (rdev->pm.default_sclk)
822 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
823 if (rdev->pm.default_mclk)
824 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
825 }
f8ed8b4c
AD		 826 /* asic init will reset the default power state */
827 mutex_lock(&rdev->pm.mutex);
828 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
829 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 830 rdev->pm.current_sclk = rdev->pm.default_sclk;
831 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 832 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 833 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 834 if (rdev->pm.pm_method == PM_METHOD_DYNPM
835 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
836 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 837 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
838 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 839 }
f8ed8b4c 840 mutex_unlock(&rdev->pm.mutex);
ce8f5370 841 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 842}
843
da321c8a
AD		 844static void radeon_pm_resume_dpm(struct radeon_device *rdev)
845{
846 int ret;
847
848 /* asic init will reset to the boot state */
849 mutex_lock(&rdev->pm.mutex);
850 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
851 radeon_dpm_setup_asic(rdev);
852 ret = radeon_dpm_enable(rdev);
853 mutex_unlock(&rdev->pm.mutex);
854 if (ret) {
855 DRM_ERROR("radeon: dpm resume failed\n");
856 if ((rdev->family >= CHIP_BARTS) &&
857 (rdev->family <= CHIP_CAYMAN) &&
858 rdev->mc_fw) {
859 if (rdev->pm.default_vddc)
860 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
861 SET_VOLTAGE_TYPE_ASIC_VDDC);
862 if (rdev->pm.default_vddci)
863 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
864 SET_VOLTAGE_TYPE_ASIC_VDDCI);
865 if (rdev->pm.default_sclk)
866 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
867 if (rdev->pm.default_mclk)
868 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
869 }
870 } else {
871 rdev->pm.dpm_enabled = true;
872 radeon_pm_compute_clocks(rdev);
873 }
874}
875
876void radeon_pm_resume(struct radeon_device *rdev)
877{
878 if (rdev->pm.pm_method == PM_METHOD_DPM)
879 radeon_pm_resume_dpm(rdev);
880 else
881 radeon_pm_resume_old(rdev);
882}
883
884static int radeon_pm_init_old(struct radeon_device *rdev)
7433874e 885{
26481fb1 886 int ret;
0d18abed 887
f8ed8b4c 888 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 889 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
890 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
891 rdev->pm.dynpm_can_upclock = true;
892 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 893 rdev->pm.default_sclk = rdev->clock.default_sclk;
894 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 895 rdev->pm.current_sclk = rdev->clock.default_sclk;
896 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 897 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 898
56278a8e
AD		 899 if (rdev->bios) {
900 if (rdev->is_atom_bios)
901 radeon_atombios_get_power_modes(rdev);
902 else
903 radeon_combios_get_power_modes(rdev);
f712d0c7 904 radeon_pm_print_states(rdev);
ce8f5370 905 radeon_pm_init_profile(rdev);
ed18a360 906 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10
AD		 907 if ((rdev->family >= CHIP_BARTS) &&
908 (rdev->family <= CHIP_CAYMAN) &&
909 rdev->mc_fw) {
ed18a360 910 if (rdev->pm.default_vddc)
8a83ec5e
AD		 911 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
912 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 913 if (rdev->pm.default_vddci)
914 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
915 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 916 if (rdev->pm.default_sclk)
917 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
918 if (rdev->pm.default_mclk)
919 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
920 }
56278a8e
AD		 921 }
922
21a8122a 923 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 924 ret = radeon_hwmon_init(rdev);
925 if (ret)
926 return ret;
32c87fca
TH		 927
928 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
929
ce8f5370 930 if (rdev->pm.num_power_states > 1) {
ce8f5370 931 /* where's the best place to put these? */
26481fb1
DA		 932 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
933 if (ret)
934 DRM_ERROR("failed to create device file for power profile\n");
935 ret = device_create_file(rdev->dev, &dev_attr_power_method);
936 if (ret)
937 DRM_ERROR("failed to create device file for power method\n");
a424816f 938
ce8f5370
AD		 939 if (radeon_debugfs_pm_init(rdev)) {
940 DRM_ERROR("Failed to register debugfs file for PM!\n");
941 }
c913e23a 942
ce8f5370
AD		 943 DRM_INFO("radeon: power management initialized\n");
944 }
c913e23a 945
7433874e
RM		 946 return 0;
947}
948
da321c8a
AD		 949static void radeon_dpm_print_power_states(struct radeon_device *rdev)
950{
951 int i;
952
953 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
954 printk("== power state %d ==\n", i);
955 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
956 }
957}
958
959static int radeon_pm_init_dpm(struct radeon_device *rdev)
960{
961 int ret;
962
963 /* default to performance state */
964 rdev->pm.dpm.state = POWER_STATE_TYPE_PERFORMANCE;
965 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
966 rdev->pm.default_sclk = rdev->clock.default_sclk;
967 rdev->pm.default_mclk = rdev->clock.default_mclk;
968 rdev->pm.current_sclk = rdev->clock.default_sclk;
969 rdev->pm.current_mclk = rdev->clock.default_mclk;
970 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
971
972 if (rdev->bios && rdev->is_atom_bios)
973 radeon_atombios_get_power_modes(rdev);
974 else
975 return -EINVAL;
976
977 /* set up the internal thermal sensor if applicable */
978 ret = radeon_hwmon_init(rdev);
979 if (ret)
980 return ret;
981
982 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
983 mutex_lock(&rdev->pm.mutex);
984 radeon_dpm_init(rdev);
985 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
986 radeon_dpm_print_power_states(rdev);
987 radeon_dpm_setup_asic(rdev);
988 ret = radeon_dpm_enable(rdev);
989 mutex_unlock(&rdev->pm.mutex);
990 if (ret) {
991 rdev->pm.dpm_enabled = false;
992 if ((rdev->family >= CHIP_BARTS) &&
993 (rdev->family <= CHIP_CAYMAN) &&
994 rdev->mc_fw) {
995 if (rdev->pm.default_vddc)
996 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
997 SET_VOLTAGE_TYPE_ASIC_VDDC);
998 if (rdev->pm.default_vddci)
999 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1000 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1001 if (rdev->pm.default_sclk)
1002 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1003 if (rdev->pm.default_mclk)
1004 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1005 }
1006 DRM_ERROR("radeon: dpm initialization failed\n");
1007 return ret;
1008 }
1009 rdev->pm.dpm_enabled = true;
1010 radeon_pm_compute_clocks(rdev);
1011
1012 if (rdev->pm.num_power_states > 1) {
1013 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1014 if (ret)
1015 DRM_ERROR("failed to create device file for dpm state\n");
1016 /* XXX: these are noops for dpm but are here for backwards compat */
1017 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1018 if (ret)
1019 DRM_ERROR("failed to create device file for power profile\n");
1020 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1021 if (ret)
1022 DRM_ERROR("failed to create device file for power method\n");
1023 DRM_INFO("radeon: dpm initialized\n");
1024 }
1025
1026 return 0;
1027}
1028
1029int radeon_pm_init(struct radeon_device *rdev)
1030{
1031 /* enable dpm on rv6xx+ */
1032 switch (rdev->family) {
1033 default:
1034 /* default to profile method */
1035 rdev->pm.pm_method = PM_METHOD_PROFILE;
1036 break;
1037 }
1038
1039 if (rdev->pm.pm_method == PM_METHOD_DPM)
1040 return radeon_pm_init_dpm(rdev);
1041 else
1042 return radeon_pm_init_old(rdev);
1043}
1044
1045static void radeon_pm_fini_old(struct radeon_device *rdev)
29fb52ca 1046{
ce8f5370 1047 if (rdev->pm.num_power_states > 1) {
a424816f 1048 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 1049 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1050 rdev->pm.profile = PM_PROFILE_DEFAULT;
1051 radeon_pm_update_profile(rdev);
1052 radeon_pm_set_clocks(rdev);
1053 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 1054 /* reset default clocks */
1055 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1056 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1057 radeon_pm_set_clocks(rdev);
1058 }
a424816f 1059 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1060
1061 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 1062
ce8f5370
AD		 1063 device_remove_file(rdev->dev, &dev_attr_power_profile);
1064 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 1065 }
a424816f 1066
0975b162
AD		 1067 if (rdev->pm.power_state)
1068 kfree(rdev->pm.power_state);
1069
21a8122a 1070 radeon_hwmon_fini(rdev);
29fb52ca
AD		 1071}
1072
da321c8a
AD		 1073static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1074{
1075 if (rdev->pm.num_power_states > 1) {
1076 mutex_lock(&rdev->pm.mutex);
1077 radeon_dpm_disable(rdev);
1078 mutex_unlock(&rdev->pm.mutex);
1079
1080 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1081 /* XXX backwards compat */
1082 device_remove_file(rdev->dev, &dev_attr_power_profile);
1083 device_remove_file(rdev->dev, &dev_attr_power_method);
1084 }
1085 radeon_dpm_fini(rdev);
1086
1087 if (rdev->pm.power_state)
1088 kfree(rdev->pm.power_state);
1089
1090 radeon_hwmon_fini(rdev);
1091}
1092
1093void radeon_pm_fini(struct radeon_device *rdev)
1094{
1095 if (rdev->pm.pm_method == PM_METHOD_DPM)
1096 radeon_pm_fini_dpm(rdev);
1097 else
1098 radeon_pm_fini_old(rdev);
1099}
1100
1101static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
c913e23a
RM		 1102{
1103 struct drm_device *ddev = rdev->ddev;
a48b9b4e 1104 struct drm_crtc *crtc;
c913e23a 1105 struct radeon_crtc *radeon_crtc;
c913e23a 1106
ce8f5370
AD		 1107 if (rdev->pm.num_power_states < 2)
1108 return;
1109
c913e23a
RM		 1110 mutex_lock(&rdev->pm.mutex);
1111
1112 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 1113 rdev->pm.active_crtc_count = 0;
1114 list_for_each_entry(crtc,
1115 &ddev->mode_config.crtc_list, head) {
1116 radeon_crtc = to_radeon_crtc(crtc);
1117 if (radeon_crtc->enabled) {
c913e23a 1118 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 1119 rdev->pm.active_crtc_count++;
c913e23a
RM		 1120 }
1121 }
1122
ce8f5370
AD		 1123 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1124 radeon_pm_update_profile(rdev);
1125 radeon_pm_set_clocks(rdev);
1126 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1127 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1128 if (rdev->pm.active_crtc_count > 1) {
1129 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1130 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1131
1132 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1133 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1134 radeon_pm_get_dynpm_state(rdev);
1135 radeon_pm_set_clocks(rdev);
1136
d9fdaafb 1137 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 1138 }
1139 } else if (rdev->pm.active_crtc_count == 1) {
1140 /* TODO: Increase clocks if needed for current mode */
1141
1142 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1143 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1144 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1145 radeon_pm_get_dynpm_state(rdev);
1146 radeon_pm_set_clocks(rdev);
1147
32c87fca
TH		 1148 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1149 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 1150 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1151 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1152 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1153 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 1154 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 1155 }
1156 } else { /* count == 0 */
1157 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1158 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1159
1160 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1161 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1162 radeon_pm_get_dynpm_state(rdev);
1163 radeon_pm_set_clocks(rdev);
1164 }
1165 }
c913e23a 1166 }
c913e23a 1167 }
73a6d3fc
RM		 1168
1169 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 1170}
1171
da321c8a
AD		 1172static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1173{
1174 struct drm_device *ddev = rdev->ddev;
1175 struct drm_crtc *crtc;
1176 struct radeon_crtc *radeon_crtc;
1177
1178 mutex_lock(&rdev->pm.mutex);
1179
1180 rdev->pm.dpm.new_active_crtcs = 0;
1181 rdev->pm.dpm.new_active_crtc_count = 0;
1182 list_for_each_entry(crtc,
1183 &ddev->mode_config.crtc_list, head) {
1184 radeon_crtc = to_radeon_crtc(crtc);
1185 if (crtc->enabled) {
1186 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1187 rdev->pm.dpm.new_active_crtc_count++;
1188 }
1189 }
1190
1191 radeon_dpm_change_power_state_locked(rdev);
1192
1193 mutex_unlock(&rdev->pm.mutex);
1194}
1195
1196void radeon_pm_compute_clocks(struct radeon_device *rdev)
1197{
1198 if (rdev->pm.pm_method == PM_METHOD_DPM)
1199 radeon_pm_compute_clocks_dpm(rdev);
1200 else
1201 radeon_pm_compute_clocks_old(rdev);
1202}
1203
ce8f5370 1204static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 1205{
75fa0b08 1206 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 1207 bool in_vbl = true;
1208
75fa0b08
MK		 1209 /* Iterate over all active crtc's. All crtc's must be in vblank,
1210 * otherwise return in_vbl == false.
1211 */
1212 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1213 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 1214 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1215 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1216 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 1217 in_vbl = false;
1218 }
1219 }
f81f2024
MG		 1220
1221 return in_vbl;
1222}
1223
ce8f5370 1224static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 1225{
1226 u32 stat_crtc = 0;
1227 bool in_vbl = radeon_pm_in_vbl(rdev);
1228
f735261b 1229 if (in_vbl == false)
d9fdaafb 1230 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 1231 finish ? "exit" : "entry");
f735261b
DA		 1232 return in_vbl;
1233}
c913e23a 1234
ce8f5370 1235static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 1236{
1237 struct radeon_device *rdev;
d9932a32 1238 int resched;
c913e23a 1239 rdev = container_of(work, struct radeon_device,
ce8f5370 1240 pm.dynpm_idle_work.work);
c913e23a 1241
d9932a32 1242 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 1243 mutex_lock(&rdev->pm.mutex);
ce8f5370 1244 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 1245 int not_processed = 0;
7465280c
AD		 1246 int i;
1247
7465280c 1248 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 1249 struct radeon_ring *ring = &rdev->ring[i];
1250
1251 if (ring->ready) {
1252 not_processed += radeon_fence_count_emitted(rdev, i);
1253 if (not_processed >= 3)
1254 break;
1255 }
c913e23a 1256 }
c913e23a
RM		 1257
1258 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 1259 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1260 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1261 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1262 rdev->pm.dynpm_can_upclock) {
1263 rdev->pm.dynpm_planned_action =
1264 DYNPM_ACTION_UPCLOCK;
1265 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1266 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1267 }
1268 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 1269 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1270 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1271 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1272 rdev->pm.dynpm_can_downclock) {
1273 rdev->pm.dynpm_planned_action =
1274 DYNPM_ACTION_DOWNCLOCK;
1275 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1276 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1277 }
1278 }
1279
d7311171
AD		 1280 /* Note, radeon_pm_set_clocks is called with static_switch set
1281 * to false since we want to wait for vbl to avoid flicker.
1282 */
ce8f5370
AD		 1283 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1284 jiffies > rdev->pm.dynpm_action_timeout) {
1285 radeon_pm_get_dynpm_state(rdev);
1286 radeon_pm_set_clocks(rdev);
c913e23a 1287 }
3f53eb6f 1288
32c87fca
TH		 1289 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1290 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 1291 }
1292 mutex_unlock(&rdev->pm.mutex);
d9932a32 1293 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 1294}
1295
7433874e
RM		 1296/*
1297 * Debugfs info
1298 */
1299#if defined(CONFIG_DEBUG_FS)
1300
1301static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1302{
1303 struct drm_info_node *node = (struct drm_info_node *) m->private;
1304 struct drm_device *dev = node->minor->dev;
1305 struct radeon_device *rdev = dev->dev_private;
1306
9ace9f7b 1307 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
bf05d998
AD		 1308 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1309 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1310 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1311 else
1312 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 1313 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
798bcf73 1314 if (rdev->asic->pm.get_memory_clock)
6234077d 1315 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 1316 if (rdev->pm.current_vddc)
1317 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
798bcf73 1318 if (rdev->asic->pm.get_pcie_lanes)
aa5120d2 1319 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 1320
1321 return 0;
1322}
1323
1324static struct drm_info_list radeon_pm_info_list[] = {
1325 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1326};
1327#endif
1328
c913e23a 1329static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 1330{
1331#if defined(CONFIG_DEBUG_FS)
1332 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1333#else
1334 return 0;
1335#endif
1336}
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