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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370 27#include <linux/power_supply.h>
21a8122a
AD		 28#include <linux/hwmon.h>
29#include <linux/hwmon-sysfs.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 34
f712d0c7 35static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 36 "",
f712d0c7
RM		 37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41};
42
ce8f5370 43static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 44static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 45static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47static void radeon_pm_update_profile(struct radeon_device *rdev);
48static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
a4c9e2ee
AD		 50int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53{
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66}
67
c4917074 68void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 69{
1c71bda0
AD		 70 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71 mutex_lock(&rdev->pm.mutex);
72 if (power_supply_is_system_supplied() > 0)
73 rdev->pm.dpm.ac_power = true;
74 else
75 rdev->pm.dpm.ac_power = false;
76 if (rdev->asic->dpm.enable_bapm)
77 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
78 mutex_unlock(&rdev->pm.mutex);
79 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
c4917074
AD		 80 if (rdev->pm.profile == PM_PROFILE_AUTO) {
81 mutex_lock(&rdev->pm.mutex);
82 radeon_pm_update_profile(rdev);
83 radeon_pm_set_clocks(rdev);
84 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 85 }
86 }
ce8f5370 87}
ce8f5370
AD		 88
89static void radeon_pm_update_profile(struct radeon_device *rdev)
90{
91 switch (rdev->pm.profile) {
92 case PM_PROFILE_DEFAULT:
93 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
94 break;
95 case PM_PROFILE_AUTO:
96 if (power_supply_is_system_supplied() > 0) {
97 if (rdev->pm.active_crtc_count > 1)
98 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
99 else
100 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
101 } else {
102 if (rdev->pm.active_crtc_count > 1)
c9e75b21 103 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 104 else
c9e75b21 105 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 106 }
107 break;
108 case PM_PROFILE_LOW:
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
111 else
112 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
113 break;
c9e75b21
AD		 114 case PM_PROFILE_MID:
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
117 else
118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
119 break;
ce8f5370
AD		 120 case PM_PROFILE_HIGH:
121 if (rdev->pm.active_crtc_count > 1)
122 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
123 else
124 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
125 break;
126 }
127
128 if (rdev->pm.active_crtc_count == 0) {
129 rdev->pm.requested_power_state_index =
130 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
131 rdev->pm.requested_clock_mode_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
133 } else {
134 rdev->pm.requested_power_state_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
136 rdev->pm.requested_clock_mode_index =
137 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
138 }
139}
c913e23a 140
5876dd24
MG		 141static void radeon_unmap_vram_bos(struct radeon_device *rdev)
142{
143 struct radeon_bo *bo, *n;
144
145 if (list_empty(&rdev->gem.objects))
146 return;
147
148 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
149 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
150 ttm_bo_unmap_virtual(&bo->tbo);
151 }
5876dd24
MG		 152}
153
ce8f5370 154static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 155{
ce8f5370
AD		 156 if (rdev->pm.active_crtcs) {
157 rdev->pm.vblank_sync = false;
158 wait_event_timeout(
159 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
160 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
161 }
162}
163
164static void radeon_set_power_state(struct radeon_device *rdev)
165{
166 u32 sclk, mclk;
92645879 167 bool misc_after = false;
ce8f5370
AD		 168
169 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
170 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
171 return;
172
173 if (radeon_gui_idle(rdev)) {
174 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
175 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 176 if (sclk > rdev->pm.default_sclk)
177 sclk = rdev->pm.default_sclk;
ce8f5370 178
27810fb2
AD		 179 /* starting with BTC, there is one state that is used for both
180 * MH and SH. Difference is that we always use the high clock index for
7ae764b1 181 * mclk and vddci.
27810fb2
AD		 182 */
183 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
184 (rdev->family >= CHIP_BARTS) &&
185 rdev->pm.active_crtc_count &&
186 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
187 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
188 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
189 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
190 else
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.requested_clock_mode_index].mclk;
193
9ace9f7b
AD		 194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
ce8f5370 196
92645879
AD		 197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
199 misc_after = true;
ce8f5370 200
92645879 201 radeon_sync_with_vblank(rdev);
ce8f5370 202
92645879 203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 204 if (!radeon_pm_in_vbl(rdev))
205 return;
92645879 206 }
ce8f5370 207
92645879 208 radeon_pm_prepare(rdev);
ce8f5370 209
92645879
AD		 210 if (!misc_after)
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
213
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 221 }
222
223 /* set memory clock */
798bcf73 224 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
d9fdaafb 229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 230 }
2aba631c 231
92645879
AD		 232 if (misc_after)
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
235
236 radeon_pm_finish(rdev);
237
ce8f5370
AD		 238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
240 } else
d9fdaafb 241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 242}
243
244static void radeon_pm_set_clocks(struct radeon_device *rdev)
245{
5f8f635e 246 int i, r;
c37d230a 247
4e186b2d
AD		 248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
251 return;
252
612e06ce 253 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 254 down_write(&rdev->pm.mclk_lock);
d6999bc7 255 mutex_lock(&rdev->ring_lock);
4f3218cb 256
95f5a3ac
AD		 257 /* wait for the rings to drain */
258 for (i = 0; i < RADEON_NUM_RINGS; i++) {
259 struct radeon_ring *ring = &rdev->ring[i];
5f8f635e
JG		 260 if (!ring->ready) {
261 continue;
262 }
263 r = radeon_fence_wait_empty_locked(rdev, i);
264 if (r) {
265 /* needs a GPU reset dont reset here */
266 mutex_unlock(&rdev->ring_lock);
267 up_write(&rdev->pm.mclk_lock);
268 mutex_unlock(&rdev->ddev->struct_mutex);
269 return;
270 }
4f3218cb 271 }
95f5a3ac 272
5876dd24
MG		 273 radeon_unmap_vram_bos(rdev);
274
ce8f5370 275 if (rdev->irq.installed) {
2aba631c
MG		 276 for (i = 0; i < rdev->num_crtc; i++) {
277 if (rdev->pm.active_crtcs & (1 << i)) {
278 rdev->pm.req_vblank |= (1 << i);
279 drm_vblank_get(rdev->ddev, i);
280 }
281 }
282 }
539d2418 283
ce8f5370 284 radeon_set_power_state(rdev);
2aba631c 285
ce8f5370 286 if (rdev->irq.installed) {
2aba631c
MG		 287 for (i = 0; i < rdev->num_crtc; i++) {
288 if (rdev->pm.req_vblank & (1 << i)) {
289 rdev->pm.req_vblank &= ~(1 << i);
290 drm_vblank_put(rdev->ddev, i);
291 }
292 }
293 }
5876dd24 294
a424816f
AD		 295 /* update display watermarks based on new power state */
296 radeon_update_bandwidth_info(rdev);
297 if (rdev->pm.active_crtc_count)
298 radeon_bandwidth_update(rdev);
299
ce8f5370 300 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 301
d6999bc7 302 mutex_unlock(&rdev->ring_lock);
db7fce39 303 up_write(&rdev->pm.mclk_lock);
612e06ce 304 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 305}
306
f712d0c7
RM		 307static void radeon_pm_print_states(struct radeon_device *rdev)
308{
309 int i, j;
310 struct radeon_power_state *power_state;
311 struct radeon_pm_clock_info *clock_info;
312
d9fdaafb 313 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 314 for (i = 0; i < rdev->pm.num_power_states; i++) {
315 power_state = &rdev->pm.power_state[i];
d9fdaafb 316 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 317 radeon_pm_state_type_name[power_state->type]);
318 if (i == rdev->pm.default_power_state_index)
d9fdaafb 319 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 320 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 321 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 322 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 323 DRM_DEBUG_DRIVER("\tSingle display only\n");
324 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 325 for (j = 0; j < power_state->num_clock_modes; j++) {
326 clock_info = &(power_state->clock_info[j]);
327 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 328 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
329 j,
330 clock_info->sclk * 10);
f712d0c7 331 else
eb2c27a0
AD		 332 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
333 j,
334 clock_info->sclk * 10,
335 clock_info->mclk * 10,
336 clock_info->voltage.voltage);
f712d0c7
RM		 337 }
338 }
339}
340
ce8f5370
AD		 341static ssize_t radeon_get_pm_profile(struct device *dev,
342 struct device_attribute *attr,
343 char *buf)
a424816f 344{
3e4e2129 345 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 346 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 347 int cp = rdev->pm.profile;
a424816f 348
ce8f5370
AD		 349 return snprintf(buf, PAGE_SIZE, "%s\n",
350 (cp == PM_PROFILE_AUTO) ? "auto" :
351 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 352 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 353 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 354}
355
ce8f5370
AD		 356static ssize_t radeon_set_pm_profile(struct device *dev,
357 struct device_attribute *attr,
358 const char *buf,
359 size_t count)
a424816f 360{
3e4e2129 361 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 362 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 363
364 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 365 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
366 if (strncmp("default", buf, strlen("default")) == 0)
367 rdev->pm.profile = PM_PROFILE_DEFAULT;
368 else if (strncmp("auto", buf, strlen("auto")) == 0)
369 rdev->pm.profile = PM_PROFILE_AUTO;
370 else if (strncmp("low", buf, strlen("low")) == 0)
371 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 372 else if (strncmp("mid", buf, strlen("mid")) == 0)
373 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 374 else if (strncmp("high", buf, strlen("high")) == 0)
375 rdev->pm.profile = PM_PROFILE_HIGH;
376 else {
1783e4bf 377 count = -EINVAL;
ce8f5370 378 goto fail;
a424816f 379 }
ce8f5370
AD		 380 radeon_pm_update_profile(rdev);
381 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 382 } else
383 count = -EINVAL;
384
ce8f5370 385fail:
a424816f
AD		 386 mutex_unlock(&rdev->pm.mutex);
387
388 return count;
389}
390
ce8f5370
AD		 391static ssize_t radeon_get_pm_method(struct device *dev,
392 struct device_attribute *attr,
393 char *buf)
a424816f 394{
3e4e2129 395 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 396 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 397 int pm = rdev->pm.pm_method;
a424816f
AD		 398
399 return snprintf(buf, PAGE_SIZE, "%s\n",
da321c8a
AD		 400 (pm == PM_METHOD_DYNPM) ? "dynpm" :
401 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
a424816f
AD		 402}
403
ce8f5370
AD		 404static ssize_t radeon_set_pm_method(struct device *dev,
405 struct device_attribute *attr,
406 const char *buf,
407 size_t count)
a424816f 408{
3e4e2129 409 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 410 struct radeon_device *rdev = ddev->dev_private;
a424816f 411
da321c8a
AD		 412 /* we don't support the legacy modes with dpm */
413 if (rdev->pm.pm_method == PM_METHOD_DPM) {
414 count = -EINVAL;
415 goto fail;
416 }
ce8f5370
AD		 417
418 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 419 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 420 rdev->pm.pm_method = PM_METHOD_DYNPM;
421 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
422 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 423 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 424 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
425 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 426 /* disable dynpm */
427 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
428 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 429 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 430 mutex_unlock(&rdev->pm.mutex);
32c87fca 431 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 432 } else {
1783e4bf 433 count = -EINVAL;
ce8f5370
AD		 434 goto fail;
435 }
436 radeon_pm_compute_clocks(rdev);
437fail:
a424816f
AD		 438 return count;
439}
440
da321c8a
AD		 441static ssize_t radeon_get_dpm_state(struct device *dev,
442 struct device_attribute *attr,
443 char *buf)
444{
3e4e2129 445 struct drm_device *ddev = dev_get_drvdata(dev);
da321c8a
AD		 446 struct radeon_device *rdev = ddev->dev_private;
447 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
448
449 return snprintf(buf, PAGE_SIZE, "%s\n",
450 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
451 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
452}
453
454static ssize_t radeon_set_dpm_state(struct device *dev,
455 struct device_attribute *attr,
456 const char *buf,
457 size_t count)
458{
3e4e2129 459 struct drm_device *ddev = dev_get_drvdata(dev);
da321c8a
AD		 460 struct radeon_device *rdev = ddev->dev_private;
461
462 mutex_lock(&rdev->pm.mutex);
463 if (strncmp("battery", buf, strlen("battery")) == 0)
464 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
465 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
466 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
467 else if (strncmp("performance", buf, strlen("performance")) == 0)
468 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
469 else {
470 mutex_unlock(&rdev->pm.mutex);
471 count = -EINVAL;
472 goto fail;
473 }
474 mutex_unlock(&rdev->pm.mutex);
475 radeon_pm_compute_clocks(rdev);
476fail:
477 return count;
478}
479
70d01a5e
AD		 480static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
481 struct device_attribute *attr,
482 char *buf)
483{
3e4e2129 484 struct drm_device *ddev = dev_get_drvdata(dev);
70d01a5e
AD		 485 struct radeon_device *rdev = ddev->dev_private;
486 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
487
488 return snprintf(buf, PAGE_SIZE, "%s\n",
489 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
490 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
491}
492
493static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
494 struct device_attribute *attr,
495 const char *buf,
496 size_t count)
497{
3e4e2129 498 struct drm_device *ddev = dev_get_drvdata(dev);
70d01a5e
AD		 499 struct radeon_device *rdev = ddev->dev_private;
500 enum radeon_dpm_forced_level level;
501 int ret = 0;
502
503 mutex_lock(&rdev->pm.mutex);
504 if (strncmp("low", buf, strlen("low")) == 0) {
505 level = RADEON_DPM_FORCED_LEVEL_LOW;
506 } else if (strncmp("high", buf, strlen("high")) == 0) {
507 level = RADEON_DPM_FORCED_LEVEL_HIGH;
508 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
509 level = RADEON_DPM_FORCED_LEVEL_AUTO;
510 } else {
70d01a5e
AD		 511 count = -EINVAL;
512 goto fail;
513 }
514 if (rdev->asic->dpm.force_performance_level) {
0a17af37
AD		 515 if (rdev->pm.dpm.thermal_active) {
516 count = -EINVAL;
517 goto fail;
518 }
70d01a5e
AD		 519 ret = radeon_dpm_force_performance_level(rdev, level);
520 if (ret)
521 count = -EINVAL;
522 }
70d01a5e 523fail:
0a17af37
AD		 524 mutex_unlock(&rdev->pm.mutex);
525
70d01a5e
AD		 526 return count;
527}
528
ce8f5370
AD		 529static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
530static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
da321c8a 531static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
70d01a5e
AD		 532static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
533 radeon_get_dpm_forced_performance_level,
534 radeon_set_dpm_forced_performance_level);
a424816f 535
21a8122a
AD		 536static ssize_t radeon_hwmon_show_temp(struct device *dev,
537 struct device_attribute *attr,
538 char *buf)
539{
ec39f64b 540 struct radeon_device *rdev = dev_get_drvdata(dev);
20d391d7 541 int temp;
21a8122a 542
6bd1c385
AD		 543 if (rdev->asic->pm.get_temperature)
544 temp = radeon_get_temperature(rdev);
545 else
21a8122a 546 temp = 0;
21a8122a
AD		 547
548 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
549}
550
6ea4e84d
JD		 551static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
552 struct device_attribute *attr,
553 char *buf)
554{
555 struct drm_device *ddev = dev_get_drvdata(dev);
556 struct radeon_device *rdev = ddev->dev_private;
557 int hyst = to_sensor_dev_attr(attr)->index;
558 int temp;
559
560 if (hyst)
561 temp = rdev->pm.dpm.thermal.min_temp;
562 else
563 temp = rdev->pm.dpm.thermal.max_temp;
564
565 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
566}
567
21a8122a 568static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
6ea4e84d
JD		 569static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
570static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
21a8122a
AD		 571
572static struct attribute *hwmon_attributes[] = {
573 &sensor_dev_attr_temp1_input.dev_attr.attr,
6ea4e84d
JD		 574 &sensor_dev_attr_temp1_crit.dev_attr.attr,
575 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
21a8122a
AD		 576 NULL
577};
578
6ea4e84d
JD		 579static umode_t hwmon_attributes_visible(struct kobject *kobj,
580 struct attribute *attr, int index)
581{
582 struct device *dev = container_of(kobj, struct device, kobj);
583 struct drm_device *ddev = dev_get_drvdata(dev);
584 struct radeon_device *rdev = ddev->dev_private;
585
586 /* Skip limit attributes if DPM is not enabled */
587 if (rdev->pm.pm_method != PM_METHOD_DPM &&
588 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
589 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
590 return 0;
591
592 return attr->mode;
593}
594
21a8122a
AD		 595static const struct attribute_group hwmon_attrgroup = {
596 .attrs = hwmon_attributes,
6ea4e84d 597 .is_visible = hwmon_attributes_visible,
21a8122a
AD		 598};
599
ec39f64b
GR		 600static const struct attribute_group *hwmon_groups[] = {
601 &hwmon_attrgroup,
602 NULL
603};
604
0d18abed 605static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 606{
0d18abed 607 int err = 0;
ec39f64b 608 struct device *hwmon_dev;
21a8122a
AD		 609
610 switch (rdev->pm.int_thermal_type) {
611 case THERMAL_TYPE_RV6XX:
612 case THERMAL_TYPE_RV770:
613 case THERMAL_TYPE_EVERGREEN:
457558ed 614 case THERMAL_TYPE_NI:
e33df25f 615 case THERMAL_TYPE_SUMO:
1bd47d2e 616 case THERMAL_TYPE_SI:
286d9cc6
AD		 617 case THERMAL_TYPE_CI:
618 case THERMAL_TYPE_KV:
6bd1c385 619 if (rdev->asic->pm.get_temperature == NULL)
5d7486c7 620 return err;
ec39f64b
GR		 621 hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
622 "radeon", rdev,
623 hwmon_groups);
624 if (IS_ERR(hwmon_dev)) {
625 err = PTR_ERR(hwmon_dev);
0d18abed
DC		 626 dev_err(rdev->dev,
627 "Unable to register hwmon device: %d\n", err);
0d18abed 628 }
21a8122a
AD		 629 break;
630 default:
631 break;
632 }
0d18abed
DC		 633
634 return err;
21a8122a
AD		 635}
636
da321c8a
AD		 637static void radeon_dpm_thermal_work_handler(struct work_struct *work)
638{
639 struct radeon_device *rdev =
640 container_of(work, struct radeon_device,
641 pm.dpm.thermal.work);
642 /* switch to the thermal state */
643 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
644
645 if (!rdev->pm.dpm_enabled)
646 return;
647
648 if (rdev->asic->pm.get_temperature) {
649 int temp = radeon_get_temperature(rdev);
650
651 if (temp < rdev->pm.dpm.thermal.min_temp)
652 /* switch back the user state */
653 dpm_state = rdev->pm.dpm.user_state;
654 } else {
655 if (rdev->pm.dpm.thermal.high_to_low)
656 /* switch back the user state */
657 dpm_state = rdev->pm.dpm.user_state;
658 }
60320347
AD		 659 mutex_lock(&rdev->pm.mutex);
660 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
661 rdev->pm.dpm.thermal_active = true;
662 else
663 rdev->pm.dpm.thermal_active = false;
664 rdev->pm.dpm.state = dpm_state;
665 mutex_unlock(&rdev->pm.mutex);
666
667 radeon_pm_compute_clocks(rdev);
da321c8a
AD		 668}
669
670static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
671 enum radeon_pm_state_type dpm_state)
672{
673 int i;
674 struct radeon_ps *ps;
675 u32 ui_class;
48783069
AD		 676 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
677 true : false;
678
679 /* check if the vblank period is too short to adjust the mclk */
680 if (single_display && rdev->asic->dpm.vblank_too_short) {
681 if (radeon_dpm_vblank_too_short(rdev))
682 single_display = false;
683 }
da321c8a 684
edcaa5b1
AD		 685 /* certain older asics have a separare 3D performance state,
686 * so try that first if the user selected performance
687 */
688 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
689 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
da321c8a
AD		 690 /* balanced states don't exist at the moment */
691 if (dpm_state == POWER_STATE_TYPE_BALANCED)
692 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
693
edcaa5b1 694restart_search:
da321c8a
AD		 695 /* Pick the best power state based on current conditions */
696 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
697 ps = &rdev->pm.dpm.ps[i];
698 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
699 switch (dpm_state) {
700 /* user states */
701 case POWER_STATE_TYPE_BATTERY:
702 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
703 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 704 if (single_display)
da321c8a
AD		 705 return ps;
706 } else
707 return ps;
708 }
709 break;
710 case POWER_STATE_TYPE_BALANCED:
711 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
712 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 713 if (single_display)
da321c8a
AD		 714 return ps;
715 } else
716 return ps;
717 }
718 break;
719 case POWER_STATE_TYPE_PERFORMANCE:
720 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
721 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 722 if (single_display)
da321c8a
AD		 723 return ps;
724 } else
725 return ps;
726 }
727 break;
728 /* internal states */
729 case POWER_STATE_TYPE_INTERNAL_UVD:
d4d3278c
AD		 730 if (rdev->pm.dpm.uvd_ps)
731 return rdev->pm.dpm.uvd_ps;
732 else
733 break;
da321c8a
AD		 734 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
735 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
736 return ps;
737 break;
738 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
739 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
740 return ps;
741 break;
742 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
743 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
744 return ps;
745 break;
746 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
747 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
748 return ps;
749 break;
750 case POWER_STATE_TYPE_INTERNAL_BOOT:
751 return rdev->pm.dpm.boot_ps;
752 case POWER_STATE_TYPE_INTERNAL_THERMAL:
753 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
754 return ps;
755 break;
756 case POWER_STATE_TYPE_INTERNAL_ACPI:
757 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
758 return ps;
759 break;
760 case POWER_STATE_TYPE_INTERNAL_ULV:
761 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
762 return ps;
763 break;
edcaa5b1
AD		 764 case POWER_STATE_TYPE_INTERNAL_3DPERF:
765 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
766 return ps;
767 break;
da321c8a
AD		 768 default:
769 break;
770 }
771 }
772 /* use a fallback state if we didn't match */
773 switch (dpm_state) {
774 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
ce3537d5
AD		 775 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
776 goto restart_search;
da321c8a
AD		 777 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
778 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
779 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
d4d3278c
AD		 780 if (rdev->pm.dpm.uvd_ps) {
781 return rdev->pm.dpm.uvd_ps;
782 } else {
783 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
784 goto restart_search;
785 }
da321c8a
AD		 786 case POWER_STATE_TYPE_INTERNAL_THERMAL:
787 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
788 goto restart_search;
789 case POWER_STATE_TYPE_INTERNAL_ACPI:
790 dpm_state = POWER_STATE_TYPE_BATTERY;
791 goto restart_search;
792 case POWER_STATE_TYPE_BATTERY:
edcaa5b1
AD		 793 case POWER_STATE_TYPE_BALANCED:
794 case POWER_STATE_TYPE_INTERNAL_3DPERF:
da321c8a
AD		 795 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
796 goto restart_search;
797 default:
798 break;
799 }
800
801 return NULL;
802}
803
804static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
805{
806 int i;
807 struct radeon_ps *ps;
808 enum radeon_pm_state_type dpm_state;
84dd1928 809 int ret;
da321c8a
AD		 810
811 /* if dpm init failed */
812 if (!rdev->pm.dpm_enabled)
813 return;
814
815 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
816 /* add other state override checks here */
8a227555
AD		 817 if ((!rdev->pm.dpm.thermal_active) &&
818 (!rdev->pm.dpm.uvd_active))
da321c8a
AD		 819 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
820 }
821 dpm_state = rdev->pm.dpm.state;
822
823 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
824 if (ps)
89c9bc56 825 rdev->pm.dpm.requested_ps = ps;
da321c8a
AD		 826 else
827 return;
828
d22b7e40 829 /* no need to reprogram if nothing changed unless we are on BTC+ */
da321c8a 830 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
d22b7e40
AD		 831 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
832 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
833 * all we need to do is update the display configuration.
834 */
835 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
836 /* update display watermarks based on new power state */
837 radeon_bandwidth_update(rdev);
838 /* update displays */
839 radeon_dpm_display_configuration_changed(rdev);
840 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
841 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
842 }
843 return;
844 } else {
845 /* for BTC+ if the num crtcs hasn't changed and state is the same,
846 * nothing to do, if the num crtcs is > 1 and state is the same,
847 * update display configuration.
848 */
849 if (rdev->pm.dpm.new_active_crtcs ==
850 rdev->pm.dpm.current_active_crtcs) {
851 return;
852 } else {
853 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
854 (rdev->pm.dpm.new_active_crtc_count > 1)) {
855 /* update display watermarks based on new power state */
856 radeon_bandwidth_update(rdev);
857 /* update displays */
858 radeon_dpm_display_configuration_changed(rdev);
859 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
860 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
861 return;
862 }
863 }
da321c8a 864 }
da321c8a
AD		 865 }
866
033a37df
AD		 867 if (radeon_dpm == 1) {
868 printk("switching from power state:\n");
869 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
870 printk("switching to power state:\n");
871 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
872 }
da321c8a
AD		 873 mutex_lock(&rdev->ddev->struct_mutex);
874 down_write(&rdev->pm.mclk_lock);
875 mutex_lock(&rdev->ring_lock);
876
89c9bc56
AD		 877 ret = radeon_dpm_pre_set_power_state(rdev);
878 if (ret)
879 goto done;
84dd1928 880
da321c8a
AD		 881 /* update display watermarks based on new power state */
882 radeon_bandwidth_update(rdev);
883 /* update displays */
884 radeon_dpm_display_configuration_changed(rdev);
885
886 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
887 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
888
889 /* wait for the rings to drain */
890 for (i = 0; i < RADEON_NUM_RINGS; i++) {
891 struct radeon_ring *ring = &rdev->ring[i];
892 if (ring->ready)
893 radeon_fence_wait_empty_locked(rdev, i);
894 }
895
896 /* program the new power state */
897 radeon_dpm_set_power_state(rdev);
898
899 /* update current power state */
900 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
901
89c9bc56 902 radeon_dpm_post_set_power_state(rdev);
84dd1928 903
1cd8b21a 904 if (rdev->asic->dpm.force_performance_level) {
14ac88af
AD		 905 if (rdev->pm.dpm.thermal_active) {
906 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1cd8b21a
AD		 907 /* force low perf level for thermal */
908 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
14ac88af
AD		 909 /* save the user's level */
910 rdev->pm.dpm.forced_level = level;
911 } else {
912 /* otherwise, user selected level */
913 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
914 }
60320347
AD		 915 }
916
84dd1928 917done:
da321c8a
AD		 918 mutex_unlock(&rdev->ring_lock);
919 up_write(&rdev->pm.mclk_lock);
920 mutex_unlock(&rdev->ddev->struct_mutex);
921}
922
ce3537d5
AD		 923void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
924{
925 enum radeon_pm_state_type dpm_state;
926
9e9d9762 927 if (rdev->asic->dpm.powergate_uvd) {
ce3537d5 928 mutex_lock(&rdev->pm.mutex);
9e9d9762
AD		 929 /* enable/disable UVD */
930 radeon_dpm_powergate_uvd(rdev, !enable);
ce3537d5
AD		 931 mutex_unlock(&rdev->pm.mutex);
932 } else {
9e9d9762
AD		 933 if (enable) {
934 mutex_lock(&rdev->pm.mutex);
935 rdev->pm.dpm.uvd_active = true;
dca5086a
AD		 936 /* disable this for now */
937#if 0
9e9d9762
AD		 938 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
939 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
940 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
941 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
942 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
943 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
944 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
945 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
946 else
dca5086a 947#endif
9e9d9762
AD		 948 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
949 rdev->pm.dpm.state = dpm_state;
950 mutex_unlock(&rdev->pm.mutex);
951 } else {
952 mutex_lock(&rdev->pm.mutex);
953 rdev->pm.dpm.uvd_active = false;
954 mutex_unlock(&rdev->pm.mutex);
955 }
ce3537d5 956
9e9d9762
AD		 957 radeon_pm_compute_clocks(rdev);
958 }
ce3537d5
AD		 959}
960
da321c8a 961static void radeon_pm_suspend_old(struct radeon_device *rdev)
56278a8e 962{
ce8f5370 963 mutex_lock(&rdev->pm.mutex);
3f53eb6f 964 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 965 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
966 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 967 }
ce8f5370 968 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 969
970 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 971}
972
da321c8a
AD		 973static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
974{
975 mutex_lock(&rdev->pm.mutex);
976 /* disable dpm */
977 radeon_dpm_disable(rdev);
978 /* reset the power state */
979 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
980 rdev->pm.dpm_enabled = false;
981 mutex_unlock(&rdev->pm.mutex);
982}
983
984void radeon_pm_suspend(struct radeon_device *rdev)
985{
986 if (rdev->pm.pm_method == PM_METHOD_DPM)
987 radeon_pm_suspend_dpm(rdev);
988 else
989 radeon_pm_suspend_old(rdev);
990}
991
992static void radeon_pm_resume_old(struct radeon_device *rdev)
d0d6cb81 993{
ed18a360 994 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 995 if ((rdev->family >= CHIP_BARTS) &&
36099186 996 (rdev->family <= CHIP_CAYMAN) &&
2e3b3b10 997 rdev->mc_fw) {
ed18a360 998 if (rdev->pm.default_vddc)
8a83ec5e
AD		 999 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1000 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 1001 if (rdev->pm.default_vddci)
1002 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1003 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1004 if (rdev->pm.default_sclk)
1005 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1006 if (rdev->pm.default_mclk)
1007 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1008 }
f8ed8b4c
AD		 1009 /* asic init will reset the default power state */
1010 mutex_lock(&rdev->pm.mutex);
1011 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1012 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 1013 rdev->pm.current_sclk = rdev->pm.default_sclk;
1014 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 1015 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 1016 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 1017 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1018 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1019 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1020 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1021 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 1022 }
f8ed8b4c 1023 mutex_unlock(&rdev->pm.mutex);
ce8f5370 1024 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 1025}
1026
da321c8a
AD		 1027static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1028{
1029 int ret;
1030
1031 /* asic init will reset to the boot state */
1032 mutex_lock(&rdev->pm.mutex);
1033 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1034 radeon_dpm_setup_asic(rdev);
1035 ret = radeon_dpm_enable(rdev);
1036 mutex_unlock(&rdev->pm.mutex);
1037 if (ret) {
1038 DRM_ERROR("radeon: dpm resume failed\n");
1039 if ((rdev->family >= CHIP_BARTS) &&
36099186 1040 (rdev->family <= CHIP_CAYMAN) &&
da321c8a
AD		 1041 rdev->mc_fw) {
1042 if (rdev->pm.default_vddc)
1043 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1044 SET_VOLTAGE_TYPE_ASIC_VDDC);
1045 if (rdev->pm.default_vddci)
1046 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1047 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1048 if (rdev->pm.default_sclk)
1049 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1050 if (rdev->pm.default_mclk)
1051 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1052 }
1053 } else {
1054 rdev->pm.dpm_enabled = true;
1055 radeon_pm_compute_clocks(rdev);
1056 }
1057}
1058
1059void radeon_pm_resume(struct radeon_device *rdev)
1060{
1061 if (rdev->pm.pm_method == PM_METHOD_DPM)
1062 radeon_pm_resume_dpm(rdev);
1063 else
1064 radeon_pm_resume_old(rdev);
1065}
1066
1067static int radeon_pm_init_old(struct radeon_device *rdev)
7433874e 1068{
26481fb1 1069 int ret;
0d18abed 1070
f8ed8b4c 1071 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 1072 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1073 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1074 rdev->pm.dynpm_can_upclock = true;
1075 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 1076 rdev->pm.default_sclk = rdev->clock.default_sclk;
1077 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 1078 rdev->pm.current_sclk = rdev->clock.default_sclk;
1079 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 1080 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 1081
56278a8e
AD		 1082 if (rdev->bios) {
1083 if (rdev->is_atom_bios)
1084 radeon_atombios_get_power_modes(rdev);
1085 else
1086 radeon_combios_get_power_modes(rdev);
f712d0c7 1087 radeon_pm_print_states(rdev);
ce8f5370 1088 radeon_pm_init_profile(rdev);
ed18a360 1089 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1090 if ((rdev->family >= CHIP_BARTS) &&
36099186 1091 (rdev->family <= CHIP_CAYMAN) &&
2e3b3b10 1092 rdev->mc_fw) {
ed18a360 1093 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1094 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1095 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 1096 if (rdev->pm.default_vddci)
1097 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1098 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1099 if (rdev->pm.default_sclk)
1100 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1101 if (rdev->pm.default_mclk)
1102 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1103 }
56278a8e
AD		 1104 }
1105
21a8122a 1106 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 1107 ret = radeon_hwmon_init(rdev);
1108 if (ret)
1109 return ret;
32c87fca
TH		 1110
1111 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1112
ce8f5370 1113 if (rdev->pm.num_power_states > 1) {
ce8f5370 1114 /* where's the best place to put these? */
26481fb1
DA		 1115 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1116 if (ret)
1117 DRM_ERROR("failed to create device file for power profile\n");
1118 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1119 if (ret)
1120 DRM_ERROR("failed to create device file for power method\n");
a424816f 1121
ce8f5370
AD		 1122 if (radeon_debugfs_pm_init(rdev)) {
1123 DRM_ERROR("Failed to register debugfs file for PM!\n");
1124 }
c913e23a 1125
ce8f5370
AD		 1126 DRM_INFO("radeon: power management initialized\n");
1127 }
c913e23a 1128
7433874e
RM		 1129 return 0;
1130}
1131
da321c8a
AD		 1132static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1133{
1134 int i;
1135
1136 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1137 printk("== power state %d ==\n", i);
1138 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1139 }
1140}
1141
1142static int radeon_pm_init_dpm(struct radeon_device *rdev)
1143{
1144 int ret;
1145
1cd8b21a 1146 /* default to balanced state */
edcaa5b1
AD		 1147 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1148 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1cd8b21a 1149 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
da321c8a
AD		 1150 rdev->pm.default_sclk = rdev->clock.default_sclk;
1151 rdev->pm.default_mclk = rdev->clock.default_mclk;
1152 rdev->pm.current_sclk = rdev->clock.default_sclk;
1153 rdev->pm.current_mclk = rdev->clock.default_mclk;
1154 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1155
1156 if (rdev->bios && rdev->is_atom_bios)
1157 radeon_atombios_get_power_modes(rdev);
1158 else
1159 return -EINVAL;
1160
1161 /* set up the internal thermal sensor if applicable */
1162 ret = radeon_hwmon_init(rdev);
1163 if (ret)
1164 return ret;
1165
1166 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1167 mutex_lock(&rdev->pm.mutex);
1168 radeon_dpm_init(rdev);
1169 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
033a37df
AD		 1170 if (radeon_dpm == 1)
1171 radeon_dpm_print_power_states(rdev);
da321c8a
AD		 1172 radeon_dpm_setup_asic(rdev);
1173 ret = radeon_dpm_enable(rdev);
1174 mutex_unlock(&rdev->pm.mutex);
1175 if (ret) {
1176 rdev->pm.dpm_enabled = false;
1177 if ((rdev->family >= CHIP_BARTS) &&
36099186 1178 (rdev->family <= CHIP_CAYMAN) &&
da321c8a
AD		 1179 rdev->mc_fw) {
1180 if (rdev->pm.default_vddc)
1181 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1182 SET_VOLTAGE_TYPE_ASIC_VDDC);
1183 if (rdev->pm.default_vddci)
1184 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1185 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1186 if (rdev->pm.default_sclk)
1187 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1188 if (rdev->pm.default_mclk)
1189 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1190 }
1191 DRM_ERROR("radeon: dpm initialization failed\n");
1192 return ret;
1193 }
1194 rdev->pm.dpm_enabled = true;
1195 radeon_pm_compute_clocks(rdev);
1196
1197 if (rdev->pm.num_power_states > 1) {
1198 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
70d01a5e
AD		 1199 if (ret)
1200 DRM_ERROR("failed to create device file for dpm state\n");
1201 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
da321c8a
AD		 1202 if (ret)
1203 DRM_ERROR("failed to create device file for dpm state\n");
1204 /* XXX: these are noops for dpm but are here for backwards compat */
1205 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1206 if (ret)
1207 DRM_ERROR("failed to create device file for power profile\n");
1208 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1209 if (ret)
1210 DRM_ERROR("failed to create device file for power method\n");
1316b792
AD		 1211
1212 if (radeon_debugfs_pm_init(rdev)) {
1213 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1214 }
1215
da321c8a
AD		 1216 DRM_INFO("radeon: dpm initialized\n");
1217 }
1218
1219 return 0;
1220}
1221
1222int radeon_pm_init(struct radeon_device *rdev)
1223{
1224 /* enable dpm on rv6xx+ */
1225 switch (rdev->family) {
4a6369e9
AD		 1226 case CHIP_RV610:
1227 case CHIP_RV630:
1228 case CHIP_RV620:
1229 case CHIP_RV635:
1230 case CHIP_RV670:
9d67006e
AD		 1231 case CHIP_RS780:
1232 case CHIP_RS880:
69e0b57a 1233 case CHIP_CAYMAN:
cc8dbbb4 1234 case CHIP_BONAIRE:
41a524ab
AD		 1235 case CHIP_KABINI:
1236 case CHIP_KAVERI:
2d40038d 1237 case CHIP_HAWAII:
8a53fa23 1238 /* DPM requires the RLC, RV770+ dGPU requires SMC */
761bfb99
AD		 1239 if (!rdev->rlc_fw)
1240 rdev->pm.pm_method = PM_METHOD_PROFILE;
8a53fa23
AD		 1241 else if ((rdev->family >= CHIP_RV770) &&
1242 (!(rdev->flags & RADEON_IS_IGP)) &&
1243 (!rdev->smc_fw))
1244 rdev->pm.pm_method = PM_METHOD_PROFILE;
761bfb99 1245 else if (radeon_dpm == 1)
9d67006e
AD		 1246 rdev->pm.pm_method = PM_METHOD_DPM;
1247 else
1248 rdev->pm.pm_method = PM_METHOD_PROFILE;
1249 break;
ab70b1dd
AD		 1250 case CHIP_RV770:
1251 case CHIP_RV730:
1252 case CHIP_RV710:
1253 case CHIP_RV740:
59f7a2f2
AD		 1254 case CHIP_CEDAR:
1255 case CHIP_REDWOOD:
1256 case CHIP_JUNIPER:
1257 case CHIP_CYPRESS:
1258 case CHIP_HEMLOCK:
5a16f761
AD		 1259 case CHIP_PALM:
1260 case CHIP_SUMO:
1261 case CHIP_SUMO2:
56684ec5
AD		 1262 case CHIP_BARTS:
1263 case CHIP_TURKS:
1264 case CHIP_CAICOS:
3a118989 1265 case CHIP_ARUBA:
68bc7785
AD		 1266 case CHIP_TAHITI:
1267 case CHIP_PITCAIRN:
1268 case CHIP_VERDE:
1269 case CHIP_OLAND:
1270 case CHIP_HAINAN:
5a16f761
AD		 1271 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1272 if (!rdev->rlc_fw)
1273 rdev->pm.pm_method = PM_METHOD_PROFILE;
1274 else if ((rdev->family >= CHIP_RV770) &&
1275 (!(rdev->flags & RADEON_IS_IGP)) &&
1276 (!rdev->smc_fw))
1277 rdev->pm.pm_method = PM_METHOD_PROFILE;
1278 else if (radeon_dpm == 0)
1279 rdev->pm.pm_method = PM_METHOD_PROFILE;
1280 else
1281 rdev->pm.pm_method = PM_METHOD_DPM;
1282 break;
da321c8a
AD		 1283 default:
1284 /* default to profile method */
1285 rdev->pm.pm_method = PM_METHOD_PROFILE;
1286 break;
1287 }
1288
1289 if (rdev->pm.pm_method == PM_METHOD_DPM)
1290 return radeon_pm_init_dpm(rdev);
1291 else
1292 return radeon_pm_init_old(rdev);
1293}
1294
1295static void radeon_pm_fini_old(struct radeon_device *rdev)
29fb52ca 1296{
ce8f5370 1297 if (rdev->pm.num_power_states > 1) {
a424816f 1298 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 1299 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1300 rdev->pm.profile = PM_PROFILE_DEFAULT;
1301 radeon_pm_update_profile(rdev);
1302 radeon_pm_set_clocks(rdev);
1303 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 1304 /* reset default clocks */
1305 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1306 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1307 radeon_pm_set_clocks(rdev);
1308 }
a424816f 1309 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1310
1311 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 1312
ce8f5370
AD		 1313 device_remove_file(rdev->dev, &dev_attr_power_profile);
1314 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 1315 }
a424816f 1316
0975b162
AD		 1317 if (rdev->pm.power_state)
1318 kfree(rdev->pm.power_state);
29fb52ca
AD		 1319}
1320
da321c8a
AD		 1321static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1322{
1323 if (rdev->pm.num_power_states > 1) {
1324 mutex_lock(&rdev->pm.mutex);
1325 radeon_dpm_disable(rdev);
1326 mutex_unlock(&rdev->pm.mutex);
1327
1328 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
70d01a5e 1329 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
da321c8a
AD		 1330 /* XXX backwards compat */
1331 device_remove_file(rdev->dev, &dev_attr_power_profile);
1332 device_remove_file(rdev->dev, &dev_attr_power_method);
1333 }
1334 radeon_dpm_fini(rdev);
1335
1336 if (rdev->pm.power_state)
1337 kfree(rdev->pm.power_state);
da321c8a
AD		 1338}
1339
1340void radeon_pm_fini(struct radeon_device *rdev)
1341{
1342 if (rdev->pm.pm_method == PM_METHOD_DPM)
1343 radeon_pm_fini_dpm(rdev);
1344 else
1345 radeon_pm_fini_old(rdev);
1346}
1347
1348static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
c913e23a
RM		 1349{
1350 struct drm_device *ddev = rdev->ddev;
a48b9b4e 1351 struct drm_crtc *crtc;
c913e23a 1352 struct radeon_crtc *radeon_crtc;
c913e23a 1353
ce8f5370
AD		 1354 if (rdev->pm.num_power_states < 2)
1355 return;
1356
c913e23a
RM		 1357 mutex_lock(&rdev->pm.mutex);
1358
1359 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 1360 rdev->pm.active_crtc_count = 0;
1361 list_for_each_entry(crtc,
1362 &ddev->mode_config.crtc_list, head) {
1363 radeon_crtc = to_radeon_crtc(crtc);
1364 if (radeon_crtc->enabled) {
c913e23a 1365 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 1366 rdev->pm.active_crtc_count++;
c913e23a
RM		 1367 }
1368 }
1369
ce8f5370
AD		 1370 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1371 radeon_pm_update_profile(rdev);
1372 radeon_pm_set_clocks(rdev);
1373 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1374 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1375 if (rdev->pm.active_crtc_count > 1) {
1376 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1377 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1378
1379 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1380 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1381 radeon_pm_get_dynpm_state(rdev);
1382 radeon_pm_set_clocks(rdev);
1383
d9fdaafb 1384 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 1385 }
1386 } else if (rdev->pm.active_crtc_count == 1) {
1387 /* TODO: Increase clocks if needed for current mode */
1388
1389 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1390 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1391 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1392 radeon_pm_get_dynpm_state(rdev);
1393 radeon_pm_set_clocks(rdev);
1394
32c87fca
TH		 1395 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1396 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 1397 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1398 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1399 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1400 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 1401 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 1402 }
1403 } else { /* count == 0 */
1404 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1405 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1406
1407 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1408 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1409 radeon_pm_get_dynpm_state(rdev);
1410 radeon_pm_set_clocks(rdev);
1411 }
1412 }
c913e23a 1413 }
c913e23a 1414 }
73a6d3fc
RM		 1415
1416 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 1417}
1418
da321c8a
AD		 1419static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1420{
1421 struct drm_device *ddev = rdev->ddev;
1422 struct drm_crtc *crtc;
1423 struct radeon_crtc *radeon_crtc;
1424
1425 mutex_lock(&rdev->pm.mutex);
1426
5ca302f7 1427 /* update active crtc counts */
da321c8a
AD		 1428 rdev->pm.dpm.new_active_crtcs = 0;
1429 rdev->pm.dpm.new_active_crtc_count = 0;
1430 list_for_each_entry(crtc,
1431 &ddev->mode_config.crtc_list, head) {
1432 radeon_crtc = to_radeon_crtc(crtc);
1433 if (crtc->enabled) {
1434 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1435 rdev->pm.dpm.new_active_crtc_count++;
1436 }
1437 }
1438
5ca302f7
AD		 1439 /* update battery/ac status */
1440 if (power_supply_is_system_supplied() > 0)
1441 rdev->pm.dpm.ac_power = true;
1442 else
1443 rdev->pm.dpm.ac_power = false;
1444
da321c8a
AD		 1445 radeon_dpm_change_power_state_locked(rdev);
1446
1447 mutex_unlock(&rdev->pm.mutex);
8a227555 1448
da321c8a
AD		 1449}
1450
1451void radeon_pm_compute_clocks(struct radeon_device *rdev)
1452{
1453 if (rdev->pm.pm_method == PM_METHOD_DPM)
1454 radeon_pm_compute_clocks_dpm(rdev);
1455 else
1456 radeon_pm_compute_clocks_old(rdev);
1457}
1458
ce8f5370 1459static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 1460{
75fa0b08 1461 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 1462 bool in_vbl = true;
1463
75fa0b08
MK		 1464 /* Iterate over all active crtc's. All crtc's must be in vblank,
1465 * otherwise return in_vbl == false.
1466 */
1467 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1468 if (rdev->pm.active_crtcs & (1 << crtc)) {
d47abc58 1469 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos, NULL, NULL);
f5a80209
MK		 1470 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1471 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 1472 in_vbl = false;
1473 }
1474 }
f81f2024
MG		 1475
1476 return in_vbl;
1477}
1478
ce8f5370 1479static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 1480{
1481 u32 stat_crtc = 0;
1482 bool in_vbl = radeon_pm_in_vbl(rdev);
1483
f735261b 1484 if (in_vbl == false)
d9fdaafb 1485 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 1486 finish ? "exit" : "entry");
f735261b
DA		 1487 return in_vbl;
1488}
c913e23a 1489
ce8f5370 1490static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 1491{
1492 struct radeon_device *rdev;
d9932a32 1493 int resched;
c913e23a 1494 rdev = container_of(work, struct radeon_device,
ce8f5370 1495 pm.dynpm_idle_work.work);
c913e23a 1496
d9932a32 1497 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 1498 mutex_lock(&rdev->pm.mutex);
ce8f5370 1499 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 1500 int not_processed = 0;
7465280c
AD		 1501 int i;
1502
7465280c 1503 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 1504 struct radeon_ring *ring = &rdev->ring[i];
1505
1506 if (ring->ready) {
1507 not_processed += radeon_fence_count_emitted(rdev, i);
1508 if (not_processed >= 3)
1509 break;
1510 }
c913e23a 1511 }
c913e23a
RM		 1512
1513 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 1514 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1515 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1516 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1517 rdev->pm.dynpm_can_upclock) {
1518 rdev->pm.dynpm_planned_action =
1519 DYNPM_ACTION_UPCLOCK;
1520 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1521 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1522 }
1523 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 1524 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1525 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1526 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1527 rdev->pm.dynpm_can_downclock) {
1528 rdev->pm.dynpm_planned_action =
1529 DYNPM_ACTION_DOWNCLOCK;
1530 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1531 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1532 }
1533 }
1534
d7311171
AD		 1535 /* Note, radeon_pm_set_clocks is called with static_switch set
1536 * to false since we want to wait for vbl to avoid flicker.
1537 */
ce8f5370
AD		 1538 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1539 jiffies > rdev->pm.dynpm_action_timeout) {
1540 radeon_pm_get_dynpm_state(rdev);
1541 radeon_pm_set_clocks(rdev);
c913e23a 1542 }
3f53eb6f 1543
32c87fca
TH		 1544 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1545 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 1546 }
1547 mutex_unlock(&rdev->pm.mutex);
d9932a32 1548 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 1549}
1550
7433874e
RM		 1551/*
1552 * Debugfs info
1553 */
1554#if defined(CONFIG_DEBUG_FS)
1555
1556static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1557{
1558 struct drm_info_node *node = (struct drm_info_node *) m->private;
1559 struct drm_device *dev = node->minor->dev;
1560 struct radeon_device *rdev = dev->dev_private;
1561
1316b792
AD		 1562 if (rdev->pm.dpm_enabled) {
1563 mutex_lock(&rdev->pm.mutex);
1564 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1565 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1566 else
71375929 1567 seq_printf(m, "Debugfs support not implemented for this asic\n");
1316b792
AD		 1568 mutex_unlock(&rdev->pm.mutex);
1569 } else {
1570 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1571 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1572 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1573 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1574 else
1575 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1576 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1577 if (rdev->asic->pm.get_memory_clock)
1578 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1579 if (rdev->pm.current_vddc)
1580 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1581 if (rdev->asic->pm.get_pcie_lanes)
1582 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1583 }
7433874e
RM		 1584
1585 return 0;
1586}
1587
1588static struct drm_info_list radeon_pm_info_list[] = {
1589 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1590};
1591#endif
1592
c913e23a 1593static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 1594{
1595#if defined(CONFIG_DEBUG_FS)
1596 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1597#else
1598 return 0;
1599#endif
1600}
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