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drm/radeon/dpm: add helper to calculate vblank time
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370 27#include <linux/power_supply.h>
21a8122a
AD		 28#include <linux/hwmon.h>
29#include <linux/hwmon-sysfs.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 34
f712d0c7 35static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 36 "",
f712d0c7
RM		 37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41};
42
ce8f5370 43static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 44static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 45static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47static void radeon_pm_update_profile(struct radeon_device *rdev);
48static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
a4c9e2ee
AD		 50int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53{
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66}
67
c4917074 68void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 69{
c4917074
AD		 70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71 if (rdev->pm.profile == PM_PROFILE_AUTO) {
72 mutex_lock(&rdev->pm.mutex);
73 radeon_pm_update_profile(rdev);
74 radeon_pm_set_clocks(rdev);
75 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 76 }
77 }
ce8f5370 78}
ce8f5370
AD		 79
80static void radeon_pm_update_profile(struct radeon_device *rdev)
81{
82 switch (rdev->pm.profile) {
83 case PM_PROFILE_DEFAULT:
84 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
85 break;
86 case PM_PROFILE_AUTO:
87 if (power_supply_is_system_supplied() > 0) {
88 if (rdev->pm.active_crtc_count > 1)
89 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
90 else
91 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
92 } else {
93 if (rdev->pm.active_crtc_count > 1)
c9e75b21 94 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 95 else
c9e75b21 96 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 97 }
98 break;
99 case PM_PROFILE_LOW:
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
104 break;
c9e75b21
AD		 105 case PM_PROFILE_MID:
106 if (rdev->pm.active_crtc_count > 1)
107 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
108 else
109 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
110 break;
ce8f5370
AD		 111 case PM_PROFILE_HIGH:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
116 break;
117 }
118
119 if (rdev->pm.active_crtc_count == 0) {
120 rdev->pm.requested_power_state_index =
121 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
122 rdev->pm.requested_clock_mode_index =
123 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
124 } else {
125 rdev->pm.requested_power_state_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
127 rdev->pm.requested_clock_mode_index =
128 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
129 }
130}
c913e23a 131
5876dd24
MG		 132static void radeon_unmap_vram_bos(struct radeon_device *rdev)
133{
134 struct radeon_bo *bo, *n;
135
136 if (list_empty(&rdev->gem.objects))
137 return;
138
139 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
140 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
141 ttm_bo_unmap_virtual(&bo->tbo);
142 }
5876dd24
MG		 143}
144
ce8f5370 145static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 146{
ce8f5370
AD		 147 if (rdev->pm.active_crtcs) {
148 rdev->pm.vblank_sync = false;
149 wait_event_timeout(
150 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
152 }
153}
154
155static void radeon_set_power_state(struct radeon_device *rdev)
156{
157 u32 sclk, mclk;
92645879 158 bool misc_after = false;
ce8f5370
AD		 159
160 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
161 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
162 return;
163
164 if (radeon_gui_idle(rdev)) {
165 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
166 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 167 if (sclk > rdev->pm.default_sclk)
168 sclk = rdev->pm.default_sclk;
ce8f5370 169
27810fb2
AD		 170 /* starting with BTC, there is one state that is used for both
171 * MH and SH. Difference is that we always use the high clock index for
7ae764b1 172 * mclk and vddci.
27810fb2
AD		 173 */
174 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
175 (rdev->family >= CHIP_BARTS) &&
176 rdev->pm.active_crtc_count &&
177 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
178 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
179 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
180 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
181 else
182 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].mclk;
184
9ace9f7b
AD		 185 if (mclk > rdev->pm.default_mclk)
186 mclk = rdev->pm.default_mclk;
ce8f5370 187
92645879
AD		 188 /* upvolt before raising clocks, downvolt after lowering clocks */
189 if (sclk < rdev->pm.current_sclk)
190 misc_after = true;
ce8f5370 191
92645879 192 radeon_sync_with_vblank(rdev);
ce8f5370 193
92645879 194 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 195 if (!radeon_pm_in_vbl(rdev))
196 return;
92645879 197 }
ce8f5370 198
92645879 199 radeon_pm_prepare(rdev);
ce8f5370 200
92645879
AD		 201 if (!misc_after)
202 /* voltage, pcie lanes, etc.*/
203 radeon_pm_misc(rdev);
204
205 /* set engine clock */
206 if (sclk != rdev->pm.current_sclk) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_set_engine_clock(rdev, sclk);
209 radeon_pm_debug_check_in_vbl(rdev, true);
210 rdev->pm.current_sclk = sclk;
d9fdaafb 211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 212 }
213
214 /* set memory clock */
798bcf73 215 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_memory_clock(rdev, mclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_mclk = mclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 221 }
2aba631c 222
92645879
AD		 223 if (misc_after)
224 /* voltage, pcie lanes, etc.*/
225 radeon_pm_misc(rdev);
226
227 radeon_pm_finish(rdev);
228
ce8f5370
AD		 229 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
230 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
231 } else
d9fdaafb 232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 233}
234
235static void radeon_pm_set_clocks(struct radeon_device *rdev)
236{
5f8f635e 237 int i, r;
c37d230a 238
4e186b2d
AD		 239 /* no need to take locks, etc. if nothing's going to change */
240 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
241 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
242 return;
243
612e06ce 244 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 245 down_write(&rdev->pm.mclk_lock);
d6999bc7 246 mutex_lock(&rdev->ring_lock);
4f3218cb 247
95f5a3ac
AD		 248 /* wait for the rings to drain */
249 for (i = 0; i < RADEON_NUM_RINGS; i++) {
250 struct radeon_ring *ring = &rdev->ring[i];
5f8f635e
JG		 251 if (!ring->ready) {
252 continue;
253 }
254 r = radeon_fence_wait_empty_locked(rdev, i);
255 if (r) {
256 /* needs a GPU reset dont reset here */
257 mutex_unlock(&rdev->ring_lock);
258 up_write(&rdev->pm.mclk_lock);
259 mutex_unlock(&rdev->ddev->struct_mutex);
260 return;
261 }
4f3218cb 262 }
95f5a3ac 263
5876dd24
MG		 264 radeon_unmap_vram_bos(rdev);
265
ce8f5370 266 if (rdev->irq.installed) {
2aba631c
MG		 267 for (i = 0; i < rdev->num_crtc; i++) {
268 if (rdev->pm.active_crtcs & (1 << i)) {
269 rdev->pm.req_vblank |= (1 << i);
270 drm_vblank_get(rdev->ddev, i);
271 }
272 }
273 }
539d2418 274
ce8f5370 275 radeon_set_power_state(rdev);
2aba631c 276
ce8f5370 277 if (rdev->irq.installed) {
2aba631c
MG		 278 for (i = 0; i < rdev->num_crtc; i++) {
279 if (rdev->pm.req_vblank & (1 << i)) {
280 rdev->pm.req_vblank &= ~(1 << i);
281 drm_vblank_put(rdev->ddev, i);
282 }
283 }
284 }
5876dd24 285
a424816f
AD		 286 /* update display watermarks based on new power state */
287 radeon_update_bandwidth_info(rdev);
288 if (rdev->pm.active_crtc_count)
289 radeon_bandwidth_update(rdev);
290
ce8f5370 291 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 292
d6999bc7 293 mutex_unlock(&rdev->ring_lock);
db7fce39 294 up_write(&rdev->pm.mclk_lock);
612e06ce 295 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 296}
297
f712d0c7
RM		 298static void radeon_pm_print_states(struct radeon_device *rdev)
299{
300 int i, j;
301 struct radeon_power_state *power_state;
302 struct radeon_pm_clock_info *clock_info;
303
d9fdaafb 304 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 305 for (i = 0; i < rdev->pm.num_power_states; i++) {
306 power_state = &rdev->pm.power_state[i];
d9fdaafb 307 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 308 radeon_pm_state_type_name[power_state->type]);
309 if (i == rdev->pm.default_power_state_index)
d9fdaafb 310 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 311 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 312 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 313 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 314 DRM_DEBUG_DRIVER("\tSingle display only\n");
315 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 316 for (j = 0; j < power_state->num_clock_modes; j++) {
317 clock_info = &(power_state->clock_info[j]);
318 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 319 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
320 j,
321 clock_info->sclk * 10);
f712d0c7 322 else
eb2c27a0
AD		 323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
324 j,
325 clock_info->sclk * 10,
326 clock_info->mclk * 10,
327 clock_info->voltage.voltage);
f712d0c7
RM		 328 }
329 }
330}
331
ce8f5370
AD		 332static ssize_t radeon_get_pm_profile(struct device *dev,
333 struct device_attribute *attr,
334 char *buf)
a424816f
AD		 335{
336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
337 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 338 int cp = rdev->pm.profile;
a424816f 339
ce8f5370
AD		 340 return snprintf(buf, PAGE_SIZE, "%s\n",
341 (cp == PM_PROFILE_AUTO) ? "auto" :
342 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 343 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 344 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 345}
346
ce8f5370
AD		 347static ssize_t radeon_set_pm_profile(struct device *dev,
348 struct device_attribute *attr,
349 const char *buf,
350 size_t count)
a424816f
AD		 351{
352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
353 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 354
355 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
357 if (strncmp("default", buf, strlen("default")) == 0)
358 rdev->pm.profile = PM_PROFILE_DEFAULT;
359 else if (strncmp("auto", buf, strlen("auto")) == 0)
360 rdev->pm.profile = PM_PROFILE_AUTO;
361 else if (strncmp("low", buf, strlen("low")) == 0)
362 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 363 else if (strncmp("mid", buf, strlen("mid")) == 0)
364 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 365 else if (strncmp("high", buf, strlen("high")) == 0)
366 rdev->pm.profile = PM_PROFILE_HIGH;
367 else {
1783e4bf 368 count = -EINVAL;
ce8f5370 369 goto fail;
a424816f 370 }
ce8f5370
AD		 371 radeon_pm_update_profile(rdev);
372 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 373 } else
374 count = -EINVAL;
375
ce8f5370 376fail:
a424816f
AD		 377 mutex_unlock(&rdev->pm.mutex);
378
379 return count;
380}
381
ce8f5370
AD		 382static ssize_t radeon_get_pm_method(struct device *dev,
383 struct device_attribute *attr,
384 char *buf)
a424816f
AD		 385{
386 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
387 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 388 int pm = rdev->pm.pm_method;
a424816f
AD		 389
390 return snprintf(buf, PAGE_SIZE, "%s\n",
da321c8a
AD		 391 (pm == PM_METHOD_DYNPM) ? "dynpm" :
392 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
a424816f
AD		 393}
394
ce8f5370
AD		 395static ssize_t radeon_set_pm_method(struct device *dev,
396 struct device_attribute *attr,
397 const char *buf,
398 size_t count)
a424816f
AD		 399{
400 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
401 struct radeon_device *rdev = ddev->dev_private;
a424816f 402
da321c8a
AD		 403 /* we don't support the legacy modes with dpm */
404 if (rdev->pm.pm_method == PM_METHOD_DPM) {
405 count = -EINVAL;
406 goto fail;
407 }
ce8f5370
AD		 408
409 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 410 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 411 rdev->pm.pm_method = PM_METHOD_DYNPM;
412 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
413 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 414 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 415 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
416 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 417 /* disable dynpm */
418 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
419 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 420 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 421 mutex_unlock(&rdev->pm.mutex);
32c87fca 422 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 423 } else {
1783e4bf 424 count = -EINVAL;
ce8f5370
AD		 425 goto fail;
426 }
427 radeon_pm_compute_clocks(rdev);
428fail:
a424816f
AD		 429 return count;
430}
431
da321c8a
AD		 432static ssize_t radeon_get_dpm_state(struct device *dev,
433 struct device_attribute *attr,
434 char *buf)
435{
436 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
437 struct radeon_device *rdev = ddev->dev_private;
438 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
439
440 return snprintf(buf, PAGE_SIZE, "%s\n",
441 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
442 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
443}
444
445static ssize_t radeon_set_dpm_state(struct device *dev,
446 struct device_attribute *attr,
447 const char *buf,
448 size_t count)
449{
450 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
451 struct radeon_device *rdev = ddev->dev_private;
452
453 mutex_lock(&rdev->pm.mutex);
454 if (strncmp("battery", buf, strlen("battery")) == 0)
455 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
456 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
457 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
458 else if (strncmp("performance", buf, strlen("performance")) == 0)
459 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
460 else {
461 mutex_unlock(&rdev->pm.mutex);
462 count = -EINVAL;
463 goto fail;
464 }
465 mutex_unlock(&rdev->pm.mutex);
466 radeon_pm_compute_clocks(rdev);
467fail:
468 return count;
469}
470
70d01a5e
AD		 471static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
472 struct device_attribute *attr,
473 char *buf)
474{
475 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
476 struct radeon_device *rdev = ddev->dev_private;
477 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
478
479 return snprintf(buf, PAGE_SIZE, "%s\n",
480 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
481 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
482}
483
484static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
485 struct device_attribute *attr,
486 const char *buf,
487 size_t count)
488{
489 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
490 struct radeon_device *rdev = ddev->dev_private;
491 enum radeon_dpm_forced_level level;
492 int ret = 0;
493
494 mutex_lock(&rdev->pm.mutex);
495 if (strncmp("low", buf, strlen("low")) == 0) {
496 level = RADEON_DPM_FORCED_LEVEL_LOW;
497 } else if (strncmp("high", buf, strlen("high")) == 0) {
498 level = RADEON_DPM_FORCED_LEVEL_HIGH;
499 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
500 level = RADEON_DPM_FORCED_LEVEL_AUTO;
501 } else {
502 mutex_unlock(&rdev->pm.mutex);
503 count = -EINVAL;
504 goto fail;
505 }
506 if (rdev->asic->dpm.force_performance_level) {
507 ret = radeon_dpm_force_performance_level(rdev, level);
508 if (ret)
509 count = -EINVAL;
510 }
511 mutex_unlock(&rdev->pm.mutex);
512fail:
513 return count;
514}
515
ce8f5370
AD		 516static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
517static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
da321c8a 518static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
70d01a5e
AD		 519static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
520 radeon_get_dpm_forced_performance_level,
521 radeon_set_dpm_forced_performance_level);
a424816f 522
21a8122a
AD		 523static ssize_t radeon_hwmon_show_temp(struct device *dev,
524 struct device_attribute *attr,
525 char *buf)
526{
527 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
528 struct radeon_device *rdev = ddev->dev_private;
20d391d7 529 int temp;
21a8122a 530
6bd1c385
AD		 531 if (rdev->asic->pm.get_temperature)
532 temp = radeon_get_temperature(rdev);
533 else
21a8122a 534 temp = 0;
21a8122a
AD		 535
536 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
537}
538
539static ssize_t radeon_hwmon_show_name(struct device *dev,
540 struct device_attribute *attr,
541 char *buf)
542{
543 return sprintf(buf, "radeon\n");
544}
545
546static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
547static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
548
549static struct attribute *hwmon_attributes[] = {
550 &sensor_dev_attr_temp1_input.dev_attr.attr,
551 &sensor_dev_attr_name.dev_attr.attr,
552 NULL
553};
554
555static const struct attribute_group hwmon_attrgroup = {
556 .attrs = hwmon_attributes,
557};
558
0d18abed 559static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 560{
0d18abed 561 int err = 0;
21a8122a
AD		 562
563 rdev->pm.int_hwmon_dev = NULL;
564
565 switch (rdev->pm.int_thermal_type) {
566 case THERMAL_TYPE_RV6XX:
567 case THERMAL_TYPE_RV770:
568 case THERMAL_TYPE_EVERGREEN:
457558ed 569 case THERMAL_TYPE_NI:
e33df25f 570 case THERMAL_TYPE_SUMO:
1bd47d2e 571 case THERMAL_TYPE_SI:
6bd1c385 572 if (rdev->asic->pm.get_temperature == NULL)
5d7486c7 573 return err;
21a8122a 574 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 575 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
576 err = PTR_ERR(rdev->pm.int_hwmon_dev);
577 dev_err(rdev->dev,
578 "Unable to register hwmon device: %d\n", err);
579 break;
580 }
21a8122a
AD		 581 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
582 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
583 &hwmon_attrgroup);
0d18abed
DC		 584 if (err) {
585 dev_err(rdev->dev,
586 "Unable to create hwmon sysfs file: %d\n", err);
587 hwmon_device_unregister(rdev->dev);
588 }
21a8122a
AD		 589 break;
590 default:
591 break;
592 }
0d18abed
DC		 593
594 return err;
21a8122a
AD		 595}
596
597static void radeon_hwmon_fini(struct radeon_device *rdev)
598{
599 if (rdev->pm.int_hwmon_dev) {
600 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
601 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
602 }
603}
604
da321c8a
AD		 605static void radeon_dpm_thermal_work_handler(struct work_struct *work)
606{
607 struct radeon_device *rdev =
608 container_of(work, struct radeon_device,
609 pm.dpm.thermal.work);
610 /* switch to the thermal state */
611 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
612
613 if (!rdev->pm.dpm_enabled)
614 return;
615
616 if (rdev->asic->pm.get_temperature) {
617 int temp = radeon_get_temperature(rdev);
618
619 if (temp < rdev->pm.dpm.thermal.min_temp)
620 /* switch back the user state */
621 dpm_state = rdev->pm.dpm.user_state;
622 } else {
623 if (rdev->pm.dpm.thermal.high_to_low)
624 /* switch back the user state */
625 dpm_state = rdev->pm.dpm.user_state;
626 }
627 radeon_dpm_enable_power_state(rdev, dpm_state);
628}
629
630static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
631 enum radeon_pm_state_type dpm_state)
632{
633 int i;
634 struct radeon_ps *ps;
635 u32 ui_class;
636
edcaa5b1
AD		 637 /* certain older asics have a separare 3D performance state,
638 * so try that first if the user selected performance
639 */
640 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
641 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
da321c8a
AD		 642 /* balanced states don't exist at the moment */
643 if (dpm_state == POWER_STATE_TYPE_BALANCED)
644 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
645
edcaa5b1 646restart_search:
da321c8a
AD		 647 /* Pick the best power state based on current conditions */
648 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
649 ps = &rdev->pm.dpm.ps[i];
650 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
651 switch (dpm_state) {
652 /* user states */
653 case POWER_STATE_TYPE_BATTERY:
654 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
655 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
656 if (rdev->pm.dpm.new_active_crtc_count < 2)
657 return ps;
658 } else
659 return ps;
660 }
661 break;
662 case POWER_STATE_TYPE_BALANCED:
663 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
664 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
665 if (rdev->pm.dpm.new_active_crtc_count < 2)
666 return ps;
667 } else
668 return ps;
669 }
670 break;
671 case POWER_STATE_TYPE_PERFORMANCE:
672 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
673 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
674 if (rdev->pm.dpm.new_active_crtc_count < 2)
675 return ps;
676 } else
677 return ps;
678 }
679 break;
680 /* internal states */
681 case POWER_STATE_TYPE_INTERNAL_UVD:
682 return rdev->pm.dpm.uvd_ps;
683 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
684 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
685 return ps;
686 break;
687 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
688 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
689 return ps;
690 break;
691 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
692 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
693 return ps;
694 break;
695 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
696 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
697 return ps;
698 break;
699 case POWER_STATE_TYPE_INTERNAL_BOOT:
700 return rdev->pm.dpm.boot_ps;
701 case POWER_STATE_TYPE_INTERNAL_THERMAL:
702 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
703 return ps;
704 break;
705 case POWER_STATE_TYPE_INTERNAL_ACPI:
706 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
707 return ps;
708 break;
709 case POWER_STATE_TYPE_INTERNAL_ULV:
710 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
711 return ps;
712 break;
edcaa5b1
AD		 713 case POWER_STATE_TYPE_INTERNAL_3DPERF:
714 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
715 return ps;
716 break;
da321c8a
AD		 717 default:
718 break;
719 }
720 }
721 /* use a fallback state if we didn't match */
722 switch (dpm_state) {
723 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
724 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
725 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
726 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
727 return rdev->pm.dpm.uvd_ps;
728 case POWER_STATE_TYPE_INTERNAL_THERMAL:
729 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
730 goto restart_search;
731 case POWER_STATE_TYPE_INTERNAL_ACPI:
732 dpm_state = POWER_STATE_TYPE_BATTERY;
733 goto restart_search;
734 case POWER_STATE_TYPE_BATTERY:
edcaa5b1
AD		 735 case POWER_STATE_TYPE_BALANCED:
736 case POWER_STATE_TYPE_INTERNAL_3DPERF:
da321c8a
AD		 737 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
738 goto restart_search;
739 default:
740 break;
741 }
742
743 return NULL;
744}
745
746static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
747{
748 int i;
749 struct radeon_ps *ps;
750 enum radeon_pm_state_type dpm_state;
84dd1928 751 int ret;
da321c8a
AD		 752
753 /* if dpm init failed */
754 if (!rdev->pm.dpm_enabled)
755 return;
756
757 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
758 /* add other state override checks here */
8a227555
AD		 759 if ((!rdev->pm.dpm.thermal_active) &&
760 (!rdev->pm.dpm.uvd_active))
da321c8a
AD		 761 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
762 }
763 dpm_state = rdev->pm.dpm.state;
764
765 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
766 if (ps)
89c9bc56 767 rdev->pm.dpm.requested_ps = ps;
da321c8a
AD		 768 else
769 return;
770
d22b7e40 771 /* no need to reprogram if nothing changed unless we are on BTC+ */
da321c8a 772 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
d22b7e40
AD		 773 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
774 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
775 * all we need to do is update the display configuration.
776 */
777 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
778 /* update display watermarks based on new power state */
779 radeon_bandwidth_update(rdev);
780 /* update displays */
781 radeon_dpm_display_configuration_changed(rdev);
782 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
783 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
784 }
785 return;
786 } else {
787 /* for BTC+ if the num crtcs hasn't changed and state is the same,
788 * nothing to do, if the num crtcs is > 1 and state is the same,
789 * update display configuration.
790 */
791 if (rdev->pm.dpm.new_active_crtcs ==
792 rdev->pm.dpm.current_active_crtcs) {
793 return;
794 } else {
795 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
796 (rdev->pm.dpm.new_active_crtc_count > 1)) {
797 /* update display watermarks based on new power state */
798 radeon_bandwidth_update(rdev);
799 /* update displays */
800 radeon_dpm_display_configuration_changed(rdev);
801 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
802 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
803 return;
804 }
805 }
da321c8a 806 }
da321c8a
AD		 807 }
808
809 printk("switching from power state:\n");
810 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
811 printk("switching to power state:\n");
812 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
813
814 mutex_lock(&rdev->ddev->struct_mutex);
815 down_write(&rdev->pm.mclk_lock);
816 mutex_lock(&rdev->ring_lock);
817
89c9bc56
AD		 818 ret = radeon_dpm_pre_set_power_state(rdev);
819 if (ret)
820 goto done;
84dd1928 821
da321c8a
AD		 822 /* update display watermarks based on new power state */
823 radeon_bandwidth_update(rdev);
824 /* update displays */
825 radeon_dpm_display_configuration_changed(rdev);
826
827 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
828 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
829
830 /* wait for the rings to drain */
831 for (i = 0; i < RADEON_NUM_RINGS; i++) {
832 struct radeon_ring *ring = &rdev->ring[i];
833 if (ring->ready)
834 radeon_fence_wait_empty_locked(rdev, i);
835 }
836
837 /* program the new power state */
838 radeon_dpm_set_power_state(rdev);
839
840 /* update current power state */
841 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
842
89c9bc56 843 radeon_dpm_post_set_power_state(rdev);
84dd1928
AD		 844
845done:
da321c8a
AD		 846 mutex_unlock(&rdev->ring_lock);
847 up_write(&rdev->pm.mclk_lock);
848 mutex_unlock(&rdev->ddev->struct_mutex);
849}
850
851void radeon_dpm_enable_power_state(struct radeon_device *rdev,
852 enum radeon_pm_state_type dpm_state)
853{
854 if (!rdev->pm.dpm_enabled)
855 return;
856
857 mutex_lock(&rdev->pm.mutex);
858 switch (dpm_state) {
859 case POWER_STATE_TYPE_INTERNAL_THERMAL:
860 rdev->pm.dpm.thermal_active = true;
861 break;
8a227555
AD		 862 case POWER_STATE_TYPE_INTERNAL_UVD:
863 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
864 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
865 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
866 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
867 rdev->pm.dpm.uvd_active = true;
868 break;
da321c8a
AD		 869 default:
870 rdev->pm.dpm.thermal_active = false;
8a227555 871 rdev->pm.dpm.uvd_active = false;
da321c8a
AD		 872 break;
873 }
874 rdev->pm.dpm.state = dpm_state;
875 mutex_unlock(&rdev->pm.mutex);
876 radeon_pm_compute_clocks(rdev);
877}
878
879static void radeon_pm_suspend_old(struct radeon_device *rdev)
56278a8e 880{
ce8f5370 881 mutex_lock(&rdev->pm.mutex);
3f53eb6f 882 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 883 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
884 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 885 }
ce8f5370 886 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 887
888 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 889}
890
da321c8a
AD		 891static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
892{
893 mutex_lock(&rdev->pm.mutex);
894 /* disable dpm */
895 radeon_dpm_disable(rdev);
896 /* reset the power state */
897 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
898 rdev->pm.dpm_enabled = false;
899 mutex_unlock(&rdev->pm.mutex);
900}
901
902void radeon_pm_suspend(struct radeon_device *rdev)
903{
904 if (rdev->pm.pm_method == PM_METHOD_DPM)
905 radeon_pm_suspend_dpm(rdev);
906 else
907 radeon_pm_suspend_old(rdev);
908}
909
910static void radeon_pm_resume_old(struct radeon_device *rdev)
d0d6cb81 911{
ed18a360 912 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 913 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 914 (rdev->family <= CHIP_HAINAN) &&
2e3b3b10 915 rdev->mc_fw) {
ed18a360 916 if (rdev->pm.default_vddc)
8a83ec5e
AD		 917 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
918 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 919 if (rdev->pm.default_vddci)
920 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
921 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 922 if (rdev->pm.default_sclk)
923 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
924 if (rdev->pm.default_mclk)
925 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
926 }
f8ed8b4c
AD		 927 /* asic init will reset the default power state */
928 mutex_lock(&rdev->pm.mutex);
929 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
930 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 931 rdev->pm.current_sclk = rdev->pm.default_sclk;
932 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 933 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 934 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 935 if (rdev->pm.pm_method == PM_METHOD_DYNPM
936 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
937 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 938 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
939 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 940 }
f8ed8b4c 941 mutex_unlock(&rdev->pm.mutex);
ce8f5370 942 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 943}
944
da321c8a
AD		 945static void radeon_pm_resume_dpm(struct radeon_device *rdev)
946{
947 int ret;
948
949 /* asic init will reset to the boot state */
950 mutex_lock(&rdev->pm.mutex);
951 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
952 radeon_dpm_setup_asic(rdev);
953 ret = radeon_dpm_enable(rdev);
954 mutex_unlock(&rdev->pm.mutex);
955 if (ret) {
956 DRM_ERROR("radeon: dpm resume failed\n");
957 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 958 (rdev->family <= CHIP_HAINAN) &&
da321c8a
AD		 959 rdev->mc_fw) {
960 if (rdev->pm.default_vddc)
961 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
962 SET_VOLTAGE_TYPE_ASIC_VDDC);
963 if (rdev->pm.default_vddci)
964 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
965 SET_VOLTAGE_TYPE_ASIC_VDDCI);
966 if (rdev->pm.default_sclk)
967 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
968 if (rdev->pm.default_mclk)
969 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
970 }
971 } else {
972 rdev->pm.dpm_enabled = true;
973 radeon_pm_compute_clocks(rdev);
974 }
975}
976
977void radeon_pm_resume(struct radeon_device *rdev)
978{
979 if (rdev->pm.pm_method == PM_METHOD_DPM)
980 radeon_pm_resume_dpm(rdev);
981 else
982 radeon_pm_resume_old(rdev);
983}
984
985static int radeon_pm_init_old(struct radeon_device *rdev)
7433874e 986{
26481fb1 987 int ret;
0d18abed 988
f8ed8b4c 989 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 990 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
991 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
992 rdev->pm.dynpm_can_upclock = true;
993 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 994 rdev->pm.default_sclk = rdev->clock.default_sclk;
995 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 996 rdev->pm.current_sclk = rdev->clock.default_sclk;
997 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 998 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 999
56278a8e
AD		 1000 if (rdev->bios) {
1001 if (rdev->is_atom_bios)
1002 radeon_atombios_get_power_modes(rdev);
1003 else
1004 radeon_combios_get_power_modes(rdev);
f712d0c7 1005 radeon_pm_print_states(rdev);
ce8f5370 1006 radeon_pm_init_profile(rdev);
ed18a360 1007 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1008 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 1009 (rdev->family <= CHIP_HAINAN) &&
2e3b3b10 1010 rdev->mc_fw) {
ed18a360 1011 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1012 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1013 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 1014 if (rdev->pm.default_vddci)
1015 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1016 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1017 if (rdev->pm.default_sclk)
1018 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1019 if (rdev->pm.default_mclk)
1020 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1021 }
56278a8e
AD		 1022 }
1023
21a8122a 1024 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 1025 ret = radeon_hwmon_init(rdev);
1026 if (ret)
1027 return ret;
32c87fca
TH		 1028
1029 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1030
ce8f5370 1031 if (rdev->pm.num_power_states > 1) {
ce8f5370 1032 /* where's the best place to put these? */
26481fb1
DA		 1033 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1034 if (ret)
1035 DRM_ERROR("failed to create device file for power profile\n");
1036 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1037 if (ret)
1038 DRM_ERROR("failed to create device file for power method\n");
a424816f 1039
ce8f5370
AD		 1040 if (radeon_debugfs_pm_init(rdev)) {
1041 DRM_ERROR("Failed to register debugfs file for PM!\n");
1042 }
c913e23a 1043
ce8f5370
AD		 1044 DRM_INFO("radeon: power management initialized\n");
1045 }
c913e23a 1046
7433874e
RM		 1047 return 0;
1048}
1049
da321c8a
AD		 1050static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1051{
1052 int i;
1053
1054 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1055 printk("== power state %d ==\n", i);
1056 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1057 }
1058}
1059
1060static int radeon_pm_init_dpm(struct radeon_device *rdev)
1061{
1062 int ret;
1063
1064 /* default to performance state */
edcaa5b1
AD		 1065 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1066 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
da321c8a
AD		 1067 rdev->pm.default_sclk = rdev->clock.default_sclk;
1068 rdev->pm.default_mclk = rdev->clock.default_mclk;
1069 rdev->pm.current_sclk = rdev->clock.default_sclk;
1070 rdev->pm.current_mclk = rdev->clock.default_mclk;
1071 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1072
1073 if (rdev->bios && rdev->is_atom_bios)
1074 radeon_atombios_get_power_modes(rdev);
1075 else
1076 return -EINVAL;
1077
1078 /* set up the internal thermal sensor if applicable */
1079 ret = radeon_hwmon_init(rdev);
1080 if (ret)
1081 return ret;
1082
1083 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1084 mutex_lock(&rdev->pm.mutex);
1085 radeon_dpm_init(rdev);
1086 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1087 radeon_dpm_print_power_states(rdev);
1088 radeon_dpm_setup_asic(rdev);
1089 ret = radeon_dpm_enable(rdev);
1090 mutex_unlock(&rdev->pm.mutex);
1091 if (ret) {
1092 rdev->pm.dpm_enabled = false;
1093 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 1094 (rdev->family <= CHIP_HAINAN) &&
da321c8a
AD		 1095 rdev->mc_fw) {
1096 if (rdev->pm.default_vddc)
1097 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1098 SET_VOLTAGE_TYPE_ASIC_VDDC);
1099 if (rdev->pm.default_vddci)
1100 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1101 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1102 if (rdev->pm.default_sclk)
1103 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1104 if (rdev->pm.default_mclk)
1105 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1106 }
1107 DRM_ERROR("radeon: dpm initialization failed\n");
1108 return ret;
1109 }
1110 rdev->pm.dpm_enabled = true;
1111 radeon_pm_compute_clocks(rdev);
1112
1113 if (rdev->pm.num_power_states > 1) {
1114 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
70d01a5e
AD		 1115 if (ret)
1116 DRM_ERROR("failed to create device file for dpm state\n");
1117 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
da321c8a
AD		 1118 if (ret)
1119 DRM_ERROR("failed to create device file for dpm state\n");
1120 /* XXX: these are noops for dpm but are here for backwards compat */
1121 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1122 if (ret)
1123 DRM_ERROR("failed to create device file for power profile\n");
1124 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1125 if (ret)
1126 DRM_ERROR("failed to create device file for power method\n");
1316b792
AD		 1127
1128 if (radeon_debugfs_pm_init(rdev)) {
1129 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1130 }
1131
da321c8a
AD		 1132 DRM_INFO("radeon: dpm initialized\n");
1133 }
1134
1135 return 0;
1136}
1137
1138int radeon_pm_init(struct radeon_device *rdev)
1139{
1140 /* enable dpm on rv6xx+ */
1141 switch (rdev->family) {
4a6369e9
AD		 1142 case CHIP_RV610:
1143 case CHIP_RV630:
1144 case CHIP_RV620:
1145 case CHIP_RV635:
1146 case CHIP_RV670:
9d67006e
AD		 1147 case CHIP_RS780:
1148 case CHIP_RS880:
66229b20
AD		 1149 case CHIP_RV770:
1150 case CHIP_RV730:
1151 case CHIP_RV710:
1152 case CHIP_RV740:
dc50ba7f
AD		 1153 case CHIP_CEDAR:
1154 case CHIP_REDWOOD:
1155 case CHIP_JUNIPER:
1156 case CHIP_CYPRESS:
1157 case CHIP_HEMLOCK:
80ea2c12
AD		 1158 case CHIP_PALM:
1159 case CHIP_SUMO:
1160 case CHIP_SUMO2:
6596afd4
AD		 1161 case CHIP_BARTS:
1162 case CHIP_TURKS:
1163 case CHIP_CAICOS:
69e0b57a 1164 case CHIP_CAYMAN:
d70229f7 1165 case CHIP_ARUBA:
a9e61410
AD		 1166 case CHIP_TAHITI:
1167 case CHIP_PITCAIRN:
1168 case CHIP_VERDE:
1169 case CHIP_OLAND:
1170 case CHIP_HAINAN:
9d67006e
AD		 1171 if (radeon_dpm == 1)
1172 rdev->pm.pm_method = PM_METHOD_DPM;
1173 else
1174 rdev->pm.pm_method = PM_METHOD_PROFILE;
1175 break;
da321c8a
AD		 1176 default:
1177 /* default to profile method */
1178 rdev->pm.pm_method = PM_METHOD_PROFILE;
1179 break;
1180 }
1181
1182 if (rdev->pm.pm_method == PM_METHOD_DPM)
1183 return radeon_pm_init_dpm(rdev);
1184 else
1185 return radeon_pm_init_old(rdev);
1186}
1187
1188static void radeon_pm_fini_old(struct radeon_device *rdev)
29fb52ca 1189{
ce8f5370 1190 if (rdev->pm.num_power_states > 1) {
a424816f 1191 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 1192 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1193 rdev->pm.profile = PM_PROFILE_DEFAULT;
1194 radeon_pm_update_profile(rdev);
1195 radeon_pm_set_clocks(rdev);
1196 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 1197 /* reset default clocks */
1198 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1199 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1200 radeon_pm_set_clocks(rdev);
1201 }
a424816f 1202 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1203
1204 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 1205
ce8f5370
AD		 1206 device_remove_file(rdev->dev, &dev_attr_power_profile);
1207 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 1208 }
a424816f 1209
0975b162
AD		 1210 if (rdev->pm.power_state)
1211 kfree(rdev->pm.power_state);
1212
21a8122a 1213 radeon_hwmon_fini(rdev);
29fb52ca
AD		 1214}
1215
da321c8a
AD		 1216static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1217{
1218 if (rdev->pm.num_power_states > 1) {
1219 mutex_lock(&rdev->pm.mutex);
1220 radeon_dpm_disable(rdev);
1221 mutex_unlock(&rdev->pm.mutex);
1222
1223 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
70d01a5e 1224 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
da321c8a
AD		 1225 /* XXX backwards compat */
1226 device_remove_file(rdev->dev, &dev_attr_power_profile);
1227 device_remove_file(rdev->dev, &dev_attr_power_method);
1228 }
1229 radeon_dpm_fini(rdev);
1230
1231 if (rdev->pm.power_state)
1232 kfree(rdev->pm.power_state);
1233
1234 radeon_hwmon_fini(rdev);
1235}
1236
1237void radeon_pm_fini(struct radeon_device *rdev)
1238{
1239 if (rdev->pm.pm_method == PM_METHOD_DPM)
1240 radeon_pm_fini_dpm(rdev);
1241 else
1242 radeon_pm_fini_old(rdev);
1243}
1244
1245static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
c913e23a
RM		 1246{
1247 struct drm_device *ddev = rdev->ddev;
a48b9b4e 1248 struct drm_crtc *crtc;
c913e23a 1249 struct radeon_crtc *radeon_crtc;
c913e23a 1250
ce8f5370
AD		 1251 if (rdev->pm.num_power_states < 2)
1252 return;
1253
c913e23a
RM		 1254 mutex_lock(&rdev->pm.mutex);
1255
1256 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 1257 rdev->pm.active_crtc_count = 0;
1258 list_for_each_entry(crtc,
1259 &ddev->mode_config.crtc_list, head) {
1260 radeon_crtc = to_radeon_crtc(crtc);
1261 if (radeon_crtc->enabled) {
c913e23a 1262 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 1263 rdev->pm.active_crtc_count++;
c913e23a
RM		 1264 }
1265 }
1266
ce8f5370
AD		 1267 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1268 radeon_pm_update_profile(rdev);
1269 radeon_pm_set_clocks(rdev);
1270 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1271 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1272 if (rdev->pm.active_crtc_count > 1) {
1273 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1274 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1275
1276 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1277 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1278 radeon_pm_get_dynpm_state(rdev);
1279 radeon_pm_set_clocks(rdev);
1280
d9fdaafb 1281 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 1282 }
1283 } else if (rdev->pm.active_crtc_count == 1) {
1284 /* TODO: Increase clocks if needed for current mode */
1285
1286 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1287 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1288 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1289 radeon_pm_get_dynpm_state(rdev);
1290 radeon_pm_set_clocks(rdev);
1291
32c87fca
TH		 1292 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1293 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 1294 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1295 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1296 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1297 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 1298 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 1299 }
1300 } else { /* count == 0 */
1301 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1302 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1303
1304 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1305 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1306 radeon_pm_get_dynpm_state(rdev);
1307 radeon_pm_set_clocks(rdev);
1308 }
1309 }
c913e23a 1310 }
c913e23a 1311 }
73a6d3fc
RM		 1312
1313 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 1314}
1315
da321c8a
AD		 1316static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1317{
1318 struct drm_device *ddev = rdev->ddev;
1319 struct drm_crtc *crtc;
1320 struct radeon_crtc *radeon_crtc;
1321
1322 mutex_lock(&rdev->pm.mutex);
1323
5ca302f7 1324 /* update active crtc counts */
da321c8a
AD		 1325 rdev->pm.dpm.new_active_crtcs = 0;
1326 rdev->pm.dpm.new_active_crtc_count = 0;
1327 list_for_each_entry(crtc,
1328 &ddev->mode_config.crtc_list, head) {
1329 radeon_crtc = to_radeon_crtc(crtc);
1330 if (crtc->enabled) {
1331 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1332 rdev->pm.dpm.new_active_crtc_count++;
1333 }
1334 }
1335
5ca302f7
AD		 1336 /* update battery/ac status */
1337 if (power_supply_is_system_supplied() > 0)
1338 rdev->pm.dpm.ac_power = true;
1339 else
1340 rdev->pm.dpm.ac_power = false;
1341
da321c8a
AD		 1342 radeon_dpm_change_power_state_locked(rdev);
1343
1344 mutex_unlock(&rdev->pm.mutex);
8a227555 1345
da321c8a
AD		 1346}
1347
1348void radeon_pm_compute_clocks(struct radeon_device *rdev)
1349{
1350 if (rdev->pm.pm_method == PM_METHOD_DPM)
1351 radeon_pm_compute_clocks_dpm(rdev);
1352 else
1353 radeon_pm_compute_clocks_old(rdev);
1354}
1355
ce8f5370 1356static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 1357{
75fa0b08 1358 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 1359 bool in_vbl = true;
1360
75fa0b08
MK		 1361 /* Iterate over all active crtc's. All crtc's must be in vblank,
1362 * otherwise return in_vbl == false.
1363 */
1364 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1365 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 1366 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1367 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1368 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 1369 in_vbl = false;
1370 }
1371 }
f81f2024
MG		 1372
1373 return in_vbl;
1374}
1375
ce8f5370 1376static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 1377{
1378 u32 stat_crtc = 0;
1379 bool in_vbl = radeon_pm_in_vbl(rdev);
1380
f735261b 1381 if (in_vbl == false)
d9fdaafb 1382 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 1383 finish ? "exit" : "entry");
f735261b
DA		 1384 return in_vbl;
1385}
c913e23a 1386
ce8f5370 1387static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 1388{
1389 struct radeon_device *rdev;
d9932a32 1390 int resched;
c913e23a 1391 rdev = container_of(work, struct radeon_device,
ce8f5370 1392 pm.dynpm_idle_work.work);
c913e23a 1393
d9932a32 1394 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 1395 mutex_lock(&rdev->pm.mutex);
ce8f5370 1396 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 1397 int not_processed = 0;
7465280c
AD		 1398 int i;
1399
7465280c 1400 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 1401 struct radeon_ring *ring = &rdev->ring[i];
1402
1403 if (ring->ready) {
1404 not_processed += radeon_fence_count_emitted(rdev, i);
1405 if (not_processed >= 3)
1406 break;
1407 }
c913e23a 1408 }
c913e23a
RM		 1409
1410 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 1411 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1412 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1413 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1414 rdev->pm.dynpm_can_upclock) {
1415 rdev->pm.dynpm_planned_action =
1416 DYNPM_ACTION_UPCLOCK;
1417 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1418 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1419 }
1420 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 1421 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1422 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1423 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1424 rdev->pm.dynpm_can_downclock) {
1425 rdev->pm.dynpm_planned_action =
1426 DYNPM_ACTION_DOWNCLOCK;
1427 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1428 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1429 }
1430 }
1431
d7311171
AD		 1432 /* Note, radeon_pm_set_clocks is called with static_switch set
1433 * to false since we want to wait for vbl to avoid flicker.
1434 */
ce8f5370
AD		 1435 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1436 jiffies > rdev->pm.dynpm_action_timeout) {
1437 radeon_pm_get_dynpm_state(rdev);
1438 radeon_pm_set_clocks(rdev);
c913e23a 1439 }
3f53eb6f 1440
32c87fca
TH		 1441 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1442 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 1443 }
1444 mutex_unlock(&rdev->pm.mutex);
d9932a32 1445 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 1446}
1447
7433874e
RM		 1448/*
1449 * Debugfs info
1450 */
1451#if defined(CONFIG_DEBUG_FS)
1452
1453static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1454{
1455 struct drm_info_node *node = (struct drm_info_node *) m->private;
1456 struct drm_device *dev = node->minor->dev;
1457 struct radeon_device *rdev = dev->dev_private;
1458
1316b792
AD		 1459 if (rdev->pm.dpm_enabled) {
1460 mutex_lock(&rdev->pm.mutex);
1461 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1462 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1463 else
71375929 1464 seq_printf(m, "Debugfs support not implemented for this asic\n");
1316b792
AD		 1465 mutex_unlock(&rdev->pm.mutex);
1466 } else {
1467 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1468 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1469 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1470 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1471 else
1472 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1473 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1474 if (rdev->asic->pm.get_memory_clock)
1475 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1476 if (rdev->pm.current_vddc)
1477 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1478 if (rdev->asic->pm.get_pcie_lanes)
1479 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1480 }
7433874e
RM		 1481
1482 return 0;
1483}
1484
1485static struct drm_info_list radeon_pm_info_list[] = {
1486 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1487};
1488#endif
1489
c913e23a 1490static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 1491{
1492#if defined(CONFIG_DEBUG_FS)
1493 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1494#else
1495 return 0;
1496#endif
1497}
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