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Commit | Line | Data |
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7433874e RM |
1 | /* |
2 | * Permission is hereby granted, free of charge, to any person obtaining a | |
3 | * copy of this software and associated documentation files (the "Software"), | |
4 | * to deal in the Software without restriction, including without limitation | |
5 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
6 | * and/or sell copies of the Software, and to permit persons to whom the | |
7 | * Software is furnished to do so, subject to the following conditions: | |
8 | * | |
9 | * The above copyright notice and this permission notice shall be included in | |
10 | * all copies or substantial portions of the Software. | |
11 | * | |
12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
13 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
14 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
15 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
16 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
17 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
18 | * OTHER DEALINGS IN THE SOFTWARE. | |
19 | * | |
20 | * Authors: Rafał Miłecki <zajec5@gmail.com> | |
56278a8e | 21 | * Alex Deucher <alexdeucher@gmail.com> |
7433874e RM |
22 | */ |
23 | #include "drmP.h" | |
24 | #include "radeon.h" | |
f735261b | 25 | #include "avivod.h" |
8a83ec5e | 26 | #include "atom.h" |
ce8f5370 | 27 | #include <linux/power_supply.h> |
21a8122a AD |
28 | #include <linux/hwmon.h> |
29 | #include <linux/hwmon-sysfs.h> | |
7433874e | 30 | |
c913e23a RM |
31 | #define RADEON_IDLE_LOOP_MS 100 |
32 | #define RADEON_RECLOCK_DELAY_MS 200 | |
73a6d3fc | 33 | #define RADEON_WAIT_VBLANK_TIMEOUT 200 |
c913e23a | 34 | |
f712d0c7 RM |
35 | static const char *radeon_pm_state_type_name[5] = { |
36 | "Default", | |
37 | "Powersave", | |
38 | "Battery", | |
39 | "Balanced", | |
40 | "Performance", | |
41 | }; | |
42 | ||
ce8f5370 | 43 | static void radeon_dynpm_idle_work_handler(struct work_struct *work); |
c913e23a | 44 | static int radeon_debugfs_pm_init(struct radeon_device *rdev); |
ce8f5370 AD |
45 | static bool radeon_pm_in_vbl(struct radeon_device *rdev); |
46 | static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); | |
47 | static void radeon_pm_update_profile(struct radeon_device *rdev); | |
48 | static void radeon_pm_set_clocks(struct radeon_device *rdev); | |
49 | ||
a4c9e2ee AD |
50 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
51 | enum radeon_pm_state_type ps_type, | |
52 | int instance) | |
53 | { | |
54 | int i; | |
55 | int found_instance = -1; | |
56 | ||
57 | for (i = 0; i < rdev->pm.num_power_states; i++) { | |
58 | if (rdev->pm.power_state[i].type == ps_type) { | |
59 | found_instance++; | |
60 | if (found_instance == instance) | |
61 | return i; | |
62 | } | |
63 | } | |
64 | /* return default if no match */ | |
65 | return rdev->pm.default_power_state_index; | |
66 | } | |
67 | ||
c4917074 | 68 | void radeon_pm_acpi_event_handler(struct radeon_device *rdev) |
ce8f5370 | 69 | { |
c4917074 AD |
70 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
71 | if (rdev->pm.profile == PM_PROFILE_AUTO) { | |
72 | mutex_lock(&rdev->pm.mutex); | |
73 | radeon_pm_update_profile(rdev); | |
74 | radeon_pm_set_clocks(rdev); | |
75 | mutex_unlock(&rdev->pm.mutex); | |
ce8f5370 AD |
76 | } |
77 | } | |
ce8f5370 | 78 | } |
ce8f5370 AD |
79 | |
80 | static void radeon_pm_update_profile(struct radeon_device *rdev) | |
81 | { | |
82 | switch (rdev->pm.profile) { | |
83 | case PM_PROFILE_DEFAULT: | |
84 | rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; | |
85 | break; | |
86 | case PM_PROFILE_AUTO: | |
87 | if (power_supply_is_system_supplied() > 0) { | |
88 | if (rdev->pm.active_crtc_count > 1) | |
89 | rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; | |
90 | else | |
91 | rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; | |
92 | } else { | |
93 | if (rdev->pm.active_crtc_count > 1) | |
c9e75b21 | 94 | rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; |
ce8f5370 | 95 | else |
c9e75b21 | 96 | rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; |
ce8f5370 AD |
97 | } |
98 | break; | |
99 | case PM_PROFILE_LOW: | |
100 | if (rdev->pm.active_crtc_count > 1) | |
101 | rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; | |
102 | else | |
103 | rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; | |
104 | break; | |
c9e75b21 AD |
105 | case PM_PROFILE_MID: |
106 | if (rdev->pm.active_crtc_count > 1) | |
107 | rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; | |
108 | else | |
109 | rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; | |
110 | break; | |
ce8f5370 AD |
111 | case PM_PROFILE_HIGH: |
112 | if (rdev->pm.active_crtc_count > 1) | |
113 | rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; | |
114 | else | |
115 | rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; | |
116 | break; | |
117 | } | |
118 | ||
119 | if (rdev->pm.active_crtc_count == 0) { | |
120 | rdev->pm.requested_power_state_index = | |
121 | rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; | |
122 | rdev->pm.requested_clock_mode_index = | |
123 | rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; | |
124 | } else { | |
125 | rdev->pm.requested_power_state_index = | |
126 | rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; | |
127 | rdev->pm.requested_clock_mode_index = | |
128 | rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; | |
129 | } | |
130 | } | |
c913e23a | 131 | |
5876dd24 MG |
132 | static void radeon_unmap_vram_bos(struct radeon_device *rdev) |
133 | { | |
134 | struct radeon_bo *bo, *n; | |
135 | ||
136 | if (list_empty(&rdev->gem.objects)) | |
137 | return; | |
138 | ||
139 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
140 | if (bo->tbo.mem.mem_type == TTM_PL_VRAM) | |
141 | ttm_bo_unmap_virtual(&bo->tbo); | |
142 | } | |
5876dd24 MG |
143 | } |
144 | ||
ce8f5370 | 145 | static void radeon_sync_with_vblank(struct radeon_device *rdev) |
a424816f | 146 | { |
ce8f5370 AD |
147 | if (rdev->pm.active_crtcs) { |
148 | rdev->pm.vblank_sync = false; | |
149 | wait_event_timeout( | |
150 | rdev->irq.vblank_queue, rdev->pm.vblank_sync, | |
151 | msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); | |
152 | } | |
153 | } | |
154 | ||
155 | static void radeon_set_power_state(struct radeon_device *rdev) | |
156 | { | |
157 | u32 sclk, mclk; | |
92645879 | 158 | bool misc_after = false; |
ce8f5370 AD |
159 | |
160 | if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && | |
161 | (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) | |
162 | return; | |
163 | ||
164 | if (radeon_gui_idle(rdev)) { | |
165 | sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
166 | clock_info[rdev->pm.requested_clock_mode_index].sclk; | |
9ace9f7b AD |
167 | if (sclk > rdev->pm.default_sclk) |
168 | sclk = rdev->pm.default_sclk; | |
ce8f5370 AD |
169 | |
170 | mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
171 | clock_info[rdev->pm.requested_clock_mode_index].mclk; | |
9ace9f7b AD |
172 | if (mclk > rdev->pm.default_mclk) |
173 | mclk = rdev->pm.default_mclk; | |
ce8f5370 | 174 | |
92645879 AD |
175 | /* upvolt before raising clocks, downvolt after lowering clocks */ |
176 | if (sclk < rdev->pm.current_sclk) | |
177 | misc_after = true; | |
ce8f5370 | 178 | |
92645879 | 179 | radeon_sync_with_vblank(rdev); |
ce8f5370 | 180 | |
92645879 | 181 | if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
ce8f5370 AD |
182 | if (!radeon_pm_in_vbl(rdev)) |
183 | return; | |
92645879 | 184 | } |
ce8f5370 | 185 | |
92645879 | 186 | radeon_pm_prepare(rdev); |
ce8f5370 | 187 | |
92645879 AD |
188 | if (!misc_after) |
189 | /* voltage, pcie lanes, etc.*/ | |
190 | radeon_pm_misc(rdev); | |
191 | ||
192 | /* set engine clock */ | |
193 | if (sclk != rdev->pm.current_sclk) { | |
194 | radeon_pm_debug_check_in_vbl(rdev, false); | |
195 | radeon_set_engine_clock(rdev, sclk); | |
196 | radeon_pm_debug_check_in_vbl(rdev, true); | |
197 | rdev->pm.current_sclk = sclk; | |
d9fdaafb | 198 | DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); |
92645879 AD |
199 | } |
200 | ||
201 | /* set memory clock */ | |
798bcf73 | 202 | if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { |
92645879 AD |
203 | radeon_pm_debug_check_in_vbl(rdev, false); |
204 | radeon_set_memory_clock(rdev, mclk); | |
205 | radeon_pm_debug_check_in_vbl(rdev, true); | |
206 | rdev->pm.current_mclk = mclk; | |
d9fdaafb | 207 | DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); |
ce8f5370 | 208 | } |
2aba631c | 209 | |
92645879 AD |
210 | if (misc_after) |
211 | /* voltage, pcie lanes, etc.*/ | |
212 | radeon_pm_misc(rdev); | |
213 | ||
214 | radeon_pm_finish(rdev); | |
215 | ||
ce8f5370 AD |
216 | rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; |
217 | rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; | |
218 | } else | |
d9fdaafb | 219 | DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); |
ce8f5370 AD |
220 | } |
221 | ||
222 | static void radeon_pm_set_clocks(struct radeon_device *rdev) | |
223 | { | |
224 | int i; | |
c37d230a | 225 | |
4e186b2d AD |
226 | /* no need to take locks, etc. if nothing's going to change */ |
227 | if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && | |
228 | (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) | |
229 | return; | |
230 | ||
612e06ce | 231 | mutex_lock(&rdev->ddev->struct_mutex); |
db7fce39 | 232 | down_write(&rdev->pm.mclk_lock); |
d6999bc7 | 233 | mutex_lock(&rdev->ring_lock); |
4f3218cb | 234 | |
95f5a3ac AD |
235 | /* wait for the rings to drain */ |
236 | for (i = 0; i < RADEON_NUM_RINGS; i++) { | |
237 | struct radeon_ring *ring = &rdev->ring[i]; | |
238 | if (ring->ready) | |
239 | radeon_fence_wait_empty_locked(rdev, i); | |
4f3218cb | 240 | } |
95f5a3ac | 241 | |
5876dd24 MG |
242 | radeon_unmap_vram_bos(rdev); |
243 | ||
ce8f5370 | 244 | if (rdev->irq.installed) { |
2aba631c MG |
245 | for (i = 0; i < rdev->num_crtc; i++) { |
246 | if (rdev->pm.active_crtcs & (1 << i)) { | |
247 | rdev->pm.req_vblank |= (1 << i); | |
248 | drm_vblank_get(rdev->ddev, i); | |
249 | } | |
250 | } | |
251 | } | |
539d2418 | 252 | |
ce8f5370 | 253 | radeon_set_power_state(rdev); |
2aba631c | 254 | |
ce8f5370 | 255 | if (rdev->irq.installed) { |
2aba631c MG |
256 | for (i = 0; i < rdev->num_crtc; i++) { |
257 | if (rdev->pm.req_vblank & (1 << i)) { | |
258 | rdev->pm.req_vblank &= ~(1 << i); | |
259 | drm_vblank_put(rdev->ddev, i); | |
260 | } | |
261 | } | |
262 | } | |
5876dd24 | 263 | |
a424816f AD |
264 | /* update display watermarks based on new power state */ |
265 | radeon_update_bandwidth_info(rdev); | |
266 | if (rdev->pm.active_crtc_count) | |
267 | radeon_bandwidth_update(rdev); | |
268 | ||
ce8f5370 | 269 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
2aba631c | 270 | |
d6999bc7 | 271 | mutex_unlock(&rdev->ring_lock); |
db7fce39 | 272 | up_write(&rdev->pm.mclk_lock); |
612e06ce | 273 | mutex_unlock(&rdev->ddev->struct_mutex); |
a424816f AD |
274 | } |
275 | ||
f712d0c7 RM |
276 | static void radeon_pm_print_states(struct radeon_device *rdev) |
277 | { | |
278 | int i, j; | |
279 | struct radeon_power_state *power_state; | |
280 | struct radeon_pm_clock_info *clock_info; | |
281 | ||
d9fdaafb | 282 | DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); |
f712d0c7 RM |
283 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
284 | power_state = &rdev->pm.power_state[i]; | |
d9fdaafb | 285 | DRM_DEBUG_DRIVER("State %d: %s\n", i, |
f712d0c7 RM |
286 | radeon_pm_state_type_name[power_state->type]); |
287 | if (i == rdev->pm.default_power_state_index) | |
d9fdaafb | 288 | DRM_DEBUG_DRIVER("\tDefault"); |
f712d0c7 | 289 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) |
d9fdaafb | 290 | DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); |
f712d0c7 | 291 | if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
d9fdaafb DA |
292 | DRM_DEBUG_DRIVER("\tSingle display only\n"); |
293 | DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); | |
f712d0c7 RM |
294 | for (j = 0; j < power_state->num_clock_modes; j++) { |
295 | clock_info = &(power_state->clock_info[j]); | |
296 | if (rdev->flags & RADEON_IS_IGP) | |
d9fdaafb | 297 | DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n", |
f712d0c7 RM |
298 | j, |
299 | clock_info->sclk * 10, | |
300 | clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : ""); | |
301 | else | |
d9fdaafb | 302 | DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n", |
f712d0c7 RM |
303 | j, |
304 | clock_info->sclk * 10, | |
305 | clock_info->mclk * 10, | |
306 | clock_info->voltage.voltage, | |
307 | clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : ""); | |
308 | } | |
309 | } | |
310 | } | |
311 | ||
ce8f5370 AD |
312 | static ssize_t radeon_get_pm_profile(struct device *dev, |
313 | struct device_attribute *attr, | |
314 | char *buf) | |
a424816f AD |
315 | { |
316 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); | |
317 | struct radeon_device *rdev = ddev->dev_private; | |
ce8f5370 | 318 | int cp = rdev->pm.profile; |
a424816f | 319 | |
ce8f5370 AD |
320 | return snprintf(buf, PAGE_SIZE, "%s\n", |
321 | (cp == PM_PROFILE_AUTO) ? "auto" : | |
322 | (cp == PM_PROFILE_LOW) ? "low" : | |
12e27be8 | 323 | (cp == PM_PROFILE_MID) ? "mid" : |
ce8f5370 | 324 | (cp == PM_PROFILE_HIGH) ? "high" : "default"); |
a424816f AD |
325 | } |
326 | ||
ce8f5370 AD |
327 | static ssize_t radeon_set_pm_profile(struct device *dev, |
328 | struct device_attribute *attr, | |
329 | const char *buf, | |
330 | size_t count) | |
a424816f AD |
331 | { |
332 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); | |
333 | struct radeon_device *rdev = ddev->dev_private; | |
a424816f AD |
334 | |
335 | mutex_lock(&rdev->pm.mutex); | |
ce8f5370 AD |
336 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
337 | if (strncmp("default", buf, strlen("default")) == 0) | |
338 | rdev->pm.profile = PM_PROFILE_DEFAULT; | |
339 | else if (strncmp("auto", buf, strlen("auto")) == 0) | |
340 | rdev->pm.profile = PM_PROFILE_AUTO; | |
341 | else if (strncmp("low", buf, strlen("low")) == 0) | |
342 | rdev->pm.profile = PM_PROFILE_LOW; | |
c9e75b21 AD |
343 | else if (strncmp("mid", buf, strlen("mid")) == 0) |
344 | rdev->pm.profile = PM_PROFILE_MID; | |
ce8f5370 AD |
345 | else if (strncmp("high", buf, strlen("high")) == 0) |
346 | rdev->pm.profile = PM_PROFILE_HIGH; | |
347 | else { | |
1783e4bf | 348 | count = -EINVAL; |
ce8f5370 | 349 | goto fail; |
a424816f | 350 | } |
ce8f5370 AD |
351 | radeon_pm_update_profile(rdev); |
352 | radeon_pm_set_clocks(rdev); | |
1783e4bf TR |
353 | } else |
354 | count = -EINVAL; | |
355 | ||
ce8f5370 | 356 | fail: |
a424816f AD |
357 | mutex_unlock(&rdev->pm.mutex); |
358 | ||
359 | return count; | |
360 | } | |
361 | ||
ce8f5370 AD |
362 | static ssize_t radeon_get_pm_method(struct device *dev, |
363 | struct device_attribute *attr, | |
364 | char *buf) | |
a424816f AD |
365 | { |
366 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); | |
367 | struct radeon_device *rdev = ddev->dev_private; | |
ce8f5370 | 368 | int pm = rdev->pm.pm_method; |
a424816f AD |
369 | |
370 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
ce8f5370 | 371 | (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile"); |
a424816f AD |
372 | } |
373 | ||
ce8f5370 AD |
374 | static ssize_t radeon_set_pm_method(struct device *dev, |
375 | struct device_attribute *attr, | |
376 | const char *buf, | |
377 | size_t count) | |
a424816f AD |
378 | { |
379 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); | |
380 | struct radeon_device *rdev = ddev->dev_private; | |
a424816f | 381 | |
ce8f5370 AD |
382 | |
383 | if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { | |
a424816f | 384 | mutex_lock(&rdev->pm.mutex); |
ce8f5370 AD |
385 | rdev->pm.pm_method = PM_METHOD_DYNPM; |
386 | rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; | |
387 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; | |
a424816f | 388 | mutex_unlock(&rdev->pm.mutex); |
ce8f5370 AD |
389 | } else if (strncmp("profile", buf, strlen("profile")) == 0) { |
390 | mutex_lock(&rdev->pm.mutex); | |
ce8f5370 AD |
391 | /* disable dynpm */ |
392 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; | |
393 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; | |
3f53eb6f | 394 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
ce8f5370 | 395 | mutex_unlock(&rdev->pm.mutex); |
32c87fca | 396 | cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); |
ce8f5370 | 397 | } else { |
1783e4bf | 398 | count = -EINVAL; |
ce8f5370 AD |
399 | goto fail; |
400 | } | |
401 | radeon_pm_compute_clocks(rdev); | |
402 | fail: | |
a424816f AD |
403 | return count; |
404 | } | |
405 | ||
ce8f5370 AD |
406 | static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); |
407 | static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); | |
a424816f | 408 | |
21a8122a AD |
409 | static ssize_t radeon_hwmon_show_temp(struct device *dev, |
410 | struct device_attribute *attr, | |
411 | char *buf) | |
412 | { | |
413 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); | |
414 | struct radeon_device *rdev = ddev->dev_private; | |
20d391d7 | 415 | int temp; |
21a8122a AD |
416 | |
417 | switch (rdev->pm.int_thermal_type) { | |
418 | case THERMAL_TYPE_RV6XX: | |
419 | temp = rv6xx_get_temp(rdev); | |
420 | break; | |
421 | case THERMAL_TYPE_RV770: | |
422 | temp = rv770_get_temp(rdev); | |
423 | break; | |
424 | case THERMAL_TYPE_EVERGREEN: | |
4fddba1f | 425 | case THERMAL_TYPE_NI: |
21a8122a AD |
426 | temp = evergreen_get_temp(rdev); |
427 | break; | |
e33df25f AD |
428 | case THERMAL_TYPE_SUMO: |
429 | temp = sumo_get_temp(rdev); | |
430 | break; | |
1bd47d2e AD |
431 | case THERMAL_TYPE_SI: |
432 | temp = si_get_temp(rdev); | |
433 | break; | |
21a8122a AD |
434 | default: |
435 | temp = 0; | |
436 | break; | |
437 | } | |
438 | ||
439 | return snprintf(buf, PAGE_SIZE, "%d\n", temp); | |
440 | } | |
441 | ||
442 | static ssize_t radeon_hwmon_show_name(struct device *dev, | |
443 | struct device_attribute *attr, | |
444 | char *buf) | |
445 | { | |
446 | return sprintf(buf, "radeon\n"); | |
447 | } | |
448 | ||
449 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); | |
450 | static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0); | |
451 | ||
452 | static struct attribute *hwmon_attributes[] = { | |
453 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
454 | &sensor_dev_attr_name.dev_attr.attr, | |
455 | NULL | |
456 | }; | |
457 | ||
458 | static const struct attribute_group hwmon_attrgroup = { | |
459 | .attrs = hwmon_attributes, | |
460 | }; | |
461 | ||
0d18abed | 462 | static int radeon_hwmon_init(struct radeon_device *rdev) |
21a8122a | 463 | { |
0d18abed | 464 | int err = 0; |
21a8122a AD |
465 | |
466 | rdev->pm.int_hwmon_dev = NULL; | |
467 | ||
468 | switch (rdev->pm.int_thermal_type) { | |
469 | case THERMAL_TYPE_RV6XX: | |
470 | case THERMAL_TYPE_RV770: | |
471 | case THERMAL_TYPE_EVERGREEN: | |
457558ed | 472 | case THERMAL_TYPE_NI: |
e33df25f | 473 | case THERMAL_TYPE_SUMO: |
1bd47d2e | 474 | case THERMAL_TYPE_SI: |
5d7486c7 AD |
475 | /* No support for TN yet */ |
476 | if (rdev->family == CHIP_ARUBA) | |
477 | return err; | |
21a8122a | 478 | rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev); |
0d18abed DC |
479 | if (IS_ERR(rdev->pm.int_hwmon_dev)) { |
480 | err = PTR_ERR(rdev->pm.int_hwmon_dev); | |
481 | dev_err(rdev->dev, | |
482 | "Unable to register hwmon device: %d\n", err); | |
483 | break; | |
484 | } | |
21a8122a AD |
485 | dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev); |
486 | err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj, | |
487 | &hwmon_attrgroup); | |
0d18abed DC |
488 | if (err) { |
489 | dev_err(rdev->dev, | |
490 | "Unable to create hwmon sysfs file: %d\n", err); | |
491 | hwmon_device_unregister(rdev->dev); | |
492 | } | |
21a8122a AD |
493 | break; |
494 | default: | |
495 | break; | |
496 | } | |
0d18abed DC |
497 | |
498 | return err; | |
21a8122a AD |
499 | } |
500 | ||
501 | static void radeon_hwmon_fini(struct radeon_device *rdev) | |
502 | { | |
503 | if (rdev->pm.int_hwmon_dev) { | |
504 | sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup); | |
505 | hwmon_device_unregister(rdev->pm.int_hwmon_dev); | |
506 | } | |
507 | } | |
508 | ||
ce8f5370 | 509 | void radeon_pm_suspend(struct radeon_device *rdev) |
56278a8e | 510 | { |
ce8f5370 | 511 | mutex_lock(&rdev->pm.mutex); |
3f53eb6f | 512 | if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
3f53eb6f RW |
513 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) |
514 | rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; | |
3f53eb6f | 515 | } |
ce8f5370 | 516 | mutex_unlock(&rdev->pm.mutex); |
32c87fca TH |
517 | |
518 | cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); | |
56278a8e AD |
519 | } |
520 | ||
ce8f5370 | 521 | void radeon_pm_resume(struct radeon_device *rdev) |
d0d6cb81 | 522 | { |
ed18a360 AD |
523 | /* set up the default clocks if the MC ucode is loaded */ |
524 | if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) { | |
525 | if (rdev->pm.default_vddc) | |
8a83ec5e AD |
526 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
527 | SET_VOLTAGE_TYPE_ASIC_VDDC); | |
2feea49a AD |
528 | if (rdev->pm.default_vddci) |
529 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, | |
530 | SET_VOLTAGE_TYPE_ASIC_VDDCI); | |
ed18a360 AD |
531 | if (rdev->pm.default_sclk) |
532 | radeon_set_engine_clock(rdev, rdev->pm.default_sclk); | |
533 | if (rdev->pm.default_mclk) | |
534 | radeon_set_memory_clock(rdev, rdev->pm.default_mclk); | |
535 | } | |
f8ed8b4c AD |
536 | /* asic init will reset the default power state */ |
537 | mutex_lock(&rdev->pm.mutex); | |
538 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; | |
539 | rdev->pm.current_clock_mode_index = 0; | |
9ace9f7b AD |
540 | rdev->pm.current_sclk = rdev->pm.default_sclk; |
541 | rdev->pm.current_mclk = rdev->pm.default_mclk; | |
4d60173f | 542 | rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; |
2feea49a | 543 | rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; |
3f53eb6f RW |
544 | if (rdev->pm.pm_method == PM_METHOD_DYNPM |
545 | && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { | |
546 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; | |
32c87fca TH |
547 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
548 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
3f53eb6f | 549 | } |
f8ed8b4c | 550 | mutex_unlock(&rdev->pm.mutex); |
ce8f5370 | 551 | radeon_pm_compute_clocks(rdev); |
d0d6cb81 RM |
552 | } |
553 | ||
7433874e RM |
554 | int radeon_pm_init(struct radeon_device *rdev) |
555 | { | |
26481fb1 | 556 | int ret; |
0d18abed | 557 | |
ce8f5370 AD |
558 | /* default to profile method */ |
559 | rdev->pm.pm_method = PM_METHOD_PROFILE; | |
f8ed8b4c | 560 | rdev->pm.profile = PM_PROFILE_DEFAULT; |
ce8f5370 AD |
561 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; |
562 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; | |
563 | rdev->pm.dynpm_can_upclock = true; | |
564 | rdev->pm.dynpm_can_downclock = true; | |
9ace9f7b AD |
565 | rdev->pm.default_sclk = rdev->clock.default_sclk; |
566 | rdev->pm.default_mclk = rdev->clock.default_mclk; | |
f8ed8b4c AD |
567 | rdev->pm.current_sclk = rdev->clock.default_sclk; |
568 | rdev->pm.current_mclk = rdev->clock.default_mclk; | |
21a8122a | 569 | rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; |
c913e23a | 570 | |
56278a8e AD |
571 | if (rdev->bios) { |
572 | if (rdev->is_atom_bios) | |
573 | radeon_atombios_get_power_modes(rdev); | |
574 | else | |
575 | radeon_combios_get_power_modes(rdev); | |
f712d0c7 | 576 | radeon_pm_print_states(rdev); |
ce8f5370 | 577 | radeon_pm_init_profile(rdev); |
ed18a360 AD |
578 | /* set up the default clocks if the MC ucode is loaded */ |
579 | if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) { | |
580 | if (rdev->pm.default_vddc) | |
8a83ec5e AD |
581 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
582 | SET_VOLTAGE_TYPE_ASIC_VDDC); | |
4639dd21 AD |
583 | if (rdev->pm.default_vddci) |
584 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, | |
585 | SET_VOLTAGE_TYPE_ASIC_VDDCI); | |
ed18a360 AD |
586 | if (rdev->pm.default_sclk) |
587 | radeon_set_engine_clock(rdev, rdev->pm.default_sclk); | |
588 | if (rdev->pm.default_mclk) | |
589 | radeon_set_memory_clock(rdev, rdev->pm.default_mclk); | |
590 | } | |
56278a8e AD |
591 | } |
592 | ||
21a8122a | 593 | /* set up the internal thermal sensor if applicable */ |
0d18abed DC |
594 | ret = radeon_hwmon_init(rdev); |
595 | if (ret) | |
596 | return ret; | |
32c87fca TH |
597 | |
598 | INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); | |
599 | ||
ce8f5370 | 600 | if (rdev->pm.num_power_states > 1) { |
ce8f5370 | 601 | /* where's the best place to put these? */ |
26481fb1 DA |
602 | ret = device_create_file(rdev->dev, &dev_attr_power_profile); |
603 | if (ret) | |
604 | DRM_ERROR("failed to create device file for power profile\n"); | |
605 | ret = device_create_file(rdev->dev, &dev_attr_power_method); | |
606 | if (ret) | |
607 | DRM_ERROR("failed to create device file for power method\n"); | |
a424816f | 608 | |
ce8f5370 AD |
609 | if (radeon_debugfs_pm_init(rdev)) { |
610 | DRM_ERROR("Failed to register debugfs file for PM!\n"); | |
611 | } | |
c913e23a | 612 | |
ce8f5370 AD |
613 | DRM_INFO("radeon: power management initialized\n"); |
614 | } | |
c913e23a | 615 | |
7433874e RM |
616 | return 0; |
617 | } | |
618 | ||
29fb52ca AD |
619 | void radeon_pm_fini(struct radeon_device *rdev) |
620 | { | |
ce8f5370 | 621 | if (rdev->pm.num_power_states > 1) { |
a424816f | 622 | mutex_lock(&rdev->pm.mutex); |
ce8f5370 AD |
623 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
624 | rdev->pm.profile = PM_PROFILE_DEFAULT; | |
625 | radeon_pm_update_profile(rdev); | |
626 | radeon_pm_set_clocks(rdev); | |
627 | } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { | |
ce8f5370 AD |
628 | /* reset default clocks */ |
629 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; | |
630 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; | |
631 | radeon_pm_set_clocks(rdev); | |
632 | } | |
a424816f | 633 | mutex_unlock(&rdev->pm.mutex); |
32c87fca TH |
634 | |
635 | cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); | |
58e21dff | 636 | |
ce8f5370 AD |
637 | device_remove_file(rdev->dev, &dev_attr_power_profile); |
638 | device_remove_file(rdev->dev, &dev_attr_power_method); | |
ce8f5370 | 639 | } |
a424816f | 640 | |
0975b162 AD |
641 | if (rdev->pm.power_state) |
642 | kfree(rdev->pm.power_state); | |
643 | ||
21a8122a | 644 | radeon_hwmon_fini(rdev); |
29fb52ca AD |
645 | } |
646 | ||
c913e23a RM |
647 | void radeon_pm_compute_clocks(struct radeon_device *rdev) |
648 | { | |
649 | struct drm_device *ddev = rdev->ddev; | |
a48b9b4e | 650 | struct drm_crtc *crtc; |
c913e23a | 651 | struct radeon_crtc *radeon_crtc; |
c913e23a | 652 | |
ce8f5370 AD |
653 | if (rdev->pm.num_power_states < 2) |
654 | return; | |
655 | ||
c913e23a RM |
656 | mutex_lock(&rdev->pm.mutex); |
657 | ||
658 | rdev->pm.active_crtcs = 0; | |
a48b9b4e AD |
659 | rdev->pm.active_crtc_count = 0; |
660 | list_for_each_entry(crtc, | |
661 | &ddev->mode_config.crtc_list, head) { | |
662 | radeon_crtc = to_radeon_crtc(crtc); | |
663 | if (radeon_crtc->enabled) { | |
c913e23a | 664 | rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); |
a48b9b4e | 665 | rdev->pm.active_crtc_count++; |
c913e23a RM |
666 | } |
667 | } | |
668 | ||
ce8f5370 AD |
669 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
670 | radeon_pm_update_profile(rdev); | |
671 | radeon_pm_set_clocks(rdev); | |
672 | } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { | |
673 | if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { | |
674 | if (rdev->pm.active_crtc_count > 1) { | |
675 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { | |
676 | cancel_delayed_work(&rdev->pm.dynpm_idle_work); | |
677 | ||
678 | rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; | |
679 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; | |
680 | radeon_pm_get_dynpm_state(rdev); | |
681 | radeon_pm_set_clocks(rdev); | |
682 | ||
d9fdaafb | 683 | DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); |
ce8f5370 AD |
684 | } |
685 | } else if (rdev->pm.active_crtc_count == 1) { | |
686 | /* TODO: Increase clocks if needed for current mode */ | |
687 | ||
688 | if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { | |
689 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; | |
690 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; | |
691 | radeon_pm_get_dynpm_state(rdev); | |
692 | radeon_pm_set_clocks(rdev); | |
693 | ||
32c87fca TH |
694 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
695 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
ce8f5370 AD |
696 | } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { |
697 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; | |
32c87fca TH |
698 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
699 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
d9fdaafb | 700 | DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); |
ce8f5370 AD |
701 | } |
702 | } else { /* count == 0 */ | |
703 | if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { | |
704 | cancel_delayed_work(&rdev->pm.dynpm_idle_work); | |
705 | ||
706 | rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; | |
707 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; | |
708 | radeon_pm_get_dynpm_state(rdev); | |
709 | radeon_pm_set_clocks(rdev); | |
710 | } | |
711 | } | |
c913e23a | 712 | } |
c913e23a | 713 | } |
73a6d3fc RM |
714 | |
715 | mutex_unlock(&rdev->pm.mutex); | |
c913e23a RM |
716 | } |
717 | ||
ce8f5370 | 718 | static bool radeon_pm_in_vbl(struct radeon_device *rdev) |
f735261b | 719 | { |
75fa0b08 | 720 | int crtc, vpos, hpos, vbl_status; |
f735261b DA |
721 | bool in_vbl = true; |
722 | ||
75fa0b08 MK |
723 | /* Iterate over all active crtc's. All crtc's must be in vblank, |
724 | * otherwise return in_vbl == false. | |
725 | */ | |
726 | for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { | |
727 | if (rdev->pm.active_crtcs & (1 << crtc)) { | |
f5a80209 MK |
728 | vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos); |
729 | if ((vbl_status & DRM_SCANOUTPOS_VALID) && | |
730 | !(vbl_status & DRM_SCANOUTPOS_INVBL)) | |
f735261b DA |
731 | in_vbl = false; |
732 | } | |
733 | } | |
f81f2024 MG |
734 | |
735 | return in_vbl; | |
736 | } | |
737 | ||
ce8f5370 | 738 | static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) |
f81f2024 MG |
739 | { |
740 | u32 stat_crtc = 0; | |
741 | bool in_vbl = radeon_pm_in_vbl(rdev); | |
742 | ||
f735261b | 743 | if (in_vbl == false) |
d9fdaafb | 744 | DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, |
bae6b562 | 745 | finish ? "exit" : "entry"); |
f735261b DA |
746 | return in_vbl; |
747 | } | |
c913e23a | 748 | |
ce8f5370 | 749 | static void radeon_dynpm_idle_work_handler(struct work_struct *work) |
c913e23a RM |
750 | { |
751 | struct radeon_device *rdev; | |
d9932a32 | 752 | int resched; |
c913e23a | 753 | rdev = container_of(work, struct radeon_device, |
ce8f5370 | 754 | pm.dynpm_idle_work.work); |
c913e23a | 755 | |
d9932a32 | 756 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
c913e23a | 757 | mutex_lock(&rdev->pm.mutex); |
ce8f5370 | 758 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { |
c913e23a | 759 | int not_processed = 0; |
7465280c AD |
760 | int i; |
761 | ||
7465280c | 762 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
0ec0612a AD |
763 | struct radeon_ring *ring = &rdev->ring[i]; |
764 | ||
765 | if (ring->ready) { | |
766 | not_processed += radeon_fence_count_emitted(rdev, i); | |
767 | if (not_processed >= 3) | |
768 | break; | |
769 | } | |
c913e23a | 770 | } |
c913e23a RM |
771 | |
772 | if (not_processed >= 3) { /* should upclock */ | |
ce8f5370 AD |
773 | if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { |
774 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; | |
775 | } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && | |
776 | rdev->pm.dynpm_can_upclock) { | |
777 | rdev->pm.dynpm_planned_action = | |
778 | DYNPM_ACTION_UPCLOCK; | |
779 | rdev->pm.dynpm_action_timeout = jiffies + | |
c913e23a RM |
780 | msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); |
781 | } | |
782 | } else if (not_processed == 0) { /* should downclock */ | |
ce8f5370 AD |
783 | if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { |
784 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; | |
785 | } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && | |
786 | rdev->pm.dynpm_can_downclock) { | |
787 | rdev->pm.dynpm_planned_action = | |
788 | DYNPM_ACTION_DOWNCLOCK; | |
789 | rdev->pm.dynpm_action_timeout = jiffies + | |
c913e23a RM |
790 | msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); |
791 | } | |
792 | } | |
793 | ||
d7311171 AD |
794 | /* Note, radeon_pm_set_clocks is called with static_switch set |
795 | * to false since we want to wait for vbl to avoid flicker. | |
796 | */ | |
ce8f5370 AD |
797 | if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && |
798 | jiffies > rdev->pm.dynpm_action_timeout) { | |
799 | radeon_pm_get_dynpm_state(rdev); | |
800 | radeon_pm_set_clocks(rdev); | |
c913e23a | 801 | } |
3f53eb6f | 802 | |
32c87fca TH |
803 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
804 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
c913e23a RM |
805 | } |
806 | mutex_unlock(&rdev->pm.mutex); | |
d9932a32 | 807 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
c913e23a RM |
808 | } |
809 | ||
7433874e RM |
810 | /* |
811 | * Debugfs info | |
812 | */ | |
813 | #if defined(CONFIG_DEBUG_FS) | |
814 | ||
815 | static int radeon_debugfs_pm_info(struct seq_file *m, void *data) | |
816 | { | |
817 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
818 | struct drm_device *dev = node->minor->dev; | |
819 | struct radeon_device *rdev = dev->dev_private; | |
820 | ||
9ace9f7b | 821 | seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); |
6234077d | 822 | seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); |
9ace9f7b | 823 | seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); |
798bcf73 | 824 | if (rdev->asic->pm.get_memory_clock) |
6234077d | 825 | seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); |
0fcbe947 RM |
826 | if (rdev->pm.current_vddc) |
827 | seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); | |
798bcf73 | 828 | if (rdev->asic->pm.get_pcie_lanes) |
aa5120d2 | 829 | seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); |
7433874e RM |
830 | |
831 | return 0; | |
832 | } | |
833 | ||
834 | static struct drm_info_list radeon_pm_info_list[] = { | |
835 | {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, | |
836 | }; | |
837 | #endif | |
838 | ||
c913e23a | 839 | static int radeon_debugfs_pm_init(struct radeon_device *rdev) |
7433874e RM |
840 | { |
841 | #if defined(CONFIG_DEBUG_FS) | |
842 | return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); | |
843 | #else | |
844 | return 0; | |
845 | #endif | |
846 | } |