]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/gpu/drm/radeon/radeon_pm.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branches 'spi/topic/res', 'spi/topic/rockchip', 'spi/topic...
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
99736703 27#include "r600_dpm.h"
ce8f5370 28#include <linux/power_supply.h>
21a8122a
AD		 29#include <linux/hwmon.h>
30#include <linux/hwmon-sysfs.h>
7433874e 31
c913e23a
RM		 32#define RADEON_IDLE_LOOP_MS 100
33#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 34#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 35
f712d0c7 36static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 37 "",
f712d0c7
RM		 38 "Powersave",
39 "Battery",
40 "Balanced",
41 "Performance",
42};
43
ce8f5370 44static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 45static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 46static bool radeon_pm_in_vbl(struct radeon_device *rdev);
47static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
48static void radeon_pm_update_profile(struct radeon_device *rdev);
49static void radeon_pm_set_clocks(struct radeon_device *rdev);
50
a4c9e2ee
AD		 51int radeon_pm_get_type_index(struct radeon_device *rdev,
52 enum radeon_pm_state_type ps_type,
53 int instance)
54{
55 int i;
56 int found_instance = -1;
57
58 for (i = 0; i < rdev->pm.num_power_states; i++) {
59 if (rdev->pm.power_state[i].type == ps_type) {
60 found_instance++;
61 if (found_instance == instance)
62 return i;
63 }
64 }
65 /* return default if no match */
66 return rdev->pm.default_power_state_index;
67}
68
c4917074 69void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 70{
1c71bda0
AD		 71 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
72 mutex_lock(&rdev->pm.mutex);
73 if (power_supply_is_system_supplied() > 0)
74 rdev->pm.dpm.ac_power = true;
75 else
76 rdev->pm.dpm.ac_power = false;
96682956
AD		 77 if (rdev->family == CHIP_ARUBA) {
78 if (rdev->asic->dpm.enable_bapm)
79 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
80 }
1c71bda0
AD		 81 mutex_unlock(&rdev->pm.mutex);
82 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
c4917074
AD		 83 if (rdev->pm.profile == PM_PROFILE_AUTO) {
84 mutex_lock(&rdev->pm.mutex);
85 radeon_pm_update_profile(rdev);
86 radeon_pm_set_clocks(rdev);
87 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 88 }
89 }
ce8f5370 90}
ce8f5370
AD		 91
92static void radeon_pm_update_profile(struct radeon_device *rdev)
93{
94 switch (rdev->pm.profile) {
95 case PM_PROFILE_DEFAULT:
96 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
97 break;
98 case PM_PROFILE_AUTO:
99 if (power_supply_is_system_supplied() > 0) {
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
104 } else {
105 if (rdev->pm.active_crtc_count > 1)
c9e75b21 106 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 107 else
c9e75b21 108 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 109 }
110 break;
111 case PM_PROFILE_LOW:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
116 break;
c9e75b21
AD		 117 case PM_PROFILE_MID:
118 if (rdev->pm.active_crtc_count > 1)
119 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
120 else
121 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
122 break;
ce8f5370
AD		 123 case PM_PROFILE_HIGH:
124 if (rdev->pm.active_crtc_count > 1)
125 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
126 else
127 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
128 break;
129 }
130
131 if (rdev->pm.active_crtc_count == 0) {
132 rdev->pm.requested_power_state_index =
133 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
134 rdev->pm.requested_clock_mode_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
136 } else {
137 rdev->pm.requested_power_state_index =
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
139 rdev->pm.requested_clock_mode_index =
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
141 }
142}
c913e23a 143
5876dd24
MG		 144static void radeon_unmap_vram_bos(struct radeon_device *rdev)
145{
146 struct radeon_bo *bo, *n;
147
148 if (list_empty(&rdev->gem.objects))
149 return;
150
151 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
152 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
153 ttm_bo_unmap_virtual(&bo->tbo);
154 }
5876dd24
MG		 155}
156
ce8f5370 157static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 158{
ce8f5370
AD		 159 if (rdev->pm.active_crtcs) {
160 rdev->pm.vblank_sync = false;
161 wait_event_timeout(
162 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
163 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
164 }
165}
166
167static void radeon_set_power_state(struct radeon_device *rdev)
168{
169 u32 sclk, mclk;
92645879 170 bool misc_after = false;
ce8f5370
AD		 171
172 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
173 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
174 return;
175
176 if (radeon_gui_idle(rdev)) {
177 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
178 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 179 if (sclk > rdev->pm.default_sclk)
180 sclk = rdev->pm.default_sclk;
ce8f5370 181
27810fb2
AD		 182 /* starting with BTC, there is one state that is used for both
183 * MH and SH. Difference is that we always use the high clock index for
7ae764b1 184 * mclk and vddci.
27810fb2
AD		 185 */
186 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
187 (rdev->family >= CHIP_BARTS) &&
188 rdev->pm.active_crtc_count &&
189 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
190 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
193 else
194 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
195 clock_info[rdev->pm.requested_clock_mode_index].mclk;
196
9ace9f7b
AD		 197 if (mclk > rdev->pm.default_mclk)
198 mclk = rdev->pm.default_mclk;
ce8f5370 199
92645879
AD		 200 /* upvolt before raising clocks, downvolt after lowering clocks */
201 if (sclk < rdev->pm.current_sclk)
202 misc_after = true;
ce8f5370 203
92645879 204 radeon_sync_with_vblank(rdev);
ce8f5370 205
92645879 206 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 207 if (!radeon_pm_in_vbl(rdev))
208 return;
92645879 209 }
ce8f5370 210
92645879 211 radeon_pm_prepare(rdev);
ce8f5370 212
92645879
AD		 213 if (!misc_after)
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev);
216
217 /* set engine clock */
218 if (sclk != rdev->pm.current_sclk) {
219 radeon_pm_debug_check_in_vbl(rdev, false);
220 radeon_set_engine_clock(rdev, sclk);
221 radeon_pm_debug_check_in_vbl(rdev, true);
222 rdev->pm.current_sclk = sclk;
d9fdaafb 223 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 224 }
225
226 /* set memory clock */
798bcf73 227 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 228 radeon_pm_debug_check_in_vbl(rdev, false);
229 radeon_set_memory_clock(rdev, mclk);
230 radeon_pm_debug_check_in_vbl(rdev, true);
231 rdev->pm.current_mclk = mclk;
d9fdaafb 232 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 233 }
2aba631c 234
92645879
AD		 235 if (misc_after)
236 /* voltage, pcie lanes, etc.*/
237 radeon_pm_misc(rdev);
238
239 radeon_pm_finish(rdev);
240
ce8f5370
AD		 241 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
242 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
243 } else
d9fdaafb 244 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 245}
246
247static void radeon_pm_set_clocks(struct radeon_device *rdev)
248{
5f8f635e 249 int i, r;
c37d230a 250
4e186b2d
AD		 251 /* no need to take locks, etc. if nothing's going to change */
252 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
253 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
254 return;
255
db7fce39 256 down_write(&rdev->pm.mclk_lock);
d6999bc7 257 mutex_lock(&rdev->ring_lock);
4f3218cb 258
95f5a3ac
AD		 259 /* wait for the rings to drain */
260 for (i = 0; i < RADEON_NUM_RINGS; i++) {
261 struct radeon_ring *ring = &rdev->ring[i];
5f8f635e
JG		 262 if (!ring->ready) {
263 continue;
264 }
37615527 265 r = radeon_fence_wait_empty(rdev, i);
5f8f635e
JG		 266 if (r) {
267 /* needs a GPU reset dont reset here */
268 mutex_unlock(&rdev->ring_lock);
269 up_write(&rdev->pm.mclk_lock);
5f8f635e
JG		 270 return;
271 }
4f3218cb 272 }
95f5a3ac 273
5876dd24
MG		 274 radeon_unmap_vram_bos(rdev);
275
ce8f5370 276 if (rdev->irq.installed) {
2aba631c
MG		 277 for (i = 0; i < rdev->num_crtc; i++) {
278 if (rdev->pm.active_crtcs & (1 << i)) {
e0b34e38
MK		 279 /* This can fail if a modeset is in progress */
280 if (drm_vblank_get(rdev->ddev, i) == 0)
281 rdev->pm.req_vblank |= (1 << i);
282 else
283 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n",
284 i);
2aba631c
MG		 285 }
286 }
287 }
539d2418 288
ce8f5370 289 radeon_set_power_state(rdev);
2aba631c 290
ce8f5370 291 if (rdev->irq.installed) {
2aba631c
MG		 292 for (i = 0; i < rdev->num_crtc; i++) {
293 if (rdev->pm.req_vblank & (1 << i)) {
294 rdev->pm.req_vblank &= ~(1 << i);
295 drm_vblank_put(rdev->ddev, i);
296 }
297 }
298 }
5876dd24 299
a424816f
AD		 300 /* update display watermarks based on new power state */
301 radeon_update_bandwidth_info(rdev);
302 if (rdev->pm.active_crtc_count)
303 radeon_bandwidth_update(rdev);
304
ce8f5370 305 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 306
d6999bc7 307 mutex_unlock(&rdev->ring_lock);
db7fce39 308 up_write(&rdev->pm.mclk_lock);
a424816f
AD		 309}
310
f712d0c7
RM		 311static void radeon_pm_print_states(struct radeon_device *rdev)
312{
313 int i, j;
314 struct radeon_power_state *power_state;
315 struct radeon_pm_clock_info *clock_info;
316
d9fdaafb 317 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 318 for (i = 0; i < rdev->pm.num_power_states; i++) {
319 power_state = &rdev->pm.power_state[i];
d9fdaafb 320 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 321 radeon_pm_state_type_name[power_state->type]);
322 if (i == rdev->pm.default_power_state_index)
d9fdaafb 323 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 324 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 325 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 326 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 327 DRM_DEBUG_DRIVER("\tSingle display only\n");
328 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 329 for (j = 0; j < power_state->num_clock_modes; j++) {
330 clock_info = &(power_state->clock_info[j]);
331 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 332 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
333 j,
334 clock_info->sclk * 10);
f712d0c7 335 else
eb2c27a0
AD		 336 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
337 j,
338 clock_info->sclk * 10,
339 clock_info->mclk * 10,
340 clock_info->voltage.voltage);
f712d0c7
RM		 341 }
342 }
343}
344
ce8f5370
AD		 345static ssize_t radeon_get_pm_profile(struct device *dev,
346 struct device_attribute *attr,
347 char *buf)
a424816f 348{
3e4e2129 349 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 350 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 351 int cp = rdev->pm.profile;
a424816f 352
ce8f5370
AD		 353 return snprintf(buf, PAGE_SIZE, "%s\n",
354 (cp == PM_PROFILE_AUTO) ? "auto" :
355 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 356 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 357 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 358}
359
ce8f5370
AD		 360static ssize_t radeon_set_pm_profile(struct device *dev,
361 struct device_attribute *attr,
362 const char *buf,
363 size_t count)
a424816f 364{
3e4e2129 365 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 366 struct radeon_device *rdev = ddev->dev_private;
a424816f 367
4f2f2039
AD		 368 /* Can't set profile when the card is off */
369 if ((rdev->flags & RADEON_IS_PX) &&
370 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
371 return -EINVAL;
372
a424816f 373 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 374 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
375 if (strncmp("default", buf, strlen("default")) == 0)
376 rdev->pm.profile = PM_PROFILE_DEFAULT;
377 else if (strncmp("auto", buf, strlen("auto")) == 0)
378 rdev->pm.profile = PM_PROFILE_AUTO;
379 else if (strncmp("low", buf, strlen("low")) == 0)
380 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 381 else if (strncmp("mid", buf, strlen("mid")) == 0)
382 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 383 else if (strncmp("high", buf, strlen("high")) == 0)
384 rdev->pm.profile = PM_PROFILE_HIGH;
385 else {
1783e4bf 386 count = -EINVAL;
ce8f5370 387 goto fail;
a424816f 388 }
ce8f5370
AD		 389 radeon_pm_update_profile(rdev);
390 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 391 } else
392 count = -EINVAL;
393
ce8f5370 394fail:
a424816f
AD		 395 mutex_unlock(&rdev->pm.mutex);
396
397 return count;
398}
399
ce8f5370
AD		 400static ssize_t radeon_get_pm_method(struct device *dev,
401 struct device_attribute *attr,
402 char *buf)
a424816f 403{
3e4e2129 404 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 405 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 406 int pm = rdev->pm.pm_method;
a424816f
AD		 407
408 return snprintf(buf, PAGE_SIZE, "%s\n",
da321c8a
AD		 409 (pm == PM_METHOD_DYNPM) ? "dynpm" :
410 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
a424816f
AD		 411}
412
ce8f5370
AD		 413static ssize_t radeon_set_pm_method(struct device *dev,
414 struct device_attribute *attr,
415 const char *buf,
416 size_t count)
a424816f 417{
3e4e2129 418 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 419 struct radeon_device *rdev = ddev->dev_private;
a424816f 420
4f2f2039
AD		 421 /* Can't set method when the card is off */
422 if ((rdev->flags & RADEON_IS_PX) &&
423 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
424 count = -EINVAL;
425 goto fail;
426 }
427
da321c8a
AD		 428 /* we don't support the legacy modes with dpm */
429 if (rdev->pm.pm_method == PM_METHOD_DPM) {
430 count = -EINVAL;
431 goto fail;
432 }
ce8f5370
AD		 433
434 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 435 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 436 rdev->pm.pm_method = PM_METHOD_DYNPM;
437 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
438 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 439 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 440 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
441 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 442 /* disable dynpm */
443 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
444 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 445 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 446 mutex_unlock(&rdev->pm.mutex);
32c87fca 447 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 448 } else {
1783e4bf 449 count = -EINVAL;
ce8f5370
AD		 450 goto fail;
451 }
452 radeon_pm_compute_clocks(rdev);
453fail:
a424816f
AD		 454 return count;
455}
456
da321c8a
AD		 457static ssize_t radeon_get_dpm_state(struct device *dev,
458 struct device_attribute *attr,
459 char *buf)
460{
3e4e2129 461 struct drm_device *ddev = dev_get_drvdata(dev);
da321c8a
AD		 462 struct radeon_device *rdev = ddev->dev_private;
463 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
464
465 return snprintf(buf, PAGE_SIZE, "%s\n",
466 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
467 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
468}
469
470static ssize_t radeon_set_dpm_state(struct device *dev,
471 struct device_attribute *attr,
472 const char *buf,
473 size_t count)
474{
3e4e2129 475 struct drm_device *ddev = dev_get_drvdata(dev);
da321c8a
AD		 476 struct radeon_device *rdev = ddev->dev_private;
477
478 mutex_lock(&rdev->pm.mutex);
479 if (strncmp("battery", buf, strlen("battery")) == 0)
480 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
481 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
482 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
483 else if (strncmp("performance", buf, strlen("performance")) == 0)
484 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
485 else {
486 mutex_unlock(&rdev->pm.mutex);
487 count = -EINVAL;
488 goto fail;
489 }
490 mutex_unlock(&rdev->pm.mutex);
b07a657e
PR		 491
492 /* Can't set dpm state when the card is off */
493 if (!(rdev->flags & RADEON_IS_PX) ||
494 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
495 radeon_pm_compute_clocks(rdev);
496
da321c8a
AD		 497fail:
498 return count;
499}
500
70d01a5e
AD		 501static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
502 struct device_attribute *attr,
503 char *buf)
504{
3e4e2129 505 struct drm_device *ddev = dev_get_drvdata(dev);
70d01a5e
AD		 506 struct radeon_device *rdev = ddev->dev_private;
507 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
508
4f2f2039
AD		 509 if ((rdev->flags & RADEON_IS_PX) &&
510 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
511 return snprintf(buf, PAGE_SIZE, "off\n");
512
70d01a5e
AD		 513 return snprintf(buf, PAGE_SIZE, "%s\n",
514 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
515 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
516}
517
518static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
519 struct device_attribute *attr,
520 const char *buf,
521 size_t count)
522{
3e4e2129 523 struct drm_device *ddev = dev_get_drvdata(dev);
70d01a5e
AD		 524 struct radeon_device *rdev = ddev->dev_private;
525 enum radeon_dpm_forced_level level;
526 int ret = 0;
527
4f2f2039
AD		 528 /* Can't force performance level when the card is off */
529 if ((rdev->flags & RADEON_IS_PX) &&
530 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
531 return -EINVAL;
532
70d01a5e
AD		 533 mutex_lock(&rdev->pm.mutex);
534 if (strncmp("low", buf, strlen("low")) == 0) {
535 level = RADEON_DPM_FORCED_LEVEL_LOW;
536 } else if (strncmp("high", buf, strlen("high")) == 0) {
537 level = RADEON_DPM_FORCED_LEVEL_HIGH;
538 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
539 level = RADEON_DPM_FORCED_LEVEL_AUTO;
540 } else {
70d01a5e
AD		 541 count = -EINVAL;
542 goto fail;
543 }
544 if (rdev->asic->dpm.force_performance_level) {
0a17af37
AD		 545 if (rdev->pm.dpm.thermal_active) {
546 count = -EINVAL;
547 goto fail;
548 }
70d01a5e
AD		 549 ret = radeon_dpm_force_performance_level(rdev, level);
550 if (ret)
551 count = -EINVAL;
552 }
70d01a5e 553fail:
0a17af37
AD		 554 mutex_unlock(&rdev->pm.mutex);
555
70d01a5e
AD		 556 return count;
557}
558
99736703
OC		 559static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
560 struct device_attribute *attr,
561 char *buf)
562{
563 struct radeon_device *rdev = dev_get_drvdata(dev);
564 u32 pwm_mode = 0;
565
566 if (rdev->asic->dpm.fan_ctrl_get_mode)
567 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
568
569 /* never 0 (full-speed), fuse or smc-controlled always */
570 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
571}
572
573static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
574 struct device_attribute *attr,
575 const char *buf,
576 size_t count)
577{
578 struct radeon_device *rdev = dev_get_drvdata(dev);
579 int err;
580 int value;
581
582 if(!rdev->asic->dpm.fan_ctrl_set_mode)
583 return -EINVAL;
584
585 err = kstrtoint(buf, 10, &value);
586 if (err)
587 return err;
588
082452e1 589 switch (value) {
99736703
OC		 590 case 1: /* manual, percent-based */
591 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
592 break;
593 default: /* disable */
594 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
595 break;
596 }
597
598 return count;
599}
600
601static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
602 struct device_attribute *attr,
603 char *buf)
604{
605 return sprintf(buf, "%i\n", 0);
606}
607
608static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
609 struct device_attribute *attr,
610 char *buf)
611{
082452e1 612 return sprintf(buf, "%i\n", 255);
99736703
OC		 613}
614
615static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
616 struct device_attribute *attr,
617 const char *buf, size_t count)
618{
619 struct radeon_device *rdev = dev_get_drvdata(dev);
620 int err;
621 u32 value;
622
623 err = kstrtou32(buf, 10, &value);
624 if (err)
625 return err;
626
082452e1
AD		 627 value = (value * 100) / 255;
628
99736703
OC		 629 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
630 if (err)
631 return err;
632
633 return count;
634}
635
636static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
637 struct device_attribute *attr,
638 char *buf)
639{
640 struct radeon_device *rdev = dev_get_drvdata(dev);
641 int err;
642 u32 speed;
643
644 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
645 if (err)
646 return err;
647
082452e1
AD		 648 speed = (speed * 255) / 100;
649
99736703
OC		 650 return sprintf(buf, "%i\n", speed);
651}
652
ce8f5370
AD		 653static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
654static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
da321c8a 655static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
70d01a5e
AD		 656static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
657 radeon_get_dpm_forced_performance_level,
658 radeon_set_dpm_forced_performance_level);
a424816f 659
21a8122a
AD		 660static ssize_t radeon_hwmon_show_temp(struct device *dev,
661 struct device_attribute *attr,
662 char *buf)
663{
ec39f64b 664 struct radeon_device *rdev = dev_get_drvdata(dev);
4f2f2039 665 struct drm_device *ddev = rdev->ddev;
20d391d7 666 int temp;
21a8122a 667
4f2f2039
AD		 668 /* Can't get temperature when the card is off */
669 if ((rdev->flags & RADEON_IS_PX) &&
670 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
671 return -EINVAL;
672
6bd1c385
AD		 673 if (rdev->asic->pm.get_temperature)
674 temp = radeon_get_temperature(rdev);
675 else
21a8122a 676 temp = 0;
21a8122a
AD		 677
678 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
679}
680
6ea4e84d
JD		 681static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
682 struct device_attribute *attr,
683 char *buf)
684{
e4158f1b 685 struct radeon_device *rdev = dev_get_drvdata(dev);
6ea4e84d
JD		 686 int hyst = to_sensor_dev_attr(attr)->index;
687 int temp;
688
689 if (hyst)
690 temp = rdev->pm.dpm.thermal.min_temp;
691 else
692 temp = rdev->pm.dpm.thermal.max_temp;
693
694 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
695}
696
21a8122a 697static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
6ea4e84d
JD		 698static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
699static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
99736703
OC		 700static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
701static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
702static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
703static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
704
21a8122a
AD		 705
706static struct attribute *hwmon_attributes[] = {
707 &sensor_dev_attr_temp1_input.dev_attr.attr,
6ea4e84d
JD		 708 &sensor_dev_attr_temp1_crit.dev_attr.attr,
709 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
99736703
OC		 710 &sensor_dev_attr_pwm1.dev_attr.attr,
711 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
712 &sensor_dev_attr_pwm1_min.dev_attr.attr,
713 &sensor_dev_attr_pwm1_max.dev_attr.attr,
21a8122a
AD		 714 NULL
715};
716
6ea4e84d
JD		 717static umode_t hwmon_attributes_visible(struct kobject *kobj,
718 struct attribute *attr, int index)
719{
e3837b00 720 struct device *dev = kobj_to_dev(kobj);
e4158f1b 721 struct radeon_device *rdev = dev_get_drvdata(dev);
99736703 722 umode_t effective_mode = attr->mode;
6ea4e84d 723
2a7d44f4 724 /* Skip attributes if DPM is not enabled */
6ea4e84d
JD		 725 if (rdev->pm.pm_method != PM_METHOD_DPM &&
726 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2a7d44f4
AD		 727 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
728 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
729 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
730 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
731 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
6ea4e84d
JD		 732 return 0;
733
99736703
OC		 734 /* Skip fan attributes if fan is not present */
735 if (rdev->pm.no_fan &&
736 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
737 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
738 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
739 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
740 return 0;
741
742 /* mask fan attributes if we have no bindings for this asic to expose */
743 if ((!rdev->asic->dpm.get_fan_speed_percent &&
744 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
745 (!rdev->asic->dpm.fan_ctrl_get_mode &&
746 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
747 effective_mode &= ~S_IRUGO;
748
749 if ((!rdev->asic->dpm.set_fan_speed_percent &&
750 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
751 (!rdev->asic->dpm.fan_ctrl_set_mode &&
752 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
753 effective_mode &= ~S_IWUSR;
754
755 /* hide max/min values if we can't both query and manage the fan */
756 if ((!rdev->asic->dpm.set_fan_speed_percent &&
757 !rdev->asic->dpm.get_fan_speed_percent) &&
758 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
759 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
760 return 0;
761
762 return effective_mode;
6ea4e84d
JD		 763}
764
21a8122a
AD		 765static const struct attribute_group hwmon_attrgroup = {
766 .attrs = hwmon_attributes,
6ea4e84d 767 .is_visible = hwmon_attributes_visible,
21a8122a
AD		 768};
769
ec39f64b
GR		 770static const struct attribute_group *hwmon_groups[] = {
771 &hwmon_attrgroup,
772 NULL
773};
774
0d18abed 775static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 776{
0d18abed 777 int err = 0;
21a8122a
AD		 778
779 switch (rdev->pm.int_thermal_type) {
780 case THERMAL_TYPE_RV6XX:
781 case THERMAL_TYPE_RV770:
782 case THERMAL_TYPE_EVERGREEN:
457558ed 783 case THERMAL_TYPE_NI:
e33df25f 784 case THERMAL_TYPE_SUMO:
1bd47d2e 785 case THERMAL_TYPE_SI:
286d9cc6
AD		 786 case THERMAL_TYPE_CI:
787 case THERMAL_TYPE_KV:
6bd1c385 788 if (rdev->asic->pm.get_temperature == NULL)
5d7486c7 789 return err;
cb3e4e7c
AD		 790 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
791 "radeon", rdev,
792 hwmon_groups);
793 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
794 err = PTR_ERR(rdev->pm.int_hwmon_dev);
0d18abed
DC		 795 dev_err(rdev->dev,
796 "Unable to register hwmon device: %d\n", err);
0d18abed 797 }
21a8122a
AD		 798 break;
799 default:
800 break;
801 }
0d18abed
DC		 802
803 return err;
21a8122a
AD		 804}
805
cb3e4e7c
AD		 806static void radeon_hwmon_fini(struct radeon_device *rdev)
807{
808 if (rdev->pm.int_hwmon_dev)
809 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
810}
811
da321c8a
AD		 812static void radeon_dpm_thermal_work_handler(struct work_struct *work)
813{
814 struct radeon_device *rdev =
815 container_of(work, struct radeon_device,
816 pm.dpm.thermal.work);
817 /* switch to the thermal state */
818 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
819
820 if (!rdev->pm.dpm_enabled)
821 return;
822
823 if (rdev->asic->pm.get_temperature) {
824 int temp = radeon_get_temperature(rdev);
825
826 if (temp < rdev->pm.dpm.thermal.min_temp)
827 /* switch back the user state */
828 dpm_state = rdev->pm.dpm.user_state;
829 } else {
830 if (rdev->pm.dpm.thermal.high_to_low)
831 /* switch back the user state */
832 dpm_state = rdev->pm.dpm.user_state;
833 }
60320347
AD		 834 mutex_lock(&rdev->pm.mutex);
835 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
836 rdev->pm.dpm.thermal_active = true;
837 else
838 rdev->pm.dpm.thermal_active = false;
839 rdev->pm.dpm.state = dpm_state;
840 mutex_unlock(&rdev->pm.mutex);
841
842 radeon_pm_compute_clocks(rdev);
da321c8a
AD		 843}
844
3899ca84 845static bool radeon_dpm_single_display(struct radeon_device *rdev)
da321c8a 846{
48783069
AD		 847 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
848 true : false;
849
850 /* check if the vblank period is too short to adjust the mclk */
851 if (single_display && rdev->asic->dpm.vblank_too_short) {
852 if (radeon_dpm_vblank_too_short(rdev))
853 single_display = false;
854 }
da321c8a 855
951caa6a
AD		 856 /* 120hz tends to be problematic even if they are under the
857 * vblank limit.
858 */
859 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
860 single_display = false;
861
3899ca84
AD		 862 return single_display;
863}
864
865static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
866 enum radeon_pm_state_type dpm_state)
867{
868 int i;
869 struct radeon_ps *ps;
870 u32 ui_class;
871 bool single_display = radeon_dpm_single_display(rdev);
872
edcaa5b1
AD		 873 /* certain older asics have a separare 3D performance state,
874 * so try that first if the user selected performance
875 */
876 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
877 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
da321c8a
AD		 878 /* balanced states don't exist at the moment */
879 if (dpm_state == POWER_STATE_TYPE_BALANCED)
880 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
881
edcaa5b1 882restart_search:
da321c8a
AD		 883 /* Pick the best power state based on current conditions */
884 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
885 ps = &rdev->pm.dpm.ps[i];
886 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
887 switch (dpm_state) {
888 /* user states */
889 case POWER_STATE_TYPE_BATTERY:
890 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
891 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 892 if (single_display)
da321c8a
AD		 893 return ps;
894 } else
895 return ps;
896 }
897 break;
898 case POWER_STATE_TYPE_BALANCED:
899 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
900 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 901 if (single_display)
da321c8a
AD		 902 return ps;
903 } else
904 return ps;
905 }
906 break;
907 case POWER_STATE_TYPE_PERFORMANCE:
908 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
909 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 910 if (single_display)
da321c8a
AD		 911 return ps;
912 } else
913 return ps;
914 }
915 break;
916 /* internal states */
917 case POWER_STATE_TYPE_INTERNAL_UVD:
d4d3278c
AD		 918 if (rdev->pm.dpm.uvd_ps)
919 return rdev->pm.dpm.uvd_ps;
920 else
921 break;
da321c8a
AD		 922 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
923 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
924 return ps;
925 break;
926 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
927 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
928 return ps;
929 break;
930 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
931 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
932 return ps;
933 break;
934 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
935 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
936 return ps;
937 break;
938 case POWER_STATE_TYPE_INTERNAL_BOOT:
939 return rdev->pm.dpm.boot_ps;
940 case POWER_STATE_TYPE_INTERNAL_THERMAL:
941 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
942 return ps;
943 break;
944 case POWER_STATE_TYPE_INTERNAL_ACPI:
945 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
946 return ps;
947 break;
948 case POWER_STATE_TYPE_INTERNAL_ULV:
949 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
950 return ps;
951 break;
edcaa5b1
AD		 952 case POWER_STATE_TYPE_INTERNAL_3DPERF:
953 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
954 return ps;
955 break;
da321c8a
AD		 956 default:
957 break;
958 }
959 }
960 /* use a fallback state if we didn't match */
961 switch (dpm_state) {
962 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
ce3537d5
AD		 963 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
964 goto restart_search;
da321c8a
AD		 965 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
966 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
967 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
d4d3278c
AD		 968 if (rdev->pm.dpm.uvd_ps) {
969 return rdev->pm.dpm.uvd_ps;
970 } else {
971 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
972 goto restart_search;
973 }
da321c8a
AD		 974 case POWER_STATE_TYPE_INTERNAL_THERMAL:
975 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
976 goto restart_search;
977 case POWER_STATE_TYPE_INTERNAL_ACPI:
978 dpm_state = POWER_STATE_TYPE_BATTERY;
979 goto restart_search;
980 case POWER_STATE_TYPE_BATTERY:
edcaa5b1
AD		 981 case POWER_STATE_TYPE_BALANCED:
982 case POWER_STATE_TYPE_INTERNAL_3DPERF:
da321c8a
AD		 983 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
984 goto restart_search;
985 default:
986 break;
987 }
988
989 return NULL;
990}
991
992static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
993{
994 int i;
995 struct radeon_ps *ps;
996 enum radeon_pm_state_type dpm_state;
84dd1928 997 int ret;
3899ca84 998 bool single_display = radeon_dpm_single_display(rdev);
da321c8a
AD		 999
1000 /* if dpm init failed */
1001 if (!rdev->pm.dpm_enabled)
1002 return;
1003
1004 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1005 /* add other state override checks here */
8a227555
AD		 1006 if ((!rdev->pm.dpm.thermal_active) &&
1007 (!rdev->pm.dpm.uvd_active))
da321c8a
AD		 1008 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1009 }
1010 dpm_state = rdev->pm.dpm.state;
1011
1012 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1013 if (ps)
89c9bc56 1014 rdev->pm.dpm.requested_ps = ps;
da321c8a
AD		 1015 else
1016 return;
1017
d22b7e40 1018 /* no need to reprogram if nothing changed unless we are on BTC+ */
da321c8a 1019 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
b62d628b
AD		 1020 /* vce just modifies an existing state so force a change */
1021 if (ps->vce_active != rdev->pm.dpm.vce_active)
1022 goto force;
3899ca84
AD		 1023 /* user has made a display change (such as timing) */
1024 if (rdev->pm.dpm.single_display != single_display)
1025 goto force;
d22b7e40
AD		 1026 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1027 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
1028 * all we need to do is update the display configuration.
1029 */
1030 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1031 /* update display watermarks based on new power state */
1032 radeon_bandwidth_update(rdev);
1033 /* update displays */
1034 radeon_dpm_display_configuration_changed(rdev);
1035 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1036 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1037 }
1038 return;
1039 } else {
1040 /* for BTC+ if the num crtcs hasn't changed and state is the same,
1041 * nothing to do, if the num crtcs is > 1 and state is the same,
1042 * update display configuration.
1043 */
1044 if (rdev->pm.dpm.new_active_crtcs ==
1045 rdev->pm.dpm.current_active_crtcs) {
1046 return;
1047 } else {
1048 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1049 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1050 /* update display watermarks based on new power state */
1051 radeon_bandwidth_update(rdev);
1052 /* update displays */
1053 radeon_dpm_display_configuration_changed(rdev);
1054 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1055 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1056 return;
1057 }
1058 }
da321c8a 1059 }
da321c8a
AD		 1060 }
1061
b62d628b 1062force:
033a37df
AD		 1063 if (radeon_dpm == 1) {
1064 printk("switching from power state:\n");
1065 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1066 printk("switching to power state:\n");
1067 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1068 }
b62d628b 1069
da321c8a
AD		 1070 down_write(&rdev->pm.mclk_lock);
1071 mutex_lock(&rdev->ring_lock);
1072
b62d628b
AD		 1073 /* update whether vce is active */
1074 ps->vce_active = rdev->pm.dpm.vce_active;
1075
89c9bc56
AD		 1076 ret = radeon_dpm_pre_set_power_state(rdev);
1077 if (ret)
1078 goto done;
84dd1928 1079
da321c8a
AD		 1080 /* update display watermarks based on new power state */
1081 radeon_bandwidth_update(rdev);
da321c8a 1082
da321c8a
AD		 1083 /* wait for the rings to drain */
1084 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1085 struct radeon_ring *ring = &rdev->ring[i];
1086 if (ring->ready)
37615527 1087 radeon_fence_wait_empty(rdev, i);
da321c8a
AD		 1088 }
1089
1090 /* program the new power state */
1091 radeon_dpm_set_power_state(rdev);
1092
1093 /* update current power state */
1094 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1095
89c9bc56 1096 radeon_dpm_post_set_power_state(rdev);
84dd1928 1097
39d42750
AD		 1098 /* update displays */
1099 radeon_dpm_display_configuration_changed(rdev);
1100
5e031d9f
AD		 1101 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1102 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1103 rdev->pm.dpm.single_display = single_display;
1104
1cd8b21a 1105 if (rdev->asic->dpm.force_performance_level) {
14ac88af
AD		 1106 if (rdev->pm.dpm.thermal_active) {
1107 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1cd8b21a
AD		 1108 /* force low perf level for thermal */
1109 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
14ac88af
AD		 1110 /* save the user's level */
1111 rdev->pm.dpm.forced_level = level;
1112 } else {
1113 /* otherwise, user selected level */
1114 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1115 }
60320347
AD		 1116 }
1117
84dd1928 1118done:
da321c8a
AD		 1119 mutex_unlock(&rdev->ring_lock);
1120 up_write(&rdev->pm.mclk_lock);
da321c8a
AD		 1121}
1122
ce3537d5
AD		 1123void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1124{
1125 enum radeon_pm_state_type dpm_state;
1126
9e9d9762 1127 if (rdev->asic->dpm.powergate_uvd) {
ce3537d5 1128 mutex_lock(&rdev->pm.mutex);
8158eb9e
CK		 1129 /* don't powergate anything if we
1130 have active but pause streams */
1131 enable |= rdev->pm.dpm.sd > 0;
1132 enable |= rdev->pm.dpm.hd > 0;
9e9d9762
AD		 1133 /* enable/disable UVD */
1134 radeon_dpm_powergate_uvd(rdev, !enable);
ce3537d5
AD		 1135 mutex_unlock(&rdev->pm.mutex);
1136 } else {
9e9d9762
AD		 1137 if (enable) {
1138 mutex_lock(&rdev->pm.mutex);
1139 rdev->pm.dpm.uvd_active = true;
0690a229
AD		 1140 /* disable this for now */
1141#if 0
9e9d9762
AD		 1142 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1143 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1144 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1145 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1146 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1147 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1148 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1149 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1150 else
0690a229 1151#endif
9e9d9762
AD		 1152 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1153 rdev->pm.dpm.state = dpm_state;
1154 mutex_unlock(&rdev->pm.mutex);
1155 } else {
1156 mutex_lock(&rdev->pm.mutex);
1157 rdev->pm.dpm.uvd_active = false;
1158 mutex_unlock(&rdev->pm.mutex);
1159 }
ce3537d5 1160
9e9d9762
AD		 1161 radeon_pm_compute_clocks(rdev);
1162 }
ce3537d5
AD		 1163}
1164
03afe6f6
AD		 1165void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1166{
1167 if (enable) {
1168 mutex_lock(&rdev->pm.mutex);
1169 rdev->pm.dpm.vce_active = true;
1170 /* XXX select vce level based on ring/task */
1171 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1172 mutex_unlock(&rdev->pm.mutex);
1173 } else {
1174 mutex_lock(&rdev->pm.mutex);
1175 rdev->pm.dpm.vce_active = false;
1176 mutex_unlock(&rdev->pm.mutex);
1177 }
1178
1179 radeon_pm_compute_clocks(rdev);
1180}
1181
da321c8a 1182static void radeon_pm_suspend_old(struct radeon_device *rdev)
56278a8e 1183{
ce8f5370 1184 mutex_lock(&rdev->pm.mutex);
3f53eb6f 1185 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 1186 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1187 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 1188 }
ce8f5370 1189 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1190
1191 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 1192}
1193
da321c8a
AD		 1194static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1195{
1196 mutex_lock(&rdev->pm.mutex);
1197 /* disable dpm */
1198 radeon_dpm_disable(rdev);
1199 /* reset the power state */
1200 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1201 rdev->pm.dpm_enabled = false;
1202 mutex_unlock(&rdev->pm.mutex);
1203}
1204
1205void radeon_pm_suspend(struct radeon_device *rdev)
1206{
1207 if (rdev->pm.pm_method == PM_METHOD_DPM)
1208 radeon_pm_suspend_dpm(rdev);
1209 else
1210 radeon_pm_suspend_old(rdev);
1211}
1212
1213static void radeon_pm_resume_old(struct radeon_device *rdev)
d0d6cb81 1214{
ed18a360 1215 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1216 if ((rdev->family >= CHIP_BARTS) &&
36099186 1217 (rdev->family <= CHIP_CAYMAN) &&
2e3b3b10 1218 rdev->mc_fw) {
ed18a360 1219 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1220 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1221 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 1222 if (rdev->pm.default_vddci)
1223 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1224 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1225 if (rdev->pm.default_sclk)
1226 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1227 if (rdev->pm.default_mclk)
1228 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1229 }
f8ed8b4c
AD		 1230 /* asic init will reset the default power state */
1231 mutex_lock(&rdev->pm.mutex);
1232 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1233 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 1234 rdev->pm.current_sclk = rdev->pm.default_sclk;
1235 rdev->pm.current_mclk = rdev->pm.default_mclk;
37016951
MD		 1236 if (rdev->pm.power_state) {
1237 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1238 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1239 }
3f53eb6f
RW		 1240 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1241 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1242 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1243 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1244 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 1245 }
f8ed8b4c 1246 mutex_unlock(&rdev->pm.mutex);
ce8f5370 1247 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 1248}
1249
da321c8a
AD		 1250static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1251{
1252 int ret;
1253
1254 /* asic init will reset to the boot state */
1255 mutex_lock(&rdev->pm.mutex);
1256 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1257 radeon_dpm_setup_asic(rdev);
1258 ret = radeon_dpm_enable(rdev);
1259 mutex_unlock(&rdev->pm.mutex);
e14cd2bb
AD		 1260 if (ret)
1261 goto dpm_resume_fail;
e14cd2bb 1262 rdev->pm.dpm_enabled = true;
e14cd2bb
AD		 1263 return;
1264
1265dpm_resume_fail:
1266 DRM_ERROR("radeon: dpm resume failed\n");
1267 if ((rdev->family >= CHIP_BARTS) &&
1268 (rdev->family <= CHIP_CAYMAN) &&
1269 rdev->mc_fw) {
1270 if (rdev->pm.default_vddc)
1271 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1272 SET_VOLTAGE_TYPE_ASIC_VDDC);
1273 if (rdev->pm.default_vddci)
1274 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1275 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1276 if (rdev->pm.default_sclk)
1277 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1278 if (rdev->pm.default_mclk)
1279 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
da321c8a
AD		 1280 }
1281}
1282
1283void radeon_pm_resume(struct radeon_device *rdev)
1284{
1285 if (rdev->pm.pm_method == PM_METHOD_DPM)
1286 radeon_pm_resume_dpm(rdev);
1287 else
1288 radeon_pm_resume_old(rdev);
1289}
1290
1291static int radeon_pm_init_old(struct radeon_device *rdev)
7433874e 1292{
26481fb1 1293 int ret;
0d18abed 1294
f8ed8b4c 1295 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 1296 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1297 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1298 rdev->pm.dynpm_can_upclock = true;
1299 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 1300 rdev->pm.default_sclk = rdev->clock.default_sclk;
1301 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 1302 rdev->pm.current_sclk = rdev->clock.default_sclk;
1303 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 1304 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 1305
56278a8e
AD		 1306 if (rdev->bios) {
1307 if (rdev->is_atom_bios)
1308 radeon_atombios_get_power_modes(rdev);
1309 else
1310 radeon_combios_get_power_modes(rdev);
f712d0c7 1311 radeon_pm_print_states(rdev);
ce8f5370 1312 radeon_pm_init_profile(rdev);
ed18a360 1313 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1314 if ((rdev->family >= CHIP_BARTS) &&
36099186 1315 (rdev->family <= CHIP_CAYMAN) &&
2e3b3b10 1316 rdev->mc_fw) {
ed18a360 1317 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1318 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1319 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 1320 if (rdev->pm.default_vddci)
1321 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1322 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1323 if (rdev->pm.default_sclk)
1324 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1325 if (rdev->pm.default_mclk)
1326 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1327 }
56278a8e
AD		 1328 }
1329
21a8122a 1330 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 1331 ret = radeon_hwmon_init(rdev);
1332 if (ret)
1333 return ret;
32c87fca
TH		 1334
1335 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1336
ce8f5370 1337 if (rdev->pm.num_power_states > 1) {
ce8f5370
AD		 1338 if (radeon_debugfs_pm_init(rdev)) {
1339 DRM_ERROR("Failed to register debugfs file for PM!\n");
1340 }
c913e23a 1341
ce8f5370
AD		 1342 DRM_INFO("radeon: power management initialized\n");
1343 }
c913e23a 1344
7433874e
RM		 1345 return 0;
1346}
1347
da321c8a
AD		 1348static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1349{
1350 int i;
1351
1352 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1353 printk("== power state %d ==\n", i);
1354 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1355 }
1356}
1357
1358static int radeon_pm_init_dpm(struct radeon_device *rdev)
1359{
1360 int ret;
1361
1cd8b21a 1362 /* default to balanced state */
edcaa5b1
AD		 1363 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1364 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1cd8b21a 1365 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
da321c8a
AD		 1366 rdev->pm.default_sclk = rdev->clock.default_sclk;
1367 rdev->pm.default_mclk = rdev->clock.default_mclk;
1368 rdev->pm.current_sclk = rdev->clock.default_sclk;
1369 rdev->pm.current_mclk = rdev->clock.default_mclk;
1370 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1371
1372 if (rdev->bios && rdev->is_atom_bios)
1373 radeon_atombios_get_power_modes(rdev);
1374 else
1375 return -EINVAL;
1376
1377 /* set up the internal thermal sensor if applicable */
1378 ret = radeon_hwmon_init(rdev);
1379 if (ret)
1380 return ret;
1381
1382 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1383 mutex_lock(&rdev->pm.mutex);
1384 radeon_dpm_init(rdev);
1385 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
033a37df
AD		 1386 if (radeon_dpm == 1)
1387 radeon_dpm_print_power_states(rdev);
da321c8a
AD		 1388 radeon_dpm_setup_asic(rdev);
1389 ret = radeon_dpm_enable(rdev);
1390 mutex_unlock(&rdev->pm.mutex);
e14cd2bb
AD		 1391 if (ret)
1392 goto dpm_failed;
da321c8a 1393 rdev->pm.dpm_enabled = true;
da321c8a 1394
bb5abf9f
AD		 1395 if (radeon_debugfs_pm_init(rdev)) {
1396 DRM_ERROR("Failed to register debugfs file for dpm!\n");
da321c8a
AD		 1397 }
1398
bb5abf9f
AD		 1399 DRM_INFO("radeon: dpm initialized\n");
1400
da321c8a 1401 return 0;
e14cd2bb
AD		 1402
1403dpm_failed:
1404 rdev->pm.dpm_enabled = false;
1405 if ((rdev->family >= CHIP_BARTS) &&
1406 (rdev->family <= CHIP_CAYMAN) &&
1407 rdev->mc_fw) {
1408 if (rdev->pm.default_vddc)
1409 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1410 SET_VOLTAGE_TYPE_ASIC_VDDC);
1411 if (rdev->pm.default_vddci)
1412 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1413 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1414 if (rdev->pm.default_sclk)
1415 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1416 if (rdev->pm.default_mclk)
1417 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1418 }
1419 DRM_ERROR("radeon: dpm initialization failed\n");
1420 return ret;
da321c8a
AD		 1421}
1422
4369a69e
AD		 1423struct radeon_dpm_quirk {
1424 u32 chip_vendor;
1425 u32 chip_device;
1426 u32 subsys_vendor;
1427 u32 subsys_device;
1428};
1429
1430/* cards with dpm stability problems */
1431static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1432 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1433 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1434 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1435 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1436 { 0, 0, 0, 0 },
1437};
1438
da321c8a
AD		 1439int radeon_pm_init(struct radeon_device *rdev)
1440{
4369a69e
AD		 1441 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1442 bool disable_dpm = false;
1443
1444 /* Apply dpm quirks */
1445 while (p && p->chip_device != 0) {
1446 if (rdev->pdev->vendor == p->chip_vendor &&
1447 rdev->pdev->device == p->chip_device &&
1448 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1449 rdev->pdev->subsystem_device == p->subsys_device) {
1450 disable_dpm = true;
1451 break;
1452 }
1453 ++p;
1454 }
1455
da321c8a
AD		 1456 /* enable dpm on rv6xx+ */
1457 switch (rdev->family) {
4a6369e9
AD		 1458 case CHIP_RV610:
1459 case CHIP_RV630:
1460 case CHIP_RV620:
1461 case CHIP_RV635:
1462 case CHIP_RV670:
9d67006e
AD		 1463 case CHIP_RS780:
1464 case CHIP_RS880:
76e6dcec 1465 case CHIP_RV770:
8a53fa23 1466 /* DPM requires the RLC, RV770+ dGPU requires SMC */
761bfb99
AD		 1467 if (!rdev->rlc_fw)
1468 rdev->pm.pm_method = PM_METHOD_PROFILE;
8a53fa23
AD		 1469 else if ((rdev->family >= CHIP_RV770) &&
1470 (!(rdev->flags & RADEON_IS_IGP)) &&
1471 (!rdev->smc_fw))
1472 rdev->pm.pm_method = PM_METHOD_PROFILE;
761bfb99 1473 else if (radeon_dpm == 1)
9d67006e
AD		 1474 rdev->pm.pm_method = PM_METHOD_DPM;
1475 else
1476 rdev->pm.pm_method = PM_METHOD_PROFILE;
1477 break;
ab70b1dd
AD		 1478 case CHIP_RV730:
1479 case CHIP_RV710:
1480 case CHIP_RV740:
59f7a2f2
AD		 1481 case CHIP_CEDAR:
1482 case CHIP_REDWOOD:
1483 case CHIP_JUNIPER:
1484 case CHIP_CYPRESS:
1485 case CHIP_HEMLOCK:
5a16f761
AD		 1486 case CHIP_PALM:
1487 case CHIP_SUMO:
1488 case CHIP_SUMO2:
c08abf11
AD		 1489 case CHIP_BARTS:
1490 case CHIP_TURKS:
1491 case CHIP_CAICOS:
8f500af4 1492 case CHIP_CAYMAN:
3a118989 1493 case CHIP_ARUBA:
68bc7785
AD		 1494 case CHIP_TAHITI:
1495 case CHIP_PITCAIRN:
1496 case CHIP_VERDE:
1497 case CHIP_OLAND:
1498 case CHIP_HAINAN:
4f22dde3 1499 case CHIP_BONAIRE:
e308b1d3
AD		 1500 case CHIP_KABINI:
1501 case CHIP_KAVERI:
4f22dde3 1502 case CHIP_HAWAII:
7d032a4b 1503 case CHIP_MULLINS:
5a16f761
AD		 1504 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1505 if (!rdev->rlc_fw)
1506 rdev->pm.pm_method = PM_METHOD_PROFILE;
1507 else if ((rdev->family >= CHIP_RV770) &&
1508 (!(rdev->flags & RADEON_IS_IGP)) &&
1509 (!rdev->smc_fw))
1510 rdev->pm.pm_method = PM_METHOD_PROFILE;
4369a69e
AD		 1511 else if (disable_dpm && (radeon_dpm == -1))
1512 rdev->pm.pm_method = PM_METHOD_PROFILE;
5a16f761
AD		 1513 else if (radeon_dpm == 0)
1514 rdev->pm.pm_method = PM_METHOD_PROFILE;
1515 else
1516 rdev->pm.pm_method = PM_METHOD_DPM;
1517 break;
da321c8a
AD		 1518 default:
1519 /* default to profile method */
1520 rdev->pm.pm_method = PM_METHOD_PROFILE;
1521 break;
1522 }
1523
1524 if (rdev->pm.pm_method == PM_METHOD_DPM)
1525 return radeon_pm_init_dpm(rdev);
1526 else
1527 return radeon_pm_init_old(rdev);
1528}
1529
914a8987
AD		 1530int radeon_pm_late_init(struct radeon_device *rdev)
1531{
1532 int ret = 0;
1533
1534 if (rdev->pm.pm_method == PM_METHOD_DPM) {
51a4726b 1535 if (rdev->pm.dpm_enabled) {
49abb266
AD		 1536 if (!rdev->pm.sysfs_initialized) {
1537 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1538 if (ret)
1539 DRM_ERROR("failed to create device file for dpm state\n");
1540 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1541 if (ret)
1542 DRM_ERROR("failed to create device file for dpm state\n");
1543 /* XXX: these are noops for dpm but are here for backwards compat */
1544 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1545 if (ret)
1546 DRM_ERROR("failed to create device file for power profile\n");
1547 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1548 if (ret)
1549 DRM_ERROR("failed to create device file for power method\n");
24dd2f64 1550 rdev->pm.sysfs_initialized = true;
49abb266 1551 }
51a4726b
AD		 1552
1553 mutex_lock(&rdev->pm.mutex);
1554 ret = radeon_dpm_late_enable(rdev);
1555 mutex_unlock(&rdev->pm.mutex);
1556 if (ret) {
1557 rdev->pm.dpm_enabled = false;
1558 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1559 } else {
1560 /* set the dpm state for PX since there won't be
1561 * a modeset to call this.
1562 */
1563 radeon_pm_compute_clocks(rdev);
1564 }
1565 }
1566 } else {
49abb266
AD		 1567 if ((rdev->pm.num_power_states > 1) &&
1568 (!rdev->pm.sysfs_initialized)) {
51a4726b
AD		 1569 /* where's the best place to put these? */
1570 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1571 if (ret)
1572 DRM_ERROR("failed to create device file for power profile\n");
1573 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1574 if (ret)
1575 DRM_ERROR("failed to create device file for power method\n");
49abb266
AD		 1576 if (!ret)
1577 rdev->pm.sysfs_initialized = true;
51a4726b 1578 }
914a8987
AD		 1579 }
1580 return ret;
1581}
1582
da321c8a 1583static void radeon_pm_fini_old(struct radeon_device *rdev)
29fb52ca 1584{
ce8f5370 1585 if (rdev->pm.num_power_states > 1) {
a424816f 1586 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 1587 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1588 rdev->pm.profile = PM_PROFILE_DEFAULT;
1589 radeon_pm_update_profile(rdev);
1590 radeon_pm_set_clocks(rdev);
1591 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 1592 /* reset default clocks */
1593 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1594 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1595 radeon_pm_set_clocks(rdev);
1596 }
a424816f 1597 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1598
1599 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 1600
ce8f5370
AD		 1601 device_remove_file(rdev->dev, &dev_attr_power_profile);
1602 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 1603 }
a424816f 1604
cb3e4e7c 1605 radeon_hwmon_fini(rdev);
9c244878 1606 kfree(rdev->pm.power_state);
29fb52ca
AD		 1607}
1608
da321c8a
AD		 1609static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1610{
1611 if (rdev->pm.num_power_states > 1) {
1612 mutex_lock(&rdev->pm.mutex);
1613 radeon_dpm_disable(rdev);
1614 mutex_unlock(&rdev->pm.mutex);
1615
1616 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
70d01a5e 1617 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
da321c8a
AD		 1618 /* XXX backwards compat */
1619 device_remove_file(rdev->dev, &dev_attr_power_profile);
1620 device_remove_file(rdev->dev, &dev_attr_power_method);
1621 }
1622 radeon_dpm_fini(rdev);
1623
cb3e4e7c 1624 radeon_hwmon_fini(rdev);
9c244878 1625 kfree(rdev->pm.power_state);
da321c8a
AD		 1626}
1627
1628void radeon_pm_fini(struct radeon_device *rdev)
1629{
1630 if (rdev->pm.pm_method == PM_METHOD_DPM)
1631 radeon_pm_fini_dpm(rdev);
1632 else
1633 radeon_pm_fini_old(rdev);
1634}
1635
1636static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
c913e23a
RM		 1637{
1638 struct drm_device *ddev = rdev->ddev;
a48b9b4e 1639 struct drm_crtc *crtc;
c913e23a 1640 struct radeon_crtc *radeon_crtc;
c913e23a 1641
ce8f5370
AD		 1642 if (rdev->pm.num_power_states < 2)
1643 return;
1644
c913e23a
RM		 1645 mutex_lock(&rdev->pm.mutex);
1646
1647 rdev->pm.active_crtcs = 0;
a48b9b4e 1648 rdev->pm.active_crtc_count = 0;
3ed9a335
AD		 1649 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1650 list_for_each_entry(crtc,
1651 &ddev->mode_config.crtc_list, head) {
1652 radeon_crtc = to_radeon_crtc(crtc);
1653 if (radeon_crtc->enabled) {
1654 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1655 rdev->pm.active_crtc_count++;
1656 }
c913e23a
RM		 1657 }
1658 }
1659
ce8f5370
AD		 1660 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1661 radeon_pm_update_profile(rdev);
1662 radeon_pm_set_clocks(rdev);
1663 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1664 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1665 if (rdev->pm.active_crtc_count > 1) {
1666 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1667 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1668
1669 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1670 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1671 radeon_pm_get_dynpm_state(rdev);
1672 radeon_pm_set_clocks(rdev);
1673
d9fdaafb 1674 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 1675 }
1676 } else if (rdev->pm.active_crtc_count == 1) {
1677 /* TODO: Increase clocks if needed for current mode */
1678
1679 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1680 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1681 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1682 radeon_pm_get_dynpm_state(rdev);
1683 radeon_pm_set_clocks(rdev);
1684
32c87fca
TH		 1685 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1686 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 1687 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1688 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1689 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1690 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 1691 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 1692 }
1693 } else { /* count == 0 */
1694 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1695 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1696
1697 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1698 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1699 radeon_pm_get_dynpm_state(rdev);
1700 radeon_pm_set_clocks(rdev);
1701 }
1702 }
c913e23a 1703 }
c913e23a 1704 }
73a6d3fc
RM		 1705
1706 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 1707}
1708
da321c8a
AD		 1709static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1710{
1711 struct drm_device *ddev = rdev->ddev;
1712 struct drm_crtc *crtc;
1713 struct radeon_crtc *radeon_crtc;
1714
6c7bccea
AD		 1715 if (!rdev->pm.dpm_enabled)
1716 return;
1717
da321c8a
AD		 1718 mutex_lock(&rdev->pm.mutex);
1719
5ca302f7 1720 /* update active crtc counts */
da321c8a
AD		 1721 rdev->pm.dpm.new_active_crtcs = 0;
1722 rdev->pm.dpm.new_active_crtc_count = 0;
3ed9a335
AD		 1723 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1724 list_for_each_entry(crtc,
1725 &ddev->mode_config.crtc_list, head) {
1726 radeon_crtc = to_radeon_crtc(crtc);
1727 if (crtc->enabled) {
1728 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1729 rdev->pm.dpm.new_active_crtc_count++;
1730 }
da321c8a
AD		 1731 }
1732 }
1733
5ca302f7
AD		 1734 /* update battery/ac status */
1735 if (power_supply_is_system_supplied() > 0)
1736 rdev->pm.dpm.ac_power = true;
1737 else
1738 rdev->pm.dpm.ac_power = false;
1739
da321c8a
AD		 1740 radeon_dpm_change_power_state_locked(rdev);
1741
1742 mutex_unlock(&rdev->pm.mutex);
8a227555 1743
da321c8a
AD		 1744}
1745
1746void radeon_pm_compute_clocks(struct radeon_device *rdev)
1747{
1748 if (rdev->pm.pm_method == PM_METHOD_DPM)
1749 radeon_pm_compute_clocks_dpm(rdev);
1750 else
1751 radeon_pm_compute_clocks_old(rdev);
1752}
1753
ce8f5370 1754static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 1755{
75fa0b08 1756 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 1757 bool in_vbl = true;
1758
75fa0b08
MK		 1759 /* Iterate over all active crtc's. All crtc's must be in vblank,
1760 * otherwise return in_vbl == false.
1761 */
1762 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1763 if (rdev->pm.active_crtcs & (1 << crtc)) {
5b5561b3
MK		 1764 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev,
1765 crtc,
1766 USE_REAL_VBLANKSTART,
3bb403bf
VS		 1767 &vpos, &hpos, NULL, NULL,
1768 &rdev->mode_info.crtcs[crtc]->base.hwmode);
f5a80209 1769 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
3d3cbd84 1770 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
f735261b
DA		 1771 in_vbl = false;
1772 }
1773 }
f81f2024
MG		 1774
1775 return in_vbl;
1776}
1777
ce8f5370 1778static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 1779{
1780 u32 stat_crtc = 0;
1781 bool in_vbl = radeon_pm_in_vbl(rdev);
1782
f735261b 1783 if (in_vbl == false)
d9fdaafb 1784 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 1785 finish ? "exit" : "entry");
f735261b
DA		 1786 return in_vbl;
1787}
c913e23a 1788
ce8f5370 1789static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 1790{
1791 struct radeon_device *rdev;
d9932a32 1792 int resched;
c913e23a 1793 rdev = container_of(work, struct radeon_device,
ce8f5370 1794 pm.dynpm_idle_work.work);
c913e23a 1795
d9932a32 1796 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 1797 mutex_lock(&rdev->pm.mutex);
ce8f5370 1798 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 1799 int not_processed = 0;
7465280c
AD		 1800 int i;
1801
7465280c 1802 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 1803 struct radeon_ring *ring = &rdev->ring[i];
1804
1805 if (ring->ready) {
1806 not_processed += radeon_fence_count_emitted(rdev, i);
1807 if (not_processed >= 3)
1808 break;
1809 }
c913e23a 1810 }
c913e23a
RM		 1811
1812 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 1813 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1814 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1815 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1816 rdev->pm.dynpm_can_upclock) {
1817 rdev->pm.dynpm_planned_action =
1818 DYNPM_ACTION_UPCLOCK;
1819 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1820 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1821 }
1822 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 1823 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1824 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1825 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1826 rdev->pm.dynpm_can_downclock) {
1827 rdev->pm.dynpm_planned_action =
1828 DYNPM_ACTION_DOWNCLOCK;
1829 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1830 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1831 }
1832 }
1833
d7311171
AD		 1834 /* Note, radeon_pm_set_clocks is called with static_switch set
1835 * to false since we want to wait for vbl to avoid flicker.
1836 */
ce8f5370
AD		 1837 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1838 jiffies > rdev->pm.dynpm_action_timeout) {
1839 radeon_pm_get_dynpm_state(rdev);
1840 radeon_pm_set_clocks(rdev);
c913e23a 1841 }
3f53eb6f 1842
32c87fca
TH		 1843 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1844 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 1845 }
1846 mutex_unlock(&rdev->pm.mutex);
d9932a32 1847 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 1848}
1849
7433874e
RM		 1850/*
1851 * Debugfs info
1852 */
1853#if defined(CONFIG_DEBUG_FS)
1854
1855static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1856{
1857 struct drm_info_node *node = (struct drm_info_node *) m->private;
1858 struct drm_device *dev = node->minor->dev;
1859 struct radeon_device *rdev = dev->dev_private;
4f2f2039 1860 struct drm_device *ddev = rdev->ddev;
7433874e 1861
4f2f2039
AD		 1862 if ((rdev->flags & RADEON_IS_PX) &&
1863 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1864 seq_printf(m, "PX asic powered off\n");
1865 } else if (rdev->pm.dpm_enabled) {
1316b792
AD		 1866 mutex_lock(&rdev->pm.mutex);
1867 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1868 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1869 else
71375929 1870 seq_printf(m, "Debugfs support not implemented for this asic\n");
1316b792
AD		 1871 mutex_unlock(&rdev->pm.mutex);
1872 } else {
1873 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1874 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1875 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1876 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1877 else
1878 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1879 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1880 if (rdev->asic->pm.get_memory_clock)
1881 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1882 if (rdev->pm.current_vddc)
1883 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1884 if (rdev->asic->pm.get_pcie_lanes)
1885 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1886 }
7433874e
RM		 1887
1888 return 0;
1889}
1890
1891static struct drm_info_list radeon_pm_info_list[] = {
1892 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1893};
1894#endif
1895
c913e23a 1896static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 1897{
1898#if defined(CONFIG_DEBUG_FS)
1899 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1900#else
1901 return 0;
1902#endif
1903}
Ubuntu Jammy Linux kernel mirror