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Commit | Line | Data |
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7433874e RM |
1 | /* |
2 | * Permission is hereby granted, free of charge, to any person obtaining a | |
3 | * copy of this software and associated documentation files (the "Software"), | |
4 | * to deal in the Software without restriction, including without limitation | |
5 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
6 | * and/or sell copies of the Software, and to permit persons to whom the | |
7 | * Software is furnished to do so, subject to the following conditions: | |
8 | * | |
9 | * The above copyright notice and this permission notice shall be included in | |
10 | * all copies or substantial portions of the Software. | |
11 | * | |
12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
13 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
14 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
15 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
16 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
17 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
18 | * OTHER DEALINGS IN THE SOFTWARE. | |
19 | * | |
20 | * Authors: Rafał Miłecki <zajec5@gmail.com> | |
56278a8e | 21 | * Alex Deucher <alexdeucher@gmail.com> |
7433874e RM |
22 | */ |
23 | #include "drmP.h" | |
24 | #include "radeon.h" | |
f735261b | 25 | #include "avivod.h" |
7433874e | 26 | |
c913e23a RM |
27 | #define RADEON_IDLE_LOOP_MS 100 |
28 | #define RADEON_RECLOCK_DELAY_MS 200 | |
73a6d3fc | 29 | #define RADEON_WAIT_VBLANK_TIMEOUT 200 |
2031f77c | 30 | #define RADEON_WAIT_IDLE_TIMEOUT 200 |
c913e23a | 31 | |
c913e23a RM |
32 | static void radeon_pm_idle_work_handler(struct work_struct *work); |
33 | static int radeon_debugfs_pm_init(struct radeon_device *rdev); | |
34 | ||
5876dd24 MG |
35 | static void radeon_unmap_vram_bos(struct radeon_device *rdev) |
36 | { | |
37 | struct radeon_bo *bo, *n; | |
38 | ||
39 | if (list_empty(&rdev->gem.objects)) | |
40 | return; | |
41 | ||
42 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
43 | if (bo->tbo.mem.mem_type == TTM_PL_VRAM) | |
44 | ttm_bo_unmap_virtual(&bo->tbo); | |
45 | } | |
46 | ||
47 | if (rdev->gart.table.vram.robj) | |
48 | ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo); | |
49 | ||
50 | if (rdev->stollen_vga_memory) | |
51 | ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo); | |
52 | ||
53 | if (rdev->r600_blit.shader_obj) | |
54 | ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo); | |
55 | } | |
56 | ||
2aba631c | 57 | static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch) |
a424816f | 58 | { |
2aba631c MG |
59 | int i; |
60 | ||
a424816f AD |
61 | mutex_lock(&rdev->cp.mutex); |
62 | ||
63 | /* wait for GPU idle */ | |
64 | rdev->pm.gui_idle = false; | |
65 | rdev->irq.gui_idle = true; | |
66 | radeon_irq_set(rdev); | |
67 | wait_event_interruptible_timeout( | |
68 | rdev->irq.idle_queue, rdev->pm.gui_idle, | |
69 | msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT)); | |
70 | rdev->irq.gui_idle = false; | |
71 | radeon_irq_set(rdev); | |
72 | ||
5876dd24 MG |
73 | mutex_lock(&rdev->vram_mutex); |
74 | ||
75 | radeon_unmap_vram_bos(rdev); | |
76 | ||
2aba631c MG |
77 | if (!static_switch) { |
78 | for (i = 0; i < rdev->num_crtc; i++) { | |
79 | if (rdev->pm.active_crtcs & (1 << i)) { | |
80 | rdev->pm.req_vblank |= (1 << i); | |
81 | drm_vblank_get(rdev->ddev, i); | |
82 | } | |
83 | } | |
84 | } | |
85 | ||
86 | radeon_set_power_state(rdev, static_switch); | |
87 | ||
88 | if (!static_switch) { | |
89 | for (i = 0; i < rdev->num_crtc; i++) { | |
90 | if (rdev->pm.req_vblank & (1 << i)) { | |
91 | rdev->pm.req_vblank &= ~(1 << i); | |
92 | drm_vblank_put(rdev->ddev, i); | |
93 | } | |
94 | } | |
95 | } | |
5876dd24 MG |
96 | |
97 | mutex_unlock(&rdev->vram_mutex); | |
2aba631c | 98 | |
a424816f AD |
99 | /* update display watermarks based on new power state */ |
100 | radeon_update_bandwidth_info(rdev); | |
101 | if (rdev->pm.active_crtc_count) | |
102 | radeon_bandwidth_update(rdev); | |
103 | ||
2aba631c MG |
104 | rdev->pm.planned_action = PM_ACTION_NONE; |
105 | ||
a424816f AD |
106 | mutex_unlock(&rdev->cp.mutex); |
107 | } | |
108 | ||
109 | static ssize_t radeon_get_power_state_static(struct device *dev, | |
110 | struct device_attribute *attr, | |
111 | char *buf) | |
112 | { | |
113 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); | |
114 | struct radeon_device *rdev = ddev->dev_private; | |
115 | ||
116 | return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index, | |
117 | rdev->pm.current_clock_mode_index); | |
118 | } | |
119 | ||
120 | static ssize_t radeon_set_power_state_static(struct device *dev, | |
121 | struct device_attribute *attr, | |
122 | const char *buf, | |
123 | size_t count) | |
124 | { | |
125 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); | |
126 | struct radeon_device *rdev = ddev->dev_private; | |
127 | int ps, cm; | |
128 | ||
129 | if (sscanf(buf, "%u.%u", &ps, &cm) != 2) { | |
130 | DRM_ERROR("Invalid power state!\n"); | |
131 | return count; | |
132 | } | |
133 | ||
8f5b5e63 | 134 | mutex_lock(&rdev->ddev->struct_mutex); |
a424816f AD |
135 | mutex_lock(&rdev->pm.mutex); |
136 | if ((ps >= 0) && (ps < rdev->pm.num_power_states) && | |
137 | (cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) { | |
138 | if ((rdev->pm.active_crtc_count > 1) && | |
139 | (rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) { | |
140 | DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm); | |
141 | } else { | |
142 | /* disable dynpm */ | |
143 | rdev->pm.state = PM_STATE_DISABLED; | |
144 | rdev->pm.planned_action = PM_ACTION_NONE; | |
145 | rdev->pm.requested_power_state_index = ps; | |
146 | rdev->pm.requested_clock_mode_index = cm; | |
2aba631c | 147 | radeon_pm_set_clocks(rdev, true); |
a424816f AD |
148 | } |
149 | } else | |
150 | DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm); | |
151 | mutex_unlock(&rdev->pm.mutex); | |
8f5b5e63 | 152 | mutex_unlock(&rdev->ddev->struct_mutex); |
a424816f AD |
153 | |
154 | return count; | |
155 | } | |
156 | ||
157 | static ssize_t radeon_get_dynpm(struct device *dev, | |
158 | struct device_attribute *attr, | |
159 | char *buf) | |
160 | { | |
161 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); | |
162 | struct radeon_device *rdev = ddev->dev_private; | |
163 | ||
164 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
165 | (rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled"); | |
166 | } | |
167 | ||
168 | static ssize_t radeon_set_dynpm(struct device *dev, | |
169 | struct device_attribute *attr, | |
170 | const char *buf, | |
171 | size_t count) | |
172 | { | |
173 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); | |
174 | struct radeon_device *rdev = ddev->dev_private; | |
175 | int tmp = simple_strtoul(buf, NULL, 10); | |
176 | ||
177 | if (tmp == 0) { | |
178 | /* update power mode info */ | |
179 | radeon_pm_compute_clocks(rdev); | |
180 | /* disable dynpm */ | |
181 | mutex_lock(&rdev->pm.mutex); | |
182 | rdev->pm.state = PM_STATE_DISABLED; | |
183 | rdev->pm.planned_action = PM_ACTION_NONE; | |
184 | mutex_unlock(&rdev->pm.mutex); | |
185 | DRM_INFO("radeon: dynamic power management disabled\n"); | |
186 | } else if (tmp == 1) { | |
187 | if (rdev->pm.num_power_states > 1) { | |
188 | /* enable dynpm */ | |
8f5b5e63 | 189 | mutex_lock(&rdev->ddev->struct_mutex); |
a424816f AD |
190 | mutex_lock(&rdev->pm.mutex); |
191 | rdev->pm.state = PM_STATE_PAUSED; | |
192 | rdev->pm.planned_action = PM_ACTION_DEFAULT; | |
193 | radeon_get_power_state(rdev, rdev->pm.planned_action); | |
194 | mutex_unlock(&rdev->pm.mutex); | |
8f5b5e63 | 195 | mutex_unlock(&rdev->ddev->struct_mutex); |
a424816f AD |
196 | /* update power mode info */ |
197 | radeon_pm_compute_clocks(rdev); | |
198 | DRM_INFO("radeon: dynamic power management enabled\n"); | |
199 | } else | |
200 | DRM_ERROR("dynpm not valid on this system\n"); | |
201 | } else | |
202 | DRM_ERROR("Invalid setting: %d\n", tmp); | |
203 | ||
204 | return count; | |
205 | } | |
206 | ||
207 | static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static); | |
208 | static DEVICE_ATTR(dynpm, S_IRUGO | S_IWUSR, radeon_get_dynpm, radeon_set_dynpm); | |
209 | ||
210 | ||
c913e23a RM |
211 | static const char *pm_state_names[4] = { |
212 | "PM_STATE_DISABLED", | |
213 | "PM_STATE_MINIMUM", | |
214 | "PM_STATE_PAUSED", | |
215 | "PM_STATE_ACTIVE" | |
216 | }; | |
7433874e | 217 | |
0ec0e74f | 218 | static const char *pm_state_types[5] = { |
d91eeb78 | 219 | "", |
0ec0e74f AD |
220 | "Powersave", |
221 | "Battery", | |
222 | "Balanced", | |
223 | "Performance", | |
224 | }; | |
225 | ||
56278a8e AD |
226 | static void radeon_print_power_mode_info(struct radeon_device *rdev) |
227 | { | |
228 | int i, j; | |
229 | bool is_default; | |
230 | ||
231 | DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states); | |
232 | for (i = 0; i < rdev->pm.num_power_states; i++) { | |
a48b9b4e | 233 | if (rdev->pm.default_power_state_index == i) |
56278a8e AD |
234 | is_default = true; |
235 | else | |
236 | is_default = false; | |
0ec0e74f AD |
237 | DRM_INFO("State %d %s %s\n", i, |
238 | pm_state_types[rdev->pm.power_state[i].type], | |
239 | is_default ? "(default)" : ""); | |
56278a8e | 240 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) |
79daedc9 | 241 | DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes); |
a48b9b4e AD |
242 | if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY) |
243 | DRM_INFO("\tSingle display only\n"); | |
56278a8e AD |
244 | DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes); |
245 | for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) { | |
246 | if (rdev->flags & RADEON_IS_IGP) | |
247 | DRM_INFO("\t\t%d engine: %d\n", | |
248 | j, | |
249 | rdev->pm.power_state[i].clock_info[j].sclk * 10); | |
250 | else | |
251 | DRM_INFO("\t\t%d engine/memory: %d/%d\n", | |
252 | j, | |
253 | rdev->pm.power_state[i].clock_info[j].sclk * 10, | |
254 | rdev->pm.power_state[i].clock_info[j].mclk * 10); | |
255 | } | |
256 | } | |
257 | } | |
258 | ||
bae6b562 | 259 | void radeon_sync_with_vblank(struct radeon_device *rdev) |
d0d6cb81 RM |
260 | { |
261 | if (rdev->pm.active_crtcs) { | |
262 | rdev->pm.vblank_sync = false; | |
263 | wait_event_timeout( | |
264 | rdev->irq.vblank_queue, rdev->pm.vblank_sync, | |
265 | msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); | |
266 | } | |
267 | } | |
268 | ||
7433874e RM |
269 | int radeon_pm_init(struct radeon_device *rdev) |
270 | { | |
c913e23a RM |
271 | rdev->pm.state = PM_STATE_DISABLED; |
272 | rdev->pm.planned_action = PM_ACTION_NONE; | |
a48b9b4e AD |
273 | rdev->pm.can_upclock = true; |
274 | rdev->pm.can_downclock = true; | |
c913e23a | 275 | |
56278a8e AD |
276 | if (rdev->bios) { |
277 | if (rdev->is_atom_bios) | |
278 | radeon_atombios_get_power_modes(rdev); | |
279 | else | |
280 | radeon_combios_get_power_modes(rdev); | |
281 | radeon_print_power_mode_info(rdev); | |
282 | } | |
283 | ||
7433874e | 284 | if (radeon_debugfs_pm_init(rdev)) { |
c142c3e5 | 285 | DRM_ERROR("Failed to register debugfs file for PM!\n"); |
7433874e RM |
286 | } |
287 | ||
a424816f AD |
288 | /* where's the best place to put this? */ |
289 | device_create_file(rdev->dev, &dev_attr_power_state); | |
290 | device_create_file(rdev->dev, &dev_attr_dynpm); | |
291 | ||
c913e23a RM |
292 | INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler); |
293 | ||
90c39059 | 294 | if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) { |
c913e23a RM |
295 | rdev->pm.state = PM_STATE_PAUSED; |
296 | DRM_INFO("radeon: dynamic power management enabled\n"); | |
297 | } | |
298 | ||
299 | DRM_INFO("radeon: power management initialized\n"); | |
300 | ||
7433874e RM |
301 | return 0; |
302 | } | |
303 | ||
29fb52ca AD |
304 | void radeon_pm_fini(struct radeon_device *rdev) |
305 | { | |
58e21dff AD |
306 | if (rdev->pm.state != PM_STATE_DISABLED) { |
307 | /* cancel work */ | |
308 | cancel_delayed_work_sync(&rdev->pm.idle_work); | |
309 | /* reset default clocks */ | |
310 | rdev->pm.state = PM_STATE_DISABLED; | |
311 | rdev->pm.planned_action = PM_ACTION_DEFAULT; | |
2aba631c | 312 | radeon_pm_set_clocks(rdev, false); |
a424816f AD |
313 | } else if ((rdev->pm.current_power_state_index != |
314 | rdev->pm.default_power_state_index) || | |
315 | (rdev->pm.current_clock_mode_index != 0)) { | |
316 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; | |
317 | rdev->pm.requested_clock_mode_index = 0; | |
8f5b5e63 | 318 | mutex_lock(&rdev->ddev->struct_mutex); |
a424816f | 319 | mutex_lock(&rdev->pm.mutex); |
2aba631c | 320 | radeon_pm_set_clocks(rdev, true); |
a424816f | 321 | mutex_unlock(&rdev->pm.mutex); |
8f5b5e63 | 322 | mutex_unlock(&rdev->ddev->struct_mutex); |
58e21dff AD |
323 | } |
324 | ||
a424816f AD |
325 | device_remove_file(rdev->dev, &dev_attr_power_state); |
326 | device_remove_file(rdev->dev, &dev_attr_dynpm); | |
327 | ||
29fb52ca AD |
328 | if (rdev->pm.i2c_bus) |
329 | radeon_i2c_destroy(rdev->pm.i2c_bus); | |
330 | } | |
331 | ||
c913e23a RM |
332 | void radeon_pm_compute_clocks(struct radeon_device *rdev) |
333 | { | |
334 | struct drm_device *ddev = rdev->ddev; | |
a48b9b4e | 335 | struct drm_crtc *crtc; |
c913e23a | 336 | struct radeon_crtc *radeon_crtc; |
c913e23a RM |
337 | |
338 | if (rdev->pm.state == PM_STATE_DISABLED) | |
339 | return; | |
340 | ||
8f5b5e63 | 341 | mutex_lock(&rdev->ddev->struct_mutex); |
c913e23a RM |
342 | mutex_lock(&rdev->pm.mutex); |
343 | ||
344 | rdev->pm.active_crtcs = 0; | |
a48b9b4e AD |
345 | rdev->pm.active_crtc_count = 0; |
346 | list_for_each_entry(crtc, | |
347 | &ddev->mode_config.crtc_list, head) { | |
348 | radeon_crtc = to_radeon_crtc(crtc); | |
349 | if (radeon_crtc->enabled) { | |
c913e23a | 350 | rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); |
a48b9b4e | 351 | rdev->pm.active_crtc_count++; |
c913e23a RM |
352 | } |
353 | } | |
354 | ||
a48b9b4e | 355 | if (rdev->pm.active_crtc_count > 1) { |
c913e23a | 356 | if (rdev->pm.state == PM_STATE_ACTIVE) { |
c913e23a RM |
357 | cancel_delayed_work(&rdev->pm.idle_work); |
358 | ||
359 | rdev->pm.state = PM_STATE_PAUSED; | |
360 | rdev->pm.planned_action = PM_ACTION_UPCLOCK; | |
2aba631c | 361 | radeon_pm_set_clocks(rdev, false); |
c913e23a RM |
362 | |
363 | DRM_DEBUG("radeon: dynamic power management deactivated\n"); | |
c913e23a | 364 | } |
a48b9b4e | 365 | } else if (rdev->pm.active_crtc_count == 1) { |
c913e23a RM |
366 | /* TODO: Increase clocks if needed for current mode */ |
367 | ||
368 | if (rdev->pm.state == PM_STATE_MINIMUM) { | |
369 | rdev->pm.state = PM_STATE_ACTIVE; | |
370 | rdev->pm.planned_action = PM_ACTION_UPCLOCK; | |
2aba631c | 371 | radeon_pm_set_clocks(rdev, false); |
c913e23a RM |
372 | |
373 | queue_delayed_work(rdev->wq, &rdev->pm.idle_work, | |
374 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
a48b9b4e | 375 | } else if (rdev->pm.state == PM_STATE_PAUSED) { |
c913e23a RM |
376 | rdev->pm.state = PM_STATE_ACTIVE; |
377 | queue_delayed_work(rdev->wq, &rdev->pm.idle_work, | |
378 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
379 | DRM_DEBUG("radeon: dynamic power management activated\n"); | |
380 | } | |
a48b9b4e | 381 | } else { /* count == 0 */ |
c913e23a RM |
382 | if (rdev->pm.state != PM_STATE_MINIMUM) { |
383 | cancel_delayed_work(&rdev->pm.idle_work); | |
384 | ||
385 | rdev->pm.state = PM_STATE_MINIMUM; | |
386 | rdev->pm.planned_action = PM_ACTION_MINIMUM; | |
2aba631c | 387 | radeon_pm_set_clocks(rdev, false); |
c913e23a | 388 | } |
c913e23a | 389 | } |
73a6d3fc RM |
390 | |
391 | mutex_unlock(&rdev->pm.mutex); | |
8f5b5e63 | 392 | mutex_unlock(&rdev->ddev->struct_mutex); |
c913e23a RM |
393 | } |
394 | ||
bae6b562 | 395 | bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) |
f735261b | 396 | { |
bae6b562 | 397 | u32 stat_crtc = 0; |
f735261b DA |
398 | bool in_vbl = true; |
399 | ||
bae6b562 AD |
400 | if (ASIC_IS_DCE4(rdev)) { |
401 | if (rdev->pm.active_crtcs & (1 << 0)) { | |
402 | stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); | |
403 | if (!(stat_crtc & 1)) | |
404 | in_vbl = false; | |
405 | } | |
406 | if (rdev->pm.active_crtcs & (1 << 1)) { | |
407 | stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
408 | if (!(stat_crtc & 1)) | |
409 | in_vbl = false; | |
410 | } | |
411 | if (rdev->pm.active_crtcs & (1 << 2)) { | |
412 | stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); | |
413 | if (!(stat_crtc & 1)) | |
414 | in_vbl = false; | |
415 | } | |
416 | if (rdev->pm.active_crtcs & (1 << 3)) { | |
417 | stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
418 | if (!(stat_crtc & 1)) | |
419 | in_vbl = false; | |
420 | } | |
421 | if (rdev->pm.active_crtcs & (1 << 4)) { | |
422 | stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); | |
423 | if (!(stat_crtc & 1)) | |
424 | in_vbl = false; | |
425 | } | |
426 | if (rdev->pm.active_crtcs & (1 << 5)) { | |
427 | stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
428 | if (!(stat_crtc & 1)) | |
429 | in_vbl = false; | |
430 | } | |
431 | } else if (ASIC_IS_AVIVO(rdev)) { | |
432 | if (rdev->pm.active_crtcs & (1 << 0)) { | |
433 | stat_crtc = RREG32(D1CRTC_STATUS); | |
434 | if (!(stat_crtc & 1)) | |
435 | in_vbl = false; | |
436 | } | |
437 | if (rdev->pm.active_crtcs & (1 << 1)) { | |
438 | stat_crtc = RREG32(D2CRTC_STATUS); | |
439 | if (!(stat_crtc & 1)) | |
440 | in_vbl = false; | |
441 | } | |
442 | } else { | |
f735261b | 443 | if (rdev->pm.active_crtcs & (1 << 0)) { |
bae6b562 AD |
444 | stat_crtc = RREG32(RADEON_CRTC_STATUS); |
445 | if (!(stat_crtc & 1)) | |
f735261b DA |
446 | in_vbl = false; |
447 | } | |
448 | if (rdev->pm.active_crtcs & (1 << 1)) { | |
bae6b562 AD |
449 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); |
450 | if (!(stat_crtc & 1)) | |
f735261b DA |
451 | in_vbl = false; |
452 | } | |
453 | } | |
454 | if (in_vbl == false) | |
bae6b562 AD |
455 | DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc, |
456 | finish ? "exit" : "entry"); | |
f735261b DA |
457 | return in_vbl; |
458 | } | |
c913e23a RM |
459 | |
460 | static void radeon_pm_idle_work_handler(struct work_struct *work) | |
461 | { | |
462 | struct radeon_device *rdev; | |
d9932a32 | 463 | int resched; |
c913e23a RM |
464 | rdev = container_of(work, struct radeon_device, |
465 | pm.idle_work.work); | |
466 | ||
d9932a32 | 467 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
8f5b5e63 | 468 | mutex_lock(&rdev->ddev->struct_mutex); |
c913e23a | 469 | mutex_lock(&rdev->pm.mutex); |
73a6d3fc | 470 | if (rdev->pm.state == PM_STATE_ACTIVE) { |
c913e23a RM |
471 | unsigned long irq_flags; |
472 | int not_processed = 0; | |
473 | ||
474 | read_lock_irqsave(&rdev->fence_drv.lock, irq_flags); | |
475 | if (!list_empty(&rdev->fence_drv.emited)) { | |
476 | struct list_head *ptr; | |
477 | list_for_each(ptr, &rdev->fence_drv.emited) { | |
478 | /* count up to 3, that's enought info */ | |
479 | if (++not_processed >= 3) | |
480 | break; | |
481 | } | |
482 | } | |
483 | read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
484 | ||
485 | if (not_processed >= 3) { /* should upclock */ | |
486 | if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) { | |
487 | rdev->pm.planned_action = PM_ACTION_NONE; | |
488 | } else if (rdev->pm.planned_action == PM_ACTION_NONE && | |
a48b9b4e | 489 | rdev->pm.can_upclock) { |
c913e23a RM |
490 | rdev->pm.planned_action = |
491 | PM_ACTION_UPCLOCK; | |
492 | rdev->pm.action_timeout = jiffies + | |
493 | msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); | |
494 | } | |
495 | } else if (not_processed == 0) { /* should downclock */ | |
496 | if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) { | |
497 | rdev->pm.planned_action = PM_ACTION_NONE; | |
498 | } else if (rdev->pm.planned_action == PM_ACTION_NONE && | |
a48b9b4e | 499 | rdev->pm.can_downclock) { |
c913e23a RM |
500 | rdev->pm.planned_action = |
501 | PM_ACTION_DOWNCLOCK; | |
502 | rdev->pm.action_timeout = jiffies + | |
503 | msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); | |
504 | } | |
505 | } | |
506 | ||
507 | if (rdev->pm.planned_action != PM_ACTION_NONE && | |
73a6d3fc | 508 | jiffies > rdev->pm.action_timeout) { |
2aba631c | 509 | radeon_pm_set_clocks(rdev, false); |
c913e23a RM |
510 | } |
511 | } | |
512 | mutex_unlock(&rdev->pm.mutex); | |
8f5b5e63 | 513 | mutex_unlock(&rdev->ddev->struct_mutex); |
d9932a32 | 514 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
c913e23a RM |
515 | |
516 | queue_delayed_work(rdev->wq, &rdev->pm.idle_work, | |
517 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
518 | } | |
519 | ||
7433874e RM |
520 | /* |
521 | * Debugfs info | |
522 | */ | |
523 | #if defined(CONFIG_DEBUG_FS) | |
524 | ||
525 | static int radeon_debugfs_pm_info(struct seq_file *m, void *data) | |
526 | { | |
527 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
528 | struct drm_device *dev = node->minor->dev; | |
529 | struct radeon_device *rdev = dev->dev_private; | |
530 | ||
c913e23a | 531 | seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]); |
6234077d RM |
532 | seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk); |
533 | seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); | |
534 | seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk); | |
535 | if (rdev->asic->get_memory_clock) | |
536 | seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); | |
aa5120d2 RM |
537 | if (rdev->asic->get_pcie_lanes) |
538 | seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); | |
7433874e RM |
539 | |
540 | return 0; | |
541 | } | |
542 | ||
543 | static struct drm_info_list radeon_pm_info_list[] = { | |
544 | {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, | |
545 | }; | |
546 | #endif | |
547 | ||
c913e23a | 548 | static int radeon_debugfs_pm_init(struct radeon_device *rdev) |
7433874e RM |
549 | { |
550 | #if defined(CONFIG_DEBUG_FS) | |
551 | return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); | |
552 | #else | |
553 | return 0; | |
554 | #endif | |
555 | } |