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drm/radeon/cik: Add support for new ucode format (v5)
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370 27#include <linux/power_supply.h>
21a8122a
AD		 28#include <linux/hwmon.h>
29#include <linux/hwmon-sysfs.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 34
f712d0c7 35static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 36 "",
f712d0c7
RM		 37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41};
42
ce8f5370 43static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 44static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 45static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47static void radeon_pm_update_profile(struct radeon_device *rdev);
48static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
a4c9e2ee
AD		 50int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53{
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66}
67
c4917074 68void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 69{
1c71bda0
AD		 70 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71 mutex_lock(&rdev->pm.mutex);
72 if (power_supply_is_system_supplied() > 0)
73 rdev->pm.dpm.ac_power = true;
74 else
75 rdev->pm.dpm.ac_power = false;
96682956
AD		 76 if (rdev->family == CHIP_ARUBA) {
77 if (rdev->asic->dpm.enable_bapm)
78 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
79 }
1c71bda0
AD		 80 mutex_unlock(&rdev->pm.mutex);
81 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
c4917074
AD		 82 if (rdev->pm.profile == PM_PROFILE_AUTO) {
83 mutex_lock(&rdev->pm.mutex);
84 radeon_pm_update_profile(rdev);
85 radeon_pm_set_clocks(rdev);
86 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 87 }
88 }
ce8f5370 89}
ce8f5370
AD		 90
91static void radeon_pm_update_profile(struct radeon_device *rdev)
92{
93 switch (rdev->pm.profile) {
94 case PM_PROFILE_DEFAULT:
95 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
96 break;
97 case PM_PROFILE_AUTO:
98 if (power_supply_is_system_supplied() > 0) {
99 if (rdev->pm.active_crtc_count > 1)
100 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
101 else
102 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
103 } else {
104 if (rdev->pm.active_crtc_count > 1)
c9e75b21 105 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 106 else
c9e75b21 107 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 108 }
109 break;
110 case PM_PROFILE_LOW:
111 if (rdev->pm.active_crtc_count > 1)
112 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
113 else
114 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
115 break;
c9e75b21
AD		 116 case PM_PROFILE_MID:
117 if (rdev->pm.active_crtc_count > 1)
118 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
119 else
120 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
121 break;
ce8f5370
AD		 122 case PM_PROFILE_HIGH:
123 if (rdev->pm.active_crtc_count > 1)
124 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
125 else
126 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
127 break;
128 }
129
130 if (rdev->pm.active_crtc_count == 0) {
131 rdev->pm.requested_power_state_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
133 rdev->pm.requested_clock_mode_index =
134 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
135 } else {
136 rdev->pm.requested_power_state_index =
137 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
138 rdev->pm.requested_clock_mode_index =
139 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
140 }
141}
c913e23a 142
5876dd24
MG		 143static void radeon_unmap_vram_bos(struct radeon_device *rdev)
144{
145 struct radeon_bo *bo, *n;
146
147 if (list_empty(&rdev->gem.objects))
148 return;
149
150 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
151 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
152 ttm_bo_unmap_virtual(&bo->tbo);
153 }
5876dd24
MG		 154}
155
ce8f5370 156static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 157{
ce8f5370
AD		 158 if (rdev->pm.active_crtcs) {
159 rdev->pm.vblank_sync = false;
160 wait_event_timeout(
161 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
162 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
163 }
164}
165
166static void radeon_set_power_state(struct radeon_device *rdev)
167{
168 u32 sclk, mclk;
92645879 169 bool misc_after = false;
ce8f5370
AD		 170
171 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
172 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
173 return;
174
175 if (radeon_gui_idle(rdev)) {
176 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
177 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 178 if (sclk > rdev->pm.default_sclk)
179 sclk = rdev->pm.default_sclk;
ce8f5370 180
27810fb2
AD		 181 /* starting with BTC, there is one state that is used for both
182 * MH and SH. Difference is that we always use the high clock index for
7ae764b1 183 * mclk and vddci.
27810fb2
AD		 184 */
185 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
186 (rdev->family >= CHIP_BARTS) &&
187 rdev->pm.active_crtc_count &&
188 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
189 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
190 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
191 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
192 else
193 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
194 clock_info[rdev->pm.requested_clock_mode_index].mclk;
195
9ace9f7b
AD		 196 if (mclk > rdev->pm.default_mclk)
197 mclk = rdev->pm.default_mclk;
ce8f5370 198
92645879
AD		 199 /* upvolt before raising clocks, downvolt after lowering clocks */
200 if (sclk < rdev->pm.current_sclk)
201 misc_after = true;
ce8f5370 202
92645879 203 radeon_sync_with_vblank(rdev);
ce8f5370 204
92645879 205 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 206 if (!radeon_pm_in_vbl(rdev))
207 return;
92645879 208 }
ce8f5370 209
92645879 210 radeon_pm_prepare(rdev);
ce8f5370 211
92645879
AD		 212 if (!misc_after)
213 /* voltage, pcie lanes, etc.*/
214 radeon_pm_misc(rdev);
215
216 /* set engine clock */
217 if (sclk != rdev->pm.current_sclk) {
218 radeon_pm_debug_check_in_vbl(rdev, false);
219 radeon_set_engine_clock(rdev, sclk);
220 radeon_pm_debug_check_in_vbl(rdev, true);
221 rdev->pm.current_sclk = sclk;
d9fdaafb 222 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 223 }
224
225 /* set memory clock */
798bcf73 226 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 227 radeon_pm_debug_check_in_vbl(rdev, false);
228 radeon_set_memory_clock(rdev, mclk);
229 radeon_pm_debug_check_in_vbl(rdev, true);
230 rdev->pm.current_mclk = mclk;
d9fdaafb 231 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 232 }
2aba631c 233
92645879
AD		 234 if (misc_after)
235 /* voltage, pcie lanes, etc.*/
236 radeon_pm_misc(rdev);
237
238 radeon_pm_finish(rdev);
239
ce8f5370
AD		 240 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
241 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
242 } else
d9fdaafb 243 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 244}
245
246static void radeon_pm_set_clocks(struct radeon_device *rdev)
247{
5f8f635e 248 int i, r;
c37d230a 249
4e186b2d
AD		 250 /* no need to take locks, etc. if nothing's going to change */
251 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
252 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
253 return;
254
612e06ce 255 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 256 down_write(&rdev->pm.mclk_lock);
d6999bc7 257 mutex_lock(&rdev->ring_lock);
4f3218cb 258
95f5a3ac
AD		 259 /* wait for the rings to drain */
260 for (i = 0; i < RADEON_NUM_RINGS; i++) {
261 struct radeon_ring *ring = &rdev->ring[i];
5f8f635e
JG		 262 if (!ring->ready) {
263 continue;
264 }
37615527 265 r = radeon_fence_wait_empty(rdev, i);
5f8f635e
JG		 266 if (r) {
267 /* needs a GPU reset dont reset here */
268 mutex_unlock(&rdev->ring_lock);
269 up_write(&rdev->pm.mclk_lock);
270 mutex_unlock(&rdev->ddev->struct_mutex);
271 return;
272 }
4f3218cb 273 }
95f5a3ac 274
5876dd24
MG		 275 radeon_unmap_vram_bos(rdev);
276
ce8f5370 277 if (rdev->irq.installed) {
2aba631c
MG		 278 for (i = 0; i < rdev->num_crtc; i++) {
279 if (rdev->pm.active_crtcs & (1 << i)) {
280 rdev->pm.req_vblank |= (1 << i);
281 drm_vblank_get(rdev->ddev, i);
282 }
283 }
284 }
539d2418 285
ce8f5370 286 radeon_set_power_state(rdev);
2aba631c 287
ce8f5370 288 if (rdev->irq.installed) {
2aba631c
MG		 289 for (i = 0; i < rdev->num_crtc; i++) {
290 if (rdev->pm.req_vblank & (1 << i)) {
291 rdev->pm.req_vblank &= ~(1 << i);
292 drm_vblank_put(rdev->ddev, i);
293 }
294 }
295 }
5876dd24 296
a424816f
AD		 297 /* update display watermarks based on new power state */
298 radeon_update_bandwidth_info(rdev);
299 if (rdev->pm.active_crtc_count)
300 radeon_bandwidth_update(rdev);
301
ce8f5370 302 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 303
d6999bc7 304 mutex_unlock(&rdev->ring_lock);
db7fce39 305 up_write(&rdev->pm.mclk_lock);
612e06ce 306 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 307}
308
f712d0c7
RM		 309static void radeon_pm_print_states(struct radeon_device *rdev)
310{
311 int i, j;
312 struct radeon_power_state *power_state;
313 struct radeon_pm_clock_info *clock_info;
314
d9fdaafb 315 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 316 for (i = 0; i < rdev->pm.num_power_states; i++) {
317 power_state = &rdev->pm.power_state[i];
d9fdaafb 318 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 319 radeon_pm_state_type_name[power_state->type]);
320 if (i == rdev->pm.default_power_state_index)
d9fdaafb 321 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 322 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 323 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 324 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 325 DRM_DEBUG_DRIVER("\tSingle display only\n");
326 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 327 for (j = 0; j < power_state->num_clock_modes; j++) {
328 clock_info = &(power_state->clock_info[j]);
329 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 330 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
331 j,
332 clock_info->sclk * 10);
f712d0c7 333 else
eb2c27a0
AD		 334 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
335 j,
336 clock_info->sclk * 10,
337 clock_info->mclk * 10,
338 clock_info->voltage.voltage);
f712d0c7
RM		 339 }
340 }
341}
342
ce8f5370
AD		 343static ssize_t radeon_get_pm_profile(struct device *dev,
344 struct device_attribute *attr,
345 char *buf)
a424816f 346{
3e4e2129 347 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 348 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 349 int cp = rdev->pm.profile;
a424816f 350
ce8f5370
AD		 351 return snprintf(buf, PAGE_SIZE, "%s\n",
352 (cp == PM_PROFILE_AUTO) ? "auto" :
353 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 354 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 355 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 356}
357
ce8f5370
AD		 358static ssize_t radeon_set_pm_profile(struct device *dev,
359 struct device_attribute *attr,
360 const char *buf,
361 size_t count)
a424816f 362{
3e4e2129 363 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 364 struct radeon_device *rdev = ddev->dev_private;
a424816f 365
4f2f2039
AD		 366 /* Can't set profile when the card is off */
367 if ((rdev->flags & RADEON_IS_PX) &&
368 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
369 return -EINVAL;
370
a424816f 371 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 372 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
373 if (strncmp("default", buf, strlen("default")) == 0)
374 rdev->pm.profile = PM_PROFILE_DEFAULT;
375 else if (strncmp("auto", buf, strlen("auto")) == 0)
376 rdev->pm.profile = PM_PROFILE_AUTO;
377 else if (strncmp("low", buf, strlen("low")) == 0)
378 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 379 else if (strncmp("mid", buf, strlen("mid")) == 0)
380 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 381 else if (strncmp("high", buf, strlen("high")) == 0)
382 rdev->pm.profile = PM_PROFILE_HIGH;
383 else {
1783e4bf 384 count = -EINVAL;
ce8f5370 385 goto fail;
a424816f 386 }
ce8f5370
AD		 387 radeon_pm_update_profile(rdev);
388 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 389 } else
390 count = -EINVAL;
391
ce8f5370 392fail:
a424816f
AD		 393 mutex_unlock(&rdev->pm.mutex);
394
395 return count;
396}
397
ce8f5370
AD		 398static ssize_t radeon_get_pm_method(struct device *dev,
399 struct device_attribute *attr,
400 char *buf)
a424816f 401{
3e4e2129 402 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 403 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 404 int pm = rdev->pm.pm_method;
a424816f
AD		 405
406 return snprintf(buf, PAGE_SIZE, "%s\n",
da321c8a
AD		 407 (pm == PM_METHOD_DYNPM) ? "dynpm" :
408 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
a424816f
AD		 409}
410
ce8f5370
AD		 411static ssize_t radeon_set_pm_method(struct device *dev,
412 struct device_attribute *attr,
413 const char *buf,
414 size_t count)
a424816f 415{
3e4e2129 416 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 417 struct radeon_device *rdev = ddev->dev_private;
a424816f 418
4f2f2039
AD		 419 /* Can't set method when the card is off */
420 if ((rdev->flags & RADEON_IS_PX) &&
421 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
422 count = -EINVAL;
423 goto fail;
424 }
425
da321c8a
AD		 426 /* we don't support the legacy modes with dpm */
427 if (rdev->pm.pm_method == PM_METHOD_DPM) {
428 count = -EINVAL;
429 goto fail;
430 }
ce8f5370
AD		 431
432 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 433 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 434 rdev->pm.pm_method = PM_METHOD_DYNPM;
435 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
436 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 437 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 438 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
439 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 440 /* disable dynpm */
441 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
442 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 443 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 444 mutex_unlock(&rdev->pm.mutex);
32c87fca 445 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 446 } else {
1783e4bf 447 count = -EINVAL;
ce8f5370
AD		 448 goto fail;
449 }
450 radeon_pm_compute_clocks(rdev);
451fail:
a424816f
AD		 452 return count;
453}
454
da321c8a
AD		 455static ssize_t radeon_get_dpm_state(struct device *dev,
456 struct device_attribute *attr,
457 char *buf)
458{
3e4e2129 459 struct drm_device *ddev = dev_get_drvdata(dev);
da321c8a
AD		 460 struct radeon_device *rdev = ddev->dev_private;
461 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
462
4f2f2039
AD		 463 if ((rdev->flags & RADEON_IS_PX) &&
464 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
465 return snprintf(buf, PAGE_SIZE, "off\n");
466
da321c8a
AD		 467 return snprintf(buf, PAGE_SIZE, "%s\n",
468 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
469 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
470}
471
472static ssize_t radeon_set_dpm_state(struct device *dev,
473 struct device_attribute *attr,
474 const char *buf,
475 size_t count)
476{
3e4e2129 477 struct drm_device *ddev = dev_get_drvdata(dev);
da321c8a
AD		 478 struct radeon_device *rdev = ddev->dev_private;
479
4f2f2039
AD		 480 /* Can't set dpm state when the card is off */
481 if ((rdev->flags & RADEON_IS_PX) &&
482 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
483 return -EINVAL;
484
da321c8a
AD		 485 mutex_lock(&rdev->pm.mutex);
486 if (strncmp("battery", buf, strlen("battery")) == 0)
487 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
488 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
489 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
490 else if (strncmp("performance", buf, strlen("performance")) == 0)
491 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
492 else {
493 mutex_unlock(&rdev->pm.mutex);
494 count = -EINVAL;
495 goto fail;
496 }
497 mutex_unlock(&rdev->pm.mutex);
498 radeon_pm_compute_clocks(rdev);
499fail:
500 return count;
501}
502
70d01a5e
AD		 503static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
504 struct device_attribute *attr,
505 char *buf)
506{
3e4e2129 507 struct drm_device *ddev = dev_get_drvdata(dev);
70d01a5e
AD		 508 struct radeon_device *rdev = ddev->dev_private;
509 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
510
4f2f2039
AD		 511 if ((rdev->flags & RADEON_IS_PX) &&
512 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
513 return snprintf(buf, PAGE_SIZE, "off\n");
514
70d01a5e
AD		 515 return snprintf(buf, PAGE_SIZE, "%s\n",
516 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
517 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
518}
519
520static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
521 struct device_attribute *attr,
522 const char *buf,
523 size_t count)
524{
3e4e2129 525 struct drm_device *ddev = dev_get_drvdata(dev);
70d01a5e
AD		 526 struct radeon_device *rdev = ddev->dev_private;
527 enum radeon_dpm_forced_level level;
528 int ret = 0;
529
4f2f2039
AD		 530 /* Can't force performance level when the card is off */
531 if ((rdev->flags & RADEON_IS_PX) &&
532 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
533 return -EINVAL;
534
70d01a5e
AD		 535 mutex_lock(&rdev->pm.mutex);
536 if (strncmp("low", buf, strlen("low")) == 0) {
537 level = RADEON_DPM_FORCED_LEVEL_LOW;
538 } else if (strncmp("high", buf, strlen("high")) == 0) {
539 level = RADEON_DPM_FORCED_LEVEL_HIGH;
540 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
541 level = RADEON_DPM_FORCED_LEVEL_AUTO;
542 } else {
70d01a5e
AD		 543 count = -EINVAL;
544 goto fail;
545 }
546 if (rdev->asic->dpm.force_performance_level) {
0a17af37
AD		 547 if (rdev->pm.dpm.thermal_active) {
548 count = -EINVAL;
549 goto fail;
550 }
70d01a5e
AD		 551 ret = radeon_dpm_force_performance_level(rdev, level);
552 if (ret)
553 count = -EINVAL;
554 }
70d01a5e 555fail:
0a17af37
AD		 556 mutex_unlock(&rdev->pm.mutex);
557
70d01a5e
AD		 558 return count;
559}
560
ce8f5370
AD		 561static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
562static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
da321c8a 563static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
70d01a5e
AD		 564static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
565 radeon_get_dpm_forced_performance_level,
566 radeon_set_dpm_forced_performance_level);
a424816f 567
21a8122a
AD		 568static ssize_t radeon_hwmon_show_temp(struct device *dev,
569 struct device_attribute *attr,
570 char *buf)
571{
ec39f64b 572 struct radeon_device *rdev = dev_get_drvdata(dev);
4f2f2039 573 struct drm_device *ddev = rdev->ddev;
20d391d7 574 int temp;
21a8122a 575
4f2f2039
AD		 576 /* Can't get temperature when the card is off */
577 if ((rdev->flags & RADEON_IS_PX) &&
578 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
579 return -EINVAL;
580
6bd1c385
AD		 581 if (rdev->asic->pm.get_temperature)
582 temp = radeon_get_temperature(rdev);
583 else
21a8122a 584 temp = 0;
21a8122a
AD		 585
586 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
587}
588
6ea4e84d
JD		 589static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
590 struct device_attribute *attr,
591 char *buf)
592{
e4158f1b 593 struct radeon_device *rdev = dev_get_drvdata(dev);
6ea4e84d
JD		 594 int hyst = to_sensor_dev_attr(attr)->index;
595 int temp;
596
597 if (hyst)
598 temp = rdev->pm.dpm.thermal.min_temp;
599 else
600 temp = rdev->pm.dpm.thermal.max_temp;
601
602 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
603}
604
21a8122a 605static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
6ea4e84d
JD		 606static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
607static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
21a8122a
AD		 608
609static struct attribute *hwmon_attributes[] = {
610 &sensor_dev_attr_temp1_input.dev_attr.attr,
6ea4e84d
JD		 611 &sensor_dev_attr_temp1_crit.dev_attr.attr,
612 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
21a8122a
AD		 613 NULL
614};
615
6ea4e84d
JD		 616static umode_t hwmon_attributes_visible(struct kobject *kobj,
617 struct attribute *attr, int index)
618{
619 struct device *dev = container_of(kobj, struct device, kobj);
e4158f1b 620 struct radeon_device *rdev = dev_get_drvdata(dev);
6ea4e84d
JD		 621
622 /* Skip limit attributes if DPM is not enabled */
623 if (rdev->pm.pm_method != PM_METHOD_DPM &&
624 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
625 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
626 return 0;
627
628 return attr->mode;
629}
630
21a8122a
AD		 631static const struct attribute_group hwmon_attrgroup = {
632 .attrs = hwmon_attributes,
6ea4e84d 633 .is_visible = hwmon_attributes_visible,
21a8122a
AD		 634};
635
ec39f64b
GR		 636static const struct attribute_group *hwmon_groups[] = {
637 &hwmon_attrgroup,
638 NULL
639};
640
0d18abed 641static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 642{
0d18abed 643 int err = 0;
21a8122a
AD		 644
645 switch (rdev->pm.int_thermal_type) {
646 case THERMAL_TYPE_RV6XX:
647 case THERMAL_TYPE_RV770:
648 case THERMAL_TYPE_EVERGREEN:
457558ed 649 case THERMAL_TYPE_NI:
e33df25f 650 case THERMAL_TYPE_SUMO:
1bd47d2e 651 case THERMAL_TYPE_SI:
286d9cc6
AD		 652 case THERMAL_TYPE_CI:
653 case THERMAL_TYPE_KV:
6bd1c385 654 if (rdev->asic->pm.get_temperature == NULL)
5d7486c7 655 return err;
cb3e4e7c
AD		 656 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
657 "radeon", rdev,
658 hwmon_groups);
659 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
660 err = PTR_ERR(rdev->pm.int_hwmon_dev);
0d18abed
DC		 661 dev_err(rdev->dev,
662 "Unable to register hwmon device: %d\n", err);
0d18abed 663 }
21a8122a
AD		 664 break;
665 default:
666 break;
667 }
0d18abed
DC		 668
669 return err;
21a8122a
AD		 670}
671
cb3e4e7c
AD		 672static void radeon_hwmon_fini(struct radeon_device *rdev)
673{
674 if (rdev->pm.int_hwmon_dev)
675 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
676}
677
da321c8a
AD		 678static void radeon_dpm_thermal_work_handler(struct work_struct *work)
679{
680 struct radeon_device *rdev =
681 container_of(work, struct radeon_device,
682 pm.dpm.thermal.work);
683 /* switch to the thermal state */
684 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
685
686 if (!rdev->pm.dpm_enabled)
687 return;
688
689 if (rdev->asic->pm.get_temperature) {
690 int temp = radeon_get_temperature(rdev);
691
692 if (temp < rdev->pm.dpm.thermal.min_temp)
693 /* switch back the user state */
694 dpm_state = rdev->pm.dpm.user_state;
695 } else {
696 if (rdev->pm.dpm.thermal.high_to_low)
697 /* switch back the user state */
698 dpm_state = rdev->pm.dpm.user_state;
699 }
60320347
AD		 700 mutex_lock(&rdev->pm.mutex);
701 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
702 rdev->pm.dpm.thermal_active = true;
703 else
704 rdev->pm.dpm.thermal_active = false;
705 rdev->pm.dpm.state = dpm_state;
706 mutex_unlock(&rdev->pm.mutex);
707
708 radeon_pm_compute_clocks(rdev);
da321c8a
AD		 709}
710
711static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
712 enum radeon_pm_state_type dpm_state)
713{
714 int i;
715 struct radeon_ps *ps;
716 u32 ui_class;
48783069
AD		 717 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
718 true : false;
719
720 /* check if the vblank period is too short to adjust the mclk */
721 if (single_display && rdev->asic->dpm.vblank_too_short) {
722 if (radeon_dpm_vblank_too_short(rdev))
723 single_display = false;
724 }
da321c8a 725
edcaa5b1
AD		 726 /* certain older asics have a separare 3D performance state,
727 * so try that first if the user selected performance
728 */
729 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
730 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
da321c8a
AD		 731 /* balanced states don't exist at the moment */
732 if (dpm_state == POWER_STATE_TYPE_BALANCED)
733 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
734
edcaa5b1 735restart_search:
da321c8a
AD		 736 /* Pick the best power state based on current conditions */
737 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
738 ps = &rdev->pm.dpm.ps[i];
739 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
740 switch (dpm_state) {
741 /* user states */
742 case POWER_STATE_TYPE_BATTERY:
743 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
744 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 745 if (single_display)
da321c8a
AD		 746 return ps;
747 } else
748 return ps;
749 }
750 break;
751 case POWER_STATE_TYPE_BALANCED:
752 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
753 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 754 if (single_display)
da321c8a
AD		 755 return ps;
756 } else
757 return ps;
758 }
759 break;
760 case POWER_STATE_TYPE_PERFORMANCE:
761 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
762 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 763 if (single_display)
da321c8a
AD		 764 return ps;
765 } else
766 return ps;
767 }
768 break;
769 /* internal states */
770 case POWER_STATE_TYPE_INTERNAL_UVD:
d4d3278c
AD		 771 if (rdev->pm.dpm.uvd_ps)
772 return rdev->pm.dpm.uvd_ps;
773 else
774 break;
da321c8a
AD		 775 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
776 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
777 return ps;
778 break;
779 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
780 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
781 return ps;
782 break;
783 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
784 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
785 return ps;
786 break;
787 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
788 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
789 return ps;
790 break;
791 case POWER_STATE_TYPE_INTERNAL_BOOT:
792 return rdev->pm.dpm.boot_ps;
793 case POWER_STATE_TYPE_INTERNAL_THERMAL:
794 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
795 return ps;
796 break;
797 case POWER_STATE_TYPE_INTERNAL_ACPI:
798 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
799 return ps;
800 break;
801 case POWER_STATE_TYPE_INTERNAL_ULV:
802 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
803 return ps;
804 break;
edcaa5b1
AD		 805 case POWER_STATE_TYPE_INTERNAL_3DPERF:
806 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
807 return ps;
808 break;
da321c8a
AD		 809 default:
810 break;
811 }
812 }
813 /* use a fallback state if we didn't match */
814 switch (dpm_state) {
815 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
ce3537d5
AD		 816 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
817 goto restart_search;
da321c8a
AD		 818 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
819 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
820 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
d4d3278c
AD		 821 if (rdev->pm.dpm.uvd_ps) {
822 return rdev->pm.dpm.uvd_ps;
823 } else {
824 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
825 goto restart_search;
826 }
da321c8a
AD		 827 case POWER_STATE_TYPE_INTERNAL_THERMAL:
828 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
829 goto restart_search;
830 case POWER_STATE_TYPE_INTERNAL_ACPI:
831 dpm_state = POWER_STATE_TYPE_BATTERY;
832 goto restart_search;
833 case POWER_STATE_TYPE_BATTERY:
edcaa5b1
AD		 834 case POWER_STATE_TYPE_BALANCED:
835 case POWER_STATE_TYPE_INTERNAL_3DPERF:
da321c8a
AD		 836 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
837 goto restart_search;
838 default:
839 break;
840 }
841
842 return NULL;
843}
844
845static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
846{
847 int i;
848 struct radeon_ps *ps;
849 enum radeon_pm_state_type dpm_state;
84dd1928 850 int ret;
da321c8a
AD		 851
852 /* if dpm init failed */
853 if (!rdev->pm.dpm_enabled)
854 return;
855
856 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
857 /* add other state override checks here */
8a227555
AD		 858 if ((!rdev->pm.dpm.thermal_active) &&
859 (!rdev->pm.dpm.uvd_active))
da321c8a
AD		 860 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
861 }
862 dpm_state = rdev->pm.dpm.state;
863
864 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
865 if (ps)
89c9bc56 866 rdev->pm.dpm.requested_ps = ps;
da321c8a
AD		 867 else
868 return;
869
d22b7e40 870 /* no need to reprogram if nothing changed unless we are on BTC+ */
da321c8a 871 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
b62d628b
AD		 872 /* vce just modifies an existing state so force a change */
873 if (ps->vce_active != rdev->pm.dpm.vce_active)
874 goto force;
d22b7e40
AD		 875 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
876 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
877 * all we need to do is update the display configuration.
878 */
879 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
880 /* update display watermarks based on new power state */
881 radeon_bandwidth_update(rdev);
882 /* update displays */
883 radeon_dpm_display_configuration_changed(rdev);
884 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
885 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
886 }
887 return;
888 } else {
889 /* for BTC+ if the num crtcs hasn't changed and state is the same,
890 * nothing to do, if the num crtcs is > 1 and state is the same,
891 * update display configuration.
892 */
893 if (rdev->pm.dpm.new_active_crtcs ==
894 rdev->pm.dpm.current_active_crtcs) {
895 return;
896 } else {
897 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
898 (rdev->pm.dpm.new_active_crtc_count > 1)) {
899 /* update display watermarks based on new power state */
900 radeon_bandwidth_update(rdev);
901 /* update displays */
902 radeon_dpm_display_configuration_changed(rdev);
903 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
904 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
905 return;
906 }
907 }
da321c8a 908 }
da321c8a
AD		 909 }
910
b62d628b 911force:
033a37df
AD		 912 if (radeon_dpm == 1) {
913 printk("switching from power state:\n");
914 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
915 printk("switching to power state:\n");
916 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
917 }
b62d628b 918
da321c8a
AD		 919 mutex_lock(&rdev->ddev->struct_mutex);
920 down_write(&rdev->pm.mclk_lock);
921 mutex_lock(&rdev->ring_lock);
922
b62d628b
AD		 923 /* update whether vce is active */
924 ps->vce_active = rdev->pm.dpm.vce_active;
925
89c9bc56
AD		 926 ret = radeon_dpm_pre_set_power_state(rdev);
927 if (ret)
928 goto done;
84dd1928 929
da321c8a
AD		 930 /* update display watermarks based on new power state */
931 radeon_bandwidth_update(rdev);
932 /* update displays */
933 radeon_dpm_display_configuration_changed(rdev);
934
935 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
936 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
937
938 /* wait for the rings to drain */
939 for (i = 0; i < RADEON_NUM_RINGS; i++) {
940 struct radeon_ring *ring = &rdev->ring[i];
941 if (ring->ready)
37615527 942 radeon_fence_wait_empty(rdev, i);
da321c8a
AD		 943 }
944
945 /* program the new power state */
946 radeon_dpm_set_power_state(rdev);
947
948 /* update current power state */
949 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
950
89c9bc56 951 radeon_dpm_post_set_power_state(rdev);
84dd1928 952
1cd8b21a 953 if (rdev->asic->dpm.force_performance_level) {
14ac88af
AD		 954 if (rdev->pm.dpm.thermal_active) {
955 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1cd8b21a
AD		 956 /* force low perf level for thermal */
957 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
14ac88af
AD		 958 /* save the user's level */
959 rdev->pm.dpm.forced_level = level;
960 } else {
961 /* otherwise, user selected level */
962 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
963 }
60320347
AD		 964 }
965
84dd1928 966done:
da321c8a
AD		 967 mutex_unlock(&rdev->ring_lock);
968 up_write(&rdev->pm.mclk_lock);
969 mutex_unlock(&rdev->ddev->struct_mutex);
970}
971
ce3537d5
AD		 972void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
973{
974 enum radeon_pm_state_type dpm_state;
975
9e9d9762 976 if (rdev->asic->dpm.powergate_uvd) {
ce3537d5 977 mutex_lock(&rdev->pm.mutex);
8158eb9e
CK		 978 /* don't powergate anything if we
979 have active but pause streams */
980 enable |= rdev->pm.dpm.sd > 0;
981 enable |= rdev->pm.dpm.hd > 0;
9e9d9762
AD		 982 /* enable/disable UVD */
983 radeon_dpm_powergate_uvd(rdev, !enable);
ce3537d5
AD		 984 mutex_unlock(&rdev->pm.mutex);
985 } else {
9e9d9762
AD		 986 if (enable) {
987 mutex_lock(&rdev->pm.mutex);
988 rdev->pm.dpm.uvd_active = true;
0690a229
AD		 989 /* disable this for now */
990#if 0
9e9d9762
AD		 991 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
992 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
993 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
994 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
995 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
996 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
997 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
998 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
999 else
0690a229 1000#endif
9e9d9762
AD		 1001 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1002 rdev->pm.dpm.state = dpm_state;
1003 mutex_unlock(&rdev->pm.mutex);
1004 } else {
1005 mutex_lock(&rdev->pm.mutex);
1006 rdev->pm.dpm.uvd_active = false;
1007 mutex_unlock(&rdev->pm.mutex);
1008 }
ce3537d5 1009
9e9d9762
AD		 1010 radeon_pm_compute_clocks(rdev);
1011 }
ce3537d5
AD		 1012}
1013
03afe6f6
AD		 1014void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1015{
1016 if (enable) {
1017 mutex_lock(&rdev->pm.mutex);
1018 rdev->pm.dpm.vce_active = true;
1019 /* XXX select vce level based on ring/task */
1020 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1021 mutex_unlock(&rdev->pm.mutex);
1022 } else {
1023 mutex_lock(&rdev->pm.mutex);
1024 rdev->pm.dpm.vce_active = false;
1025 mutex_unlock(&rdev->pm.mutex);
1026 }
1027
1028 radeon_pm_compute_clocks(rdev);
1029}
1030
da321c8a 1031static void radeon_pm_suspend_old(struct radeon_device *rdev)
56278a8e 1032{
ce8f5370 1033 mutex_lock(&rdev->pm.mutex);
3f53eb6f 1034 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 1035 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1036 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 1037 }
ce8f5370 1038 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1039
1040 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 1041}
1042
da321c8a
AD		 1043static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1044{
1045 mutex_lock(&rdev->pm.mutex);
1046 /* disable dpm */
1047 radeon_dpm_disable(rdev);
1048 /* reset the power state */
1049 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1050 rdev->pm.dpm_enabled = false;
1051 mutex_unlock(&rdev->pm.mutex);
1052}
1053
1054void radeon_pm_suspend(struct radeon_device *rdev)
1055{
1056 if (rdev->pm.pm_method == PM_METHOD_DPM)
1057 radeon_pm_suspend_dpm(rdev);
1058 else
1059 radeon_pm_suspend_old(rdev);
1060}
1061
1062static void radeon_pm_resume_old(struct radeon_device *rdev)
d0d6cb81 1063{
ed18a360 1064 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1065 if ((rdev->family >= CHIP_BARTS) &&
36099186 1066 (rdev->family <= CHIP_CAYMAN) &&
2e3b3b10 1067 rdev->mc_fw) {
ed18a360 1068 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1069 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1070 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 1071 if (rdev->pm.default_vddci)
1072 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1073 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1074 if (rdev->pm.default_sclk)
1075 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1076 if (rdev->pm.default_mclk)
1077 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1078 }
f8ed8b4c
AD		 1079 /* asic init will reset the default power state */
1080 mutex_lock(&rdev->pm.mutex);
1081 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1082 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 1083 rdev->pm.current_sclk = rdev->pm.default_sclk;
1084 rdev->pm.current_mclk = rdev->pm.default_mclk;
37016951
MD		 1085 if (rdev->pm.power_state) {
1086 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1087 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1088 }
3f53eb6f
RW		 1089 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1090 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1091 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1092 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1093 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 1094 }
f8ed8b4c 1095 mutex_unlock(&rdev->pm.mutex);
ce8f5370 1096 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 1097}
1098
da321c8a
AD		 1099static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1100{
1101 int ret;
1102
1103 /* asic init will reset to the boot state */
1104 mutex_lock(&rdev->pm.mutex);
1105 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1106 radeon_dpm_setup_asic(rdev);
1107 ret = radeon_dpm_enable(rdev);
1108 mutex_unlock(&rdev->pm.mutex);
e14cd2bb
AD		 1109 if (ret)
1110 goto dpm_resume_fail;
e14cd2bb 1111 rdev->pm.dpm_enabled = true;
e14cd2bb
AD		 1112 return;
1113
1114dpm_resume_fail:
1115 DRM_ERROR("radeon: dpm resume failed\n");
1116 if ((rdev->family >= CHIP_BARTS) &&
1117 (rdev->family <= CHIP_CAYMAN) &&
1118 rdev->mc_fw) {
1119 if (rdev->pm.default_vddc)
1120 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1121 SET_VOLTAGE_TYPE_ASIC_VDDC);
1122 if (rdev->pm.default_vddci)
1123 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1124 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1125 if (rdev->pm.default_sclk)
1126 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1127 if (rdev->pm.default_mclk)
1128 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
da321c8a
AD		 1129 }
1130}
1131
1132void radeon_pm_resume(struct radeon_device *rdev)
1133{
1134 if (rdev->pm.pm_method == PM_METHOD_DPM)
1135 radeon_pm_resume_dpm(rdev);
1136 else
1137 radeon_pm_resume_old(rdev);
1138}
1139
1140static int radeon_pm_init_old(struct radeon_device *rdev)
7433874e 1141{
26481fb1 1142 int ret;
0d18abed 1143
f8ed8b4c 1144 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 1145 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1146 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1147 rdev->pm.dynpm_can_upclock = true;
1148 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 1149 rdev->pm.default_sclk = rdev->clock.default_sclk;
1150 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 1151 rdev->pm.current_sclk = rdev->clock.default_sclk;
1152 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 1153 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 1154
56278a8e
AD		 1155 if (rdev->bios) {
1156 if (rdev->is_atom_bios)
1157 radeon_atombios_get_power_modes(rdev);
1158 else
1159 radeon_combios_get_power_modes(rdev);
f712d0c7 1160 radeon_pm_print_states(rdev);
ce8f5370 1161 radeon_pm_init_profile(rdev);
ed18a360 1162 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1163 if ((rdev->family >= CHIP_BARTS) &&
36099186 1164 (rdev->family <= CHIP_CAYMAN) &&
2e3b3b10 1165 rdev->mc_fw) {
ed18a360 1166 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1167 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1168 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 1169 if (rdev->pm.default_vddci)
1170 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1171 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1172 if (rdev->pm.default_sclk)
1173 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1174 if (rdev->pm.default_mclk)
1175 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1176 }
56278a8e
AD		 1177 }
1178
21a8122a 1179 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 1180 ret = radeon_hwmon_init(rdev);
1181 if (ret)
1182 return ret;
32c87fca
TH		 1183
1184 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1185
ce8f5370 1186 if (rdev->pm.num_power_states > 1) {
ce8f5370 1187 /* where's the best place to put these? */
26481fb1
DA		 1188 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1189 if (ret)
1190 DRM_ERROR("failed to create device file for power profile\n");
1191 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1192 if (ret)
1193 DRM_ERROR("failed to create device file for power method\n");
a424816f 1194
ce8f5370
AD		 1195 if (radeon_debugfs_pm_init(rdev)) {
1196 DRM_ERROR("Failed to register debugfs file for PM!\n");
1197 }
c913e23a 1198
ce8f5370
AD		 1199 DRM_INFO("radeon: power management initialized\n");
1200 }
c913e23a 1201
7433874e
RM		 1202 return 0;
1203}
1204
da321c8a
AD		 1205static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1206{
1207 int i;
1208
1209 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1210 printk("== power state %d ==\n", i);
1211 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1212 }
1213}
1214
1215static int radeon_pm_init_dpm(struct radeon_device *rdev)
1216{
1217 int ret;
1218
1cd8b21a 1219 /* default to balanced state */
edcaa5b1
AD		 1220 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1221 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1cd8b21a 1222 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
da321c8a
AD		 1223 rdev->pm.default_sclk = rdev->clock.default_sclk;
1224 rdev->pm.default_mclk = rdev->clock.default_mclk;
1225 rdev->pm.current_sclk = rdev->clock.default_sclk;
1226 rdev->pm.current_mclk = rdev->clock.default_mclk;
1227 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1228
1229 if (rdev->bios && rdev->is_atom_bios)
1230 radeon_atombios_get_power_modes(rdev);
1231 else
1232 return -EINVAL;
1233
1234 /* set up the internal thermal sensor if applicable */
1235 ret = radeon_hwmon_init(rdev);
1236 if (ret)
1237 return ret;
1238
1239 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1240 mutex_lock(&rdev->pm.mutex);
1241 radeon_dpm_init(rdev);
1242 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
033a37df
AD		 1243 if (radeon_dpm == 1)
1244 radeon_dpm_print_power_states(rdev);
da321c8a
AD		 1245 radeon_dpm_setup_asic(rdev);
1246 ret = radeon_dpm_enable(rdev);
1247 mutex_unlock(&rdev->pm.mutex);
e14cd2bb
AD		 1248 if (ret)
1249 goto dpm_failed;
da321c8a 1250 rdev->pm.dpm_enabled = true;
da321c8a 1251
bb5abf9f
AD		 1252 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1253 if (ret)
1254 DRM_ERROR("failed to create device file for dpm state\n");
1255 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1256 if (ret)
1257 DRM_ERROR("failed to create device file for dpm state\n");
1258 /* XXX: these are noops for dpm but are here for backwards compat */
1259 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1260 if (ret)
1261 DRM_ERROR("failed to create device file for power profile\n");
1262 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1263 if (ret)
1264 DRM_ERROR("failed to create device file for power method\n");
1316b792 1265
bb5abf9f
AD		 1266 if (radeon_debugfs_pm_init(rdev)) {
1267 DRM_ERROR("Failed to register debugfs file for dpm!\n");
da321c8a
AD		 1268 }
1269
bb5abf9f
AD		 1270 DRM_INFO("radeon: dpm initialized\n");
1271
da321c8a 1272 return 0;
e14cd2bb
AD		 1273
1274dpm_failed:
1275 rdev->pm.dpm_enabled = false;
1276 if ((rdev->family >= CHIP_BARTS) &&
1277 (rdev->family <= CHIP_CAYMAN) &&
1278 rdev->mc_fw) {
1279 if (rdev->pm.default_vddc)
1280 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1281 SET_VOLTAGE_TYPE_ASIC_VDDC);
1282 if (rdev->pm.default_vddci)
1283 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1284 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1285 if (rdev->pm.default_sclk)
1286 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1287 if (rdev->pm.default_mclk)
1288 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1289 }
1290 DRM_ERROR("radeon: dpm initialization failed\n");
1291 return ret;
da321c8a
AD		 1292}
1293
1294int radeon_pm_init(struct radeon_device *rdev)
1295{
1296 /* enable dpm on rv6xx+ */
1297 switch (rdev->family) {
4a6369e9
AD		 1298 case CHIP_RV610:
1299 case CHIP_RV630:
1300 case CHIP_RV620:
1301 case CHIP_RV635:
1302 case CHIP_RV670:
9d67006e
AD		 1303 case CHIP_RS780:
1304 case CHIP_RS880:
76e6dcec 1305 case CHIP_RV770:
919cf555
AD		 1306 case CHIP_BARTS:
1307 case CHIP_TURKS:
1308 case CHIP_CAICOS:
69e0b57a 1309 case CHIP_CAYMAN:
8a53fa23 1310 /* DPM requires the RLC, RV770+ dGPU requires SMC */
761bfb99
AD		 1311 if (!rdev->rlc_fw)
1312 rdev->pm.pm_method = PM_METHOD_PROFILE;
8a53fa23
AD		 1313 else if ((rdev->family >= CHIP_RV770) &&
1314 (!(rdev->flags & RADEON_IS_IGP)) &&
1315 (!rdev->smc_fw))
1316 rdev->pm.pm_method = PM_METHOD_PROFILE;
761bfb99 1317 else if (radeon_dpm == 1)
9d67006e
AD		 1318 rdev->pm.pm_method = PM_METHOD_DPM;
1319 else
1320 rdev->pm.pm_method = PM_METHOD_PROFILE;
1321 break;
ab70b1dd
AD		 1322 case CHIP_RV730:
1323 case CHIP_RV710:
1324 case CHIP_RV740:
59f7a2f2
AD		 1325 case CHIP_CEDAR:
1326 case CHIP_REDWOOD:
1327 case CHIP_JUNIPER:
1328 case CHIP_CYPRESS:
1329 case CHIP_HEMLOCK:
5a16f761
AD		 1330 case CHIP_PALM:
1331 case CHIP_SUMO:
1332 case CHIP_SUMO2:
3a118989 1333 case CHIP_ARUBA:
68bc7785
AD		 1334 case CHIP_TAHITI:
1335 case CHIP_PITCAIRN:
1336 case CHIP_VERDE:
1337 case CHIP_OLAND:
1338 case CHIP_HAINAN:
4f22dde3 1339 case CHIP_BONAIRE:
e308b1d3
AD		 1340 case CHIP_KABINI:
1341 case CHIP_KAVERI:
4f22dde3 1342 case CHIP_HAWAII:
7d032a4b 1343 case CHIP_MULLINS:
5a16f761
AD		 1344 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1345 if (!rdev->rlc_fw)
1346 rdev->pm.pm_method = PM_METHOD_PROFILE;
1347 else if ((rdev->family >= CHIP_RV770) &&
1348 (!(rdev->flags & RADEON_IS_IGP)) &&
1349 (!rdev->smc_fw))
1350 rdev->pm.pm_method = PM_METHOD_PROFILE;
1351 else if (radeon_dpm == 0)
1352 rdev->pm.pm_method = PM_METHOD_PROFILE;
1353 else
1354 rdev->pm.pm_method = PM_METHOD_DPM;
1355 break;
da321c8a
AD		 1356 default:
1357 /* default to profile method */
1358 rdev->pm.pm_method = PM_METHOD_PROFILE;
1359 break;
1360 }
1361
1362 if (rdev->pm.pm_method == PM_METHOD_DPM)
1363 return radeon_pm_init_dpm(rdev);
1364 else
1365 return radeon_pm_init_old(rdev);
1366}
1367
914a8987
AD		 1368int radeon_pm_late_init(struct radeon_device *rdev)
1369{
1370 int ret = 0;
1371
1372 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1373 mutex_lock(&rdev->pm.mutex);
1374 ret = radeon_dpm_late_enable(rdev);
1375 mutex_unlock(&rdev->pm.mutex);
1376 }
1377 return ret;
1378}
1379
da321c8a 1380static void radeon_pm_fini_old(struct radeon_device *rdev)
29fb52ca 1381{
ce8f5370 1382 if (rdev->pm.num_power_states > 1) {
a424816f 1383 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 1384 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1385 rdev->pm.profile = PM_PROFILE_DEFAULT;
1386 radeon_pm_update_profile(rdev);
1387 radeon_pm_set_clocks(rdev);
1388 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 1389 /* reset default clocks */
1390 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1391 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1392 radeon_pm_set_clocks(rdev);
1393 }
a424816f 1394 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1395
1396 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 1397
ce8f5370
AD		 1398 device_remove_file(rdev->dev, &dev_attr_power_profile);
1399 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 1400 }
a424816f 1401
cb3e4e7c
AD		 1402 radeon_hwmon_fini(rdev);
1403
0975b162
AD		 1404 if (rdev->pm.power_state)
1405 kfree(rdev->pm.power_state);
29fb52ca
AD		 1406}
1407
da321c8a
AD		 1408static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1409{
1410 if (rdev->pm.num_power_states > 1) {
1411 mutex_lock(&rdev->pm.mutex);
1412 radeon_dpm_disable(rdev);
1413 mutex_unlock(&rdev->pm.mutex);
1414
1415 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
70d01a5e 1416 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
da321c8a
AD		 1417 /* XXX backwards compat */
1418 device_remove_file(rdev->dev, &dev_attr_power_profile);
1419 device_remove_file(rdev->dev, &dev_attr_power_method);
1420 }
1421 radeon_dpm_fini(rdev);
1422
cb3e4e7c
AD		 1423 radeon_hwmon_fini(rdev);
1424
da321c8a
AD		 1425 if (rdev->pm.power_state)
1426 kfree(rdev->pm.power_state);
da321c8a
AD		 1427}
1428
1429void radeon_pm_fini(struct radeon_device *rdev)
1430{
1431 if (rdev->pm.pm_method == PM_METHOD_DPM)
1432 radeon_pm_fini_dpm(rdev);
1433 else
1434 radeon_pm_fini_old(rdev);
1435}
1436
1437static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
c913e23a
RM		 1438{
1439 struct drm_device *ddev = rdev->ddev;
a48b9b4e 1440 struct drm_crtc *crtc;
c913e23a 1441 struct radeon_crtc *radeon_crtc;
c913e23a 1442
ce8f5370
AD		 1443 if (rdev->pm.num_power_states < 2)
1444 return;
1445
c913e23a
RM		 1446 mutex_lock(&rdev->pm.mutex);
1447
1448 rdev->pm.active_crtcs = 0;
a48b9b4e 1449 rdev->pm.active_crtc_count = 0;
3ed9a335
AD		 1450 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1451 list_for_each_entry(crtc,
1452 &ddev->mode_config.crtc_list, head) {
1453 radeon_crtc = to_radeon_crtc(crtc);
1454 if (radeon_crtc->enabled) {
1455 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1456 rdev->pm.active_crtc_count++;
1457 }
c913e23a
RM		 1458 }
1459 }
1460
ce8f5370
AD		 1461 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1462 radeon_pm_update_profile(rdev);
1463 radeon_pm_set_clocks(rdev);
1464 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1465 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1466 if (rdev->pm.active_crtc_count > 1) {
1467 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1468 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1469
1470 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1471 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1472 radeon_pm_get_dynpm_state(rdev);
1473 radeon_pm_set_clocks(rdev);
1474
d9fdaafb 1475 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 1476 }
1477 } else if (rdev->pm.active_crtc_count == 1) {
1478 /* TODO: Increase clocks if needed for current mode */
1479
1480 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1481 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1482 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1483 radeon_pm_get_dynpm_state(rdev);
1484 radeon_pm_set_clocks(rdev);
1485
32c87fca
TH		 1486 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1487 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 1488 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1489 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1490 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1491 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 1492 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 1493 }
1494 } else { /* count == 0 */
1495 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1496 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1497
1498 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1499 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1500 radeon_pm_get_dynpm_state(rdev);
1501 radeon_pm_set_clocks(rdev);
1502 }
1503 }
c913e23a 1504 }
c913e23a 1505 }
73a6d3fc
RM		 1506
1507 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 1508}
1509
da321c8a
AD		 1510static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1511{
1512 struct drm_device *ddev = rdev->ddev;
1513 struct drm_crtc *crtc;
1514 struct radeon_crtc *radeon_crtc;
1515
6c7bccea
AD		 1516 if (!rdev->pm.dpm_enabled)
1517 return;
1518
da321c8a
AD		 1519 mutex_lock(&rdev->pm.mutex);
1520
5ca302f7 1521 /* update active crtc counts */
da321c8a
AD		 1522 rdev->pm.dpm.new_active_crtcs = 0;
1523 rdev->pm.dpm.new_active_crtc_count = 0;
3ed9a335
AD		 1524 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1525 list_for_each_entry(crtc,
1526 &ddev->mode_config.crtc_list, head) {
1527 radeon_crtc = to_radeon_crtc(crtc);
1528 if (crtc->enabled) {
1529 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1530 rdev->pm.dpm.new_active_crtc_count++;
1531 }
da321c8a
AD		 1532 }
1533 }
1534
5ca302f7
AD		 1535 /* update battery/ac status */
1536 if (power_supply_is_system_supplied() > 0)
1537 rdev->pm.dpm.ac_power = true;
1538 else
1539 rdev->pm.dpm.ac_power = false;
1540
da321c8a
AD		 1541 radeon_dpm_change_power_state_locked(rdev);
1542
1543 mutex_unlock(&rdev->pm.mutex);
8a227555 1544
da321c8a
AD		 1545}
1546
1547void radeon_pm_compute_clocks(struct radeon_device *rdev)
1548{
1549 if (rdev->pm.pm_method == PM_METHOD_DPM)
1550 radeon_pm_compute_clocks_dpm(rdev);
1551 else
1552 radeon_pm_compute_clocks_old(rdev);
1553}
1554
ce8f5370 1555static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 1556{
75fa0b08 1557 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 1558 bool in_vbl = true;
1559
75fa0b08
MK		 1560 /* Iterate over all active crtc's. All crtc's must be in vblank,
1561 * otherwise return in_vbl == false.
1562 */
1563 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1564 if (rdev->pm.active_crtcs & (1 << crtc)) {
abca9e45 1565 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
f5a80209
MK		 1566 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1567 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 1568 in_vbl = false;
1569 }
1570 }
f81f2024
MG		 1571
1572 return in_vbl;
1573}
1574
ce8f5370 1575static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 1576{
1577 u32 stat_crtc = 0;
1578 bool in_vbl = radeon_pm_in_vbl(rdev);
1579
f735261b 1580 if (in_vbl == false)
d9fdaafb 1581 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 1582 finish ? "exit" : "entry");
f735261b
DA		 1583 return in_vbl;
1584}
c913e23a 1585
ce8f5370 1586static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 1587{
1588 struct radeon_device *rdev;
d9932a32 1589 int resched;
c913e23a 1590 rdev = container_of(work, struct radeon_device,
ce8f5370 1591 pm.dynpm_idle_work.work);
c913e23a 1592
d9932a32 1593 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 1594 mutex_lock(&rdev->pm.mutex);
ce8f5370 1595 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 1596 int not_processed = 0;
7465280c
AD		 1597 int i;
1598
7465280c 1599 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 1600 struct radeon_ring *ring = &rdev->ring[i];
1601
1602 if (ring->ready) {
1603 not_processed += radeon_fence_count_emitted(rdev, i);
1604 if (not_processed >= 3)
1605 break;
1606 }
c913e23a 1607 }
c913e23a
RM		 1608
1609 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 1610 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1611 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1612 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1613 rdev->pm.dynpm_can_upclock) {
1614 rdev->pm.dynpm_planned_action =
1615 DYNPM_ACTION_UPCLOCK;
1616 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1617 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1618 }
1619 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 1620 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1621 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1622 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1623 rdev->pm.dynpm_can_downclock) {
1624 rdev->pm.dynpm_planned_action =
1625 DYNPM_ACTION_DOWNCLOCK;
1626 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1627 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1628 }
1629 }
1630
d7311171
AD		 1631 /* Note, radeon_pm_set_clocks is called with static_switch set
1632 * to false since we want to wait for vbl to avoid flicker.
1633 */
ce8f5370
AD		 1634 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1635 jiffies > rdev->pm.dynpm_action_timeout) {
1636 radeon_pm_get_dynpm_state(rdev);
1637 radeon_pm_set_clocks(rdev);
c913e23a 1638 }
3f53eb6f 1639
32c87fca
TH		 1640 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1641 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 1642 }
1643 mutex_unlock(&rdev->pm.mutex);
d9932a32 1644 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 1645}
1646
7433874e
RM		 1647/*
1648 * Debugfs info
1649 */
1650#if defined(CONFIG_DEBUG_FS)
1651
1652static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1653{
1654 struct drm_info_node *node = (struct drm_info_node *) m->private;
1655 struct drm_device *dev = node->minor->dev;
1656 struct radeon_device *rdev = dev->dev_private;
4f2f2039 1657 struct drm_device *ddev = rdev->ddev;
7433874e 1658
4f2f2039
AD		 1659 if ((rdev->flags & RADEON_IS_PX) &&
1660 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1661 seq_printf(m, "PX asic powered off\n");
1662 } else if (rdev->pm.dpm_enabled) {
1316b792
AD		 1663 mutex_lock(&rdev->pm.mutex);
1664 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1665 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1666 else
71375929 1667 seq_printf(m, "Debugfs support not implemented for this asic\n");
1316b792
AD		 1668 mutex_unlock(&rdev->pm.mutex);
1669 } else {
1670 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1671 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1672 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1673 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1674 else
1675 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1676 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1677 if (rdev->asic->pm.get_memory_clock)
1678 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1679 if (rdev->pm.current_vddc)
1680 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1681 if (rdev->asic->pm.get_pcie_lanes)
1682 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1683 }
7433874e
RM		 1684
1685 return 0;
1686}
1687
1688static struct drm_info_list radeon_pm_info_list[] = {
1689 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1690};
1691#endif
1692
c913e23a 1693static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 1694{
1695#if defined(CONFIG_DEBUG_FS)
1696 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1697#else
1698 return 0;
1699#endif
1700}
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