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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
c507f7ef | 27 | * Christian König |
771fe6b9 JG |
28 | */ |
29 | #include <linux/seq_file.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
771fe6b9 JG |
31 | #include "drmP.h" |
32 | #include "radeon_drm.h" | |
33 | #include "radeon_reg.h" | |
34 | #include "radeon.h" | |
35 | #include "atom.h" | |
36 | ||
c507f7ef | 37 | /* |
75923280 AD |
38 | * IB |
39 | * IBs (Indirect Buffers) and areas of GPU accessible memory where | |
40 | * commands are stored. You can put a pointer to the IB in the | |
41 | * command ring and the hw will fetch the commands from the IB | |
42 | * and execute them. Generally userspace acceleration drivers | |
43 | * produce command buffers which are send to the kernel and | |
44 | * put in IBs for execution by the requested ring. | |
c507f7ef JG |
45 | */ |
46 | int radeon_debugfs_sa_init(struct radeon_device *rdev); | |
771fe6b9 | 47 | |
75923280 AD |
48 | /** |
49 | * radeon_ib_get - request an IB (Indirect Buffer) | |
50 | * | |
51 | * @rdev: radeon_device pointer | |
52 | * @ring: ring index the IB is associated with | |
53 | * @ib: IB object returned | |
54 | * @size: requested IB size | |
55 | * | |
56 | * Request an IB (all asics). IBs are allocated using the | |
57 | * suballocator. | |
58 | * Returns 0 on success, error on failure. | |
59 | */ | |
69e130a6 | 60 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
f2e39221 | 61 | struct radeon_ib *ib, unsigned size) |
771fe6b9 | 62 | { |
220907d9 | 63 | int i, r; |
b15ba512 | 64 | |
f2e39221 | 65 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); |
c507f7ef JG |
66 | if (r) { |
67 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); | |
c507f7ef | 68 | return r; |
b15ba512 | 69 | } |
c507f7ef | 70 | |
220907d9 CK |
71 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
72 | if (r) { | |
73 | return r; | |
74 | } | |
75 | ||
876dc9f3 CK |
76 | ib->ring = ring; |
77 | ib->fence = NULL; | |
f2e39221 JG |
78 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
79 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); | |
80 | ib->vm_id = 0; | |
81 | ib->is_const_ib = false; | |
220907d9 CK |
82 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
83 | ib->sync_to[i] = NULL; | |
c507f7ef JG |
84 | |
85 | return 0; | |
771fe6b9 JG |
86 | } |
87 | ||
75923280 AD |
88 | /** |
89 | * radeon_ib_free - free an IB (Indirect Buffer) | |
90 | * | |
91 | * @rdev: radeon_device pointer | |
92 | * @ib: IB object to free | |
93 | * | |
94 | * Free an IB (all asics). | |
95 | */ | |
f2e39221 | 96 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
771fe6b9 | 97 | { |
220907d9 | 98 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
f2e39221 JG |
99 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
100 | radeon_fence_unref(&ib->fence); | |
771fe6b9 JG |
101 | } |
102 | ||
75923280 AD |
103 | /** |
104 | * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring | |
105 | * | |
106 | * @rdev: radeon_device pointer | |
107 | * @ib: IB object to schedule | |
108 | * @const_ib: Const IB to schedule (SI only) | |
109 | * | |
110 | * Schedule an IB on the associated ring (all asics). | |
111 | * Returns 0 on success, error on failure. | |
112 | * | |
113 | * On SI, there are two parallel engines fed from the primary ring, | |
114 | * the CE (Constant Engine) and the DE (Drawing Engine). Since | |
115 | * resource descriptors have moved to memory, the CE allows you to | |
116 | * prime the caches while the DE is updating register state so that | |
117 | * the resource descriptors will be already in cache when the draw is | |
118 | * processed. To accomplish this, the userspace driver submits two | |
119 | * IBs, one for the CE and one for the DE. If there is a CE IB (called | |
120 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior | |
121 | * to SI there was just a DE IB. | |
122 | */ | |
4ef72566 CK |
123 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
124 | struct radeon_ib *const_ib) | |
771fe6b9 | 125 | { |
876dc9f3 | 126 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
220907d9 CK |
127 | bool need_sync = false; |
128 | int i, r = 0; | |
771fe6b9 | 129 | |
e32eb50d | 130 | if (!ib->length_dw || !ring->ready) { |
771fe6b9 | 131 | /* TODO: Nothings in the ib we should report. */ |
c507f7ef | 132 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
771fe6b9 JG |
133 | return -EINVAL; |
134 | } | |
ecb114a1 | 135 | |
6cdf6585 | 136 | /* 64 dwords should be enough for fence too */ |
220907d9 | 137 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); |
771fe6b9 | 138 | if (r) { |
c507f7ef | 139 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
771fe6b9 JG |
140 | return r; |
141 | } | |
220907d9 CK |
142 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
143 | struct radeon_fence *fence = ib->sync_to[i]; | |
144 | if (radeon_fence_need_sync(fence, ib->ring)) { | |
145 | need_sync = true; | |
146 | radeon_semaphore_sync_rings(rdev, ib->semaphore, | |
147 | fence->ring, ib->ring); | |
148 | radeon_fence_note_sync(fence, ib->ring); | |
149 | } | |
150 | } | |
151 | /* immediately free semaphore when we don't need to sync */ | |
152 | if (!need_sync) { | |
153 | radeon_semaphore_free(rdev, &ib->semaphore, NULL); | |
154 | } | |
4ef72566 CK |
155 | if (const_ib) { |
156 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); | |
157 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); | |
158 | } | |
876dc9f3 CK |
159 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
160 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); | |
161 | if (r) { | |
162 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); | |
163 | radeon_ring_unlock_undo(rdev, ring); | |
164 | return r; | |
165 | } | |
4ef72566 CK |
166 | if (const_ib) { |
167 | const_ib->fence = radeon_fence_ref(ib->fence); | |
168 | } | |
e32eb50d | 169 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
170 | return 0; |
171 | } | |
172 | ||
75923280 AD |
173 | /** |
174 | * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool | |
175 | * | |
176 | * @rdev: radeon_device pointer | |
177 | * | |
178 | * Initialize the suballocator to manage a pool of memory | |
179 | * for use as IBs (all asics). | |
180 | * Returns 0 on success, error on failure. | |
181 | */ | |
771fe6b9 JG |
182 | int radeon_ib_pool_init(struct radeon_device *rdev) |
183 | { | |
c507f7ef | 184 | int r; |
771fe6b9 | 185 | |
c507f7ef | 186 | if (rdev->ib_pool_ready) { |
d54fbd49 JG |
187 | return 0; |
188 | } | |
c507f7ef | 189 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
c3b7fe8b CK |
190 | RADEON_IB_POOL_SIZE*64*1024, |
191 | RADEON_GEM_DOMAIN_GTT); | |
192 | if (r) { | |
c3b7fe8b CK |
193 | return r; |
194 | } | |
2898c348 CK |
195 | |
196 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); | |
197 | if (r) { | |
198 | return r; | |
199 | } | |
200 | ||
c507f7ef JG |
201 | rdev->ib_pool_ready = true; |
202 | if (radeon_debugfs_sa_init(rdev)) { | |
203 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); | |
771fe6b9 | 204 | } |
b15ba512 | 205 | return 0; |
771fe6b9 JG |
206 | } |
207 | ||
75923280 AD |
208 | /** |
209 | * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool | |
210 | * | |
211 | * @rdev: radeon_device pointer | |
212 | * | |
213 | * Tear down the suballocator managing the pool of memory | |
214 | * for use as IBs (all asics). | |
215 | */ | |
771fe6b9 JG |
216 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
217 | { | |
c507f7ef | 218 | if (rdev->ib_pool_ready) { |
2898c348 | 219 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
c507f7ef JG |
220 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
221 | rdev->ib_pool_ready = false; | |
771fe6b9 | 222 | } |
771fe6b9 JG |
223 | } |
224 | ||
75923280 AD |
225 | /** |
226 | * radeon_ib_ring_tests - test IBs on the rings | |
227 | * | |
228 | * @rdev: radeon_device pointer | |
229 | * | |
230 | * Test an IB (Indirect Buffer) on each ring. | |
231 | * If the test fails, disable the ring. | |
232 | * Returns 0 on success, error if the primary GFX ring | |
233 | * IB test fails. | |
234 | */ | |
7bd560e8 CK |
235 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
236 | { | |
237 | unsigned i; | |
238 | int r; | |
239 | ||
240 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
241 | struct radeon_ring *ring = &rdev->ring[i]; | |
242 | ||
243 | if (!ring->ready) | |
244 | continue; | |
245 | ||
246 | r = radeon_ib_test(rdev, i, ring); | |
247 | if (r) { | |
248 | ring->ready = false; | |
249 | ||
250 | if (i == RADEON_RING_TYPE_GFX_INDEX) { | |
251 | /* oh, oh, that's really bad */ | |
252 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); | |
253 | rdev->accel_working = false; | |
254 | return r; | |
255 | ||
256 | } else { | |
257 | /* still not good, but we can live with it */ | |
258 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); | |
259 | } | |
260 | } | |
261 | } | |
262 | return 0; | |
263 | } | |
264 | ||
771fe6b9 | 265 | /* |
75923280 AD |
266 | * Rings |
267 | * Most engines on the GPU are fed via ring buffers. Ring | |
268 | * buffers are areas of GPU accessible memory that the host | |
269 | * writes commands into and the GPU reads commands out of. | |
270 | * There is a rptr (read pointer) that determines where the | |
271 | * GPU is currently reading, and a wptr (write pointer) | |
272 | * which determines where the host has written. When the | |
273 | * pointers are equal, the ring is idle. When the host | |
274 | * writes commands to the ring buffer, it increments the | |
275 | * wptr. The GPU then starts fetching commands and executes | |
276 | * them until the pointers are equal again. | |
771fe6b9 | 277 | */ |
c507f7ef JG |
278 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
279 | ||
75923280 AD |
280 | /** |
281 | * radeon_ring_write - write a value to the ring | |
282 | * | |
283 | * @ring: radeon_ring structure holding ring information | |
284 | * @v: dword (dw) value to write | |
285 | * | |
286 | * Write a value to the requested ring buffer (all asics). | |
287 | */ | |
c507f7ef JG |
288 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
289 | { | |
290 | #if DRM_DEBUG_CODE | |
291 | if (ring->count_dw <= 0) { | |
292 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); | |
293 | } | |
294 | #endif | |
295 | ring->ring[ring->wptr++] = v; | |
296 | ring->wptr &= ring->ptr_mask; | |
297 | ring->count_dw--; | |
298 | ring->ring_free_dw--; | |
299 | } | |
300 | ||
75923280 AD |
301 | /** |
302 | * radeon_ring_supports_scratch_reg - check if the ring supports | |
303 | * writing to scratch registers | |
304 | * | |
305 | * @rdev: radeon_device pointer | |
306 | * @ring: radeon_ring structure holding ring information | |
307 | * | |
308 | * Check if a specific ring supports writing to scratch registers (all asics). | |
309 | * Returns true if the ring supports writing to scratch regs, false if not. | |
310 | */ | |
89d35807 AD |
311 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
312 | struct radeon_ring *ring) | |
313 | { | |
314 | switch (ring->idx) { | |
315 | case RADEON_RING_TYPE_GFX_INDEX: | |
316 | case CAYMAN_RING_TYPE_CP1_INDEX: | |
317 | case CAYMAN_RING_TYPE_CP2_INDEX: | |
318 | return true; | |
319 | default: | |
320 | return false; | |
321 | } | |
322 | } | |
323 | ||
75923280 AD |
324 | /** |
325 | * radeon_ring_free_size - update the free size | |
326 | * | |
327 | * @rdev: radeon_device pointer | |
328 | * @ring: radeon_ring structure holding ring information | |
329 | * | |
330 | * Update the free dw slots in the ring buffer (all asics). | |
331 | */ | |
e32eb50d | 332 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 333 | { |
78c5560a AD |
334 | u32 rptr; |
335 | ||
724c80e1 | 336 | if (rdev->wb.enabled) |
78c5560a | 337 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
5596a9db | 338 | else |
78c5560a AD |
339 | rptr = RREG32(ring->rptr_reg); |
340 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; | |
771fe6b9 | 341 | /* This works because ring_size is a power of 2 */ |
e32eb50d CK |
342 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
343 | ring->ring_free_dw -= ring->wptr; | |
344 | ring->ring_free_dw &= ring->ptr_mask; | |
345 | if (!ring->ring_free_dw) { | |
346 | ring->ring_free_dw = ring->ring_size / 4; | |
771fe6b9 JG |
347 | } |
348 | } | |
349 | ||
75923280 AD |
350 | /** |
351 | * radeon_ring_alloc - allocate space on the ring buffer | |
352 | * | |
353 | * @rdev: radeon_device pointer | |
354 | * @ring: radeon_ring structure holding ring information | |
355 | * @ndw: number of dwords to allocate in the ring buffer | |
356 | * | |
357 | * Allocate @ndw dwords in the ring buffer (all asics). | |
358 | * Returns 0 on success, error on failure. | |
359 | */ | |
e32eb50d | 360 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
771fe6b9 JG |
361 | { |
362 | int r; | |
363 | ||
364 | /* Align requested size with padding so unlock_commit can | |
365 | * pad safely */ | |
e32eb50d CK |
366 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
367 | while (ndw > (ring->ring_free_dw - 1)) { | |
368 | radeon_ring_free_size(rdev, ring); | |
369 | if (ndw < ring->ring_free_dw) { | |
771fe6b9 JG |
370 | break; |
371 | } | |
8b25ed34 | 372 | r = radeon_fence_wait_next_locked(rdev, ring->idx); |
91700f3c | 373 | if (r) |
771fe6b9 | 374 | return r; |
771fe6b9 | 375 | } |
e32eb50d CK |
376 | ring->count_dw = ndw; |
377 | ring->wptr_old = ring->wptr; | |
771fe6b9 JG |
378 | return 0; |
379 | } | |
380 | ||
75923280 AD |
381 | /** |
382 | * radeon_ring_lock - lock the ring and allocate space on it | |
383 | * | |
384 | * @rdev: radeon_device pointer | |
385 | * @ring: radeon_ring structure holding ring information | |
386 | * @ndw: number of dwords to allocate in the ring buffer | |
387 | * | |
388 | * Lock the ring and allocate @ndw dwords in the ring buffer | |
389 | * (all asics). | |
390 | * Returns 0 on success, error on failure. | |
391 | */ | |
e32eb50d | 392 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
91700f3c MG |
393 | { |
394 | int r; | |
395 | ||
d6999bc7 | 396 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 397 | r = radeon_ring_alloc(rdev, ring, ndw); |
91700f3c | 398 | if (r) { |
d6999bc7 | 399 | mutex_unlock(&rdev->ring_lock); |
91700f3c MG |
400 | return r; |
401 | } | |
402 | return 0; | |
403 | } | |
404 | ||
75923280 AD |
405 | /** |
406 | * radeon_ring_commit - tell the GPU to execute the new | |
407 | * commands on the ring buffer | |
408 | * | |
409 | * @rdev: radeon_device pointer | |
410 | * @ring: radeon_ring structure holding ring information | |
411 | * | |
412 | * Update the wptr (write pointer) to tell the GPU to | |
413 | * execute new commands on the ring buffer (all asics). | |
414 | */ | |
e32eb50d | 415 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 416 | { |
771fe6b9 | 417 | /* We pad to match fetch size */ |
07a71330 | 418 | while (ring->wptr & ring->align_mask) { |
78c5560a | 419 | radeon_ring_write(ring, ring->nop); |
771fe6b9 JG |
420 | } |
421 | DRM_MEMORYBARRIER(); | |
78c5560a | 422 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
e32eb50d | 423 | (void)RREG32(ring->wptr_reg); |
91700f3c MG |
424 | } |
425 | ||
75923280 AD |
426 | /** |
427 | * radeon_ring_unlock_commit - tell the GPU to execute the new | |
428 | * commands on the ring buffer and unlock it | |
429 | * | |
430 | * @rdev: radeon_device pointer | |
431 | * @ring: radeon_ring structure holding ring information | |
432 | * | |
433 | * Call radeon_ring_commit() then unlock the ring (all asics). | |
434 | */ | |
e32eb50d | 435 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
91700f3c | 436 | { |
e32eb50d | 437 | radeon_ring_commit(rdev, ring); |
d6999bc7 | 438 | mutex_unlock(&rdev->ring_lock); |
771fe6b9 JG |
439 | } |
440 | ||
75923280 AD |
441 | /** |
442 | * radeon_ring_undo - reset the wptr | |
443 | * | |
444 | * @ring: radeon_ring structure holding ring information | |
445 | * | |
446 | * Reset the driver's copy of the wtpr (all asics). | |
447 | */ | |
d6999bc7 | 448 | void radeon_ring_undo(struct radeon_ring *ring) |
771fe6b9 | 449 | { |
e32eb50d | 450 | ring->wptr = ring->wptr_old; |
d6999bc7 CK |
451 | } |
452 | ||
75923280 AD |
453 | /** |
454 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring | |
455 | * | |
456 | * @ring: radeon_ring structure holding ring information | |
457 | * | |
458 | * Call radeon_ring_undo() then unlock the ring (all asics). | |
459 | */ | |
d6999bc7 CK |
460 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
461 | { | |
462 | radeon_ring_undo(ring); | |
463 | mutex_unlock(&rdev->ring_lock); | |
771fe6b9 JG |
464 | } |
465 | ||
75923280 AD |
466 | /** |
467 | * radeon_ring_force_activity - add some nop packets to the ring | |
468 | * | |
469 | * @rdev: radeon_device pointer | |
470 | * @ring: radeon_ring structure holding ring information | |
471 | * | |
472 | * Add some nop packets to the ring to force activity (all asics). | |
473 | * Used for lockup detection to see if the rptr is advancing. | |
474 | */ | |
7b9ef16b CK |
475 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
476 | { | |
477 | int r; | |
478 | ||
7b9ef16b CK |
479 | radeon_ring_free_size(rdev, ring); |
480 | if (ring->rptr == ring->wptr) { | |
481 | r = radeon_ring_alloc(rdev, ring, 1); | |
482 | if (!r) { | |
483 | radeon_ring_write(ring, ring->nop); | |
484 | radeon_ring_commit(rdev, ring); | |
485 | } | |
486 | } | |
7b9ef16b CK |
487 | } |
488 | ||
75923280 AD |
489 | /** |
490 | * radeon_ring_force_activity - update lockup variables | |
491 | * | |
492 | * @ring: radeon_ring structure holding ring information | |
493 | * | |
494 | * Update the last rptr value and timestamp (all asics). | |
495 | */ | |
069211e5 CK |
496 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
497 | { | |
498 | ring->last_rptr = ring->rptr; | |
499 | ring->last_activity = jiffies; | |
500 | } | |
501 | ||
502 | /** | |
503 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information | |
504 | * @rdev: radeon device structure | |
505 | * @ring: radeon_ring structure holding ring information | |
506 | * | |
507 | * We don't need to initialize the lockup tracking information as we will either | |
508 | * have CP rptr to a different value of jiffies wrap around which will force | |
509 | * initialization of the lockup tracking informations. | |
510 | * | |
511 | * A possible false positivie is if we get call after while and last_cp_rptr == | |
512 | * the current CP rptr, even if it's unlikely it might happen. To avoid this | |
513 | * if the elapsed time since last call is bigger than 2 second than we return | |
514 | * false and update the tracking information. Due to this the caller must call | |
515 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported | |
516 | * the fencing code should be cautious about that. | |
517 | * | |
518 | * Caller should write to the ring to force CP to do something so we don't get | |
519 | * false positive when CP is just gived nothing to do. | |
520 | * | |
521 | **/ | |
522 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
523 | { | |
524 | unsigned long cjiffies, elapsed; | |
525 | uint32_t rptr; | |
526 | ||
527 | cjiffies = jiffies; | |
528 | if (!time_after(cjiffies, ring->last_activity)) { | |
529 | /* likely a wrap around */ | |
530 | radeon_ring_lockup_update(ring); | |
531 | return false; | |
532 | } | |
533 | rptr = RREG32(ring->rptr_reg); | |
534 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; | |
535 | if (ring->rptr != ring->last_rptr) { | |
536 | /* CP is still working no lockup */ | |
537 | radeon_ring_lockup_update(ring); | |
538 | return false; | |
539 | } | |
540 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); | |
3368ff0c | 541 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
069211e5 CK |
542 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
543 | return true; | |
544 | } | |
545 | /* give a chance to the GPU ... */ | |
546 | return false; | |
547 | } | |
548 | ||
55d7c221 CK |
549 | /** |
550 | * radeon_ring_backup - Back up the content of a ring | |
551 | * | |
552 | * @rdev: radeon_device pointer | |
553 | * @ring: the ring we want to back up | |
554 | * | |
555 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. | |
556 | */ | |
557 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, | |
558 | uint32_t **data) | |
559 | { | |
560 | unsigned size, ptr, i; | |
55d7c221 CK |
561 | |
562 | /* just in case lock the ring */ | |
563 | mutex_lock(&rdev->ring_lock); | |
564 | *data = NULL; | |
565 | ||
89d35807 | 566 | if (ring->ring_obj == NULL) { |
55d7c221 CK |
567 | mutex_unlock(&rdev->ring_lock); |
568 | return 0; | |
569 | } | |
570 | ||
571 | /* it doesn't make sense to save anything if all fences are signaled */ | |
8b25ed34 | 572 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
55d7c221 CK |
573 | mutex_unlock(&rdev->ring_lock); |
574 | return 0; | |
575 | } | |
576 | ||
577 | /* calculate the number of dw on the ring */ | |
89d35807 AD |
578 | if (ring->rptr_save_reg) |
579 | ptr = RREG32(ring->rptr_save_reg); | |
580 | else if (rdev->wb.enabled) | |
581 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); | |
582 | else { | |
583 | /* no way to read back the next rptr */ | |
584 | mutex_unlock(&rdev->ring_lock); | |
585 | return 0; | |
586 | } | |
587 | ||
55d7c221 CK |
588 | size = ring->wptr + (ring->ring_size / 4); |
589 | size -= ptr; | |
590 | size &= ring->ptr_mask; | |
591 | if (size == 0) { | |
592 | mutex_unlock(&rdev->ring_lock); | |
593 | return 0; | |
594 | } | |
595 | ||
596 | /* and then save the content of the ring */ | |
1e179d4e DC |
597 | *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); |
598 | if (!*data) { | |
599 | mutex_unlock(&rdev->ring_lock); | |
600 | return 0; | |
601 | } | |
55d7c221 CK |
602 | for (i = 0; i < size; ++i) { |
603 | (*data)[i] = ring->ring[ptr++]; | |
604 | ptr &= ring->ptr_mask; | |
605 | } | |
606 | ||
607 | mutex_unlock(&rdev->ring_lock); | |
608 | return size; | |
609 | } | |
610 | ||
611 | /** | |
612 | * radeon_ring_restore - append saved commands to the ring again | |
613 | * | |
614 | * @rdev: radeon_device pointer | |
615 | * @ring: ring to append commands to | |
616 | * @size: number of dwords we want to write | |
617 | * @data: saved commands | |
618 | * | |
619 | * Allocates space on the ring and restore the previously saved commands. | |
620 | */ | |
621 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
622 | unsigned size, uint32_t *data) | |
623 | { | |
624 | int i, r; | |
625 | ||
626 | if (!size || !data) | |
627 | return 0; | |
628 | ||
629 | /* restore the saved ring content */ | |
630 | r = radeon_ring_lock(rdev, ring, size); | |
631 | if (r) | |
632 | return r; | |
633 | ||
634 | for (i = 0; i < size; ++i) { | |
635 | radeon_ring_write(ring, data[i]); | |
636 | } | |
637 | ||
638 | radeon_ring_unlock_commit(rdev, ring); | |
639 | kfree(data); | |
640 | return 0; | |
641 | } | |
642 | ||
75923280 AD |
643 | /** |
644 | * radeon_ring_init - init driver ring struct. | |
645 | * | |
646 | * @rdev: radeon_device pointer | |
647 | * @ring: radeon_ring structure holding ring information | |
648 | * @ring_size: size of the ring | |
649 | * @rptr_offs: offset of the rptr writeback location in the WB buffer | |
650 | * @rptr_reg: MMIO offset of the rptr register | |
651 | * @wptr_reg: MMIO offset of the wptr register | |
652 | * @ptr_reg_shift: bit offset of the rptr/wptr values | |
653 | * @ptr_reg_mask: bit mask of the rptr/wptr values | |
654 | * @nop: nop packet for this ring | |
655 | * | |
656 | * Initialize the driver information for the selected ring (all asics). | |
657 | * Returns 0 on success, error on failure. | |
658 | */ | |
e32eb50d | 659 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
78c5560a AD |
660 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
661 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) | |
771fe6b9 JG |
662 | { |
663 | int r; | |
664 | ||
e32eb50d CK |
665 | ring->ring_size = ring_size; |
666 | ring->rptr_offs = rptr_offs; | |
667 | ring->rptr_reg = rptr_reg; | |
668 | ring->wptr_reg = wptr_reg; | |
78c5560a AD |
669 | ring->ptr_reg_shift = ptr_reg_shift; |
670 | ring->ptr_reg_mask = ptr_reg_mask; | |
671 | ring->nop = nop; | |
771fe6b9 | 672 | /* Allocate ring buffer */ |
e32eb50d CK |
673 | if (ring->ring_obj == NULL) { |
674 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, | |
40f5cf99 AD |
675 | RADEON_GEM_DOMAIN_GTT, |
676 | NULL, &ring->ring_obj); | |
771fe6b9 | 677 | if (r) { |
4c788679 | 678 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
771fe6b9 JG |
679 | return r; |
680 | } | |
e32eb50d | 681 | r = radeon_bo_reserve(ring->ring_obj, false); |
4c788679 JG |
682 | if (unlikely(r != 0)) |
683 | return r; | |
e32eb50d CK |
684 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
685 | &ring->gpu_addr); | |
771fe6b9 | 686 | if (r) { |
e32eb50d | 687 | radeon_bo_unreserve(ring->ring_obj); |
4c788679 | 688 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
771fe6b9 JG |
689 | return r; |
690 | } | |
e32eb50d CK |
691 | r = radeon_bo_kmap(ring->ring_obj, |
692 | (void **)&ring->ring); | |
693 | radeon_bo_unreserve(ring->ring_obj); | |
771fe6b9 | 694 | if (r) { |
4c788679 | 695 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
771fe6b9 JG |
696 | return r; |
697 | } | |
698 | } | |
e32eb50d CK |
699 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
700 | ring->ring_free_dw = ring->ring_size / 4; | |
89d35807 AD |
701 | if (rdev->wb.enabled) { |
702 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); | |
703 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; | |
704 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; | |
705 | } | |
ec1a6cce CK |
706 | if (radeon_debugfs_ring_init(rdev, ring)) { |
707 | DRM_ERROR("Failed to register debugfs file for rings !\n"); | |
708 | } | |
48c0ac99 | 709 | radeon_ring_lockup_update(ring); |
771fe6b9 JG |
710 | return 0; |
711 | } | |
712 | ||
75923280 AD |
713 | /** |
714 | * radeon_ring_fini - tear down the driver ring struct. | |
715 | * | |
716 | * @rdev: radeon_device pointer | |
717 | * @ring: radeon_ring structure holding ring information | |
718 | * | |
719 | * Tear down the driver information for the selected ring (all asics). | |
720 | */ | |
e32eb50d | 721 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 722 | { |
4c788679 | 723 | int r; |
ca2af923 | 724 | struct radeon_bo *ring_obj; |
4c788679 | 725 | |
d6999bc7 | 726 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 727 | ring_obj = ring->ring_obj; |
d6999bc7 | 728 | ring->ready = false; |
e32eb50d CK |
729 | ring->ring = NULL; |
730 | ring->ring_obj = NULL; | |
d6999bc7 | 731 | mutex_unlock(&rdev->ring_lock); |
ca2af923 AD |
732 | |
733 | if (ring_obj) { | |
734 | r = radeon_bo_reserve(ring_obj, false); | |
4c788679 | 735 | if (likely(r == 0)) { |
ca2af923 AD |
736 | radeon_bo_kunmap(ring_obj); |
737 | radeon_bo_unpin(ring_obj); | |
738 | radeon_bo_unreserve(ring_obj); | |
4c788679 | 739 | } |
ca2af923 | 740 | radeon_bo_unref(&ring_obj); |
771fe6b9 | 741 | } |
771fe6b9 JG |
742 | } |
743 | ||
771fe6b9 JG |
744 | /* |
745 | * Debugfs info | |
746 | */ | |
747 | #if defined(CONFIG_DEBUG_FS) | |
af9720f4 CK |
748 | |
749 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) | |
750 | { | |
751 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
752 | struct drm_device *dev = node->minor->dev; | |
753 | struct radeon_device *rdev = dev->dev_private; | |
754 | int ridx = *(int*)node->info_ent->data; | |
755 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
756 | unsigned count, i, j; | |
757 | ||
758 | radeon_ring_free_size(rdev, ring); | |
759 | count = (ring->ring_size / 4) - ring->ring_free_dw; | |
760 | seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg)); | |
761 | seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg)); | |
45df6803 CK |
762 | if (ring->rptr_save_reg) { |
763 | seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, | |
764 | RREG32(ring->rptr_save_reg)); | |
765 | } | |
af9720f4 CK |
766 | seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr); |
767 | seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr); | |
768 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); | |
769 | seq_printf(m, "%u dwords in ring\n", count); | |
770 | i = ring->rptr; | |
771 | for (j = 0; j <= count; j++) { | |
772 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); | |
773 | i = (i + 1) & ring->ptr_mask; | |
774 | } | |
775 | return 0; | |
776 | } | |
777 | ||
778 | static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; | |
779 | static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; | |
780 | static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; | |
781 | ||
782 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { | |
783 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, | |
784 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, | |
785 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, | |
786 | }; | |
787 | ||
711a9729 CK |
788 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
789 | { | |
790 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
791 | struct drm_device *dev = node->minor->dev; | |
792 | struct radeon_device *rdev = dev->dev_private; | |
793 | ||
c507f7ef | 794 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
711a9729 CK |
795 | |
796 | return 0; | |
797 | ||
798 | } | |
799 | ||
800 | static struct drm_info_list radeon_debugfs_sa_list[] = { | |
801 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, | |
802 | }; | |
803 | ||
771fe6b9 JG |
804 | #endif |
805 | ||
ec1a6cce | 806 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
af9720f4 CK |
807 | { |
808 | #if defined(CONFIG_DEBUG_FS) | |
ec1a6cce CK |
809 | unsigned i; |
810 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { | |
811 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; | |
812 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; | |
813 | unsigned r; | |
814 | ||
815 | if (&rdev->ring[ridx] != ring) | |
816 | continue; | |
817 | ||
818 | r = radeon_debugfs_add_files(rdev, info, 1); | |
819 | if (r) | |
820 | return r; | |
821 | } | |
af9720f4 | 822 | #endif |
ec1a6cce | 823 | return 0; |
af9720f4 CK |
824 | } |
825 | ||
c507f7ef | 826 | int radeon_debugfs_sa_init(struct radeon_device *rdev) |
771fe6b9 JG |
827 | { |
828 | #if defined(CONFIG_DEBUG_FS) | |
c507f7ef | 829 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
771fe6b9 JG |
830 | #else |
831 | return 0; | |
832 | #endif | |
833 | } |