]>
Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
771fe6b9 JG |
30 | #include "drmP.h" |
31 | #include "radeon_drm.h" | |
32 | #include "radeon_reg.h" | |
33 | #include "radeon.h" | |
34 | #include "atom.h" | |
35 | ||
36 | int radeon_debugfs_ib_init(struct radeon_device *rdev); | |
ec1a6cce | 37 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
771fe6b9 | 38 | |
ce580fab AK |
39 | u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
40 | { | |
41 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
42 | u32 pg_idx, pg_offset; | |
43 | u32 idx_value = 0; | |
44 | int new_page; | |
45 | ||
46 | pg_idx = (idx * 4) / PAGE_SIZE; | |
47 | pg_offset = (idx * 4) % PAGE_SIZE; | |
48 | ||
49 | if (ibc->kpage_idx[0] == pg_idx) | |
50 | return ibc->kpage[0][pg_offset/4]; | |
51 | if (ibc->kpage_idx[1] == pg_idx) | |
52 | return ibc->kpage[1][pg_offset/4]; | |
53 | ||
54 | new_page = radeon_cs_update_pages(p, pg_idx); | |
55 | if (new_page < 0) { | |
56 | p->parser_error = new_page; | |
57 | return 0; | |
58 | } | |
59 | ||
60 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
61 | return idx_value; | |
62 | } | |
63 | ||
e32eb50d | 64 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
ce580fab AK |
65 | { |
66 | #if DRM_DEBUG_CODE | |
e32eb50d | 67 | if (ring->count_dw <= 0) { |
ce580fab AK |
68 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
69 | } | |
70 | #endif | |
e32eb50d CK |
71 | ring->ring[ring->wptr++] = v; |
72 | ring->wptr &= ring->ptr_mask; | |
73 | ring->count_dw--; | |
74 | ring->ring_free_dw--; | |
ce580fab AK |
75 | } |
76 | ||
b15ba512 JG |
77 | /* |
78 | * IB. | |
79 | */ | |
c1341e52 | 80 | bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib) |
9f93ed39 | 81 | { |
b15ba512 JG |
82 | bool done = false; |
83 | ||
84 | /* only free ib which have been emited */ | |
85 | if (ib->fence && ib->fence->emitted) { | |
86 | if (radeon_fence_signaled(ib->fence)) { | |
87 | radeon_fence_unref(&ib->fence); | |
88 | radeon_sa_bo_free(rdev, &ib->sa_bo); | |
89 | done = true; | |
90 | } | |
9f93ed39 | 91 | } |
b15ba512 | 92 | return done; |
9f93ed39 JG |
93 | } |
94 | ||
69e130a6 JG |
95 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
96 | struct radeon_ib **ib, unsigned size) | |
771fe6b9 JG |
97 | { |
98 | struct radeon_fence *fence; | |
b15ba512 JG |
99 | unsigned cretry = 0; |
100 | int r = 0, i, idx; | |
771fe6b9 JG |
101 | |
102 | *ib = NULL; | |
69e130a6 JG |
103 | /* align size on 256 bytes */ |
104 | size = ALIGN(size, 256); | |
b15ba512 | 105 | |
7b1f2485 | 106 | r = radeon_fence_create(rdev, &fence, ring); |
771fe6b9 | 107 | if (r) { |
91cb91be | 108 | dev_err(rdev->dev, "failed to create fence for new IB\n"); |
771fe6b9 JG |
109 | return r; |
110 | } | |
b15ba512 | 111 | |
9fc04b50 | 112 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
b15ba512 JG |
113 | idx = rdev->ib_pool.head_id; |
114 | retry: | |
115 | if (cretry > 5) { | |
116 | dev_err(rdev->dev, "failed to get an ib after 5 retry\n"); | |
9fc04b50 | 117 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
91cb91be | 118 | radeon_fence_unref(&fence); |
b15ba512 | 119 | return -ENOMEM; |
771fe6b9 | 120 | } |
b15ba512 JG |
121 | cretry++; |
122 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { | |
123 | radeon_ib_try_free(rdev, &rdev->ib_pool.ibs[idx]); | |
124 | if (rdev->ib_pool.ibs[idx].fence == NULL) { | |
125 | r = radeon_sa_bo_new(rdev, &rdev->ib_pool.sa_manager, | |
126 | &rdev->ib_pool.ibs[idx].sa_bo, | |
69e130a6 | 127 | size, 256); |
b15ba512 JG |
128 | if (!r) { |
129 | *ib = &rdev->ib_pool.ibs[idx]; | |
130 | (*ib)->ptr = rdev->ib_pool.sa_manager.cpu_ptr; | |
131 | (*ib)->ptr += ((*ib)->sa_bo.offset >> 2); | |
132 | (*ib)->gpu_addr = rdev->ib_pool.sa_manager.gpu_addr; | |
133 | (*ib)->gpu_addr += (*ib)->sa_bo.offset; | |
134 | (*ib)->fence = fence; | |
721604a1 | 135 | (*ib)->vm_id = 0; |
dfcf5f36 | 136 | (*ib)->is_const_ib = false; |
b15ba512 JG |
137 | /* ib are most likely to be allocated in a ring fashion |
138 | * thus rdev->ib_pool.head_id should be the id of the | |
139 | * oldest ib | |
140 | */ | |
141 | rdev->ib_pool.head_id = (1 + idx); | |
142 | rdev->ib_pool.head_id &= (RADEON_IB_POOL_SIZE - 1); | |
9fc04b50 | 143 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
b15ba512 JG |
144 | return 0; |
145 | } | |
91cb91be | 146 | } |
b15ba512 JG |
147 | idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1); |
148 | } | |
149 | /* this should be rare event, ie all ib scheduled none signaled yet. | |
150 | */ | |
151 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { | |
c1341e52 | 152 | if (rdev->ib_pool.ibs[idx].fence && rdev->ib_pool.ibs[idx].fence->emitted) { |
b15ba512 JG |
153 | r = radeon_fence_wait(rdev->ib_pool.ibs[idx].fence, false); |
154 | if (!r) { | |
155 | goto retry; | |
156 | } | |
157 | /* an error happened */ | |
158 | break; | |
159 | } | |
160 | idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1); | |
771fe6b9 | 161 | } |
9fc04b50 | 162 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
b15ba512 JG |
163 | radeon_fence_unref(&fence); |
164 | return r; | |
771fe6b9 JG |
165 | } |
166 | ||
167 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) | |
168 | { | |
169 | struct radeon_ib *tmp = *ib; | |
170 | ||
171 | *ib = NULL; | |
172 | if (tmp == NULL) { | |
173 | return; | |
174 | } | |
9fc04b50 | 175 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
b15ba512 JG |
176 | if (tmp->fence && !tmp->fence->emitted) { |
177 | radeon_sa_bo_free(rdev, &tmp->sa_bo); | |
178 | radeon_fence_unref(&tmp->fence); | |
179 | } | |
9fc04b50 | 180 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
771fe6b9 JG |
181 | } |
182 | ||
771fe6b9 JG |
183 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) |
184 | { | |
e32eb50d | 185 | struct radeon_ring *ring = &rdev->ring[ib->fence->ring]; |
771fe6b9 JG |
186 | int r = 0; |
187 | ||
e32eb50d | 188 | if (!ib->length_dw || !ring->ready) { |
771fe6b9 | 189 | /* TODO: Nothings in the ib we should report. */ |
91cb91be | 190 | DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx); |
771fe6b9 JG |
191 | return -EINVAL; |
192 | } | |
ecb114a1 | 193 | |
6cdf6585 | 194 | /* 64 dwords should be enough for fence too */ |
e32eb50d | 195 | r = radeon_ring_lock(rdev, ring, 64); |
771fe6b9 | 196 | if (r) { |
ec4f2ac4 | 197 | DRM_ERROR("radeon: scheduling IB failed (%d).\n", r); |
771fe6b9 JG |
198 | return r; |
199 | } | |
4c87bc26 | 200 | radeon_ring_ib_execute(rdev, ib->fence->ring, ib); |
771fe6b9 | 201 | radeon_fence_emit(rdev, ib->fence); |
e32eb50d | 202 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
203 | return 0; |
204 | } | |
205 | ||
206 | int radeon_ib_pool_init(struct radeon_device *rdev) | |
207 | { | |
d54fbd49 | 208 | struct radeon_sa_manager tmp; |
b15ba512 | 209 | int i, r; |
771fe6b9 | 210 | |
d54fbd49 | 211 | r = radeon_sa_bo_manager_init(rdev, &tmp, |
b15ba512 JG |
212 | RADEON_IB_POOL_SIZE*64*1024, |
213 | RADEON_GEM_DOMAIN_GTT); | |
771fe6b9 | 214 | if (r) { |
771fe6b9 JG |
215 | return r; |
216 | } | |
771fe6b9 | 217 | |
9fc04b50 | 218 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
d54fbd49 | 219 | if (rdev->ib_pool.ready) { |
9fc04b50 | 220 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
d54fbd49 JG |
221 | radeon_sa_bo_manager_fini(rdev, &tmp); |
222 | return 0; | |
223 | } | |
224 | ||
225 | rdev->ib_pool.sa_manager = tmp; | |
226 | INIT_LIST_HEAD(&rdev->ib_pool.sa_manager.sa_bo); | |
b15ba512 JG |
227 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
228 | rdev->ib_pool.ibs[i].fence = NULL; | |
771fe6b9 JG |
229 | rdev->ib_pool.ibs[i].idx = i; |
230 | rdev->ib_pool.ibs[i].length_dw = 0; | |
b15ba512 | 231 | INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].sa_bo.list); |
771fe6b9 | 232 | } |
91cb91be | 233 | rdev->ib_pool.head_id = 0; |
771fe6b9 JG |
234 | rdev->ib_pool.ready = true; |
235 | DRM_INFO("radeon: ib pool ready.\n"); | |
b15ba512 | 236 | |
771fe6b9 JG |
237 | if (radeon_debugfs_ib_init(rdev)) { |
238 | DRM_ERROR("Failed to register debugfs file for IB !\n"); | |
239 | } | |
9fc04b50 | 240 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
b15ba512 | 241 | return 0; |
771fe6b9 JG |
242 | } |
243 | ||
244 | void radeon_ib_pool_fini(struct radeon_device *rdev) | |
245 | { | |
b15ba512 | 246 | unsigned i; |
4c788679 | 247 | |
9fc04b50 | 248 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
b15ba512 JG |
249 | if (rdev->ib_pool.ready) { |
250 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { | |
251 | radeon_sa_bo_free(rdev, &rdev->ib_pool.ibs[i].sa_bo); | |
252 | radeon_fence_unref(&rdev->ib_pool.ibs[i].fence); | |
4c788679 | 253 | } |
b15ba512 JG |
254 | radeon_sa_bo_manager_fini(rdev, &rdev->ib_pool.sa_manager); |
255 | rdev->ib_pool.ready = false; | |
771fe6b9 | 256 | } |
9fc04b50 | 257 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
771fe6b9 JG |
258 | } |
259 | ||
b15ba512 JG |
260 | int radeon_ib_pool_start(struct radeon_device *rdev) |
261 | { | |
262 | return radeon_sa_bo_manager_start(rdev, &rdev->ib_pool.sa_manager); | |
263 | } | |
264 | ||
265 | int radeon_ib_pool_suspend(struct radeon_device *rdev) | |
266 | { | |
267 | return radeon_sa_bo_manager_suspend(rdev, &rdev->ib_pool.sa_manager); | |
268 | } | |
771fe6b9 | 269 | |
7bd560e8 CK |
270 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
271 | { | |
272 | unsigned i; | |
273 | int r; | |
274 | ||
275 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
276 | struct radeon_ring *ring = &rdev->ring[i]; | |
277 | ||
278 | if (!ring->ready) | |
279 | continue; | |
280 | ||
281 | r = radeon_ib_test(rdev, i, ring); | |
282 | if (r) { | |
283 | ring->ready = false; | |
284 | ||
285 | if (i == RADEON_RING_TYPE_GFX_INDEX) { | |
286 | /* oh, oh, that's really bad */ | |
287 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); | |
288 | rdev->accel_working = false; | |
289 | return r; | |
290 | ||
291 | } else { | |
292 | /* still not good, but we can live with it */ | |
293 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); | |
294 | } | |
295 | } | |
296 | } | |
297 | return 0; | |
298 | } | |
299 | ||
771fe6b9 JG |
300 | /* |
301 | * Ring. | |
302 | */ | |
e32eb50d | 303 | int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *ring) |
bf852799 CK |
304 | { |
305 | /* r1xx-r5xx only has CP ring */ | |
306 | if (rdev->family < CHIP_R600) | |
307 | return RADEON_RING_TYPE_GFX_INDEX; | |
308 | ||
309 | if (rdev->family >= CHIP_CAYMAN) { | |
e32eb50d | 310 | if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]) |
bf852799 | 311 | return CAYMAN_RING_TYPE_CP1_INDEX; |
e32eb50d | 312 | else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]) |
bf852799 CK |
313 | return CAYMAN_RING_TYPE_CP2_INDEX; |
314 | } | |
315 | return RADEON_RING_TYPE_GFX_INDEX; | |
316 | } | |
317 | ||
e32eb50d | 318 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 319 | { |
78c5560a AD |
320 | u32 rptr; |
321 | ||
724c80e1 | 322 | if (rdev->wb.enabled) |
78c5560a | 323 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
5596a9db | 324 | else |
78c5560a AD |
325 | rptr = RREG32(ring->rptr_reg); |
326 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; | |
771fe6b9 | 327 | /* This works because ring_size is a power of 2 */ |
e32eb50d CK |
328 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
329 | ring->ring_free_dw -= ring->wptr; | |
330 | ring->ring_free_dw &= ring->ptr_mask; | |
331 | if (!ring->ring_free_dw) { | |
332 | ring->ring_free_dw = ring->ring_size / 4; | |
771fe6b9 JG |
333 | } |
334 | } | |
335 | ||
7b1f2485 | 336 | |
e32eb50d | 337 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
771fe6b9 JG |
338 | { |
339 | int r; | |
340 | ||
341 | /* Align requested size with padding so unlock_commit can | |
342 | * pad safely */ | |
e32eb50d CK |
343 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
344 | while (ndw > (ring->ring_free_dw - 1)) { | |
345 | radeon_ring_free_size(rdev, ring); | |
346 | if (ndw < ring->ring_free_dw) { | |
771fe6b9 JG |
347 | break; |
348 | } | |
e32eb50d | 349 | r = radeon_fence_wait_next(rdev, radeon_ring_index(rdev, ring)); |
91700f3c | 350 | if (r) |
771fe6b9 | 351 | return r; |
771fe6b9 | 352 | } |
e32eb50d CK |
353 | ring->count_dw = ndw; |
354 | ring->wptr_old = ring->wptr; | |
771fe6b9 JG |
355 | return 0; |
356 | } | |
357 | ||
e32eb50d | 358 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
91700f3c MG |
359 | { |
360 | int r; | |
361 | ||
e32eb50d CK |
362 | mutex_lock(&ring->mutex); |
363 | r = radeon_ring_alloc(rdev, ring, ndw); | |
91700f3c | 364 | if (r) { |
e32eb50d | 365 | mutex_unlock(&ring->mutex); |
91700f3c MG |
366 | return r; |
367 | } | |
368 | return 0; | |
369 | } | |
370 | ||
e32eb50d | 371 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 JG |
372 | { |
373 | unsigned count_dw_pad; | |
374 | unsigned i; | |
375 | ||
376 | /* We pad to match fetch size */ | |
e32eb50d CK |
377 | count_dw_pad = (ring->align_mask + 1) - |
378 | (ring->wptr & ring->align_mask); | |
771fe6b9 | 379 | for (i = 0; i < count_dw_pad; i++) { |
78c5560a | 380 | radeon_ring_write(ring, ring->nop); |
771fe6b9 JG |
381 | } |
382 | DRM_MEMORYBARRIER(); | |
78c5560a | 383 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
e32eb50d | 384 | (void)RREG32(ring->wptr_reg); |
91700f3c MG |
385 | } |
386 | ||
e32eb50d | 387 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
91700f3c | 388 | { |
e32eb50d CK |
389 | radeon_ring_commit(rdev, ring); |
390 | mutex_unlock(&ring->mutex); | |
771fe6b9 JG |
391 | } |
392 | ||
e32eb50d | 393 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 394 | { |
e32eb50d CK |
395 | ring->wptr = ring->wptr_old; |
396 | mutex_unlock(&ring->mutex); | |
771fe6b9 JG |
397 | } |
398 | ||
e32eb50d | 399 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
78c5560a AD |
400 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
401 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) | |
771fe6b9 JG |
402 | { |
403 | int r; | |
404 | ||
e32eb50d CK |
405 | ring->ring_size = ring_size; |
406 | ring->rptr_offs = rptr_offs; | |
407 | ring->rptr_reg = rptr_reg; | |
408 | ring->wptr_reg = wptr_reg; | |
78c5560a AD |
409 | ring->ptr_reg_shift = ptr_reg_shift; |
410 | ring->ptr_reg_mask = ptr_reg_mask; | |
411 | ring->nop = nop; | |
771fe6b9 | 412 | /* Allocate ring buffer */ |
e32eb50d CK |
413 | if (ring->ring_obj == NULL) { |
414 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, | |
4c788679 | 415 | RADEON_GEM_DOMAIN_GTT, |
e32eb50d | 416 | &ring->ring_obj); |
771fe6b9 | 417 | if (r) { |
4c788679 | 418 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
771fe6b9 JG |
419 | return r; |
420 | } | |
e32eb50d | 421 | r = radeon_bo_reserve(ring->ring_obj, false); |
4c788679 JG |
422 | if (unlikely(r != 0)) |
423 | return r; | |
e32eb50d CK |
424 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
425 | &ring->gpu_addr); | |
771fe6b9 | 426 | if (r) { |
e32eb50d | 427 | radeon_bo_unreserve(ring->ring_obj); |
4c788679 | 428 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
771fe6b9 JG |
429 | return r; |
430 | } | |
e32eb50d CK |
431 | r = radeon_bo_kmap(ring->ring_obj, |
432 | (void **)&ring->ring); | |
433 | radeon_bo_unreserve(ring->ring_obj); | |
771fe6b9 | 434 | if (r) { |
4c788679 | 435 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
771fe6b9 JG |
436 | return r; |
437 | } | |
438 | } | |
e32eb50d CK |
439 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
440 | ring->ring_free_dw = ring->ring_size / 4; | |
ec1a6cce CK |
441 | if (radeon_debugfs_ring_init(rdev, ring)) { |
442 | DRM_ERROR("Failed to register debugfs file for rings !\n"); | |
443 | } | |
771fe6b9 JG |
444 | return 0; |
445 | } | |
446 | ||
e32eb50d | 447 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 448 | { |
4c788679 | 449 | int r; |
ca2af923 | 450 | struct radeon_bo *ring_obj; |
4c788679 | 451 | |
e32eb50d CK |
452 | mutex_lock(&ring->mutex); |
453 | ring_obj = ring->ring_obj; | |
454 | ring->ring = NULL; | |
455 | ring->ring_obj = NULL; | |
456 | mutex_unlock(&ring->mutex); | |
ca2af923 AD |
457 | |
458 | if (ring_obj) { | |
459 | r = radeon_bo_reserve(ring_obj, false); | |
4c788679 | 460 | if (likely(r == 0)) { |
ca2af923 AD |
461 | radeon_bo_kunmap(ring_obj); |
462 | radeon_bo_unpin(ring_obj); | |
463 | radeon_bo_unreserve(ring_obj); | |
4c788679 | 464 | } |
ca2af923 | 465 | radeon_bo_unref(&ring_obj); |
771fe6b9 | 466 | } |
771fe6b9 JG |
467 | } |
468 | ||
771fe6b9 JG |
469 | /* |
470 | * Debugfs info | |
471 | */ | |
472 | #if defined(CONFIG_DEBUG_FS) | |
af9720f4 CK |
473 | |
474 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) | |
475 | { | |
476 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
477 | struct drm_device *dev = node->minor->dev; | |
478 | struct radeon_device *rdev = dev->dev_private; | |
479 | int ridx = *(int*)node->info_ent->data; | |
480 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
481 | unsigned count, i, j; | |
482 | ||
483 | radeon_ring_free_size(rdev, ring); | |
484 | count = (ring->ring_size / 4) - ring->ring_free_dw; | |
485 | seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg)); | |
486 | seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg)); | |
487 | seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr); | |
488 | seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr); | |
489 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); | |
490 | seq_printf(m, "%u dwords in ring\n", count); | |
491 | i = ring->rptr; | |
492 | for (j = 0; j <= count; j++) { | |
493 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); | |
494 | i = (i + 1) & ring->ptr_mask; | |
495 | } | |
496 | return 0; | |
497 | } | |
498 | ||
499 | static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; | |
500 | static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; | |
501 | static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; | |
502 | ||
503 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { | |
504 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, | |
505 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, | |
506 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, | |
507 | }; | |
508 | ||
771fe6b9 JG |
509 | static int radeon_debugfs_ib_info(struct seq_file *m, void *data) |
510 | { | |
511 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
293f9fd5 CK |
512 | struct drm_device *dev = node->minor->dev; |
513 | struct radeon_device *rdev = dev->dev_private; | |
514 | struct radeon_ib *ib = &rdev->ib_pool.ibs[*((unsigned*)node->info_ent->data)]; | |
771fe6b9 JG |
515 | unsigned i; |
516 | ||
517 | if (ib == NULL) { | |
518 | return 0; | |
519 | } | |
91cb91be | 520 | seq_printf(m, "IB %04u\n", ib->idx); |
771fe6b9 JG |
521 | seq_printf(m, "IB fence %p\n", ib->fence); |
522 | seq_printf(m, "IB size %05u dwords\n", ib->length_dw); | |
523 | for (i = 0; i < ib->length_dw; i++) { | |
524 | seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); | |
525 | } | |
526 | return 0; | |
527 | } | |
528 | ||
529 | static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; | |
530 | static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; | |
293f9fd5 | 531 | static unsigned radeon_debugfs_ib_idx[RADEON_IB_POOL_SIZE]; |
771fe6b9 JG |
532 | #endif |
533 | ||
ec1a6cce | 534 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
af9720f4 CK |
535 | { |
536 | #if defined(CONFIG_DEBUG_FS) | |
ec1a6cce CK |
537 | unsigned i; |
538 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { | |
539 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; | |
540 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; | |
541 | unsigned r; | |
542 | ||
543 | if (&rdev->ring[ridx] != ring) | |
544 | continue; | |
545 | ||
546 | r = radeon_debugfs_add_files(rdev, info, 1); | |
547 | if (r) | |
548 | return r; | |
549 | } | |
af9720f4 | 550 | #endif |
ec1a6cce | 551 | return 0; |
af9720f4 CK |
552 | } |
553 | ||
771fe6b9 JG |
554 | int radeon_debugfs_ib_init(struct radeon_device *rdev) |
555 | { | |
556 | #if defined(CONFIG_DEBUG_FS) | |
557 | unsigned i; | |
558 | ||
559 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { | |
560 | sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); | |
293f9fd5 | 561 | radeon_debugfs_ib_idx[i] = i; |
771fe6b9 JG |
562 | radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; |
563 | radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info; | |
564 | radeon_debugfs_ib_list[i].driver_features = 0; | |
293f9fd5 | 565 | radeon_debugfs_ib_list[i].data = &radeon_debugfs_ib_idx[i]; |
771fe6b9 JG |
566 | } |
567 | return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, | |
568 | RADEON_IB_POOL_SIZE); | |
569 | #else | |
570 | return 0; | |
571 | #endif | |
572 | } |