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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
771fe6b9 JG |
30 | #include "drmP.h" |
31 | #include "radeon_drm.h" | |
32 | #include "radeon_reg.h" | |
33 | #include "radeon.h" | |
34 | #include "atom.h" | |
35 | ||
36 | int radeon_debugfs_ib_init(struct radeon_device *rdev); | |
ec1a6cce | 37 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
771fe6b9 | 38 | |
ce580fab AK |
39 | u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
40 | { | |
41 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
42 | u32 pg_idx, pg_offset; | |
43 | u32 idx_value = 0; | |
44 | int new_page; | |
45 | ||
46 | pg_idx = (idx * 4) / PAGE_SIZE; | |
47 | pg_offset = (idx * 4) % PAGE_SIZE; | |
48 | ||
49 | if (ibc->kpage_idx[0] == pg_idx) | |
50 | return ibc->kpage[0][pg_offset/4]; | |
51 | if (ibc->kpage_idx[1] == pg_idx) | |
52 | return ibc->kpage[1][pg_offset/4]; | |
53 | ||
54 | new_page = radeon_cs_update_pages(p, pg_idx); | |
55 | if (new_page < 0) { | |
56 | p->parser_error = new_page; | |
57 | return 0; | |
58 | } | |
59 | ||
60 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
61 | return idx_value; | |
62 | } | |
63 | ||
e32eb50d | 64 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
ce580fab AK |
65 | { |
66 | #if DRM_DEBUG_CODE | |
e32eb50d | 67 | if (ring->count_dw <= 0) { |
ce580fab AK |
68 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
69 | } | |
70 | #endif | |
e32eb50d CK |
71 | ring->ring[ring->wptr++] = v; |
72 | ring->wptr &= ring->ptr_mask; | |
73 | ring->count_dw--; | |
74 | ring->ring_free_dw--; | |
ce580fab AK |
75 | } |
76 | ||
b15ba512 JG |
77 | /* |
78 | * IB. | |
79 | */ | |
c1341e52 | 80 | bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib) |
9f93ed39 | 81 | { |
b15ba512 JG |
82 | bool done = false; |
83 | ||
84 | /* only free ib which have been emited */ | |
bb635567 | 85 | if (ib->fence && ib->fence->seq < RADEON_FENCE_NOTEMITED_SEQ) { |
b15ba512 JG |
86 | if (radeon_fence_signaled(ib->fence)) { |
87 | radeon_fence_unref(&ib->fence); | |
557017a0 | 88 | radeon_sa_bo_free(rdev, &ib->sa_bo, NULL); |
b15ba512 JG |
89 | done = true; |
90 | } | |
9f93ed39 | 91 | } |
b15ba512 | 92 | return done; |
9f93ed39 JG |
93 | } |
94 | ||
69e130a6 JG |
95 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
96 | struct radeon_ib **ib, unsigned size) | |
771fe6b9 JG |
97 | { |
98 | struct radeon_fence *fence; | |
b15ba512 JG |
99 | unsigned cretry = 0; |
100 | int r = 0, i, idx; | |
771fe6b9 JG |
101 | |
102 | *ib = NULL; | |
69e130a6 JG |
103 | /* align size on 256 bytes */ |
104 | size = ALIGN(size, 256); | |
b15ba512 | 105 | |
7b1f2485 | 106 | r = radeon_fence_create(rdev, &fence, ring); |
771fe6b9 | 107 | if (r) { |
91cb91be | 108 | dev_err(rdev->dev, "failed to create fence for new IB\n"); |
771fe6b9 JG |
109 | return r; |
110 | } | |
b15ba512 | 111 | |
9fc04b50 | 112 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
b15ba512 JG |
113 | idx = rdev->ib_pool.head_id; |
114 | retry: | |
115 | if (cretry > 5) { | |
116 | dev_err(rdev->dev, "failed to get an ib after 5 retry\n"); | |
9fc04b50 | 117 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
91cb91be | 118 | radeon_fence_unref(&fence); |
b15ba512 | 119 | return -ENOMEM; |
771fe6b9 | 120 | } |
b15ba512 JG |
121 | cretry++; |
122 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { | |
123 | radeon_ib_try_free(rdev, &rdev->ib_pool.ibs[idx]); | |
124 | if (rdev->ib_pool.ibs[idx].fence == NULL) { | |
125 | r = radeon_sa_bo_new(rdev, &rdev->ib_pool.sa_manager, | |
126 | &rdev->ib_pool.ibs[idx].sa_bo, | |
557017a0 | 127 | size, 256, false); |
b15ba512 JG |
128 | if (!r) { |
129 | *ib = &rdev->ib_pool.ibs[idx]; | |
2e0d9910 CK |
130 | (*ib)->ptr = radeon_sa_bo_cpu_addr((*ib)->sa_bo); |
131 | (*ib)->gpu_addr = radeon_sa_bo_gpu_addr((*ib)->sa_bo); | |
b15ba512 | 132 | (*ib)->fence = fence; |
721604a1 | 133 | (*ib)->vm_id = 0; |
dfcf5f36 | 134 | (*ib)->is_const_ib = false; |
b15ba512 JG |
135 | /* ib are most likely to be allocated in a ring fashion |
136 | * thus rdev->ib_pool.head_id should be the id of the | |
137 | * oldest ib | |
138 | */ | |
139 | rdev->ib_pool.head_id = (1 + idx); | |
140 | rdev->ib_pool.head_id &= (RADEON_IB_POOL_SIZE - 1); | |
9fc04b50 | 141 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
b15ba512 JG |
142 | return 0; |
143 | } | |
91cb91be | 144 | } |
b15ba512 JG |
145 | idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1); |
146 | } | |
147 | /* this should be rare event, ie all ib scheduled none signaled yet. | |
148 | */ | |
149 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { | |
bb635567 JG |
150 | struct radeon_fence *fence = rdev->ib_pool.ibs[idx].fence; |
151 | if (fence && fence->seq < RADEON_FENCE_NOTEMITED_SEQ) { | |
152 | r = radeon_fence_wait(fence, false); | |
b15ba512 JG |
153 | if (!r) { |
154 | goto retry; | |
155 | } | |
156 | /* an error happened */ | |
157 | break; | |
158 | } | |
159 | idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1); | |
771fe6b9 | 160 | } |
9fc04b50 | 161 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
b15ba512 JG |
162 | radeon_fence_unref(&fence); |
163 | return r; | |
771fe6b9 JG |
164 | } |
165 | ||
166 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) | |
167 | { | |
168 | struct radeon_ib *tmp = *ib; | |
169 | ||
170 | *ib = NULL; | |
171 | if (tmp == NULL) { | |
172 | return; | |
173 | } | |
9fc04b50 | 174 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
bb635567 | 175 | if (tmp->fence && tmp->fence->seq == RADEON_FENCE_NOTEMITED_SEQ) { |
557017a0 | 176 | radeon_sa_bo_free(rdev, &tmp->sa_bo, NULL); |
b15ba512 JG |
177 | radeon_fence_unref(&tmp->fence); |
178 | } | |
9fc04b50 | 179 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
771fe6b9 JG |
180 | } |
181 | ||
771fe6b9 JG |
182 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) |
183 | { | |
e32eb50d | 184 | struct radeon_ring *ring = &rdev->ring[ib->fence->ring]; |
771fe6b9 JG |
185 | int r = 0; |
186 | ||
e32eb50d | 187 | if (!ib->length_dw || !ring->ready) { |
771fe6b9 | 188 | /* TODO: Nothings in the ib we should report. */ |
91cb91be | 189 | DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx); |
771fe6b9 JG |
190 | return -EINVAL; |
191 | } | |
ecb114a1 | 192 | |
6cdf6585 | 193 | /* 64 dwords should be enough for fence too */ |
e32eb50d | 194 | r = radeon_ring_lock(rdev, ring, 64); |
771fe6b9 | 195 | if (r) { |
ec4f2ac4 | 196 | DRM_ERROR("radeon: scheduling IB failed (%d).\n", r); |
771fe6b9 JG |
197 | return r; |
198 | } | |
4c87bc26 | 199 | radeon_ring_ib_execute(rdev, ib->fence->ring, ib); |
771fe6b9 | 200 | radeon_fence_emit(rdev, ib->fence); |
e32eb50d | 201 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
202 | return 0; |
203 | } | |
204 | ||
205 | int radeon_ib_pool_init(struct radeon_device *rdev) | |
206 | { | |
b15ba512 | 207 | int i, r; |
771fe6b9 | 208 | |
9fc04b50 | 209 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
d54fbd49 | 210 | if (rdev->ib_pool.ready) { |
9fc04b50 | 211 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
d54fbd49 JG |
212 | return 0; |
213 | } | |
214 | ||
c3b7fe8b CK |
215 | r = radeon_sa_bo_manager_init(rdev, &rdev->ib_pool.sa_manager, |
216 | RADEON_IB_POOL_SIZE*64*1024, | |
217 | RADEON_GEM_DOMAIN_GTT); | |
218 | if (r) { | |
219 | radeon_mutex_unlock(&rdev->ib_pool.mutex); | |
220 | return r; | |
221 | } | |
222 | ||
b15ba512 JG |
223 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
224 | rdev->ib_pool.ibs[i].fence = NULL; | |
771fe6b9 JG |
225 | rdev->ib_pool.ibs[i].idx = i; |
226 | rdev->ib_pool.ibs[i].length_dw = 0; | |
2e0d9910 | 227 | rdev->ib_pool.ibs[i].sa_bo = NULL; |
771fe6b9 | 228 | } |
91cb91be | 229 | rdev->ib_pool.head_id = 0; |
771fe6b9 JG |
230 | rdev->ib_pool.ready = true; |
231 | DRM_INFO("radeon: ib pool ready.\n"); | |
b15ba512 | 232 | |
771fe6b9 JG |
233 | if (radeon_debugfs_ib_init(rdev)) { |
234 | DRM_ERROR("Failed to register debugfs file for IB !\n"); | |
235 | } | |
9fc04b50 | 236 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
b15ba512 | 237 | return 0; |
771fe6b9 JG |
238 | } |
239 | ||
240 | void radeon_ib_pool_fini(struct radeon_device *rdev) | |
241 | { | |
b15ba512 | 242 | unsigned i; |
4c788679 | 243 | |
9fc04b50 | 244 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
b15ba512 JG |
245 | if (rdev->ib_pool.ready) { |
246 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { | |
557017a0 | 247 | radeon_sa_bo_free(rdev, &rdev->ib_pool.ibs[i].sa_bo, NULL); |
b15ba512 | 248 | radeon_fence_unref(&rdev->ib_pool.ibs[i].fence); |
4c788679 | 249 | } |
b15ba512 JG |
250 | radeon_sa_bo_manager_fini(rdev, &rdev->ib_pool.sa_manager); |
251 | rdev->ib_pool.ready = false; | |
771fe6b9 | 252 | } |
9fc04b50 | 253 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
771fe6b9 JG |
254 | } |
255 | ||
b15ba512 JG |
256 | int radeon_ib_pool_start(struct radeon_device *rdev) |
257 | { | |
258 | return radeon_sa_bo_manager_start(rdev, &rdev->ib_pool.sa_manager); | |
259 | } | |
260 | ||
261 | int radeon_ib_pool_suspend(struct radeon_device *rdev) | |
262 | { | |
263 | return radeon_sa_bo_manager_suspend(rdev, &rdev->ib_pool.sa_manager); | |
264 | } | |
771fe6b9 | 265 | |
7bd560e8 CK |
266 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
267 | { | |
268 | unsigned i; | |
269 | int r; | |
270 | ||
271 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
272 | struct radeon_ring *ring = &rdev->ring[i]; | |
273 | ||
274 | if (!ring->ready) | |
275 | continue; | |
276 | ||
277 | r = radeon_ib_test(rdev, i, ring); | |
278 | if (r) { | |
279 | ring->ready = false; | |
280 | ||
281 | if (i == RADEON_RING_TYPE_GFX_INDEX) { | |
282 | /* oh, oh, that's really bad */ | |
283 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); | |
284 | rdev->accel_working = false; | |
285 | return r; | |
286 | ||
287 | } else { | |
288 | /* still not good, but we can live with it */ | |
289 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); | |
290 | } | |
291 | } | |
292 | } | |
293 | return 0; | |
294 | } | |
295 | ||
771fe6b9 JG |
296 | /* |
297 | * Ring. | |
298 | */ | |
e32eb50d | 299 | int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *ring) |
bf852799 CK |
300 | { |
301 | /* r1xx-r5xx only has CP ring */ | |
302 | if (rdev->family < CHIP_R600) | |
303 | return RADEON_RING_TYPE_GFX_INDEX; | |
304 | ||
305 | if (rdev->family >= CHIP_CAYMAN) { | |
e32eb50d | 306 | if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]) |
bf852799 | 307 | return CAYMAN_RING_TYPE_CP1_INDEX; |
e32eb50d | 308 | else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]) |
bf852799 CK |
309 | return CAYMAN_RING_TYPE_CP2_INDEX; |
310 | } | |
311 | return RADEON_RING_TYPE_GFX_INDEX; | |
312 | } | |
313 | ||
e32eb50d | 314 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 315 | { |
78c5560a AD |
316 | u32 rptr; |
317 | ||
724c80e1 | 318 | if (rdev->wb.enabled) |
78c5560a | 319 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
5596a9db | 320 | else |
78c5560a AD |
321 | rptr = RREG32(ring->rptr_reg); |
322 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; | |
771fe6b9 | 323 | /* This works because ring_size is a power of 2 */ |
e32eb50d CK |
324 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
325 | ring->ring_free_dw -= ring->wptr; | |
326 | ring->ring_free_dw &= ring->ptr_mask; | |
327 | if (!ring->ring_free_dw) { | |
328 | ring->ring_free_dw = ring->ring_size / 4; | |
771fe6b9 JG |
329 | } |
330 | } | |
331 | ||
7b1f2485 | 332 | |
e32eb50d | 333 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
771fe6b9 JG |
334 | { |
335 | int r; | |
336 | ||
337 | /* Align requested size with padding so unlock_commit can | |
338 | * pad safely */ | |
e32eb50d CK |
339 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
340 | while (ndw > (ring->ring_free_dw - 1)) { | |
341 | radeon_ring_free_size(rdev, ring); | |
342 | if (ndw < ring->ring_free_dw) { | |
771fe6b9 JG |
343 | break; |
344 | } | |
8a47cc9e | 345 | r = radeon_fence_wait_next_locked(rdev, radeon_ring_index(rdev, ring)); |
91700f3c | 346 | if (r) |
771fe6b9 | 347 | return r; |
771fe6b9 | 348 | } |
e32eb50d CK |
349 | ring->count_dw = ndw; |
350 | ring->wptr_old = ring->wptr; | |
771fe6b9 JG |
351 | return 0; |
352 | } | |
353 | ||
e32eb50d | 354 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
91700f3c MG |
355 | { |
356 | int r; | |
357 | ||
d6999bc7 | 358 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 359 | r = radeon_ring_alloc(rdev, ring, ndw); |
91700f3c | 360 | if (r) { |
d6999bc7 | 361 | mutex_unlock(&rdev->ring_lock); |
91700f3c MG |
362 | return r; |
363 | } | |
364 | return 0; | |
365 | } | |
366 | ||
e32eb50d | 367 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 JG |
368 | { |
369 | unsigned count_dw_pad; | |
370 | unsigned i; | |
371 | ||
372 | /* We pad to match fetch size */ | |
e32eb50d CK |
373 | count_dw_pad = (ring->align_mask + 1) - |
374 | (ring->wptr & ring->align_mask); | |
771fe6b9 | 375 | for (i = 0; i < count_dw_pad; i++) { |
78c5560a | 376 | radeon_ring_write(ring, ring->nop); |
771fe6b9 JG |
377 | } |
378 | DRM_MEMORYBARRIER(); | |
78c5560a | 379 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
e32eb50d | 380 | (void)RREG32(ring->wptr_reg); |
91700f3c MG |
381 | } |
382 | ||
e32eb50d | 383 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
91700f3c | 384 | { |
e32eb50d | 385 | radeon_ring_commit(rdev, ring); |
d6999bc7 | 386 | mutex_unlock(&rdev->ring_lock); |
771fe6b9 JG |
387 | } |
388 | ||
d6999bc7 | 389 | void radeon_ring_undo(struct radeon_ring *ring) |
771fe6b9 | 390 | { |
e32eb50d | 391 | ring->wptr = ring->wptr_old; |
d6999bc7 CK |
392 | } |
393 | ||
394 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) | |
395 | { | |
396 | radeon_ring_undo(ring); | |
397 | mutex_unlock(&rdev->ring_lock); | |
771fe6b9 JG |
398 | } |
399 | ||
7b9ef16b CK |
400 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
401 | { | |
402 | int r; | |
403 | ||
7b9ef16b CK |
404 | radeon_ring_free_size(rdev, ring); |
405 | if (ring->rptr == ring->wptr) { | |
406 | r = radeon_ring_alloc(rdev, ring, 1); | |
407 | if (!r) { | |
408 | radeon_ring_write(ring, ring->nop); | |
409 | radeon_ring_commit(rdev, ring); | |
410 | } | |
411 | } | |
7b9ef16b CK |
412 | } |
413 | ||
069211e5 CK |
414 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
415 | { | |
416 | ring->last_rptr = ring->rptr; | |
417 | ring->last_activity = jiffies; | |
418 | } | |
419 | ||
420 | /** | |
421 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information | |
422 | * @rdev: radeon device structure | |
423 | * @ring: radeon_ring structure holding ring information | |
424 | * | |
425 | * We don't need to initialize the lockup tracking information as we will either | |
426 | * have CP rptr to a different value of jiffies wrap around which will force | |
427 | * initialization of the lockup tracking informations. | |
428 | * | |
429 | * A possible false positivie is if we get call after while and last_cp_rptr == | |
430 | * the current CP rptr, even if it's unlikely it might happen. To avoid this | |
431 | * if the elapsed time since last call is bigger than 2 second than we return | |
432 | * false and update the tracking information. Due to this the caller must call | |
433 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported | |
434 | * the fencing code should be cautious about that. | |
435 | * | |
436 | * Caller should write to the ring to force CP to do something so we don't get | |
437 | * false positive when CP is just gived nothing to do. | |
438 | * | |
439 | **/ | |
440 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
441 | { | |
442 | unsigned long cjiffies, elapsed; | |
443 | uint32_t rptr; | |
444 | ||
445 | cjiffies = jiffies; | |
446 | if (!time_after(cjiffies, ring->last_activity)) { | |
447 | /* likely a wrap around */ | |
448 | radeon_ring_lockup_update(ring); | |
449 | return false; | |
450 | } | |
451 | rptr = RREG32(ring->rptr_reg); | |
452 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; | |
453 | if (ring->rptr != ring->last_rptr) { | |
454 | /* CP is still working no lockup */ | |
455 | radeon_ring_lockup_update(ring); | |
456 | return false; | |
457 | } | |
458 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); | |
3368ff0c | 459 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
069211e5 CK |
460 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
461 | return true; | |
462 | } | |
463 | /* give a chance to the GPU ... */ | |
464 | return false; | |
465 | } | |
466 | ||
e32eb50d | 467 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
78c5560a AD |
468 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
469 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) | |
771fe6b9 JG |
470 | { |
471 | int r; | |
472 | ||
e32eb50d CK |
473 | ring->ring_size = ring_size; |
474 | ring->rptr_offs = rptr_offs; | |
475 | ring->rptr_reg = rptr_reg; | |
476 | ring->wptr_reg = wptr_reg; | |
78c5560a AD |
477 | ring->ptr_reg_shift = ptr_reg_shift; |
478 | ring->ptr_reg_mask = ptr_reg_mask; | |
479 | ring->nop = nop; | |
771fe6b9 | 480 | /* Allocate ring buffer */ |
e32eb50d CK |
481 | if (ring->ring_obj == NULL) { |
482 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, | |
4c788679 | 483 | RADEON_GEM_DOMAIN_GTT, |
e32eb50d | 484 | &ring->ring_obj); |
771fe6b9 | 485 | if (r) { |
4c788679 | 486 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
771fe6b9 JG |
487 | return r; |
488 | } | |
e32eb50d | 489 | r = radeon_bo_reserve(ring->ring_obj, false); |
4c788679 JG |
490 | if (unlikely(r != 0)) |
491 | return r; | |
e32eb50d CK |
492 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
493 | &ring->gpu_addr); | |
771fe6b9 | 494 | if (r) { |
e32eb50d | 495 | radeon_bo_unreserve(ring->ring_obj); |
4c788679 | 496 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
771fe6b9 JG |
497 | return r; |
498 | } | |
e32eb50d CK |
499 | r = radeon_bo_kmap(ring->ring_obj, |
500 | (void **)&ring->ring); | |
501 | radeon_bo_unreserve(ring->ring_obj); | |
771fe6b9 | 502 | if (r) { |
4c788679 | 503 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
771fe6b9 JG |
504 | return r; |
505 | } | |
506 | } | |
e32eb50d CK |
507 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
508 | ring->ring_free_dw = ring->ring_size / 4; | |
ec1a6cce CK |
509 | if (radeon_debugfs_ring_init(rdev, ring)) { |
510 | DRM_ERROR("Failed to register debugfs file for rings !\n"); | |
511 | } | |
771fe6b9 JG |
512 | return 0; |
513 | } | |
514 | ||
e32eb50d | 515 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 516 | { |
4c788679 | 517 | int r; |
ca2af923 | 518 | struct radeon_bo *ring_obj; |
4c788679 | 519 | |
d6999bc7 | 520 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 521 | ring_obj = ring->ring_obj; |
d6999bc7 | 522 | ring->ready = false; |
e32eb50d CK |
523 | ring->ring = NULL; |
524 | ring->ring_obj = NULL; | |
d6999bc7 | 525 | mutex_unlock(&rdev->ring_lock); |
ca2af923 AD |
526 | |
527 | if (ring_obj) { | |
528 | r = radeon_bo_reserve(ring_obj, false); | |
4c788679 | 529 | if (likely(r == 0)) { |
ca2af923 AD |
530 | radeon_bo_kunmap(ring_obj); |
531 | radeon_bo_unpin(ring_obj); | |
532 | radeon_bo_unreserve(ring_obj); | |
4c788679 | 533 | } |
ca2af923 | 534 | radeon_bo_unref(&ring_obj); |
771fe6b9 | 535 | } |
771fe6b9 JG |
536 | } |
537 | ||
771fe6b9 JG |
538 | /* |
539 | * Debugfs info | |
540 | */ | |
541 | #if defined(CONFIG_DEBUG_FS) | |
af9720f4 CK |
542 | |
543 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) | |
544 | { | |
545 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
546 | struct drm_device *dev = node->minor->dev; | |
547 | struct radeon_device *rdev = dev->dev_private; | |
548 | int ridx = *(int*)node->info_ent->data; | |
549 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
550 | unsigned count, i, j; | |
551 | ||
552 | radeon_ring_free_size(rdev, ring); | |
553 | count = (ring->ring_size / 4) - ring->ring_free_dw; | |
554 | seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg)); | |
555 | seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg)); | |
556 | seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr); | |
557 | seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr); | |
558 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); | |
559 | seq_printf(m, "%u dwords in ring\n", count); | |
560 | i = ring->rptr; | |
561 | for (j = 0; j <= count; j++) { | |
562 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); | |
563 | i = (i + 1) & ring->ptr_mask; | |
564 | } | |
565 | return 0; | |
566 | } | |
567 | ||
568 | static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; | |
569 | static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; | |
570 | static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; | |
571 | ||
572 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { | |
573 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, | |
574 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, | |
575 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, | |
576 | }; | |
577 | ||
771fe6b9 JG |
578 | static int radeon_debugfs_ib_info(struct seq_file *m, void *data) |
579 | { | |
580 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
293f9fd5 CK |
581 | struct drm_device *dev = node->minor->dev; |
582 | struct radeon_device *rdev = dev->dev_private; | |
583 | struct radeon_ib *ib = &rdev->ib_pool.ibs[*((unsigned*)node->info_ent->data)]; | |
771fe6b9 JG |
584 | unsigned i; |
585 | ||
586 | if (ib == NULL) { | |
587 | return 0; | |
588 | } | |
91cb91be | 589 | seq_printf(m, "IB %04u\n", ib->idx); |
771fe6b9 JG |
590 | seq_printf(m, "IB fence %p\n", ib->fence); |
591 | seq_printf(m, "IB size %05u dwords\n", ib->length_dw); | |
592 | for (i = 0; i < ib->length_dw; i++) { | |
593 | seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); | |
594 | } | |
595 | return 0; | |
596 | } | |
597 | ||
598 | static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; | |
599 | static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; | |
293f9fd5 | 600 | static unsigned radeon_debugfs_ib_idx[RADEON_IB_POOL_SIZE]; |
711a9729 CK |
601 | |
602 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) | |
603 | { | |
604 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
605 | struct drm_device *dev = node->minor->dev; | |
606 | struct radeon_device *rdev = dev->dev_private; | |
607 | ||
608 | radeon_sa_bo_dump_debug_info(&rdev->ib_pool.sa_manager, m); | |
609 | ||
610 | return 0; | |
611 | ||
612 | } | |
613 | ||
614 | static struct drm_info_list radeon_debugfs_sa_list[] = { | |
615 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, | |
616 | }; | |
617 | ||
771fe6b9 JG |
618 | #endif |
619 | ||
ec1a6cce | 620 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
af9720f4 CK |
621 | { |
622 | #if defined(CONFIG_DEBUG_FS) | |
ec1a6cce CK |
623 | unsigned i; |
624 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { | |
625 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; | |
626 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; | |
627 | unsigned r; | |
628 | ||
629 | if (&rdev->ring[ridx] != ring) | |
630 | continue; | |
631 | ||
632 | r = radeon_debugfs_add_files(rdev, info, 1); | |
633 | if (r) | |
634 | return r; | |
635 | } | |
af9720f4 | 636 | #endif |
ec1a6cce | 637 | return 0; |
af9720f4 CK |
638 | } |
639 | ||
771fe6b9 JG |
640 | int radeon_debugfs_ib_init(struct radeon_device *rdev) |
641 | { | |
642 | #if defined(CONFIG_DEBUG_FS) | |
643 | unsigned i; | |
711a9729 CK |
644 | int r; |
645 | ||
646 | r = radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); | |
647 | if (r) | |
648 | return r; | |
771fe6b9 JG |
649 | |
650 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { | |
651 | sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); | |
293f9fd5 | 652 | radeon_debugfs_ib_idx[i] = i; |
771fe6b9 JG |
653 | radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; |
654 | radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info; | |
655 | radeon_debugfs_ib_list[i].driver_features = 0; | |
293f9fd5 | 656 | radeon_debugfs_ib_list[i].data = &radeon_debugfs_ib_idx[i]; |
771fe6b9 JG |
657 | } |
658 | return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, | |
659 | RADEON_IB_POOL_SIZE); | |
660 | #else | |
661 | return 0; | |
662 | #endif | |
663 | } |