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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
f9183127 SR |
32 | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/pagemap.h> | |
2ef79416 | 35 | #include <linux/pci.h> |
f9183127 SR |
36 | #include <linux/seq_file.h> |
37 | #include <linux/slab.h> | |
38 | #include <linux/swap.h> | |
39 | #include <linux/swiotlb.h> | |
40 | ||
41 | #include <drm/drm_agpsupport.h> | |
42 | #include <drm/drm_debugfs.h> | |
43 | #include <drm/drm_device.h> | |
44 | #include <drm/drm_file.h> | |
f9183127 SR |
45 | #include <drm/drm_prime.h> |
46 | #include <drm/radeon_drm.h> | |
64a9dfc4 MY |
47 | #include <drm/ttm/ttm_bo_api.h> |
48 | #include <drm/ttm/ttm_bo_driver.h> | |
64a9dfc4 MY |
49 | #include <drm/ttm/ttm_module.h> |
50 | #include <drm/ttm/ttm_page_alloc.h> | |
f9183127 SR |
51 | #include <drm/ttm/ttm_placement.h> |
52 | ||
771fe6b9 JG |
53 | #include "radeon_reg.h" |
54 | #include "radeon.h" | |
55 | ||
fa8a1238 | 56 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
2014b569 | 57 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); |
fa8a1238 | 58 | |
a0e4a298 | 59 | struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
771fe6b9 JG |
60 | { |
61 | struct radeon_mman *mman; | |
62 | struct radeon_device *rdev; | |
63 | ||
64 | mman = container_of(bdev, struct radeon_mman, bdev); | |
65 | rdev = container_of(mman, struct radeon_device, mman); | |
66 | return rdev; | |
67 | } | |
68 | ||
b0691b34 CK |
69 | static int radeon_ttm_init_vram(struct radeon_device *rdev) |
70 | { | |
37205891 DA |
71 | return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM, |
72 | TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC, | |
73 | TTM_PL_FLAG_WC, false, | |
e33dc182 | 74 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
b0691b34 CK |
75 | } |
76 | ||
77 | static int radeon_ttm_init_gtt(struct radeon_device *rdev) | |
78 | { | |
37205891 | 79 | return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT, |
82dd1809 CK |
80 | TTM_PL_MASK_CACHING, |
81 | TTM_PL_FLAG_CACHED, true, | |
e33dc182 | 82 | rdev->mc.gtt_size >> PAGE_SHIFT); |
771fe6b9 JG |
83 | } |
84 | ||
312ea8da JG |
85 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
86 | struct ttm_placement *placement) | |
771fe6b9 | 87 | { |
46886dbf | 88 | static const struct ttm_place placements = { |
f1217ed0 CK |
89 | .fpfn = 0, |
90 | .lpfn = 0, | |
48e07c23 CK |
91 | .mem_type = TTM_PL_SYSTEM, |
92 | .flags = TTM_PL_MASK_CACHING | |
f1217ed0 CK |
93 | }; |
94 | ||
d03d8589 | 95 | struct radeon_bo *rbo; |
d03d8589 JG |
96 | |
97 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { | |
d03d8589 JG |
98 | placement->placement = &placements; |
99 | placement->busy_placement = &placements; | |
100 | placement->num_placement = 1; | |
101 | placement->num_busy_placement = 1; | |
102 | return; | |
103 | } | |
104 | rbo = container_of(bo, struct radeon_bo, tbo); | |
771fe6b9 | 105 | switch (bo->mem.mem_type) { |
312ea8da | 106 | case TTM_PL_VRAM: |
5e5c21ca | 107 | if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) |
9270eb1b | 108 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
2a85aedd MD |
109 | else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && |
110 | bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { | |
111 | unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
112 | int i; | |
113 | ||
114 | /* Try evicting to the CPU inaccessible part of VRAM | |
115 | * first, but only set GTT as busy placement, so this | |
116 | * BO will be evicted to GTT rather than causing other | |
117 | * BOs to be evicted from VRAM | |
118 | */ | |
119 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | | |
120 | RADEON_GEM_DOMAIN_GTT); | |
121 | rbo->placement.num_busy_placement = 0; | |
122 | for (i = 0; i < rbo->placement.num_placement; i++) { | |
48e07c23 | 123 | if (rbo->placements[i].mem_type == TTM_PL_VRAM) { |
ce4b4f22 MD |
124 | if (rbo->placements[i].fpfn < fpfn) |
125 | rbo->placements[i].fpfn = fpfn; | |
2a85aedd MD |
126 | } else { |
127 | rbo->placement.busy_placement = | |
128 | &rbo->placements[i]; | |
129 | rbo->placement.num_busy_placement = 1; | |
130 | } | |
131 | } | |
132 | } else | |
9270eb1b | 133 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); |
312ea8da JG |
134 | break; |
135 | case TTM_PL_TT: | |
771fe6b9 | 136 | default: |
312ea8da | 137 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
771fe6b9 | 138 | } |
eaa5fd1a | 139 | *placement = rbo->placement; |
771fe6b9 JG |
140 | } |
141 | ||
142 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
143 | { | |
acb46527 | 144 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
a68bb193 | 145 | struct radeon_device *rdev = radeon_get_rdev(bo->bdev); |
acb46527 | 146 | |
a68bb193 | 147 | if (radeon_ttm_tt_has_userptr(rdev, bo->ttm)) |
b5dcec69 | 148 | return -EPERM; |
ce77038f | 149 | return drm_vma_node_verify_access(&rbo->tbo.base.vma_node, |
d9a1f0b4 | 150 | filp->private_data); |
771fe6b9 JG |
151 | } |
152 | ||
771fe6b9 | 153 | static int radeon_move_blit(struct ttm_buffer_object *bo, |
97a875cb | 154 | bool evict, bool no_wait_gpu, |
2966141a DA |
155 | struct ttm_resource *new_mem, |
156 | struct ttm_resource *old_mem) | |
771fe6b9 JG |
157 | { |
158 | struct radeon_device *rdev; | |
159 | uint64_t old_start, new_start; | |
876dc9f3 | 160 | struct radeon_fence *fence; |
57d20a43 | 161 | unsigned num_pages; |
876dc9f3 | 162 | int r, ridx; |
771fe6b9 JG |
163 | |
164 | rdev = radeon_get_rdev(bo->bdev); | |
876dc9f3 | 165 | ridx = radeon_copy_ring_index(rdev); |
13f479b9 CK |
166 | old_start = (u64)old_mem->start << PAGE_SHIFT; |
167 | new_start = (u64)new_mem->start << PAGE_SHIFT; | |
771fe6b9 JG |
168 | |
169 | switch (old_mem->mem_type) { | |
170 | case TTM_PL_VRAM: | |
d594e46a | 171 | old_start += rdev->mc.vram_start; |
771fe6b9 JG |
172 | break; |
173 | case TTM_PL_TT: | |
d594e46a | 174 | old_start += rdev->mc.gtt_start; |
771fe6b9 JG |
175 | break; |
176 | default: | |
177 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
178 | return -EINVAL; | |
179 | } | |
180 | switch (new_mem->mem_type) { | |
181 | case TTM_PL_VRAM: | |
d594e46a | 182 | new_start += rdev->mc.vram_start; |
771fe6b9 JG |
183 | break; |
184 | case TTM_PL_TT: | |
d594e46a | 185 | new_start += rdev->mc.gtt_start; |
771fe6b9 JG |
186 | break; |
187 | default: | |
188 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
189 | return -EINVAL; | |
190 | } | |
876dc9f3 | 191 | if (!rdev->ring[ridx].ready) { |
3000bf39 | 192 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
771fe6b9 JG |
193 | return -EINVAL; |
194 | } | |
003cefe0 AD |
195 | |
196 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); | |
197 | ||
57d20a43 | 198 | num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); |
336ac942 | 199 | fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv); |
57d20a43 CK |
200 | if (IS_ERR(fence)) |
201 | return PTR_ERR(fence); | |
202 | ||
74561cd4 | 203 | r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem); |
771fe6b9 JG |
204 | radeon_fence_unref(&fence); |
205 | return r; | |
206 | } | |
207 | ||
208 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, | |
9d87fa21 | 209 | bool evict, bool interruptible, |
97a875cb | 210 | bool no_wait_gpu, |
2966141a | 211 | struct ttm_resource *new_mem) |
771fe6b9 | 212 | { |
c13c55d6 | 213 | struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; |
2966141a DA |
214 | struct ttm_resource *old_mem = &bo->mem; |
215 | struct ttm_resource tmp_mem; | |
f1217ed0 | 216 | struct ttm_place placements; |
312ea8da | 217 | struct ttm_placement placement; |
771fe6b9 JG |
218 | int r; |
219 | ||
771fe6b9 JG |
220 | tmp_mem = *new_mem; |
221 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
222 | placement.num_placement = 1; |
223 | placement.placement = &placements; | |
224 | placement.num_busy_placement = 1; | |
225 | placement.busy_placement = &placements; | |
f1217ed0 CK |
226 | placements.fpfn = 0; |
227 | placements.lpfn = 0; | |
48e07c23 CK |
228 | placements.mem_type = TTM_PL_TT; |
229 | placements.flags = TTM_PL_MASK_CACHING; | |
c13c55d6 | 230 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); |
771fe6b9 JG |
231 | if (unlikely(r)) { |
232 | return r; | |
233 | } | |
df67bed9 DA |
234 | |
235 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); | |
236 | if (unlikely(r)) { | |
237 | goto out_cleanup; | |
238 | } | |
239 | ||
0a667b50 | 240 | r = ttm_tt_bind(bo->bdev, bo->ttm, &tmp_mem, &ctx); |
771fe6b9 JG |
241 | if (unlikely(r)) { |
242 | goto out_cleanup; | |
243 | } | |
97a875cb | 244 | r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); |
771fe6b9 JG |
245 | if (unlikely(r)) { |
246 | goto out_cleanup; | |
247 | } | |
3e98d829 | 248 | r = ttm_bo_move_ttm(bo, &ctx, new_mem); |
771fe6b9 | 249 | out_cleanup: |
b2458726 | 250 | ttm_resource_free(bo, &tmp_mem); |
771fe6b9 JG |
251 | return r; |
252 | } | |
253 | ||
254 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, | |
9d87fa21 | 255 | bool evict, bool interruptible, |
97a875cb | 256 | bool no_wait_gpu, |
2966141a | 257 | struct ttm_resource *new_mem) |
771fe6b9 | 258 | { |
c13c55d6 | 259 | struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; |
2966141a DA |
260 | struct ttm_resource *old_mem = &bo->mem; |
261 | struct ttm_resource tmp_mem; | |
312ea8da | 262 | struct ttm_placement placement; |
f1217ed0 | 263 | struct ttm_place placements; |
771fe6b9 JG |
264 | int r; |
265 | ||
771fe6b9 JG |
266 | tmp_mem = *new_mem; |
267 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
268 | placement.num_placement = 1; |
269 | placement.placement = &placements; | |
270 | placement.num_busy_placement = 1; | |
271 | placement.busy_placement = &placements; | |
f1217ed0 CK |
272 | placements.fpfn = 0; |
273 | placements.lpfn = 0; | |
48e07c23 CK |
274 | placements.mem_type = TTM_PL_TT; |
275 | placements.flags = TTM_PL_MASK_CACHING; | |
c13c55d6 | 276 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); |
771fe6b9 JG |
277 | if (unlikely(r)) { |
278 | return r; | |
279 | } | |
3e98d829 | 280 | r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem); |
771fe6b9 JG |
281 | if (unlikely(r)) { |
282 | goto out_cleanup; | |
283 | } | |
97a875cb | 284 | r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); |
771fe6b9 JG |
285 | if (unlikely(r)) { |
286 | goto out_cleanup; | |
287 | } | |
288 | out_cleanup: | |
b2458726 | 289 | ttm_resource_free(bo, &tmp_mem); |
771fe6b9 JG |
290 | return r; |
291 | } | |
292 | ||
2823f4f0 CK |
293 | static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, |
294 | struct ttm_operation_ctx *ctx, | |
2966141a | 295 | struct ttm_resource *new_mem) |
771fe6b9 JG |
296 | { |
297 | struct radeon_device *rdev; | |
e1a575ad | 298 | struct radeon_bo *rbo; |
2966141a | 299 | struct ttm_resource *old_mem = &bo->mem; |
771fe6b9 JG |
300 | int r; |
301 | ||
2823f4f0 | 302 | r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); |
88932a7b CK |
303 | if (r) |
304 | return r; | |
305 | ||
e1a575ad MD |
306 | /* Can't move a pinned BO */ |
307 | rbo = container_of(bo, struct radeon_bo, tbo); | |
308 | if (WARN_ON_ONCE(rbo->pin_count > 0)) | |
309 | return -EINVAL; | |
310 | ||
771fe6b9 JG |
311 | rdev = radeon_get_rdev(bo->bdev); |
312 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { | |
ecfe6953 | 313 | ttm_bo_move_null(bo, new_mem); |
771fe6b9 JG |
314 | return 0; |
315 | } | |
316 | if ((old_mem->mem_type == TTM_PL_TT && | |
317 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
318 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
319 | new_mem->mem_type == TTM_PL_TT)) { | |
af901ca1 | 320 | /* bind is enough */ |
ecfe6953 | 321 | ttm_bo_move_null(bo, new_mem); |
771fe6b9 JG |
322 | return 0; |
323 | } | |
27cd7769 AD |
324 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || |
325 | rdev->asic->copy.copy == NULL) { | |
771fe6b9 | 326 | /* use memcpy */ |
1ab2e105 | 327 | goto memcpy; |
771fe6b9 JG |
328 | } |
329 | ||
330 | if (old_mem->mem_type == TTM_PL_VRAM && | |
331 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
2823f4f0 CK |
332 | r = radeon_move_vram_ram(bo, evict, ctx->interruptible, |
333 | ctx->no_wait_gpu, new_mem); | |
771fe6b9 JG |
334 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
335 | new_mem->mem_type == TTM_PL_VRAM) { | |
2823f4f0 CK |
336 | r = radeon_move_ram_vram(bo, evict, ctx->interruptible, |
337 | ctx->no_wait_gpu, new_mem); | |
771fe6b9 | 338 | } else { |
2823f4f0 CK |
339 | r = radeon_move_blit(bo, evict, ctx->no_wait_gpu, |
340 | new_mem, old_mem); | |
771fe6b9 | 341 | } |
1ab2e105 MD |
342 | |
343 | if (r) { | |
344 | memcpy: | |
3e98d829 | 345 | r = ttm_bo_move_memcpy(bo, ctx, new_mem); |
67e8e3f9 MO |
346 | if (r) { |
347 | return r; | |
348 | } | |
1ab2e105 | 349 | } |
67e8e3f9 MO |
350 | |
351 | /* update statistics */ | |
352 | atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); | |
353 | return 0; | |
771fe6b9 JG |
354 | } |
355 | ||
2966141a | 356 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem) |
0a2d50e3 | 357 | { |
0a2d50e3 | 358 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
ebb21aa1 | 359 | size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; |
0a2d50e3 | 360 | |
0a2d50e3 JG |
361 | switch (mem->mem_type) { |
362 | case TTM_PL_SYSTEM: | |
363 | /* system memory */ | |
364 | return 0; | |
365 | case TTM_PL_TT: | |
a7fb8a23 | 366 | #if IS_ENABLED(CONFIG_AGP) |
0a2d50e3 JG |
367 | if (rdev->flags & RADEON_IS_AGP) { |
368 | /* RADEON_IS_AGP is set only if AGP is active */ | |
54d04ea8 CK |
369 | mem->bus.offset = (mem->start << PAGE_SHIFT) + |
370 | rdev->mc.agp_base; | |
365048ff | 371 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
0a2d50e3 JG |
372 | } |
373 | #endif | |
374 | break; | |
375 | case TTM_PL_VRAM: | |
d961db75 | 376 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 | 377 | /* check if it's visible */ |
ebb21aa1 | 378 | if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size) |
0a2d50e3 | 379 | return -EINVAL; |
54d04ea8 | 380 | mem->bus.offset += rdev->mc.aper_base; |
0a2d50e3 | 381 | mem->bus.is_iomem = true; |
ffb57c4b JE |
382 | #ifdef __alpha__ |
383 | /* | |
384 | * Alpha: use bus.addr to hold the ioremap() return, | |
385 | * so we can modify bus.base below. | |
386 | */ | |
387 | if (mem->placement & TTM_PL_FLAG_WC) | |
388 | mem->bus.addr = | |
54d04ea8 | 389 | ioremap_wc(mem->bus.offset, bus_size); |
ffb57c4b JE |
390 | else |
391 | mem->bus.addr = | |
54d04ea8 | 392 | ioremap(mem->bus.offset, bus_size); |
3b2c6932 AY |
393 | if (!mem->bus.addr) |
394 | return -ENOMEM; | |
ffb57c4b JE |
395 | |
396 | /* | |
397 | * Alpha: Use just the bus offset plus | |
398 | * the hose/domain memory base for bus.base. | |
399 | * It then can be used to build PTEs for VRAM | |
400 | * access, as done in ttm_bo_vm_fault(). | |
401 | */ | |
54d04ea8 | 402 | mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) + |
ffb57c4b JE |
403 | rdev->ddev->hose->dense_mem_base; |
404 | #endif | |
0a2d50e3 JG |
405 | break; |
406 | default: | |
407 | return -EINVAL; | |
408 | } | |
409 | return 0; | |
410 | } | |
411 | ||
649bf3ca JG |
412 | /* |
413 | * TTM backend functions. | |
414 | */ | |
415 | struct radeon_ttm_tt { | |
8e7e7052 | 416 | struct ttm_dma_tt ttm; |
649bf3ca | 417 | u64 offset; |
f72a113a CK |
418 | |
419 | uint64_t userptr; | |
420 | struct mm_struct *usermm; | |
421 | uint32_t userflags; | |
649bf3ca JG |
422 | }; |
423 | ||
f72a113a | 424 | /* prepare the sg table with the user pages */ |
0a667b50 | 425 | static int radeon_ttm_tt_pin_userptr(struct ttm_bo_device *bdev, struct ttm_tt *ttm) |
f72a113a | 426 | { |
0a667b50 | 427 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
f72a113a | 428 | struct radeon_ttm_tt *gtt = (void *)ttm; |
7b814900 | 429 | unsigned pinned = 0; |
f72a113a CK |
430 | int r; |
431 | ||
432 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
433 | enum dma_data_direction direction = write ? | |
434 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
435 | ||
436 | if (current->mm != gtt->usermm) | |
437 | return -EPERM; | |
438 | ||
ddd00e33 CK |
439 | if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { |
440 | /* check that we only pin down anonymous memory | |
441 | to prevent problems with writeback */ | |
442 | unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; | |
443 | struct vm_area_struct *vma; | |
444 | vma = find_vma(gtt->usermm, gtt->userptr); | |
445 | if (!vma || vma->vm_file || vma->vm_end < end) | |
446 | return -EPERM; | |
447 | } | |
448 | ||
f72a113a CK |
449 | do { |
450 | unsigned num_pages = ttm->num_pages - pinned; | |
451 | uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; | |
452 | struct page **pages = ttm->pages + pinned; | |
453 | ||
768ae309 LS |
454 | r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0, |
455 | pages, NULL); | |
f72a113a CK |
456 | if (r < 0) |
457 | goto release_pages; | |
458 | ||
459 | pinned += r; | |
460 | ||
461 | } while (pinned < ttm->num_pages); | |
462 | ||
463 | r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, | |
464 | ttm->num_pages << PAGE_SHIFT, | |
465 | GFP_KERNEL); | |
466 | if (r) | |
467 | goto release_sg; | |
468 | ||
7b814900 MS |
469 | r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0); |
470 | if (r) | |
f72a113a CK |
471 | goto release_sg; |
472 | ||
473 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
474 | gtt->ttm.dma_address, ttm->num_pages); | |
475 | ||
476 | return 0; | |
477 | ||
478 | release_sg: | |
479 | kfree(ttm->sg); | |
480 | ||
481 | release_pages: | |
c6f92f9f | 482 | release_pages(ttm->pages, pinned); |
f72a113a CK |
483 | return r; |
484 | } | |
485 | ||
0a667b50 | 486 | static void radeon_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev, struct ttm_tt *ttm) |
f72a113a | 487 | { |
0a667b50 | 488 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
f72a113a | 489 | struct radeon_ttm_tt *gtt = (void *)ttm; |
db12973c | 490 | struct sg_page_iter sg_iter; |
f72a113a CK |
491 | |
492 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
493 | enum dma_data_direction direction = write ? | |
494 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
495 | ||
863653fe CK |
496 | /* double check that we don't free the table twice */ |
497 | if (!ttm->sg->sgl) | |
498 | return; | |
499 | ||
f72a113a | 500 | /* free the sg table and pages again */ |
7b814900 | 501 | dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0); |
f72a113a | 502 | |
7b814900 | 503 | for_each_sgtable_page(ttm->sg, &sg_iter, 0) { |
db12973c | 504 | struct page *page = sg_page_iter_page(&sg_iter); |
f72a113a CK |
505 | if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) |
506 | set_page_dirty(page); | |
507 | ||
508 | mark_page_accessed(page); | |
09cbfeaf | 509 | put_page(page); |
f72a113a CK |
510 | } |
511 | ||
512 | sg_free_table(ttm->sg); | |
513 | } | |
514 | ||
0a667b50 DA |
515 | static int radeon_ttm_backend_bind(struct ttm_bo_device *bdev, |
516 | struct ttm_tt *ttm, | |
2966141a | 517 | struct ttm_resource *bo_mem) |
649bf3ca | 518 | { |
8e7e7052 | 519 | struct radeon_ttm_tt *gtt = (void*)ttm; |
0a667b50 | 520 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
77497f27 MD |
521 | uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | |
522 | RADEON_GART_PAGE_WRITE; | |
649bf3ca JG |
523 | int r; |
524 | ||
f72a113a | 525 | if (gtt->userptr) { |
0a667b50 | 526 | radeon_ttm_tt_pin_userptr(bdev, ttm); |
f72a113a CK |
527 | flags &= ~RADEON_GART_PAGE_WRITE; |
528 | } | |
529 | ||
649bf3ca JG |
530 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
531 | if (!ttm->num_pages) { | |
532 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", | |
533 | ttm->num_pages, bo_mem, ttm); | |
534 | } | |
77497f27 MD |
535 | if (ttm->caching_state == tt_cached) |
536 | flags |= RADEON_GART_PAGE_SNOOP; | |
8e6c0a2f | 537 | r = radeon_gart_bind(rdev, gtt->offset, ttm->num_pages, |
77497f27 | 538 | ttm->pages, gtt->ttm.dma_address, flags); |
649bf3ca JG |
539 | if (r) { |
540 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", | |
541 | ttm->num_pages, (unsigned)gtt->offset); | |
542 | return r; | |
543 | } | |
544 | return 0; | |
545 | } | |
546 | ||
0a667b50 | 547 | static void radeon_ttm_backend_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm) |
649bf3ca | 548 | { |
8e7e7052 | 549 | struct radeon_ttm_tt *gtt = (void *)ttm; |
0a667b50 | 550 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
649bf3ca | 551 | |
8e6c0a2f | 552 | radeon_gart_unbind(rdev, gtt->offset, ttm->num_pages); |
f72a113a CK |
553 | |
554 | if (gtt->userptr) | |
0a667b50 | 555 | radeon_ttm_tt_unpin_userptr(bdev, ttm); |
649bf3ca JG |
556 | } |
557 | ||
0a667b50 | 558 | static void radeon_ttm_backend_destroy(struct ttm_bo_device *bdev, struct ttm_tt *ttm) |
649bf3ca | 559 | { |
8e7e7052 | 560 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 561 | |
8e7e7052 | 562 | ttm_dma_tt_fini(>t->ttm); |
649bf3ca JG |
563 | kfree(gtt); |
564 | } | |
565 | ||
dde5da23 CK |
566 | static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo, |
567 | uint32_t page_flags) | |
649bf3ca JG |
568 | { |
569 | struct radeon_device *rdev; | |
570 | struct radeon_ttm_tt *gtt; | |
571 | ||
dde5da23 | 572 | rdev = radeon_get_rdev(bo->bdev); |
a7fb8a23 | 573 | #if IS_ENABLED(CONFIG_AGP) |
649bf3ca | 574 | if (rdev->flags & RADEON_IS_AGP) { |
dde5da23 CK |
575 | return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge, |
576 | page_flags); | |
649bf3ca JG |
577 | } |
578 | #endif | |
579 | ||
580 | gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); | |
581 | if (gtt == NULL) { | |
582 | return NULL; | |
583 | } | |
dde5da23 | 584 | if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) { |
8e7e7052 | 585 | kfree(gtt); |
649bf3ca JG |
586 | return NULL; |
587 | } | |
8e7e7052 | 588 | return >t->ttm.ttm; |
649bf3ca JG |
589 | } |
590 | ||
a68bb193 DA |
591 | static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct radeon_device *rdev, |
592 | struct ttm_tt *ttm) | |
3840a656 | 593 | { |
a68bb193 DA |
594 | #if IS_ENABLED(CONFIG_AGP) |
595 | if (rdev->flags & RADEON_IS_AGP) | |
596 | return NULL; | |
597 | #endif | |
598 | ||
599 | if (!ttm) | |
3840a656 | 600 | return NULL; |
a68bb193 | 601 | return container_of(ttm, struct radeon_ttm_tt, ttm.ttm); |
3840a656 CK |
602 | } |
603 | ||
0a667b50 DA |
604 | static int radeon_ttm_tt_populate(struct ttm_bo_device *bdev, |
605 | struct ttm_tt *ttm, | |
606 | struct ttm_operation_ctx *ctx) | |
c52494f6 | 607 | { |
a68bb193 DA |
608 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
609 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); | |
40f5cf99 | 610 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
c52494f6 | 611 | |
3840a656 | 612 | if (gtt && gtt->userptr) { |
69ee2410 | 613 | ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); |
f72a113a CK |
614 | if (!ttm->sg) |
615 | return -ENOMEM; | |
616 | ||
617 | ttm->page_flags |= TTM_PAGE_FLAG_SG; | |
618 | ttm->state = tt_unbound; | |
619 | return 0; | |
620 | } | |
621 | ||
40f5cf99 AD |
622 | if (slave && ttm->sg) { |
623 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
624 | gtt->ttm.dma_address, ttm->num_pages); | |
625 | ttm->state = tt_unbound; | |
626 | return 0; | |
627 | } | |
628 | ||
a7fb8a23 | 629 | #if IS_ENABLED(CONFIG_AGP) |
dea7e0ac | 630 | if (rdev->flags & RADEON_IS_AGP) { |
43482554 | 631 | return ttm_pool_populate(ttm, ctx); |
dea7e0ac JG |
632 | } |
633 | #endif | |
c52494f6 KRW |
634 | |
635 | #ifdef CONFIG_SWIOTLB | |
1bc3d3cc | 636 | if (rdev->need_swiotlb && swiotlb_nr_tbl()) { |
d0cef9fa | 637 | return ttm_dma_populate(>t->ttm, rdev->dev, ctx); |
c52494f6 KRW |
638 | } |
639 | #endif | |
640 | ||
d0cef9fa | 641 | return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx); |
c52494f6 KRW |
642 | } |
643 | ||
0a667b50 | 644 | static void radeon_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm) |
c52494f6 | 645 | { |
a68bb193 DA |
646 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
647 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); | |
40f5cf99 AD |
648 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
649 | ||
3840a656 | 650 | if (gtt && gtt->userptr) { |
f72a113a CK |
651 | kfree(ttm->sg); |
652 | ttm->page_flags &= ~TTM_PAGE_FLAG_SG; | |
653 | return; | |
654 | } | |
655 | ||
40f5cf99 AD |
656 | if (slave) |
657 | return; | |
c52494f6 | 658 | |
a7fb8a23 | 659 | #if IS_ENABLED(CONFIG_AGP) |
dea7e0ac | 660 | if (rdev->flags & RADEON_IS_AGP) { |
43482554 | 661 | ttm_pool_unpopulate(ttm); |
dea7e0ac JG |
662 | return; |
663 | } | |
664 | #endif | |
c52494f6 KRW |
665 | |
666 | #ifdef CONFIG_SWIOTLB | |
1bc3d3cc | 667 | if (rdev->need_swiotlb && swiotlb_nr_tbl()) { |
8e7e7052 | 668 | ttm_dma_unpopulate(>t->ttm, rdev->dev); |
c52494f6 KRW |
669 | return; |
670 | } | |
671 | #endif | |
672 | ||
f7871fd1 | 673 | ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm); |
c52494f6 | 674 | } |
649bf3ca | 675 | |
a68bb193 DA |
676 | int radeon_ttm_tt_set_userptr(struct radeon_device *rdev, |
677 | struct ttm_tt *ttm, uint64_t addr, | |
f72a113a CK |
678 | uint32_t flags) |
679 | { | |
a68bb193 | 680 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); |
f72a113a CK |
681 | |
682 | if (gtt == NULL) | |
683 | return -EINVAL; | |
684 | ||
685 | gtt->userptr = addr; | |
686 | gtt->usermm = current->mm; | |
687 | gtt->userflags = flags; | |
688 | return 0; | |
689 | } | |
690 | ||
a68bb193 DA |
691 | static int radeon_ttm_tt_bind(struct ttm_bo_device *bdev, |
692 | struct ttm_tt *ttm, | |
693 | struct ttm_resource *bo_mem) | |
694 | { | |
695 | struct radeon_device *rdev = radeon_get_rdev(bdev); | |
696 | ||
697 | #if IS_ENABLED(CONFIG_AGP) | |
698 | if (rdev->flags & RADEON_IS_AGP) | |
48efa57e | 699 | return ttm_agp_bind(ttm, bo_mem); |
a68bb193 DA |
700 | #endif |
701 | ||
702 | return radeon_ttm_backend_bind(bdev, ttm, bo_mem); | |
703 | } | |
704 | ||
705 | static void radeon_ttm_tt_unbind(struct ttm_bo_device *bdev, | |
706 | struct ttm_tt *ttm) | |
707 | { | |
708 | #if IS_ENABLED(CONFIG_AGP) | |
709 | struct radeon_device *rdev = radeon_get_rdev(bdev); | |
710 | ||
711 | if (rdev->flags & RADEON_IS_AGP) { | |
48efa57e | 712 | ttm_agp_unbind(ttm); |
a68bb193 DA |
713 | return; |
714 | } | |
715 | #endif | |
716 | radeon_ttm_backend_unbind(bdev, ttm); | |
717 | } | |
718 | ||
719 | static void radeon_ttm_tt_destroy(struct ttm_bo_device *bdev, | |
720 | struct ttm_tt *ttm) | |
721 | { | |
722 | #if IS_ENABLED(CONFIG_AGP) | |
723 | struct radeon_device *rdev = radeon_get_rdev(bdev); | |
724 | ||
725 | if (rdev->flags & RADEON_IS_AGP) { | |
48efa57e | 726 | ttm_agp_destroy(ttm); |
a68bb193 DA |
727 | return; |
728 | } | |
729 | #endif | |
730 | radeon_ttm_backend_destroy(bdev, ttm); | |
731 | } | |
732 | ||
733 | bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, | |
734 | struct ttm_tt *ttm) | |
f72a113a | 735 | { |
a68bb193 | 736 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); |
f72a113a CK |
737 | |
738 | if (gtt == NULL) | |
739 | return false; | |
740 | ||
741 | return !!gtt->userptr; | |
742 | } | |
743 | ||
a68bb193 DA |
744 | bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, |
745 | struct ttm_tt *ttm) | |
f72a113a | 746 | { |
a68bb193 | 747 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); |
f72a113a CK |
748 | |
749 | if (gtt == NULL) | |
750 | return false; | |
751 | ||
752 | return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
753 | } | |
754 | ||
771fe6b9 | 755 | static struct ttm_bo_driver radeon_bo_driver = { |
649bf3ca | 756 | .ttm_tt_create = &radeon_ttm_tt_create, |
c52494f6 KRW |
757 | .ttm_tt_populate = &radeon_ttm_tt_populate, |
758 | .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, | |
a68bb193 DA |
759 | .ttm_tt_bind = &radeon_ttm_tt_bind, |
760 | .ttm_tt_unbind = &radeon_ttm_tt_unbind, | |
761 | .ttm_tt_destroy = &radeon_ttm_tt_destroy, | |
a2ab19fe | 762 | .eviction_valuable = ttm_bo_eviction_valuable, |
771fe6b9 JG |
763 | .evict_flags = &radeon_evict_flags, |
764 | .move = &radeon_bo_move, | |
765 | .verify_access = &radeon_verify_access, | |
e024e110 DA |
766 | .move_notify = &radeon_bo_move_notify, |
767 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, | |
0a2d50e3 | 768 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
771fe6b9 JG |
769 | }; |
770 | ||
771 | int radeon_ttm_init(struct radeon_device *rdev) | |
772 | { | |
773 | int r; | |
774 | ||
771fe6b9 JG |
775 | /* No others user of address space so set it to 0 */ |
776 | r = ttm_bo_device_init(&rdev->mman.bdev, | |
44d847b7 DH |
777 | &radeon_bo_driver, |
778 | rdev->ddev->anon_inode->i_mapping, | |
8b53e1cb | 779 | rdev->ddev->vma_offset_manager, |
33b3ad37 | 780 | dma_addressing_limited(&rdev->pdev->dev)); |
771fe6b9 JG |
781 | if (r) { |
782 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
783 | return r; | |
784 | } | |
0a0c7596 | 785 | rdev->mman.initialized = true; |
b0691b34 CK |
786 | |
787 | r = radeon_ttm_init_vram(rdev); | |
771fe6b9 JG |
788 | if (r) { |
789 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
790 | return r; | |
791 | } | |
14eedc32 LK |
792 | /* Change the size here instead of the init above so only lpfn is affected */ |
793 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
794 | ||
441921d5 | 795 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
831b6966 | 796 | RADEON_GEM_DOMAIN_VRAM, 0, NULL, |
4aa5b92f | 797 | NULL, &rdev->stolen_vga_memory); |
771fe6b9 JG |
798 | if (r) { |
799 | return r; | |
800 | } | |
4aa5b92f | 801 | r = radeon_bo_reserve(rdev->stolen_vga_memory, false); |
4c788679 JG |
802 | if (r) |
803 | return r; | |
4aa5b92f KR |
804 | r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); |
805 | radeon_bo_unreserve(rdev->stolen_vga_memory); | |
771fe6b9 | 806 | if (r) { |
4aa5b92f | 807 | radeon_bo_unref(&rdev->stolen_vga_memory); |
771fe6b9 JG |
808 | return r; |
809 | } | |
810 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | |
fc986034 | 811 | (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); |
b0691b34 CK |
812 | |
813 | r = radeon_ttm_init_gtt(rdev); | |
771fe6b9 JG |
814 | if (r) { |
815 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
816 | return r; | |
817 | } | |
818 | DRM_INFO("radeon: %uM of GTT memory ready.\n", | |
3ce0a23d | 819 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
fa8a1238 DA |
820 | |
821 | r = radeon_ttm_debugfs_init(rdev); | |
822 | if (r) { | |
823 | DRM_ERROR("Failed to init debugfs\n"); | |
824 | return r; | |
825 | } | |
771fe6b9 JG |
826 | return 0; |
827 | } | |
828 | ||
829 | void radeon_ttm_fini(struct radeon_device *rdev) | |
830 | { | |
4c788679 JG |
831 | int r; |
832 | ||
0a0c7596 JG |
833 | if (!rdev->mman.initialized) |
834 | return; | |
2014b569 | 835 | radeon_ttm_debugfs_fini(rdev); |
4aa5b92f KR |
836 | if (rdev->stolen_vga_memory) { |
837 | r = radeon_bo_reserve(rdev->stolen_vga_memory, false); | |
4c788679 | 838 | if (r == 0) { |
4aa5b92f KR |
839 | radeon_bo_unpin(rdev->stolen_vga_memory); |
840 | radeon_bo_unreserve(rdev->stolen_vga_memory); | |
4c788679 | 841 | } |
4aa5b92f | 842 | radeon_bo_unref(&rdev->stolen_vga_memory); |
771fe6b9 | 843 | } |
37205891 DA |
844 | ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_VRAM); |
845 | ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_TT); | |
771fe6b9 JG |
846 | ttm_bo_device_release(&rdev->mman.bdev); |
847 | radeon_gart_fini(rdev); | |
0a0c7596 | 848 | rdev->mman.initialized = false; |
771fe6b9 JG |
849 | DRM_INFO("radeon: ttm finalized\n"); |
850 | } | |
851 | ||
53595338 DA |
852 | /* this should only be called at bootup or when userspace |
853 | * isn't running */ | |
854 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) | |
855 | { | |
9de59bc2 | 856 | struct ttm_resource_manager *man; |
53595338 DA |
857 | |
858 | if (!rdev->mman.initialized) | |
859 | return; | |
860 | ||
47c0550f | 861 | man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); |
53595338 DA |
862 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ |
863 | man->size = size >> PAGE_SHIFT; | |
864 | } | |
865 | ||
2bfb0b67 | 866 | static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf) |
771fe6b9 JG |
867 | { |
868 | struct ttm_buffer_object *bo; | |
5876dd24 | 869 | struct radeon_device *rdev; |
2bfb0b67 | 870 | vm_fault_t ret; |
771fe6b9 | 871 | |
11bac800 | 872 | bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data; |
165d3448 | 873 | if (bo == NULL) |
771fe6b9 | 874 | return VM_FAULT_NOPAGE; |
165d3448 | 875 | |
5876dd24 | 876 | rdev = radeon_get_rdev(bo->bdev); |
db7fce39 | 877 | down_read(&rdev->pm.mclk_lock); |
165d3448 | 878 | ret = ttm_bo_vm_fault(vmf); |
db7fce39 | 879 | up_read(&rdev->pm.mclk_lock); |
2bfb0b67 | 880 | return ret; |
771fe6b9 JG |
881 | } |
882 | ||
165d3448 CK |
883 | static struct vm_operations_struct radeon_ttm_vm_ops = { |
884 | .fault = radeon_ttm_fault, | |
885 | .open = ttm_bo_vm_open, | |
886 | .close = ttm_bo_vm_close, | |
887 | .access = ttm_bo_vm_access | |
888 | }; | |
889 | ||
771fe6b9 JG |
890 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) |
891 | { | |
771fe6b9 | 892 | int r; |
bed2dd84 TZ |
893 | struct drm_file *file_priv = filp->private_data; |
894 | struct radeon_device *rdev = file_priv->minor->dev->dev_private; | |
771fe6b9 | 895 | |
165d3448 | 896 | if (rdev == NULL) |
771fe6b9 | 897 | return -EINVAL; |
165d3448 | 898 | |
771fe6b9 | 899 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); |
165d3448 | 900 | if (unlikely(r != 0)) |
771fe6b9 | 901 | return r; |
165d3448 | 902 | |
771fe6b9 JG |
903 | vma->vm_ops = &radeon_ttm_vm_ops; |
904 | return 0; | |
905 | } | |
906 | ||
fa8a1238 | 907 | #if defined(CONFIG_DEBUG_FS) |
893d6e6e | 908 | |
fa8a1238 DA |
909 | static int radeon_mm_dump_table(struct seq_file *m, void *data) |
910 | { | |
911 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
bbbb29ef | 912 | unsigned ttm_pl = *(int*)node->info_ent->data; |
fa8a1238 DA |
913 | struct drm_device *dev = node->minor->dev; |
914 | struct radeon_device *rdev = dev->dev_private; | |
9de59bc2 | 915 | struct ttm_resource_manager *man = ttm_manager_type(&rdev->mman.bdev, ttm_pl); |
b5c3714f | 916 | struct drm_printer p = drm_seq_file_printer(m); |
fa8a1238 | 917 | |
bbbb29ef | 918 | man->func->debug(man, &p); |
b5c3714f | 919 | return 0; |
fa8a1238 | 920 | } |
893d6e6e | 921 | |
bbbb29ef | 922 | |
893d6e6e CK |
923 | static int ttm_pl_vram = TTM_PL_VRAM; |
924 | static int ttm_pl_tt = TTM_PL_TT; | |
925 | ||
926 | static struct drm_info_list radeon_ttm_debugfs_list[] = { | |
927 | {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, | |
928 | {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, | |
929 | {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, | |
930 | #ifdef CONFIG_SWIOTLB | |
931 | {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} | |
932 | #endif | |
933 | }; | |
934 | ||
2014b569 CK |
935 | static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) |
936 | { | |
937 | struct radeon_device *rdev = inode->i_private; | |
938 | i_size_write(inode, rdev->mc.mc_vram_size); | |
939 | filep->private_data = inode->i_private; | |
940 | return 0; | |
941 | } | |
942 | ||
943 | static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, | |
944 | size_t size, loff_t *pos) | |
945 | { | |
946 | struct radeon_device *rdev = f->private_data; | |
947 | ssize_t result = 0; | |
948 | int r; | |
949 | ||
950 | if (size & 0x3 || *pos & 0x3) | |
951 | return -EINVAL; | |
952 | ||
953 | while (size) { | |
954 | unsigned long flags; | |
955 | uint32_t value; | |
956 | ||
957 | if (*pos >= rdev->mc.mc_vram_size) | |
958 | return result; | |
959 | ||
960 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
961 | WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); | |
962 | if (rdev->family >= CHIP_CEDAR) | |
963 | WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); | |
964 | value = RREG32(RADEON_MM_DATA); | |
965 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); | |
966 | ||
967 | r = put_user(value, (uint32_t *)buf); | |
968 | if (r) | |
969 | return r; | |
970 | ||
971 | result += 4; | |
972 | buf += 4; | |
973 | *pos += 4; | |
974 | size -= 4; | |
975 | } | |
976 | ||
977 | return result; | |
978 | } | |
979 | ||
980 | static const struct file_operations radeon_ttm_vram_fops = { | |
981 | .owner = THIS_MODULE, | |
982 | .open = radeon_ttm_vram_open, | |
983 | .read = radeon_ttm_vram_read, | |
984 | .llseek = default_llseek | |
985 | }; | |
986 | ||
dd66d20e CK |
987 | static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) |
988 | { | |
989 | struct radeon_device *rdev = inode->i_private; | |
990 | i_size_write(inode, rdev->mc.gtt_size); | |
991 | filep->private_data = inode->i_private; | |
992 | return 0; | |
993 | } | |
994 | ||
995 | static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, | |
996 | size_t size, loff_t *pos) | |
997 | { | |
998 | struct radeon_device *rdev = f->private_data; | |
999 | ssize_t result = 0; | |
1000 | int r; | |
1001 | ||
1002 | while (size) { | |
1003 | loff_t p = *pos / PAGE_SIZE; | |
1004 | unsigned off = *pos & ~PAGE_MASK; | |
0d997b68 | 1005 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); |
dd66d20e CK |
1006 | struct page *page; |
1007 | void *ptr; | |
1008 | ||
1009 | if (p >= rdev->gart.num_cpu_pages) | |
1010 | return result; | |
1011 | ||
1012 | page = rdev->gart.pages[p]; | |
1013 | if (page) { | |
1014 | ptr = kmap(page); | |
1015 | ptr += off; | |
1016 | ||
1017 | r = copy_to_user(buf, ptr, cur_size); | |
1018 | kunmap(rdev->gart.pages[p]); | |
1019 | } else | |
1020 | r = clear_user(buf, cur_size); | |
1021 | ||
1022 | if (r) | |
1023 | return -EFAULT; | |
1024 | ||
1025 | result += cur_size; | |
1026 | buf += cur_size; | |
1027 | *pos += cur_size; | |
1028 | size -= cur_size; | |
1029 | } | |
1030 | ||
1031 | return result; | |
1032 | } | |
1033 | ||
1034 | static const struct file_operations radeon_ttm_gtt_fops = { | |
1035 | .owner = THIS_MODULE, | |
1036 | .open = radeon_ttm_gtt_open, | |
1037 | .read = radeon_ttm_gtt_read, | |
1038 | .llseek = default_llseek | |
1039 | }; | |
1040 | ||
fa8a1238 DA |
1041 | #endif |
1042 | ||
1043 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | |
1044 | { | |
f4e45d02 | 1045 | #if defined(CONFIG_DEBUG_FS) |
2014b569 CK |
1046 | unsigned count; |
1047 | ||
1048 | struct drm_minor *minor = rdev->ddev->primary; | |
bb1d26b4 GKH |
1049 | struct dentry *root = minor->debugfs_root; |
1050 | ||
1051 | rdev->mman.vram = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, | |
1052 | root, rdev, | |
1053 | &radeon_ttm_vram_fops); | |
1054 | ||
1055 | rdev->mman.gtt = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, | |
1056 | root, rdev, &radeon_ttm_gtt_fops); | |
dd66d20e | 1057 | |
2014b569 | 1058 | count = ARRAY_SIZE(radeon_ttm_debugfs_list); |
fa8a1238 | 1059 | |
c52494f6 | 1060 | #ifdef CONFIG_SWIOTLB |
1bc3d3cc | 1061 | if (!(rdev->need_swiotlb && swiotlb_nr_tbl())) |
893d6e6e | 1062 | --count; |
c52494f6 | 1063 | #endif |
fa8a1238 | 1064 | |
893d6e6e CK |
1065 | return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); |
1066 | #else | |
1067 | ||
fa8a1238 | 1068 | return 0; |
893d6e6e | 1069 | #endif |
fa8a1238 | 1070 | } |
2014b569 CK |
1071 | |
1072 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) | |
1073 | { | |
1074 | #if defined(CONFIG_DEBUG_FS) | |
1075 | ||
1076 | debugfs_remove(rdev->mman.vram); | |
1077 | rdev->mman.vram = NULL; | |
dd66d20e CK |
1078 | |
1079 | debugfs_remove(rdev->mman.gtt); | |
1080 | rdev->mman.gtt = NULL; | |
2014b569 CK |
1081 | #endif |
1082 | } |