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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
f9183127 SR |
32 | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/pagemap.h> | |
2ef79416 | 35 | #include <linux/pci.h> |
f9183127 SR |
36 | #include <linux/seq_file.h> |
37 | #include <linux/slab.h> | |
38 | #include <linux/swap.h> | |
39 | #include <linux/swiotlb.h> | |
40 | ||
41 | #include <drm/drm_agpsupport.h> | |
42 | #include <drm/drm_debugfs.h> | |
43 | #include <drm/drm_device.h> | |
44 | #include <drm/drm_file.h> | |
f9183127 SR |
45 | #include <drm/drm_prime.h> |
46 | #include <drm/radeon_drm.h> | |
64a9dfc4 MY |
47 | #include <drm/ttm/ttm_bo_api.h> |
48 | #include <drm/ttm/ttm_bo_driver.h> | |
64a9dfc4 MY |
49 | #include <drm/ttm/ttm_module.h> |
50 | #include <drm/ttm/ttm_page_alloc.h> | |
f9183127 SR |
51 | #include <drm/ttm/ttm_placement.h> |
52 | ||
771fe6b9 JG |
53 | #include "radeon_reg.h" |
54 | #include "radeon.h" | |
55 | ||
fa8a1238 | 56 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
2014b569 | 57 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); |
fa8a1238 | 58 | |
a0e4a298 | 59 | struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
771fe6b9 JG |
60 | { |
61 | struct radeon_mman *mman; | |
62 | struct radeon_device *rdev; | |
63 | ||
64 | mman = container_of(bdev, struct radeon_mman, bdev); | |
65 | rdev = container_of(mman, struct radeon_device, mman); | |
66 | return rdev; | |
67 | } | |
68 | ||
b0691b34 CK |
69 | static int radeon_ttm_init_vram(struct radeon_device *rdev) |
70 | { | |
47c0550f | 71 | struct ttm_mem_type_manager *man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); |
771fe6b9 | 72 | |
b0691b34 CK |
73 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; |
74 | man->default_caching = TTM_PL_FLAG_WC; | |
75 | ||
e33dc182 DA |
76 | return ttm_range_man_init(&rdev->mman.bdev, man, |
77 | rdev->mc.real_vram_size >> PAGE_SHIFT); | |
b0691b34 CK |
78 | } |
79 | ||
80 | static int radeon_ttm_init_gtt(struct radeon_device *rdev) | |
81 | { | |
47c0550f | 82 | struct ttm_mem_type_manager *man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT); |
b0691b34 | 83 | |
b0691b34 CK |
84 | man->available_caching = TTM_PL_MASK_CACHING; |
85 | man->default_caching = TTM_PL_FLAG_CACHED; | |
86 | man->use_tt = true; | |
a7fb8a23 | 87 | #if IS_ENABLED(CONFIG_AGP) |
b0691b34 CK |
88 | if (rdev->flags & RADEON_IS_AGP) { |
89 | if (!rdev->ddev->agp) { | |
90 | DRM_ERROR("AGP is not enabled\n"); | |
91 | return -EINVAL; | |
771fe6b9 | 92 | } |
b0691b34 CK |
93 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
94 | TTM_PL_FLAG_WC; | |
771fe6b9 | 95 | man->default_caching = TTM_PL_FLAG_WC; |
771fe6b9 | 96 | } |
b0691b34 CK |
97 | #endif |
98 | ||
e33dc182 DA |
99 | return ttm_range_man_init(&rdev->mman.bdev, man, |
100 | rdev->mc.gtt_size >> PAGE_SHIFT); | |
771fe6b9 JG |
101 | } |
102 | ||
312ea8da JG |
103 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
104 | struct ttm_placement *placement) | |
771fe6b9 | 105 | { |
46886dbf | 106 | static const struct ttm_place placements = { |
f1217ed0 CK |
107 | .fpfn = 0, |
108 | .lpfn = 0, | |
109 | .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM | |
110 | }; | |
111 | ||
d03d8589 | 112 | struct radeon_bo *rbo; |
d03d8589 JG |
113 | |
114 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { | |
d03d8589 JG |
115 | placement->placement = &placements; |
116 | placement->busy_placement = &placements; | |
117 | placement->num_placement = 1; | |
118 | placement->num_busy_placement = 1; | |
119 | return; | |
120 | } | |
121 | rbo = container_of(bo, struct radeon_bo, tbo); | |
771fe6b9 | 122 | switch (bo->mem.mem_type) { |
312ea8da | 123 | case TTM_PL_VRAM: |
5e5c21ca | 124 | if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) |
9270eb1b | 125 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
2a85aedd MD |
126 | else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && |
127 | bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { | |
128 | unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
129 | int i; | |
130 | ||
131 | /* Try evicting to the CPU inaccessible part of VRAM | |
132 | * first, but only set GTT as busy placement, so this | |
133 | * BO will be evicted to GTT rather than causing other | |
134 | * BOs to be evicted from VRAM | |
135 | */ | |
136 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | | |
137 | RADEON_GEM_DOMAIN_GTT); | |
138 | rbo->placement.num_busy_placement = 0; | |
139 | for (i = 0; i < rbo->placement.num_placement; i++) { | |
140 | if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { | |
ce4b4f22 MD |
141 | if (rbo->placements[i].fpfn < fpfn) |
142 | rbo->placements[i].fpfn = fpfn; | |
2a85aedd MD |
143 | } else { |
144 | rbo->placement.busy_placement = | |
145 | &rbo->placements[i]; | |
146 | rbo->placement.num_busy_placement = 1; | |
147 | } | |
148 | } | |
149 | } else | |
9270eb1b | 150 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); |
312ea8da JG |
151 | break; |
152 | case TTM_PL_TT: | |
771fe6b9 | 153 | default: |
312ea8da | 154 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
771fe6b9 | 155 | } |
eaa5fd1a | 156 | *placement = rbo->placement; |
771fe6b9 JG |
157 | } |
158 | ||
159 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
160 | { | |
acb46527 DH |
161 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
162 | ||
b5dcec69 JG |
163 | if (radeon_ttm_tt_has_userptr(bo->ttm)) |
164 | return -EPERM; | |
ce77038f | 165 | return drm_vma_node_verify_access(&rbo->tbo.base.vma_node, |
d9a1f0b4 | 166 | filp->private_data); |
771fe6b9 JG |
167 | } |
168 | ||
169 | static void radeon_move_null(struct ttm_buffer_object *bo, | |
170 | struct ttm_mem_reg *new_mem) | |
171 | { | |
172 | struct ttm_mem_reg *old_mem = &bo->mem; | |
173 | ||
174 | BUG_ON(old_mem->mm_node != NULL); | |
175 | *old_mem = *new_mem; | |
176 | new_mem->mm_node = NULL; | |
177 | } | |
178 | ||
179 | static int radeon_move_blit(struct ttm_buffer_object *bo, | |
97a875cb | 180 | bool evict, bool no_wait_gpu, |
9d87fa21 JG |
181 | struct ttm_mem_reg *new_mem, |
182 | struct ttm_mem_reg *old_mem) | |
771fe6b9 JG |
183 | { |
184 | struct radeon_device *rdev; | |
185 | uint64_t old_start, new_start; | |
876dc9f3 | 186 | struct radeon_fence *fence; |
57d20a43 | 187 | unsigned num_pages; |
876dc9f3 | 188 | int r, ridx; |
771fe6b9 JG |
189 | |
190 | rdev = radeon_get_rdev(bo->bdev); | |
876dc9f3 | 191 | ridx = radeon_copy_ring_index(rdev); |
13f479b9 CK |
192 | old_start = (u64)old_mem->start << PAGE_SHIFT; |
193 | new_start = (u64)new_mem->start << PAGE_SHIFT; | |
771fe6b9 JG |
194 | |
195 | switch (old_mem->mem_type) { | |
196 | case TTM_PL_VRAM: | |
d594e46a | 197 | old_start += rdev->mc.vram_start; |
771fe6b9 JG |
198 | break; |
199 | case TTM_PL_TT: | |
d594e46a | 200 | old_start += rdev->mc.gtt_start; |
771fe6b9 JG |
201 | break; |
202 | default: | |
203 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
204 | return -EINVAL; | |
205 | } | |
206 | switch (new_mem->mem_type) { | |
207 | case TTM_PL_VRAM: | |
d594e46a | 208 | new_start += rdev->mc.vram_start; |
771fe6b9 JG |
209 | break; |
210 | case TTM_PL_TT: | |
d594e46a | 211 | new_start += rdev->mc.gtt_start; |
771fe6b9 JG |
212 | break; |
213 | default: | |
214 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
215 | return -EINVAL; | |
216 | } | |
876dc9f3 | 217 | if (!rdev->ring[ridx].ready) { |
3000bf39 | 218 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
771fe6b9 JG |
219 | return -EINVAL; |
220 | } | |
003cefe0 AD |
221 | |
222 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); | |
223 | ||
57d20a43 | 224 | num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); |
336ac942 | 225 | fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv); |
57d20a43 CK |
226 | if (IS_ERR(fence)) |
227 | return PTR_ERR(fence); | |
228 | ||
74561cd4 | 229 | r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem); |
771fe6b9 JG |
230 | radeon_fence_unref(&fence); |
231 | return r; | |
232 | } | |
233 | ||
234 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, | |
9d87fa21 | 235 | bool evict, bool interruptible, |
97a875cb | 236 | bool no_wait_gpu, |
771fe6b9 JG |
237 | struct ttm_mem_reg *new_mem) |
238 | { | |
c13c55d6 | 239 | struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; |
771fe6b9 JG |
240 | struct ttm_mem_reg *old_mem = &bo->mem; |
241 | struct ttm_mem_reg tmp_mem; | |
f1217ed0 | 242 | struct ttm_place placements; |
312ea8da | 243 | struct ttm_placement placement; |
771fe6b9 JG |
244 | int r; |
245 | ||
771fe6b9 JG |
246 | tmp_mem = *new_mem; |
247 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
248 | placement.num_placement = 1; |
249 | placement.placement = &placements; | |
250 | placement.num_busy_placement = 1; | |
251 | placement.busy_placement = &placements; | |
f1217ed0 CK |
252 | placements.fpfn = 0; |
253 | placements.lpfn = 0; | |
254 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
c13c55d6 | 255 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); |
771fe6b9 JG |
256 | if (unlikely(r)) { |
257 | return r; | |
258 | } | |
df67bed9 DA |
259 | |
260 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); | |
261 | if (unlikely(r)) { | |
262 | goto out_cleanup; | |
263 | } | |
264 | ||
993baf15 | 265 | r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx); |
771fe6b9 JG |
266 | if (unlikely(r)) { |
267 | goto out_cleanup; | |
268 | } | |
97a875cb | 269 | r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); |
771fe6b9 JG |
270 | if (unlikely(r)) { |
271 | goto out_cleanup; | |
272 | } | |
3e98d829 | 273 | r = ttm_bo_move_ttm(bo, &ctx, new_mem); |
771fe6b9 | 274 | out_cleanup: |
42311ff9 | 275 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
276 | return r; |
277 | } | |
278 | ||
279 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, | |
9d87fa21 | 280 | bool evict, bool interruptible, |
97a875cb | 281 | bool no_wait_gpu, |
771fe6b9 JG |
282 | struct ttm_mem_reg *new_mem) |
283 | { | |
c13c55d6 | 284 | struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; |
771fe6b9 JG |
285 | struct ttm_mem_reg *old_mem = &bo->mem; |
286 | struct ttm_mem_reg tmp_mem; | |
312ea8da | 287 | struct ttm_placement placement; |
f1217ed0 | 288 | struct ttm_place placements; |
771fe6b9 JG |
289 | int r; |
290 | ||
771fe6b9 JG |
291 | tmp_mem = *new_mem; |
292 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
293 | placement.num_placement = 1; |
294 | placement.placement = &placements; | |
295 | placement.num_busy_placement = 1; | |
296 | placement.busy_placement = &placements; | |
f1217ed0 CK |
297 | placements.fpfn = 0; |
298 | placements.lpfn = 0; | |
299 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
c13c55d6 | 300 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); |
771fe6b9 JG |
301 | if (unlikely(r)) { |
302 | return r; | |
303 | } | |
3e98d829 | 304 | r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem); |
771fe6b9 JG |
305 | if (unlikely(r)) { |
306 | goto out_cleanup; | |
307 | } | |
97a875cb | 308 | r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); |
771fe6b9 JG |
309 | if (unlikely(r)) { |
310 | goto out_cleanup; | |
311 | } | |
312 | out_cleanup: | |
42311ff9 | 313 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
314 | return r; |
315 | } | |
316 | ||
2823f4f0 CK |
317 | static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, |
318 | struct ttm_operation_ctx *ctx, | |
319 | struct ttm_mem_reg *new_mem) | |
771fe6b9 JG |
320 | { |
321 | struct radeon_device *rdev; | |
e1a575ad | 322 | struct radeon_bo *rbo; |
771fe6b9 JG |
323 | struct ttm_mem_reg *old_mem = &bo->mem; |
324 | int r; | |
325 | ||
2823f4f0 | 326 | r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); |
88932a7b CK |
327 | if (r) |
328 | return r; | |
329 | ||
e1a575ad MD |
330 | /* Can't move a pinned BO */ |
331 | rbo = container_of(bo, struct radeon_bo, tbo); | |
332 | if (WARN_ON_ONCE(rbo->pin_count > 0)) | |
333 | return -EINVAL; | |
334 | ||
771fe6b9 JG |
335 | rdev = radeon_get_rdev(bo->bdev); |
336 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { | |
337 | radeon_move_null(bo, new_mem); | |
338 | return 0; | |
339 | } | |
340 | if ((old_mem->mem_type == TTM_PL_TT && | |
341 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
342 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
343 | new_mem->mem_type == TTM_PL_TT)) { | |
af901ca1 | 344 | /* bind is enough */ |
771fe6b9 JG |
345 | radeon_move_null(bo, new_mem); |
346 | return 0; | |
347 | } | |
27cd7769 AD |
348 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || |
349 | rdev->asic->copy.copy == NULL) { | |
771fe6b9 | 350 | /* use memcpy */ |
1ab2e105 | 351 | goto memcpy; |
771fe6b9 JG |
352 | } |
353 | ||
354 | if (old_mem->mem_type == TTM_PL_VRAM && | |
355 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
2823f4f0 CK |
356 | r = radeon_move_vram_ram(bo, evict, ctx->interruptible, |
357 | ctx->no_wait_gpu, new_mem); | |
771fe6b9 JG |
358 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
359 | new_mem->mem_type == TTM_PL_VRAM) { | |
2823f4f0 CK |
360 | r = radeon_move_ram_vram(bo, evict, ctx->interruptible, |
361 | ctx->no_wait_gpu, new_mem); | |
771fe6b9 | 362 | } else { |
2823f4f0 CK |
363 | r = radeon_move_blit(bo, evict, ctx->no_wait_gpu, |
364 | new_mem, old_mem); | |
771fe6b9 | 365 | } |
1ab2e105 MD |
366 | |
367 | if (r) { | |
368 | memcpy: | |
3e98d829 | 369 | r = ttm_bo_move_memcpy(bo, ctx, new_mem); |
67e8e3f9 MO |
370 | if (r) { |
371 | return r; | |
372 | } | |
1ab2e105 | 373 | } |
67e8e3f9 MO |
374 | |
375 | /* update statistics */ | |
376 | atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); | |
377 | return 0; | |
771fe6b9 JG |
378 | } |
379 | ||
0a2d50e3 JG |
380 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
381 | { | |
0a2d50e3 JG |
382 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
383 | ||
384 | mem->bus.addr = NULL; | |
385 | mem->bus.offset = 0; | |
386 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
387 | mem->bus.base = 0; | |
388 | mem->bus.is_iomem = false; | |
8401e2ed | 389 | |
0a2d50e3 JG |
390 | switch (mem->mem_type) { |
391 | case TTM_PL_SYSTEM: | |
392 | /* system memory */ | |
393 | return 0; | |
394 | case TTM_PL_TT: | |
a7fb8a23 | 395 | #if IS_ENABLED(CONFIG_AGP) |
0a2d50e3 JG |
396 | if (rdev->flags & RADEON_IS_AGP) { |
397 | /* RADEON_IS_AGP is set only if AGP is active */ | |
d961db75 | 398 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 | 399 | mem->bus.base = rdev->mc.agp_base; |
365048ff | 400 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
0a2d50e3 JG |
401 | } |
402 | #endif | |
403 | break; | |
404 | case TTM_PL_VRAM: | |
d961db75 | 405 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 JG |
406 | /* check if it's visible */ |
407 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) | |
408 | return -EINVAL; | |
409 | mem->bus.base = rdev->mc.aper_base; | |
410 | mem->bus.is_iomem = true; | |
ffb57c4b JE |
411 | #ifdef __alpha__ |
412 | /* | |
413 | * Alpha: use bus.addr to hold the ioremap() return, | |
414 | * so we can modify bus.base below. | |
415 | */ | |
416 | if (mem->placement & TTM_PL_FLAG_WC) | |
417 | mem->bus.addr = | |
418 | ioremap_wc(mem->bus.base + mem->bus.offset, | |
419 | mem->bus.size); | |
420 | else | |
421 | mem->bus.addr = | |
4bdc0d67 | 422 | ioremap(mem->bus.base + mem->bus.offset, |
ffb57c4b | 423 | mem->bus.size); |
3b2c6932 AY |
424 | if (!mem->bus.addr) |
425 | return -ENOMEM; | |
ffb57c4b JE |
426 | |
427 | /* | |
428 | * Alpha: Use just the bus offset plus | |
429 | * the hose/domain memory base for bus.base. | |
430 | * It then can be used to build PTEs for VRAM | |
431 | * access, as done in ttm_bo_vm_fault(). | |
432 | */ | |
433 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + | |
434 | rdev->ddev->hose->dense_mem_base; | |
435 | #endif | |
0a2d50e3 JG |
436 | break; |
437 | default: | |
438 | return -EINVAL; | |
439 | } | |
440 | return 0; | |
441 | } | |
442 | ||
649bf3ca JG |
443 | /* |
444 | * TTM backend functions. | |
445 | */ | |
446 | struct radeon_ttm_tt { | |
8e7e7052 | 447 | struct ttm_dma_tt ttm; |
649bf3ca JG |
448 | struct radeon_device *rdev; |
449 | u64 offset; | |
f72a113a CK |
450 | |
451 | uint64_t userptr; | |
452 | struct mm_struct *usermm; | |
453 | uint32_t userflags; | |
649bf3ca JG |
454 | }; |
455 | ||
f72a113a CK |
456 | /* prepare the sg table with the user pages */ |
457 | static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm) | |
458 | { | |
459 | struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); | |
460 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
7b814900 | 461 | unsigned pinned = 0; |
f72a113a CK |
462 | int r; |
463 | ||
464 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
465 | enum dma_data_direction direction = write ? | |
466 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
467 | ||
468 | if (current->mm != gtt->usermm) | |
469 | return -EPERM; | |
470 | ||
ddd00e33 CK |
471 | if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { |
472 | /* check that we only pin down anonymous memory | |
473 | to prevent problems with writeback */ | |
474 | unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; | |
475 | struct vm_area_struct *vma; | |
476 | vma = find_vma(gtt->usermm, gtt->userptr); | |
477 | if (!vma || vma->vm_file || vma->vm_end < end) | |
478 | return -EPERM; | |
479 | } | |
480 | ||
f72a113a CK |
481 | do { |
482 | unsigned num_pages = ttm->num_pages - pinned; | |
483 | uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; | |
484 | struct page **pages = ttm->pages + pinned; | |
485 | ||
768ae309 LS |
486 | r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0, |
487 | pages, NULL); | |
f72a113a CK |
488 | if (r < 0) |
489 | goto release_pages; | |
490 | ||
491 | pinned += r; | |
492 | ||
493 | } while (pinned < ttm->num_pages); | |
494 | ||
495 | r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, | |
496 | ttm->num_pages << PAGE_SHIFT, | |
497 | GFP_KERNEL); | |
498 | if (r) | |
499 | goto release_sg; | |
500 | ||
7b814900 MS |
501 | r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0); |
502 | if (r) | |
f72a113a CK |
503 | goto release_sg; |
504 | ||
505 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
506 | gtt->ttm.dma_address, ttm->num_pages); | |
507 | ||
508 | return 0; | |
509 | ||
510 | release_sg: | |
511 | kfree(ttm->sg); | |
512 | ||
513 | release_pages: | |
c6f92f9f | 514 | release_pages(ttm->pages, pinned); |
f72a113a CK |
515 | return r; |
516 | } | |
517 | ||
518 | static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm) | |
519 | { | |
520 | struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); | |
521 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
db12973c | 522 | struct sg_page_iter sg_iter; |
f72a113a CK |
523 | |
524 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
525 | enum dma_data_direction direction = write ? | |
526 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
527 | ||
863653fe CK |
528 | /* double check that we don't free the table twice */ |
529 | if (!ttm->sg->sgl) | |
530 | return; | |
531 | ||
f72a113a | 532 | /* free the sg table and pages again */ |
7b814900 | 533 | dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0); |
f72a113a | 534 | |
7b814900 | 535 | for_each_sgtable_page(ttm->sg, &sg_iter, 0) { |
db12973c | 536 | struct page *page = sg_page_iter_page(&sg_iter); |
f72a113a CK |
537 | if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) |
538 | set_page_dirty(page); | |
539 | ||
540 | mark_page_accessed(page); | |
09cbfeaf | 541 | put_page(page); |
f72a113a CK |
542 | } |
543 | ||
544 | sg_free_table(ttm->sg); | |
545 | } | |
546 | ||
649bf3ca JG |
547 | static int radeon_ttm_backend_bind(struct ttm_tt *ttm, |
548 | struct ttm_mem_reg *bo_mem) | |
549 | { | |
8e7e7052 | 550 | struct radeon_ttm_tt *gtt = (void*)ttm; |
77497f27 MD |
551 | uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | |
552 | RADEON_GART_PAGE_WRITE; | |
649bf3ca JG |
553 | int r; |
554 | ||
f72a113a CK |
555 | if (gtt->userptr) { |
556 | radeon_ttm_tt_pin_userptr(ttm); | |
557 | flags &= ~RADEON_GART_PAGE_WRITE; | |
558 | } | |
559 | ||
649bf3ca JG |
560 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
561 | if (!ttm->num_pages) { | |
562 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", | |
563 | ttm->num_pages, bo_mem, ttm); | |
564 | } | |
77497f27 MD |
565 | if (ttm->caching_state == tt_cached) |
566 | flags |= RADEON_GART_PAGE_SNOOP; | |
567 | r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, | |
568 | ttm->pages, gtt->ttm.dma_address, flags); | |
649bf3ca JG |
569 | if (r) { |
570 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", | |
571 | ttm->num_pages, (unsigned)gtt->offset); | |
572 | return r; | |
573 | } | |
574 | return 0; | |
575 | } | |
576 | ||
577 | static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) | |
578 | { | |
8e7e7052 | 579 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 580 | |
649bf3ca | 581 | radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); |
f72a113a CK |
582 | |
583 | if (gtt->userptr) | |
584 | radeon_ttm_tt_unpin_userptr(ttm); | |
585 | ||
649bf3ca JG |
586 | return 0; |
587 | } | |
588 | ||
589 | static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) | |
590 | { | |
8e7e7052 | 591 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 592 | |
8e7e7052 | 593 | ttm_dma_tt_fini(>t->ttm); |
649bf3ca JG |
594 | kfree(gtt); |
595 | } | |
596 | ||
597 | static struct ttm_backend_func radeon_backend_func = { | |
598 | .bind = &radeon_ttm_backend_bind, | |
599 | .unbind = &radeon_ttm_backend_unbind, | |
600 | .destroy = &radeon_ttm_backend_destroy, | |
601 | }; | |
602 | ||
dde5da23 CK |
603 | static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo, |
604 | uint32_t page_flags) | |
649bf3ca JG |
605 | { |
606 | struct radeon_device *rdev; | |
607 | struct radeon_ttm_tt *gtt; | |
608 | ||
dde5da23 | 609 | rdev = radeon_get_rdev(bo->bdev); |
a7fb8a23 | 610 | #if IS_ENABLED(CONFIG_AGP) |
649bf3ca | 611 | if (rdev->flags & RADEON_IS_AGP) { |
dde5da23 CK |
612 | return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge, |
613 | page_flags); | |
649bf3ca JG |
614 | } |
615 | #endif | |
616 | ||
617 | gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); | |
618 | if (gtt == NULL) { | |
619 | return NULL; | |
620 | } | |
8e7e7052 | 621 | gtt->ttm.ttm.func = &radeon_backend_func; |
649bf3ca | 622 | gtt->rdev = rdev; |
dde5da23 | 623 | if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) { |
8e7e7052 | 624 | kfree(gtt); |
649bf3ca JG |
625 | return NULL; |
626 | } | |
8e7e7052 | 627 | return >t->ttm.ttm; |
649bf3ca JG |
628 | } |
629 | ||
3840a656 CK |
630 | static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm) |
631 | { | |
632 | if (!ttm || ttm->func != &radeon_backend_func) | |
633 | return NULL; | |
634 | return (struct radeon_ttm_tt *)ttm; | |
635 | } | |
636 | ||
d0cef9fa RH |
637 | static int radeon_ttm_tt_populate(struct ttm_tt *ttm, |
638 | struct ttm_operation_ctx *ctx) | |
c52494f6 | 639 | { |
3840a656 | 640 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
c52494f6 | 641 | struct radeon_device *rdev; |
40f5cf99 | 642 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
c52494f6 | 643 | |
3840a656 | 644 | if (gtt && gtt->userptr) { |
69ee2410 | 645 | ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); |
f72a113a CK |
646 | if (!ttm->sg) |
647 | return -ENOMEM; | |
648 | ||
649 | ttm->page_flags |= TTM_PAGE_FLAG_SG; | |
650 | ttm->state = tt_unbound; | |
651 | return 0; | |
652 | } | |
653 | ||
40f5cf99 AD |
654 | if (slave && ttm->sg) { |
655 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
656 | gtt->ttm.dma_address, ttm->num_pages); | |
657 | ttm->state = tt_unbound; | |
658 | return 0; | |
659 | } | |
660 | ||
c52494f6 | 661 | rdev = radeon_get_rdev(ttm->bdev); |
a7fb8a23 | 662 | #if IS_ENABLED(CONFIG_AGP) |
dea7e0ac | 663 | if (rdev->flags & RADEON_IS_AGP) { |
d0cef9fa | 664 | return ttm_agp_tt_populate(ttm, ctx); |
dea7e0ac JG |
665 | } |
666 | #endif | |
c52494f6 KRW |
667 | |
668 | #ifdef CONFIG_SWIOTLB | |
1bc3d3cc | 669 | if (rdev->need_swiotlb && swiotlb_nr_tbl()) { |
d0cef9fa | 670 | return ttm_dma_populate(>t->ttm, rdev->dev, ctx); |
c52494f6 KRW |
671 | } |
672 | #endif | |
673 | ||
d0cef9fa | 674 | return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx); |
c52494f6 KRW |
675 | } |
676 | ||
677 | static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
678 | { | |
679 | struct radeon_device *rdev; | |
3840a656 | 680 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
40f5cf99 AD |
681 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
682 | ||
3840a656 | 683 | if (gtt && gtt->userptr) { |
f72a113a CK |
684 | kfree(ttm->sg); |
685 | ttm->page_flags &= ~TTM_PAGE_FLAG_SG; | |
686 | return; | |
687 | } | |
688 | ||
40f5cf99 AD |
689 | if (slave) |
690 | return; | |
c52494f6 KRW |
691 | |
692 | rdev = radeon_get_rdev(ttm->bdev); | |
a7fb8a23 | 693 | #if IS_ENABLED(CONFIG_AGP) |
dea7e0ac JG |
694 | if (rdev->flags & RADEON_IS_AGP) { |
695 | ttm_agp_tt_unpopulate(ttm); | |
696 | return; | |
697 | } | |
698 | #endif | |
c52494f6 KRW |
699 | |
700 | #ifdef CONFIG_SWIOTLB | |
1bc3d3cc | 701 | if (rdev->need_swiotlb && swiotlb_nr_tbl()) { |
8e7e7052 | 702 | ttm_dma_unpopulate(>t->ttm, rdev->dev); |
c52494f6 KRW |
703 | return; |
704 | } | |
705 | #endif | |
706 | ||
f7871fd1 | 707 | ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm); |
c52494f6 | 708 | } |
649bf3ca | 709 | |
f72a113a CK |
710 | int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
711 | uint32_t flags) | |
712 | { | |
3840a656 | 713 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
f72a113a CK |
714 | |
715 | if (gtt == NULL) | |
716 | return -EINVAL; | |
717 | ||
718 | gtt->userptr = addr; | |
719 | gtt->usermm = current->mm; | |
720 | gtt->userflags = flags; | |
721 | return 0; | |
722 | } | |
723 | ||
724 | bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm) | |
725 | { | |
3840a656 | 726 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
f72a113a CK |
727 | |
728 | if (gtt == NULL) | |
729 | return false; | |
730 | ||
731 | return !!gtt->userptr; | |
732 | } | |
733 | ||
734 | bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm) | |
735 | { | |
3840a656 | 736 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
f72a113a CK |
737 | |
738 | if (gtt == NULL) | |
739 | return false; | |
740 | ||
741 | return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
742 | } | |
743 | ||
771fe6b9 | 744 | static struct ttm_bo_driver radeon_bo_driver = { |
649bf3ca | 745 | .ttm_tt_create = &radeon_ttm_tt_create, |
c52494f6 KRW |
746 | .ttm_tt_populate = &radeon_ttm_tt_populate, |
747 | .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, | |
a2ab19fe | 748 | .eviction_valuable = ttm_bo_eviction_valuable, |
771fe6b9 JG |
749 | .evict_flags = &radeon_evict_flags, |
750 | .move = &radeon_bo_move, | |
751 | .verify_access = &radeon_verify_access, | |
e024e110 DA |
752 | .move_notify = &radeon_bo_move_notify, |
753 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, | |
0a2d50e3 | 754 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
771fe6b9 JG |
755 | }; |
756 | ||
757 | int radeon_ttm_init(struct radeon_device *rdev) | |
758 | { | |
759 | int r; | |
760 | ||
771fe6b9 JG |
761 | /* No others user of address space so set it to 0 */ |
762 | r = ttm_bo_device_init(&rdev->mman.bdev, | |
44d847b7 DH |
763 | &radeon_bo_driver, |
764 | rdev->ddev->anon_inode->i_mapping, | |
8b53e1cb | 765 | rdev->ddev->vma_offset_manager, |
33b3ad37 | 766 | dma_addressing_limited(&rdev->pdev->dev)); |
771fe6b9 JG |
767 | if (r) { |
768 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
769 | return r; | |
770 | } | |
0a0c7596 | 771 | rdev->mman.initialized = true; |
b0691b34 CK |
772 | |
773 | r = radeon_ttm_init_vram(rdev); | |
771fe6b9 JG |
774 | if (r) { |
775 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
776 | return r; | |
777 | } | |
14eedc32 LK |
778 | /* Change the size here instead of the init above so only lpfn is affected */ |
779 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
780 | ||
441921d5 | 781 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
831b6966 | 782 | RADEON_GEM_DOMAIN_VRAM, 0, NULL, |
4aa5b92f | 783 | NULL, &rdev->stolen_vga_memory); |
771fe6b9 JG |
784 | if (r) { |
785 | return r; | |
786 | } | |
4aa5b92f | 787 | r = radeon_bo_reserve(rdev->stolen_vga_memory, false); |
4c788679 JG |
788 | if (r) |
789 | return r; | |
4aa5b92f KR |
790 | r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); |
791 | radeon_bo_unreserve(rdev->stolen_vga_memory); | |
771fe6b9 | 792 | if (r) { |
4aa5b92f | 793 | radeon_bo_unref(&rdev->stolen_vga_memory); |
771fe6b9 JG |
794 | return r; |
795 | } | |
796 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | |
fc986034 | 797 | (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); |
b0691b34 CK |
798 | |
799 | r = radeon_ttm_init_gtt(rdev); | |
771fe6b9 JG |
800 | if (r) { |
801 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
802 | return r; | |
803 | } | |
804 | DRM_INFO("radeon: %uM of GTT memory ready.\n", | |
3ce0a23d | 805 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
fa8a1238 DA |
806 | |
807 | r = radeon_ttm_debugfs_init(rdev); | |
808 | if (r) { | |
809 | DRM_ERROR("Failed to init debugfs\n"); | |
810 | return r; | |
811 | } | |
771fe6b9 JG |
812 | return 0; |
813 | } | |
814 | ||
815 | void radeon_ttm_fini(struct radeon_device *rdev) | |
816 | { | |
4c788679 JG |
817 | int r; |
818 | ||
0a0c7596 JG |
819 | if (!rdev->mman.initialized) |
820 | return; | |
2014b569 | 821 | radeon_ttm_debugfs_fini(rdev); |
4aa5b92f KR |
822 | if (rdev->stolen_vga_memory) { |
823 | r = radeon_bo_reserve(rdev->stolen_vga_memory, false); | |
4c788679 | 824 | if (r == 0) { |
4aa5b92f KR |
825 | radeon_bo_unpin(rdev->stolen_vga_memory); |
826 | radeon_bo_unreserve(rdev->stolen_vga_memory); | |
4c788679 | 827 | } |
4aa5b92f | 828 | radeon_bo_unref(&rdev->stolen_vga_memory); |
771fe6b9 | 829 | } |
47c0550f DA |
830 | ttm_range_man_fini(&rdev->mman.bdev, ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM)); |
831 | ttm_range_man_fini(&rdev->mman.bdev, ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT)); | |
771fe6b9 JG |
832 | ttm_bo_device_release(&rdev->mman.bdev); |
833 | radeon_gart_fini(rdev); | |
0a0c7596 | 834 | rdev->mman.initialized = false; |
771fe6b9 JG |
835 | DRM_INFO("radeon: ttm finalized\n"); |
836 | } | |
837 | ||
53595338 DA |
838 | /* this should only be called at bootup or when userspace |
839 | * isn't running */ | |
840 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) | |
841 | { | |
842 | struct ttm_mem_type_manager *man; | |
843 | ||
844 | if (!rdev->mman.initialized) | |
845 | return; | |
846 | ||
47c0550f | 847 | man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); |
53595338 DA |
848 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ |
849 | man->size = size >> PAGE_SHIFT; | |
850 | } | |
851 | ||
2bfb0b67 | 852 | static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf) |
771fe6b9 JG |
853 | { |
854 | struct ttm_buffer_object *bo; | |
5876dd24 | 855 | struct radeon_device *rdev; |
2bfb0b67 | 856 | vm_fault_t ret; |
771fe6b9 | 857 | |
11bac800 | 858 | bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data; |
165d3448 | 859 | if (bo == NULL) |
771fe6b9 | 860 | return VM_FAULT_NOPAGE; |
165d3448 | 861 | |
5876dd24 | 862 | rdev = radeon_get_rdev(bo->bdev); |
db7fce39 | 863 | down_read(&rdev->pm.mclk_lock); |
165d3448 | 864 | ret = ttm_bo_vm_fault(vmf); |
db7fce39 | 865 | up_read(&rdev->pm.mclk_lock); |
2bfb0b67 | 866 | return ret; |
771fe6b9 JG |
867 | } |
868 | ||
165d3448 CK |
869 | static struct vm_operations_struct radeon_ttm_vm_ops = { |
870 | .fault = radeon_ttm_fault, | |
871 | .open = ttm_bo_vm_open, | |
872 | .close = ttm_bo_vm_close, | |
873 | .access = ttm_bo_vm_access | |
874 | }; | |
875 | ||
771fe6b9 JG |
876 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) |
877 | { | |
771fe6b9 | 878 | int r; |
bed2dd84 TZ |
879 | struct drm_file *file_priv = filp->private_data; |
880 | struct radeon_device *rdev = file_priv->minor->dev->dev_private; | |
771fe6b9 | 881 | |
165d3448 | 882 | if (rdev == NULL) |
771fe6b9 | 883 | return -EINVAL; |
165d3448 | 884 | |
771fe6b9 | 885 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); |
165d3448 | 886 | if (unlikely(r != 0)) |
771fe6b9 | 887 | return r; |
165d3448 | 888 | |
771fe6b9 JG |
889 | vma->vm_ops = &radeon_ttm_vm_ops; |
890 | return 0; | |
891 | } | |
892 | ||
fa8a1238 | 893 | #if defined(CONFIG_DEBUG_FS) |
893d6e6e | 894 | |
fa8a1238 DA |
895 | static int radeon_mm_dump_table(struct seq_file *m, void *data) |
896 | { | |
897 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
bbbb29ef | 898 | unsigned ttm_pl = *(int*)node->info_ent->data; |
fa8a1238 DA |
899 | struct drm_device *dev = node->minor->dev; |
900 | struct radeon_device *rdev = dev->dev_private; | |
47c0550f | 901 | struct ttm_mem_type_manager *man = ttm_manager_type(&rdev->mman.bdev, ttm_pl); |
b5c3714f | 902 | struct drm_printer p = drm_seq_file_printer(m); |
fa8a1238 | 903 | |
bbbb29ef | 904 | man->func->debug(man, &p); |
b5c3714f | 905 | return 0; |
fa8a1238 | 906 | } |
893d6e6e | 907 | |
bbbb29ef | 908 | |
893d6e6e CK |
909 | static int ttm_pl_vram = TTM_PL_VRAM; |
910 | static int ttm_pl_tt = TTM_PL_TT; | |
911 | ||
912 | static struct drm_info_list radeon_ttm_debugfs_list[] = { | |
913 | {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, | |
914 | {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, | |
915 | {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, | |
916 | #ifdef CONFIG_SWIOTLB | |
917 | {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} | |
918 | #endif | |
919 | }; | |
920 | ||
2014b569 CK |
921 | static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) |
922 | { | |
923 | struct radeon_device *rdev = inode->i_private; | |
924 | i_size_write(inode, rdev->mc.mc_vram_size); | |
925 | filep->private_data = inode->i_private; | |
926 | return 0; | |
927 | } | |
928 | ||
929 | static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, | |
930 | size_t size, loff_t *pos) | |
931 | { | |
932 | struct radeon_device *rdev = f->private_data; | |
933 | ssize_t result = 0; | |
934 | int r; | |
935 | ||
936 | if (size & 0x3 || *pos & 0x3) | |
937 | return -EINVAL; | |
938 | ||
939 | while (size) { | |
940 | unsigned long flags; | |
941 | uint32_t value; | |
942 | ||
943 | if (*pos >= rdev->mc.mc_vram_size) | |
944 | return result; | |
945 | ||
946 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
947 | WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); | |
948 | if (rdev->family >= CHIP_CEDAR) | |
949 | WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); | |
950 | value = RREG32(RADEON_MM_DATA); | |
951 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); | |
952 | ||
953 | r = put_user(value, (uint32_t *)buf); | |
954 | if (r) | |
955 | return r; | |
956 | ||
957 | result += 4; | |
958 | buf += 4; | |
959 | *pos += 4; | |
960 | size -= 4; | |
961 | } | |
962 | ||
963 | return result; | |
964 | } | |
965 | ||
966 | static const struct file_operations radeon_ttm_vram_fops = { | |
967 | .owner = THIS_MODULE, | |
968 | .open = radeon_ttm_vram_open, | |
969 | .read = radeon_ttm_vram_read, | |
970 | .llseek = default_llseek | |
971 | }; | |
972 | ||
dd66d20e CK |
973 | static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) |
974 | { | |
975 | struct radeon_device *rdev = inode->i_private; | |
976 | i_size_write(inode, rdev->mc.gtt_size); | |
977 | filep->private_data = inode->i_private; | |
978 | return 0; | |
979 | } | |
980 | ||
981 | static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, | |
982 | size_t size, loff_t *pos) | |
983 | { | |
984 | struct radeon_device *rdev = f->private_data; | |
985 | ssize_t result = 0; | |
986 | int r; | |
987 | ||
988 | while (size) { | |
989 | loff_t p = *pos / PAGE_SIZE; | |
990 | unsigned off = *pos & ~PAGE_MASK; | |
0d997b68 | 991 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); |
dd66d20e CK |
992 | struct page *page; |
993 | void *ptr; | |
994 | ||
995 | if (p >= rdev->gart.num_cpu_pages) | |
996 | return result; | |
997 | ||
998 | page = rdev->gart.pages[p]; | |
999 | if (page) { | |
1000 | ptr = kmap(page); | |
1001 | ptr += off; | |
1002 | ||
1003 | r = copy_to_user(buf, ptr, cur_size); | |
1004 | kunmap(rdev->gart.pages[p]); | |
1005 | } else | |
1006 | r = clear_user(buf, cur_size); | |
1007 | ||
1008 | if (r) | |
1009 | return -EFAULT; | |
1010 | ||
1011 | result += cur_size; | |
1012 | buf += cur_size; | |
1013 | *pos += cur_size; | |
1014 | size -= cur_size; | |
1015 | } | |
1016 | ||
1017 | return result; | |
1018 | } | |
1019 | ||
1020 | static const struct file_operations radeon_ttm_gtt_fops = { | |
1021 | .owner = THIS_MODULE, | |
1022 | .open = radeon_ttm_gtt_open, | |
1023 | .read = radeon_ttm_gtt_read, | |
1024 | .llseek = default_llseek | |
1025 | }; | |
1026 | ||
fa8a1238 DA |
1027 | #endif |
1028 | ||
1029 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | |
1030 | { | |
f4e45d02 | 1031 | #if defined(CONFIG_DEBUG_FS) |
2014b569 CK |
1032 | unsigned count; |
1033 | ||
1034 | struct drm_minor *minor = rdev->ddev->primary; | |
bb1d26b4 GKH |
1035 | struct dentry *root = minor->debugfs_root; |
1036 | ||
1037 | rdev->mman.vram = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, | |
1038 | root, rdev, | |
1039 | &radeon_ttm_vram_fops); | |
1040 | ||
1041 | rdev->mman.gtt = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, | |
1042 | root, rdev, &radeon_ttm_gtt_fops); | |
dd66d20e | 1043 | |
2014b569 | 1044 | count = ARRAY_SIZE(radeon_ttm_debugfs_list); |
fa8a1238 | 1045 | |
c52494f6 | 1046 | #ifdef CONFIG_SWIOTLB |
1bc3d3cc | 1047 | if (!(rdev->need_swiotlb && swiotlb_nr_tbl())) |
893d6e6e | 1048 | --count; |
c52494f6 | 1049 | #endif |
fa8a1238 | 1050 | |
893d6e6e CK |
1051 | return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); |
1052 | #else | |
1053 | ||
fa8a1238 | 1054 | return 0; |
893d6e6e | 1055 | #endif |
fa8a1238 | 1056 | } |
2014b569 CK |
1057 | |
1058 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) | |
1059 | { | |
1060 | #if defined(CONFIG_DEBUG_FS) | |
1061 | ||
1062 | debugfs_remove(rdev->mman.vram); | |
1063 | rdev->mman.vram = NULL; | |
dd66d20e CK |
1064 | |
1065 | debugfs_remove(rdev->mman.gtt); | |
1066 | rdev->mman.gtt = NULL; | |
2014b569 CK |
1067 | #endif |
1068 | } |