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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
f9183127 SR |
32 | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/pagemap.h> | |
2ef79416 | 35 | #include <linux/pci.h> |
f9183127 SR |
36 | #include <linux/seq_file.h> |
37 | #include <linux/slab.h> | |
38 | #include <linux/swap.h> | |
39 | #include <linux/swiotlb.h> | |
40 | ||
41 | #include <drm/drm_agpsupport.h> | |
42 | #include <drm/drm_debugfs.h> | |
43 | #include <drm/drm_device.h> | |
44 | #include <drm/drm_file.h> | |
f9183127 SR |
45 | #include <drm/drm_prime.h> |
46 | #include <drm/radeon_drm.h> | |
64a9dfc4 MY |
47 | #include <drm/ttm/ttm_bo_api.h> |
48 | #include <drm/ttm/ttm_bo_driver.h> | |
64a9dfc4 MY |
49 | #include <drm/ttm/ttm_module.h> |
50 | #include <drm/ttm/ttm_page_alloc.h> | |
f9183127 SR |
51 | #include <drm/ttm/ttm_placement.h> |
52 | ||
771fe6b9 JG |
53 | #include "radeon_reg.h" |
54 | #include "radeon.h" | |
55 | ||
fa8a1238 | 56 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
2014b569 | 57 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); |
fa8a1238 | 58 | |
a0e4a298 | 59 | struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
771fe6b9 JG |
60 | { |
61 | struct radeon_mman *mman; | |
62 | struct radeon_device *rdev; | |
63 | ||
64 | mman = container_of(bdev, struct radeon_mman, bdev); | |
65 | rdev = container_of(mman, struct radeon_device, mman); | |
66 | return rdev; | |
67 | } | |
68 | ||
b0691b34 CK |
69 | static int radeon_ttm_init_vram(struct radeon_device *rdev) |
70 | { | |
71 | struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[TTM_PL_VRAM]; | |
771fe6b9 | 72 | |
b0691b34 CK |
73 | man->func = &ttm_bo_manager_func; |
74 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; | |
75 | man->default_caching = TTM_PL_FLAG_WC; | |
76 | ||
77 | return ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, | |
78 | rdev->mc.real_vram_size >> PAGE_SHIFT); | |
79 | } | |
80 | ||
81 | static int radeon_ttm_init_gtt(struct radeon_device *rdev) | |
82 | { | |
83 | struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[TTM_PL_TT]; | |
84 | ||
85 | man->func = &ttm_bo_manager_func; | |
86 | man->available_caching = TTM_PL_MASK_CACHING; | |
87 | man->default_caching = TTM_PL_FLAG_CACHED; | |
88 | man->use_tt = true; | |
a7fb8a23 | 89 | #if IS_ENABLED(CONFIG_AGP) |
b0691b34 CK |
90 | if (rdev->flags & RADEON_IS_AGP) { |
91 | if (!rdev->ddev->agp) { | |
92 | DRM_ERROR("AGP is not enabled\n"); | |
93 | return -EINVAL; | |
771fe6b9 | 94 | } |
b0691b34 CK |
95 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
96 | TTM_PL_FLAG_WC; | |
771fe6b9 | 97 | man->default_caching = TTM_PL_FLAG_WC; |
771fe6b9 | 98 | } |
b0691b34 CK |
99 | #endif |
100 | ||
101 | return ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, | |
102 | rdev->mc.gtt_size >> PAGE_SHIFT); | |
771fe6b9 JG |
103 | } |
104 | ||
312ea8da JG |
105 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
106 | struct ttm_placement *placement) | |
771fe6b9 | 107 | { |
46886dbf | 108 | static const struct ttm_place placements = { |
f1217ed0 CK |
109 | .fpfn = 0, |
110 | .lpfn = 0, | |
111 | .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM | |
112 | }; | |
113 | ||
d03d8589 | 114 | struct radeon_bo *rbo; |
d03d8589 JG |
115 | |
116 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { | |
d03d8589 JG |
117 | placement->placement = &placements; |
118 | placement->busy_placement = &placements; | |
119 | placement->num_placement = 1; | |
120 | placement->num_busy_placement = 1; | |
121 | return; | |
122 | } | |
123 | rbo = container_of(bo, struct radeon_bo, tbo); | |
771fe6b9 | 124 | switch (bo->mem.mem_type) { |
312ea8da | 125 | case TTM_PL_VRAM: |
5e5c21ca | 126 | if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) |
9270eb1b | 127 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
2a85aedd MD |
128 | else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && |
129 | bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { | |
130 | unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
131 | int i; | |
132 | ||
133 | /* Try evicting to the CPU inaccessible part of VRAM | |
134 | * first, but only set GTT as busy placement, so this | |
135 | * BO will be evicted to GTT rather than causing other | |
136 | * BOs to be evicted from VRAM | |
137 | */ | |
138 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | | |
139 | RADEON_GEM_DOMAIN_GTT); | |
140 | rbo->placement.num_busy_placement = 0; | |
141 | for (i = 0; i < rbo->placement.num_placement; i++) { | |
142 | if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { | |
ce4b4f22 MD |
143 | if (rbo->placements[i].fpfn < fpfn) |
144 | rbo->placements[i].fpfn = fpfn; | |
2a85aedd MD |
145 | } else { |
146 | rbo->placement.busy_placement = | |
147 | &rbo->placements[i]; | |
148 | rbo->placement.num_busy_placement = 1; | |
149 | } | |
150 | } | |
151 | } else | |
9270eb1b | 152 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); |
312ea8da JG |
153 | break; |
154 | case TTM_PL_TT: | |
771fe6b9 | 155 | default: |
312ea8da | 156 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
771fe6b9 | 157 | } |
eaa5fd1a | 158 | *placement = rbo->placement; |
771fe6b9 JG |
159 | } |
160 | ||
161 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
162 | { | |
acb46527 DH |
163 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
164 | ||
b5dcec69 JG |
165 | if (radeon_ttm_tt_has_userptr(bo->ttm)) |
166 | return -EPERM; | |
ce77038f | 167 | return drm_vma_node_verify_access(&rbo->tbo.base.vma_node, |
d9a1f0b4 | 168 | filp->private_data); |
771fe6b9 JG |
169 | } |
170 | ||
171 | static void radeon_move_null(struct ttm_buffer_object *bo, | |
172 | struct ttm_mem_reg *new_mem) | |
173 | { | |
174 | struct ttm_mem_reg *old_mem = &bo->mem; | |
175 | ||
176 | BUG_ON(old_mem->mm_node != NULL); | |
177 | *old_mem = *new_mem; | |
178 | new_mem->mm_node = NULL; | |
179 | } | |
180 | ||
181 | static int radeon_move_blit(struct ttm_buffer_object *bo, | |
97a875cb | 182 | bool evict, bool no_wait_gpu, |
9d87fa21 JG |
183 | struct ttm_mem_reg *new_mem, |
184 | struct ttm_mem_reg *old_mem) | |
771fe6b9 JG |
185 | { |
186 | struct radeon_device *rdev; | |
187 | uint64_t old_start, new_start; | |
876dc9f3 | 188 | struct radeon_fence *fence; |
57d20a43 | 189 | unsigned num_pages; |
876dc9f3 | 190 | int r, ridx; |
771fe6b9 JG |
191 | |
192 | rdev = radeon_get_rdev(bo->bdev); | |
876dc9f3 | 193 | ridx = radeon_copy_ring_index(rdev); |
13f479b9 CK |
194 | old_start = (u64)old_mem->start << PAGE_SHIFT; |
195 | new_start = (u64)new_mem->start << PAGE_SHIFT; | |
771fe6b9 JG |
196 | |
197 | switch (old_mem->mem_type) { | |
198 | case TTM_PL_VRAM: | |
d594e46a | 199 | old_start += rdev->mc.vram_start; |
771fe6b9 JG |
200 | break; |
201 | case TTM_PL_TT: | |
d594e46a | 202 | old_start += rdev->mc.gtt_start; |
771fe6b9 JG |
203 | break; |
204 | default: | |
205 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
206 | return -EINVAL; | |
207 | } | |
208 | switch (new_mem->mem_type) { | |
209 | case TTM_PL_VRAM: | |
d594e46a | 210 | new_start += rdev->mc.vram_start; |
771fe6b9 JG |
211 | break; |
212 | case TTM_PL_TT: | |
d594e46a | 213 | new_start += rdev->mc.gtt_start; |
771fe6b9 JG |
214 | break; |
215 | default: | |
216 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
217 | return -EINVAL; | |
218 | } | |
876dc9f3 | 219 | if (!rdev->ring[ridx].ready) { |
3000bf39 | 220 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
771fe6b9 JG |
221 | return -EINVAL; |
222 | } | |
003cefe0 AD |
223 | |
224 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); | |
225 | ||
57d20a43 | 226 | num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); |
336ac942 | 227 | fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv); |
57d20a43 CK |
228 | if (IS_ERR(fence)) |
229 | return PTR_ERR(fence); | |
230 | ||
74561cd4 | 231 | r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem); |
771fe6b9 JG |
232 | radeon_fence_unref(&fence); |
233 | return r; | |
234 | } | |
235 | ||
236 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, | |
9d87fa21 | 237 | bool evict, bool interruptible, |
97a875cb | 238 | bool no_wait_gpu, |
771fe6b9 JG |
239 | struct ttm_mem_reg *new_mem) |
240 | { | |
c13c55d6 | 241 | struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; |
771fe6b9 JG |
242 | struct ttm_mem_reg *old_mem = &bo->mem; |
243 | struct ttm_mem_reg tmp_mem; | |
f1217ed0 | 244 | struct ttm_place placements; |
312ea8da | 245 | struct ttm_placement placement; |
771fe6b9 JG |
246 | int r; |
247 | ||
771fe6b9 JG |
248 | tmp_mem = *new_mem; |
249 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
250 | placement.num_placement = 1; |
251 | placement.placement = &placements; | |
252 | placement.num_busy_placement = 1; | |
253 | placement.busy_placement = &placements; | |
f1217ed0 CK |
254 | placements.fpfn = 0; |
255 | placements.lpfn = 0; | |
256 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
c13c55d6 | 257 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); |
771fe6b9 JG |
258 | if (unlikely(r)) { |
259 | return r; | |
260 | } | |
df67bed9 DA |
261 | |
262 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); | |
263 | if (unlikely(r)) { | |
264 | goto out_cleanup; | |
265 | } | |
266 | ||
993baf15 | 267 | r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx); |
771fe6b9 JG |
268 | if (unlikely(r)) { |
269 | goto out_cleanup; | |
270 | } | |
97a875cb | 271 | r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); |
771fe6b9 JG |
272 | if (unlikely(r)) { |
273 | goto out_cleanup; | |
274 | } | |
3e98d829 | 275 | r = ttm_bo_move_ttm(bo, &ctx, new_mem); |
771fe6b9 | 276 | out_cleanup: |
42311ff9 | 277 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
278 | return r; |
279 | } | |
280 | ||
281 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, | |
9d87fa21 | 282 | bool evict, bool interruptible, |
97a875cb | 283 | bool no_wait_gpu, |
771fe6b9 JG |
284 | struct ttm_mem_reg *new_mem) |
285 | { | |
c13c55d6 | 286 | struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; |
771fe6b9 JG |
287 | struct ttm_mem_reg *old_mem = &bo->mem; |
288 | struct ttm_mem_reg tmp_mem; | |
312ea8da | 289 | struct ttm_placement placement; |
f1217ed0 | 290 | struct ttm_place placements; |
771fe6b9 JG |
291 | int r; |
292 | ||
771fe6b9 JG |
293 | tmp_mem = *new_mem; |
294 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
295 | placement.num_placement = 1; |
296 | placement.placement = &placements; | |
297 | placement.num_busy_placement = 1; | |
298 | placement.busy_placement = &placements; | |
f1217ed0 CK |
299 | placements.fpfn = 0; |
300 | placements.lpfn = 0; | |
301 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
c13c55d6 | 302 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); |
771fe6b9 JG |
303 | if (unlikely(r)) { |
304 | return r; | |
305 | } | |
3e98d829 | 306 | r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem); |
771fe6b9 JG |
307 | if (unlikely(r)) { |
308 | goto out_cleanup; | |
309 | } | |
97a875cb | 310 | r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); |
771fe6b9 JG |
311 | if (unlikely(r)) { |
312 | goto out_cleanup; | |
313 | } | |
314 | out_cleanup: | |
42311ff9 | 315 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
316 | return r; |
317 | } | |
318 | ||
2823f4f0 CK |
319 | static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, |
320 | struct ttm_operation_ctx *ctx, | |
321 | struct ttm_mem_reg *new_mem) | |
771fe6b9 JG |
322 | { |
323 | struct radeon_device *rdev; | |
e1a575ad | 324 | struct radeon_bo *rbo; |
771fe6b9 JG |
325 | struct ttm_mem_reg *old_mem = &bo->mem; |
326 | int r; | |
327 | ||
2823f4f0 | 328 | r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); |
88932a7b CK |
329 | if (r) |
330 | return r; | |
331 | ||
e1a575ad MD |
332 | /* Can't move a pinned BO */ |
333 | rbo = container_of(bo, struct radeon_bo, tbo); | |
334 | if (WARN_ON_ONCE(rbo->pin_count > 0)) | |
335 | return -EINVAL; | |
336 | ||
771fe6b9 JG |
337 | rdev = radeon_get_rdev(bo->bdev); |
338 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { | |
339 | radeon_move_null(bo, new_mem); | |
340 | return 0; | |
341 | } | |
342 | if ((old_mem->mem_type == TTM_PL_TT && | |
343 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
344 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
345 | new_mem->mem_type == TTM_PL_TT)) { | |
af901ca1 | 346 | /* bind is enough */ |
771fe6b9 JG |
347 | radeon_move_null(bo, new_mem); |
348 | return 0; | |
349 | } | |
27cd7769 AD |
350 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || |
351 | rdev->asic->copy.copy == NULL) { | |
771fe6b9 | 352 | /* use memcpy */ |
1ab2e105 | 353 | goto memcpy; |
771fe6b9 JG |
354 | } |
355 | ||
356 | if (old_mem->mem_type == TTM_PL_VRAM && | |
357 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
2823f4f0 CK |
358 | r = radeon_move_vram_ram(bo, evict, ctx->interruptible, |
359 | ctx->no_wait_gpu, new_mem); | |
771fe6b9 JG |
360 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
361 | new_mem->mem_type == TTM_PL_VRAM) { | |
2823f4f0 CK |
362 | r = radeon_move_ram_vram(bo, evict, ctx->interruptible, |
363 | ctx->no_wait_gpu, new_mem); | |
771fe6b9 | 364 | } else { |
2823f4f0 CK |
365 | r = radeon_move_blit(bo, evict, ctx->no_wait_gpu, |
366 | new_mem, old_mem); | |
771fe6b9 | 367 | } |
1ab2e105 MD |
368 | |
369 | if (r) { | |
370 | memcpy: | |
3e98d829 | 371 | r = ttm_bo_move_memcpy(bo, ctx, new_mem); |
67e8e3f9 MO |
372 | if (r) { |
373 | return r; | |
374 | } | |
1ab2e105 | 375 | } |
67e8e3f9 MO |
376 | |
377 | /* update statistics */ | |
378 | atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); | |
379 | return 0; | |
771fe6b9 JG |
380 | } |
381 | ||
0a2d50e3 JG |
382 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
383 | { | |
0a2d50e3 JG |
384 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
385 | ||
386 | mem->bus.addr = NULL; | |
387 | mem->bus.offset = 0; | |
388 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
389 | mem->bus.base = 0; | |
390 | mem->bus.is_iomem = false; | |
8401e2ed | 391 | |
0a2d50e3 JG |
392 | switch (mem->mem_type) { |
393 | case TTM_PL_SYSTEM: | |
394 | /* system memory */ | |
395 | return 0; | |
396 | case TTM_PL_TT: | |
a7fb8a23 | 397 | #if IS_ENABLED(CONFIG_AGP) |
0a2d50e3 JG |
398 | if (rdev->flags & RADEON_IS_AGP) { |
399 | /* RADEON_IS_AGP is set only if AGP is active */ | |
d961db75 | 400 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 | 401 | mem->bus.base = rdev->mc.agp_base; |
365048ff | 402 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
0a2d50e3 JG |
403 | } |
404 | #endif | |
405 | break; | |
406 | case TTM_PL_VRAM: | |
d961db75 | 407 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 JG |
408 | /* check if it's visible */ |
409 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) | |
410 | return -EINVAL; | |
411 | mem->bus.base = rdev->mc.aper_base; | |
412 | mem->bus.is_iomem = true; | |
ffb57c4b JE |
413 | #ifdef __alpha__ |
414 | /* | |
415 | * Alpha: use bus.addr to hold the ioremap() return, | |
416 | * so we can modify bus.base below. | |
417 | */ | |
418 | if (mem->placement & TTM_PL_FLAG_WC) | |
419 | mem->bus.addr = | |
420 | ioremap_wc(mem->bus.base + mem->bus.offset, | |
421 | mem->bus.size); | |
422 | else | |
423 | mem->bus.addr = | |
4bdc0d67 | 424 | ioremap(mem->bus.base + mem->bus.offset, |
ffb57c4b | 425 | mem->bus.size); |
3b2c6932 AY |
426 | if (!mem->bus.addr) |
427 | return -ENOMEM; | |
ffb57c4b JE |
428 | |
429 | /* | |
430 | * Alpha: Use just the bus offset plus | |
431 | * the hose/domain memory base for bus.base. | |
432 | * It then can be used to build PTEs for VRAM | |
433 | * access, as done in ttm_bo_vm_fault(). | |
434 | */ | |
435 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + | |
436 | rdev->ddev->hose->dense_mem_base; | |
437 | #endif | |
0a2d50e3 JG |
438 | break; |
439 | default: | |
440 | return -EINVAL; | |
441 | } | |
442 | return 0; | |
443 | } | |
444 | ||
649bf3ca JG |
445 | /* |
446 | * TTM backend functions. | |
447 | */ | |
448 | struct radeon_ttm_tt { | |
8e7e7052 | 449 | struct ttm_dma_tt ttm; |
649bf3ca JG |
450 | struct radeon_device *rdev; |
451 | u64 offset; | |
f72a113a CK |
452 | |
453 | uint64_t userptr; | |
454 | struct mm_struct *usermm; | |
455 | uint32_t userflags; | |
649bf3ca JG |
456 | }; |
457 | ||
f72a113a CK |
458 | /* prepare the sg table with the user pages */ |
459 | static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm) | |
460 | { | |
461 | struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); | |
462 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
7b814900 | 463 | unsigned pinned = 0; |
f72a113a CK |
464 | int r; |
465 | ||
466 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
467 | enum dma_data_direction direction = write ? | |
468 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
469 | ||
470 | if (current->mm != gtt->usermm) | |
471 | return -EPERM; | |
472 | ||
ddd00e33 CK |
473 | if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { |
474 | /* check that we only pin down anonymous memory | |
475 | to prevent problems with writeback */ | |
476 | unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; | |
477 | struct vm_area_struct *vma; | |
478 | vma = find_vma(gtt->usermm, gtt->userptr); | |
479 | if (!vma || vma->vm_file || vma->vm_end < end) | |
480 | return -EPERM; | |
481 | } | |
482 | ||
f72a113a CK |
483 | do { |
484 | unsigned num_pages = ttm->num_pages - pinned; | |
485 | uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; | |
486 | struct page **pages = ttm->pages + pinned; | |
487 | ||
768ae309 LS |
488 | r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0, |
489 | pages, NULL); | |
f72a113a CK |
490 | if (r < 0) |
491 | goto release_pages; | |
492 | ||
493 | pinned += r; | |
494 | ||
495 | } while (pinned < ttm->num_pages); | |
496 | ||
497 | r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, | |
498 | ttm->num_pages << PAGE_SHIFT, | |
499 | GFP_KERNEL); | |
500 | if (r) | |
501 | goto release_sg; | |
502 | ||
7b814900 MS |
503 | r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0); |
504 | if (r) | |
f72a113a CK |
505 | goto release_sg; |
506 | ||
507 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
508 | gtt->ttm.dma_address, ttm->num_pages); | |
509 | ||
510 | return 0; | |
511 | ||
512 | release_sg: | |
513 | kfree(ttm->sg); | |
514 | ||
515 | release_pages: | |
c6f92f9f | 516 | release_pages(ttm->pages, pinned); |
f72a113a CK |
517 | return r; |
518 | } | |
519 | ||
520 | static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm) | |
521 | { | |
522 | struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); | |
523 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
db12973c | 524 | struct sg_page_iter sg_iter; |
f72a113a CK |
525 | |
526 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
527 | enum dma_data_direction direction = write ? | |
528 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
529 | ||
863653fe CK |
530 | /* double check that we don't free the table twice */ |
531 | if (!ttm->sg->sgl) | |
532 | return; | |
533 | ||
f72a113a | 534 | /* free the sg table and pages again */ |
7b814900 | 535 | dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0); |
f72a113a | 536 | |
7b814900 | 537 | for_each_sgtable_page(ttm->sg, &sg_iter, 0) { |
db12973c | 538 | struct page *page = sg_page_iter_page(&sg_iter); |
f72a113a CK |
539 | if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) |
540 | set_page_dirty(page); | |
541 | ||
542 | mark_page_accessed(page); | |
09cbfeaf | 543 | put_page(page); |
f72a113a CK |
544 | } |
545 | ||
546 | sg_free_table(ttm->sg); | |
547 | } | |
548 | ||
649bf3ca JG |
549 | static int radeon_ttm_backend_bind(struct ttm_tt *ttm, |
550 | struct ttm_mem_reg *bo_mem) | |
551 | { | |
8e7e7052 | 552 | struct radeon_ttm_tt *gtt = (void*)ttm; |
77497f27 MD |
553 | uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | |
554 | RADEON_GART_PAGE_WRITE; | |
649bf3ca JG |
555 | int r; |
556 | ||
f72a113a CK |
557 | if (gtt->userptr) { |
558 | radeon_ttm_tt_pin_userptr(ttm); | |
559 | flags &= ~RADEON_GART_PAGE_WRITE; | |
560 | } | |
561 | ||
649bf3ca JG |
562 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
563 | if (!ttm->num_pages) { | |
564 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", | |
565 | ttm->num_pages, bo_mem, ttm); | |
566 | } | |
77497f27 MD |
567 | if (ttm->caching_state == tt_cached) |
568 | flags |= RADEON_GART_PAGE_SNOOP; | |
569 | r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, | |
570 | ttm->pages, gtt->ttm.dma_address, flags); | |
649bf3ca JG |
571 | if (r) { |
572 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", | |
573 | ttm->num_pages, (unsigned)gtt->offset); | |
574 | return r; | |
575 | } | |
576 | return 0; | |
577 | } | |
578 | ||
579 | static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) | |
580 | { | |
8e7e7052 | 581 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 582 | |
649bf3ca | 583 | radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); |
f72a113a CK |
584 | |
585 | if (gtt->userptr) | |
586 | radeon_ttm_tt_unpin_userptr(ttm); | |
587 | ||
649bf3ca JG |
588 | return 0; |
589 | } | |
590 | ||
591 | static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) | |
592 | { | |
8e7e7052 | 593 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 594 | |
8e7e7052 | 595 | ttm_dma_tt_fini(>t->ttm); |
649bf3ca JG |
596 | kfree(gtt); |
597 | } | |
598 | ||
599 | static struct ttm_backend_func radeon_backend_func = { | |
600 | .bind = &radeon_ttm_backend_bind, | |
601 | .unbind = &radeon_ttm_backend_unbind, | |
602 | .destroy = &radeon_ttm_backend_destroy, | |
603 | }; | |
604 | ||
dde5da23 CK |
605 | static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo, |
606 | uint32_t page_flags) | |
649bf3ca JG |
607 | { |
608 | struct radeon_device *rdev; | |
609 | struct radeon_ttm_tt *gtt; | |
610 | ||
dde5da23 | 611 | rdev = radeon_get_rdev(bo->bdev); |
a7fb8a23 | 612 | #if IS_ENABLED(CONFIG_AGP) |
649bf3ca | 613 | if (rdev->flags & RADEON_IS_AGP) { |
dde5da23 CK |
614 | return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge, |
615 | page_flags); | |
649bf3ca JG |
616 | } |
617 | #endif | |
618 | ||
619 | gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); | |
620 | if (gtt == NULL) { | |
621 | return NULL; | |
622 | } | |
8e7e7052 | 623 | gtt->ttm.ttm.func = &radeon_backend_func; |
649bf3ca | 624 | gtt->rdev = rdev; |
dde5da23 | 625 | if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) { |
8e7e7052 | 626 | kfree(gtt); |
649bf3ca JG |
627 | return NULL; |
628 | } | |
8e7e7052 | 629 | return >t->ttm.ttm; |
649bf3ca JG |
630 | } |
631 | ||
3840a656 CK |
632 | static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm) |
633 | { | |
634 | if (!ttm || ttm->func != &radeon_backend_func) | |
635 | return NULL; | |
636 | return (struct radeon_ttm_tt *)ttm; | |
637 | } | |
638 | ||
d0cef9fa RH |
639 | static int radeon_ttm_tt_populate(struct ttm_tt *ttm, |
640 | struct ttm_operation_ctx *ctx) | |
c52494f6 | 641 | { |
3840a656 | 642 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
c52494f6 | 643 | struct radeon_device *rdev; |
40f5cf99 | 644 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
c52494f6 | 645 | |
3840a656 | 646 | if (gtt && gtt->userptr) { |
69ee2410 | 647 | ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); |
f72a113a CK |
648 | if (!ttm->sg) |
649 | return -ENOMEM; | |
650 | ||
651 | ttm->page_flags |= TTM_PAGE_FLAG_SG; | |
652 | ttm->state = tt_unbound; | |
653 | return 0; | |
654 | } | |
655 | ||
40f5cf99 AD |
656 | if (slave && ttm->sg) { |
657 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
658 | gtt->ttm.dma_address, ttm->num_pages); | |
659 | ttm->state = tt_unbound; | |
660 | return 0; | |
661 | } | |
662 | ||
c52494f6 | 663 | rdev = radeon_get_rdev(ttm->bdev); |
a7fb8a23 | 664 | #if IS_ENABLED(CONFIG_AGP) |
dea7e0ac | 665 | if (rdev->flags & RADEON_IS_AGP) { |
d0cef9fa | 666 | return ttm_agp_tt_populate(ttm, ctx); |
dea7e0ac JG |
667 | } |
668 | #endif | |
c52494f6 KRW |
669 | |
670 | #ifdef CONFIG_SWIOTLB | |
1bc3d3cc | 671 | if (rdev->need_swiotlb && swiotlb_nr_tbl()) { |
d0cef9fa | 672 | return ttm_dma_populate(>t->ttm, rdev->dev, ctx); |
c52494f6 KRW |
673 | } |
674 | #endif | |
675 | ||
d0cef9fa | 676 | return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx); |
c52494f6 KRW |
677 | } |
678 | ||
679 | static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
680 | { | |
681 | struct radeon_device *rdev; | |
3840a656 | 682 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
40f5cf99 AD |
683 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
684 | ||
3840a656 | 685 | if (gtt && gtt->userptr) { |
f72a113a CK |
686 | kfree(ttm->sg); |
687 | ttm->page_flags &= ~TTM_PAGE_FLAG_SG; | |
688 | return; | |
689 | } | |
690 | ||
40f5cf99 AD |
691 | if (slave) |
692 | return; | |
c52494f6 KRW |
693 | |
694 | rdev = radeon_get_rdev(ttm->bdev); | |
a7fb8a23 | 695 | #if IS_ENABLED(CONFIG_AGP) |
dea7e0ac JG |
696 | if (rdev->flags & RADEON_IS_AGP) { |
697 | ttm_agp_tt_unpopulate(ttm); | |
698 | return; | |
699 | } | |
700 | #endif | |
c52494f6 KRW |
701 | |
702 | #ifdef CONFIG_SWIOTLB | |
1bc3d3cc | 703 | if (rdev->need_swiotlb && swiotlb_nr_tbl()) { |
8e7e7052 | 704 | ttm_dma_unpopulate(>t->ttm, rdev->dev); |
c52494f6 KRW |
705 | return; |
706 | } | |
707 | #endif | |
708 | ||
f7871fd1 | 709 | ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm); |
c52494f6 | 710 | } |
649bf3ca | 711 | |
f72a113a CK |
712 | int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
713 | uint32_t flags) | |
714 | { | |
3840a656 | 715 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
f72a113a CK |
716 | |
717 | if (gtt == NULL) | |
718 | return -EINVAL; | |
719 | ||
720 | gtt->userptr = addr; | |
721 | gtt->usermm = current->mm; | |
722 | gtt->userflags = flags; | |
723 | return 0; | |
724 | } | |
725 | ||
726 | bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm) | |
727 | { | |
3840a656 | 728 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
f72a113a CK |
729 | |
730 | if (gtt == NULL) | |
731 | return false; | |
732 | ||
733 | return !!gtt->userptr; | |
734 | } | |
735 | ||
736 | bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm) | |
737 | { | |
3840a656 | 738 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
f72a113a CK |
739 | |
740 | if (gtt == NULL) | |
741 | return false; | |
742 | ||
743 | return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
744 | } | |
745 | ||
771fe6b9 | 746 | static struct ttm_bo_driver radeon_bo_driver = { |
649bf3ca | 747 | .ttm_tt_create = &radeon_ttm_tt_create, |
c52494f6 KRW |
748 | .ttm_tt_populate = &radeon_ttm_tt_populate, |
749 | .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, | |
a2ab19fe | 750 | .eviction_valuable = ttm_bo_eviction_valuable, |
771fe6b9 JG |
751 | .evict_flags = &radeon_evict_flags, |
752 | .move = &radeon_bo_move, | |
753 | .verify_access = &radeon_verify_access, | |
e024e110 DA |
754 | .move_notify = &radeon_bo_move_notify, |
755 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, | |
0a2d50e3 | 756 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
771fe6b9 JG |
757 | }; |
758 | ||
759 | int radeon_ttm_init(struct radeon_device *rdev) | |
760 | { | |
761 | int r; | |
762 | ||
771fe6b9 JG |
763 | /* No others user of address space so set it to 0 */ |
764 | r = ttm_bo_device_init(&rdev->mman.bdev, | |
44d847b7 DH |
765 | &radeon_bo_driver, |
766 | rdev->ddev->anon_inode->i_mapping, | |
8b53e1cb | 767 | rdev->ddev->vma_offset_manager, |
33b3ad37 | 768 | dma_addressing_limited(&rdev->pdev->dev)); |
771fe6b9 JG |
769 | if (r) { |
770 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
771 | return r; | |
772 | } | |
0a0c7596 | 773 | rdev->mman.initialized = true; |
b0691b34 CK |
774 | |
775 | r = radeon_ttm_init_vram(rdev); | |
771fe6b9 JG |
776 | if (r) { |
777 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
778 | return r; | |
779 | } | |
14eedc32 LK |
780 | /* Change the size here instead of the init above so only lpfn is affected */ |
781 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
782 | ||
441921d5 | 783 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
831b6966 | 784 | RADEON_GEM_DOMAIN_VRAM, 0, NULL, |
4aa5b92f | 785 | NULL, &rdev->stolen_vga_memory); |
771fe6b9 JG |
786 | if (r) { |
787 | return r; | |
788 | } | |
4aa5b92f | 789 | r = radeon_bo_reserve(rdev->stolen_vga_memory, false); |
4c788679 JG |
790 | if (r) |
791 | return r; | |
4aa5b92f KR |
792 | r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); |
793 | radeon_bo_unreserve(rdev->stolen_vga_memory); | |
771fe6b9 | 794 | if (r) { |
4aa5b92f | 795 | radeon_bo_unref(&rdev->stolen_vga_memory); |
771fe6b9 JG |
796 | return r; |
797 | } | |
798 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | |
fc986034 | 799 | (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); |
b0691b34 CK |
800 | |
801 | r = radeon_ttm_init_gtt(rdev); | |
771fe6b9 JG |
802 | if (r) { |
803 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
804 | return r; | |
805 | } | |
806 | DRM_INFO("radeon: %uM of GTT memory ready.\n", | |
3ce0a23d | 807 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
fa8a1238 DA |
808 | |
809 | r = radeon_ttm_debugfs_init(rdev); | |
810 | if (r) { | |
811 | DRM_ERROR("Failed to init debugfs\n"); | |
812 | return r; | |
813 | } | |
771fe6b9 JG |
814 | return 0; |
815 | } | |
816 | ||
817 | void radeon_ttm_fini(struct radeon_device *rdev) | |
818 | { | |
4c788679 JG |
819 | int r; |
820 | ||
0a0c7596 JG |
821 | if (!rdev->mman.initialized) |
822 | return; | |
2014b569 | 823 | radeon_ttm_debugfs_fini(rdev); |
4aa5b92f KR |
824 | if (rdev->stolen_vga_memory) { |
825 | r = radeon_bo_reserve(rdev->stolen_vga_memory, false); | |
4c788679 | 826 | if (r == 0) { |
4aa5b92f KR |
827 | radeon_bo_unpin(rdev->stolen_vga_memory); |
828 | radeon_bo_unreserve(rdev->stolen_vga_memory); | |
4c788679 | 829 | } |
4aa5b92f | 830 | radeon_bo_unref(&rdev->stolen_vga_memory); |
771fe6b9 JG |
831 | } |
832 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
833 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); | |
834 | ttm_bo_device_release(&rdev->mman.bdev); | |
835 | radeon_gart_fini(rdev); | |
0a0c7596 | 836 | rdev->mman.initialized = false; |
771fe6b9 JG |
837 | DRM_INFO("radeon: ttm finalized\n"); |
838 | } | |
839 | ||
53595338 DA |
840 | /* this should only be called at bootup or when userspace |
841 | * isn't running */ | |
842 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) | |
843 | { | |
844 | struct ttm_mem_type_manager *man; | |
845 | ||
846 | if (!rdev->mman.initialized) | |
847 | return; | |
848 | ||
849 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; | |
850 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ | |
851 | man->size = size >> PAGE_SHIFT; | |
852 | } | |
853 | ||
2bfb0b67 | 854 | static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf) |
771fe6b9 JG |
855 | { |
856 | struct ttm_buffer_object *bo; | |
5876dd24 | 857 | struct radeon_device *rdev; |
2bfb0b67 | 858 | vm_fault_t ret; |
771fe6b9 | 859 | |
11bac800 | 860 | bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data; |
165d3448 | 861 | if (bo == NULL) |
771fe6b9 | 862 | return VM_FAULT_NOPAGE; |
165d3448 | 863 | |
5876dd24 | 864 | rdev = radeon_get_rdev(bo->bdev); |
db7fce39 | 865 | down_read(&rdev->pm.mclk_lock); |
165d3448 | 866 | ret = ttm_bo_vm_fault(vmf); |
db7fce39 | 867 | up_read(&rdev->pm.mclk_lock); |
2bfb0b67 | 868 | return ret; |
771fe6b9 JG |
869 | } |
870 | ||
165d3448 CK |
871 | static struct vm_operations_struct radeon_ttm_vm_ops = { |
872 | .fault = radeon_ttm_fault, | |
873 | .open = ttm_bo_vm_open, | |
874 | .close = ttm_bo_vm_close, | |
875 | .access = ttm_bo_vm_access | |
876 | }; | |
877 | ||
771fe6b9 JG |
878 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) |
879 | { | |
771fe6b9 | 880 | int r; |
bed2dd84 TZ |
881 | struct drm_file *file_priv = filp->private_data; |
882 | struct radeon_device *rdev = file_priv->minor->dev->dev_private; | |
771fe6b9 | 883 | |
165d3448 | 884 | if (rdev == NULL) |
771fe6b9 | 885 | return -EINVAL; |
165d3448 | 886 | |
771fe6b9 | 887 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); |
165d3448 | 888 | if (unlikely(r != 0)) |
771fe6b9 | 889 | return r; |
165d3448 | 890 | |
771fe6b9 JG |
891 | vma->vm_ops = &radeon_ttm_vm_ops; |
892 | return 0; | |
893 | } | |
894 | ||
fa8a1238 | 895 | #if defined(CONFIG_DEBUG_FS) |
893d6e6e | 896 | |
fa8a1238 DA |
897 | static int radeon_mm_dump_table(struct seq_file *m, void *data) |
898 | { | |
899 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
bbbb29ef | 900 | unsigned ttm_pl = *(int*)node->info_ent->data; |
fa8a1238 DA |
901 | struct drm_device *dev = node->minor->dev; |
902 | struct radeon_device *rdev = dev->dev_private; | |
bbbb29ef | 903 | struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[ttm_pl]; |
b5c3714f | 904 | struct drm_printer p = drm_seq_file_printer(m); |
fa8a1238 | 905 | |
bbbb29ef | 906 | man->func->debug(man, &p); |
b5c3714f | 907 | return 0; |
fa8a1238 | 908 | } |
893d6e6e | 909 | |
bbbb29ef | 910 | |
893d6e6e CK |
911 | static int ttm_pl_vram = TTM_PL_VRAM; |
912 | static int ttm_pl_tt = TTM_PL_TT; | |
913 | ||
914 | static struct drm_info_list radeon_ttm_debugfs_list[] = { | |
915 | {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, | |
916 | {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, | |
917 | {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, | |
918 | #ifdef CONFIG_SWIOTLB | |
919 | {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} | |
920 | #endif | |
921 | }; | |
922 | ||
2014b569 CK |
923 | static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) |
924 | { | |
925 | struct radeon_device *rdev = inode->i_private; | |
926 | i_size_write(inode, rdev->mc.mc_vram_size); | |
927 | filep->private_data = inode->i_private; | |
928 | return 0; | |
929 | } | |
930 | ||
931 | static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, | |
932 | size_t size, loff_t *pos) | |
933 | { | |
934 | struct radeon_device *rdev = f->private_data; | |
935 | ssize_t result = 0; | |
936 | int r; | |
937 | ||
938 | if (size & 0x3 || *pos & 0x3) | |
939 | return -EINVAL; | |
940 | ||
941 | while (size) { | |
942 | unsigned long flags; | |
943 | uint32_t value; | |
944 | ||
945 | if (*pos >= rdev->mc.mc_vram_size) | |
946 | return result; | |
947 | ||
948 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
949 | WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); | |
950 | if (rdev->family >= CHIP_CEDAR) | |
951 | WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); | |
952 | value = RREG32(RADEON_MM_DATA); | |
953 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); | |
954 | ||
955 | r = put_user(value, (uint32_t *)buf); | |
956 | if (r) | |
957 | return r; | |
958 | ||
959 | result += 4; | |
960 | buf += 4; | |
961 | *pos += 4; | |
962 | size -= 4; | |
963 | } | |
964 | ||
965 | return result; | |
966 | } | |
967 | ||
968 | static const struct file_operations radeon_ttm_vram_fops = { | |
969 | .owner = THIS_MODULE, | |
970 | .open = radeon_ttm_vram_open, | |
971 | .read = radeon_ttm_vram_read, | |
972 | .llseek = default_llseek | |
973 | }; | |
974 | ||
dd66d20e CK |
975 | static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) |
976 | { | |
977 | struct radeon_device *rdev = inode->i_private; | |
978 | i_size_write(inode, rdev->mc.gtt_size); | |
979 | filep->private_data = inode->i_private; | |
980 | return 0; | |
981 | } | |
982 | ||
983 | static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, | |
984 | size_t size, loff_t *pos) | |
985 | { | |
986 | struct radeon_device *rdev = f->private_data; | |
987 | ssize_t result = 0; | |
988 | int r; | |
989 | ||
990 | while (size) { | |
991 | loff_t p = *pos / PAGE_SIZE; | |
992 | unsigned off = *pos & ~PAGE_MASK; | |
0d997b68 | 993 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); |
dd66d20e CK |
994 | struct page *page; |
995 | void *ptr; | |
996 | ||
997 | if (p >= rdev->gart.num_cpu_pages) | |
998 | return result; | |
999 | ||
1000 | page = rdev->gart.pages[p]; | |
1001 | if (page) { | |
1002 | ptr = kmap(page); | |
1003 | ptr += off; | |
1004 | ||
1005 | r = copy_to_user(buf, ptr, cur_size); | |
1006 | kunmap(rdev->gart.pages[p]); | |
1007 | } else | |
1008 | r = clear_user(buf, cur_size); | |
1009 | ||
1010 | if (r) | |
1011 | return -EFAULT; | |
1012 | ||
1013 | result += cur_size; | |
1014 | buf += cur_size; | |
1015 | *pos += cur_size; | |
1016 | size -= cur_size; | |
1017 | } | |
1018 | ||
1019 | return result; | |
1020 | } | |
1021 | ||
1022 | static const struct file_operations radeon_ttm_gtt_fops = { | |
1023 | .owner = THIS_MODULE, | |
1024 | .open = radeon_ttm_gtt_open, | |
1025 | .read = radeon_ttm_gtt_read, | |
1026 | .llseek = default_llseek | |
1027 | }; | |
1028 | ||
fa8a1238 DA |
1029 | #endif |
1030 | ||
1031 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | |
1032 | { | |
f4e45d02 | 1033 | #if defined(CONFIG_DEBUG_FS) |
2014b569 CK |
1034 | unsigned count; |
1035 | ||
1036 | struct drm_minor *minor = rdev->ddev->primary; | |
bb1d26b4 GKH |
1037 | struct dentry *root = minor->debugfs_root; |
1038 | ||
1039 | rdev->mman.vram = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, | |
1040 | root, rdev, | |
1041 | &radeon_ttm_vram_fops); | |
1042 | ||
1043 | rdev->mman.gtt = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, | |
1044 | root, rdev, &radeon_ttm_gtt_fops); | |
dd66d20e | 1045 | |
2014b569 | 1046 | count = ARRAY_SIZE(radeon_ttm_debugfs_list); |
fa8a1238 | 1047 | |
c52494f6 | 1048 | #ifdef CONFIG_SWIOTLB |
1bc3d3cc | 1049 | if (!(rdev->need_swiotlb && swiotlb_nr_tbl())) |
893d6e6e | 1050 | --count; |
c52494f6 | 1051 | #endif |
fa8a1238 | 1052 | |
893d6e6e CK |
1053 | return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); |
1054 | #else | |
1055 | ||
fa8a1238 | 1056 | return 0; |
893d6e6e | 1057 | #endif |
fa8a1238 | 1058 | } |
2014b569 CK |
1059 | |
1060 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) | |
1061 | { | |
1062 | #if defined(CONFIG_DEBUG_FS) | |
1063 | ||
1064 | debugfs_remove(rdev->mman.vram); | |
1065 | rdev->mman.vram = NULL; | |
dd66d20e CK |
1066 | |
1067 | debugfs_remove(rdev->mman.gtt); | |
1068 | rdev->mman.gtt = NULL; | |
2014b569 CK |
1069 | #endif |
1070 | } |