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2280ab57 CK |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/radeon_drm.h> | |
30 | #include "radeon.h" | |
31 | #include "radeon_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
53 | /** | |
54 | * radeon_vm_num_pde - return the number of page directory entries | |
55 | * | |
56 | * @rdev: radeon_device pointer | |
57 | * | |
58 | * Calculate the number of page directory entries (cayman+). | |
59 | */ | |
60 | static unsigned radeon_vm_num_pdes(struct radeon_device *rdev) | |
61 | { | |
4510fb98 | 62 | return rdev->vm_manager.max_pfn >> radeon_vm_block_size; |
2280ab57 CK |
63 | } |
64 | ||
65 | /** | |
66 | * radeon_vm_directory_size - returns the size of the page directory in bytes | |
67 | * | |
68 | * @rdev: radeon_device pointer | |
69 | * | |
70 | * Calculate the size of the page directory in bytes (cayman+). | |
71 | */ | |
72 | static unsigned radeon_vm_directory_size(struct radeon_device *rdev) | |
73 | { | |
74 | return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8); | |
75 | } | |
76 | ||
77 | /** | |
78 | * radeon_vm_manager_init - init the vm manager | |
79 | * | |
80 | * @rdev: radeon_device pointer | |
81 | * | |
82 | * Init the vm manager (cayman+). | |
83 | * Returns 0 for success, error for failure. | |
84 | */ | |
85 | int radeon_vm_manager_init(struct radeon_device *rdev) | |
86 | { | |
2280ab57 | 87 | int r; |
2280ab57 CK |
88 | |
89 | if (!rdev->vm_manager.enabled) { | |
2280ab57 CK |
90 | r = radeon_asic_vm_init(rdev); |
91 | if (r) | |
92 | return r; | |
93 | ||
94 | rdev->vm_manager.enabled = true; | |
2280ab57 CK |
95 | } |
96 | return 0; | |
97 | } | |
98 | ||
2280ab57 CK |
99 | /** |
100 | * radeon_vm_manager_fini - tear down the vm manager | |
101 | * | |
102 | * @rdev: radeon_device pointer | |
103 | * | |
104 | * Tear down the VM manager (cayman+). | |
105 | */ | |
106 | void radeon_vm_manager_fini(struct radeon_device *rdev) | |
107 | { | |
2280ab57 CK |
108 | int i; |
109 | ||
110 | if (!rdev->vm_manager.enabled) | |
111 | return; | |
112 | ||
6d2f2944 | 113 | for (i = 0; i < RADEON_NUM_VM; ++i) |
2280ab57 | 114 | radeon_fence_unref(&rdev->vm_manager.active[i]); |
2280ab57 | 115 | radeon_asic_vm_fini(rdev); |
2280ab57 CK |
116 | rdev->vm_manager.enabled = false; |
117 | } | |
118 | ||
119 | /** | |
6d2f2944 | 120 | * radeon_vm_get_bos - add the vm BOs to a validation list |
2280ab57 | 121 | * |
6d2f2944 CK |
122 | * @vm: vm providing the BOs |
123 | * @head: head of validation list | |
2280ab57 | 124 | * |
6d2f2944 CK |
125 | * Add the page directory to the list of BOs to |
126 | * validate for command submission (cayman+). | |
2280ab57 | 127 | */ |
df0af440 CK |
128 | struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, |
129 | struct radeon_vm *vm, | |
130 | struct list_head *head) | |
2280ab57 | 131 | { |
df0af440 | 132 | struct radeon_cs_reloc *list; |
7d95f6cc | 133 | unsigned i, idx; |
2280ab57 | 134 | |
e5a5fd4d MD |
135 | list = drm_malloc_ab(vm->max_pde_used + 2, |
136 | sizeof(struct radeon_cs_reloc)); | |
6d2f2944 CK |
137 | if (!list) |
138 | return NULL; | |
2280ab57 | 139 | |
6d2f2944 | 140 | /* add the vm page table to the list */ |
df0af440 CK |
141 | list[0].gobj = NULL; |
142 | list[0].robj = vm->page_directory; | |
ce6758c8 CK |
143 | list[0].prefered_domains = RADEON_GEM_DOMAIN_VRAM; |
144 | list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM; | |
6d2f2944 | 145 | list[0].tv.bo = &vm->page_directory->tbo; |
587cdda8 | 146 | list[0].tv.shared = true; |
df0af440 CK |
147 | list[0].tiling_flags = 0; |
148 | list[0].handle = 0; | |
6d2f2944 | 149 | list_add(&list[0].tv.head, head); |
2280ab57 | 150 | |
6d2f2944 CK |
151 | for (i = 0, idx = 1; i <= vm->max_pde_used; i++) { |
152 | if (!vm->page_tables[i].bo) | |
153 | continue; | |
2280ab57 | 154 | |
df0af440 CK |
155 | list[idx].gobj = NULL; |
156 | list[idx].robj = vm->page_tables[i].bo; | |
ce6758c8 CK |
157 | list[idx].prefered_domains = RADEON_GEM_DOMAIN_VRAM; |
158 | list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM; | |
df0af440 | 159 | list[idx].tv.bo = &list[idx].robj->tbo; |
587cdda8 | 160 | list[idx].tv.shared = true; |
df0af440 CK |
161 | list[idx].tiling_flags = 0; |
162 | list[idx].handle = 0; | |
6d2f2944 | 163 | list_add(&list[idx++].tv.head, head); |
2280ab57 CK |
164 | } |
165 | ||
6d2f2944 | 166 | return list; |
2280ab57 CK |
167 | } |
168 | ||
169 | /** | |
170 | * radeon_vm_grab_id - allocate the next free VMID | |
171 | * | |
172 | * @rdev: radeon_device pointer | |
173 | * @vm: vm to allocate id for | |
174 | * @ring: ring we want to submit job to | |
175 | * | |
176 | * Allocate an id for the vm (cayman+). | |
177 | * Returns the fence we need to sync to (if any). | |
178 | * | |
179 | * Global and local mutex must be locked! | |
180 | */ | |
181 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, | |
182 | struct radeon_vm *vm, int ring) | |
183 | { | |
184 | struct radeon_fence *best[RADEON_NUM_RINGS] = {}; | |
7c42bc1a CK |
185 | struct radeon_vm_id *vm_id = &vm->ids[ring]; |
186 | ||
2280ab57 CK |
187 | unsigned choices[2] = {}; |
188 | unsigned i; | |
189 | ||
190 | /* check if the id is still valid */ | |
7c42bc1a CK |
191 | if (vm_id->id && vm_id->last_id_use && |
192 | vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) | |
2280ab57 CK |
193 | return NULL; |
194 | ||
195 | /* we definately need to flush */ | |
7c42bc1a | 196 | vm_id->pd_gpu_addr = ~0ll; |
2280ab57 CK |
197 | |
198 | /* skip over VMID 0, since it is the system VM */ | |
199 | for (i = 1; i < rdev->vm_manager.nvm; ++i) { | |
200 | struct radeon_fence *fence = rdev->vm_manager.active[i]; | |
201 | ||
202 | if (fence == NULL) { | |
203 | /* found a free one */ | |
7c42bc1a CK |
204 | vm_id->id = i; |
205 | trace_radeon_vm_grab_id(i, ring); | |
2280ab57 CK |
206 | return NULL; |
207 | } | |
208 | ||
209 | if (radeon_fence_is_earlier(fence, best[fence->ring])) { | |
210 | best[fence->ring] = fence; | |
211 | choices[fence->ring == ring ? 0 : 1] = i; | |
212 | } | |
213 | } | |
214 | ||
215 | for (i = 0; i < 2; ++i) { | |
216 | if (choices[i]) { | |
7c42bc1a CK |
217 | vm_id->id = choices[i]; |
218 | trace_radeon_vm_grab_id(choices[i], ring); | |
2280ab57 CK |
219 | return rdev->vm_manager.active[choices[i]]; |
220 | } | |
221 | } | |
222 | ||
223 | /* should never happen */ | |
224 | BUG(); | |
225 | return NULL; | |
226 | } | |
227 | ||
fa688343 CK |
228 | /** |
229 | * radeon_vm_flush - hardware flush the vm | |
230 | * | |
231 | * @rdev: radeon_device pointer | |
232 | * @vm: vm we want to flush | |
233 | * @ring: ring to use for flush | |
ad1a58a4 | 234 | * @updates: last vm update that is waited for |
fa688343 CK |
235 | * |
236 | * Flush the vm (cayman+). | |
237 | * | |
238 | * Global and local mutex must be locked! | |
239 | */ | |
240 | void radeon_vm_flush(struct radeon_device *rdev, | |
241 | struct radeon_vm *vm, | |
ad1a58a4 | 242 | int ring, struct radeon_fence *updates) |
fa688343 | 243 | { |
6d2f2944 | 244 | uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory); |
7c42bc1a | 245 | struct radeon_vm_id *vm_id = &vm->ids[ring]; |
6d2f2944 | 246 | |
7c42bc1a CK |
247 | if (pd_addr != vm_id->pd_gpu_addr || !vm_id->flushed_updates || |
248 | radeon_fence_is_earlier(vm_id->flushed_updates, updates)) { | |
ad1a58a4 | 249 | |
7c42bc1a CK |
250 | trace_radeon_vm_flush(pd_addr, ring, vm->ids[ring].id); |
251 | radeon_fence_unref(&vm_id->flushed_updates); | |
252 | vm_id->flushed_updates = radeon_fence_ref(updates); | |
253 | vm_id->pd_gpu_addr = pd_addr; | |
faffaf62 | 254 | radeon_ring_vm_flush(rdev, &rdev->ring[ring], |
7c42bc1a CK |
255 | vm_id->id, vm_id->pd_gpu_addr); |
256 | ||
6d2f2944 | 257 | } |
fa688343 CK |
258 | } |
259 | ||
2280ab57 CK |
260 | /** |
261 | * radeon_vm_fence - remember fence for vm | |
262 | * | |
263 | * @rdev: radeon_device pointer | |
264 | * @vm: vm we want to fence | |
265 | * @fence: fence to remember | |
266 | * | |
267 | * Fence the vm (cayman+). | |
268 | * Set the fence used to protect page table and id. | |
269 | * | |
270 | * Global and local mutex must be locked! | |
271 | */ | |
272 | void radeon_vm_fence(struct radeon_device *rdev, | |
273 | struct radeon_vm *vm, | |
274 | struct radeon_fence *fence) | |
275 | { | |
7c42bc1a CK |
276 | unsigned vm_id = vm->ids[fence->ring].id; |
277 | ||
2280ab57 CK |
278 | radeon_fence_unref(&vm->fence); |
279 | vm->fence = radeon_fence_ref(fence); | |
280 | ||
7c42bc1a CK |
281 | radeon_fence_unref(&rdev->vm_manager.active[vm_id]); |
282 | rdev->vm_manager.active[vm_id] = radeon_fence_ref(fence); | |
fa688343 | 283 | |
7c42bc1a CK |
284 | radeon_fence_unref(&vm->ids[fence->ring].last_id_use); |
285 | vm->ids[fence->ring].last_id_use = radeon_fence_ref(fence); | |
2280ab57 CK |
286 | } |
287 | ||
288 | /** | |
289 | * radeon_vm_bo_find - find the bo_va for a specific vm & bo | |
290 | * | |
291 | * @vm: requested vm | |
292 | * @bo: requested buffer object | |
293 | * | |
294 | * Find @bo inside the requested vm (cayman+). | |
295 | * Search inside the @bos vm list for the requested vm | |
296 | * Returns the found bo_va or NULL if none is found | |
297 | * | |
298 | * Object has to be reserved! | |
299 | */ | |
300 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, | |
301 | struct radeon_bo *bo) | |
302 | { | |
303 | struct radeon_bo_va *bo_va; | |
304 | ||
305 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
306 | if (bo_va->vm == vm) { | |
307 | return bo_va; | |
308 | } | |
309 | } | |
310 | return NULL; | |
311 | } | |
312 | ||
313 | /** | |
314 | * radeon_vm_bo_add - add a bo to a specific vm | |
315 | * | |
316 | * @rdev: radeon_device pointer | |
317 | * @vm: requested vm | |
318 | * @bo: radeon buffer object | |
319 | * | |
320 | * Add @bo into the requested vm (cayman+). | |
321 | * Add @bo to the list of bos associated with the vm | |
322 | * Returns newly added bo_va or NULL for failure | |
323 | * | |
324 | * Object has to be reserved! | |
325 | */ | |
326 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, | |
327 | struct radeon_vm *vm, | |
328 | struct radeon_bo *bo) | |
329 | { | |
330 | struct radeon_bo_va *bo_va; | |
331 | ||
332 | bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); | |
333 | if (bo_va == NULL) { | |
334 | return NULL; | |
335 | } | |
336 | bo_va->vm = vm; | |
337 | bo_va->bo = bo; | |
0aea5e4a AD |
338 | bo_va->it.start = 0; |
339 | bo_va->it.last = 0; | |
2280ab57 | 340 | bo_va->flags = 0; |
e31ad969 | 341 | bo_va->addr = 0; |
2280ab57 CK |
342 | bo_va->ref_count = 1; |
343 | INIT_LIST_HEAD(&bo_va->bo_list); | |
036bf46a | 344 | INIT_LIST_HEAD(&bo_va->vm_status); |
2280ab57 CK |
345 | |
346 | mutex_lock(&vm->mutex); | |
2280ab57 CK |
347 | list_add_tail(&bo_va->bo_list, &bo->va); |
348 | mutex_unlock(&vm->mutex); | |
349 | ||
350 | return bo_va; | |
351 | } | |
352 | ||
03f62abd CK |
353 | /** |
354 | * radeon_vm_set_pages - helper to call the right asic function | |
355 | * | |
356 | * @rdev: radeon_device pointer | |
357 | * @ib: indirect buffer to fill with commands | |
358 | * @pe: addr of the page entry | |
359 | * @addr: dst addr to write into pe | |
360 | * @count: number of page entries to update | |
361 | * @incr: increase next addr by incr bytes | |
362 | * @flags: hw access flags | |
363 | * | |
364 | * Traces the parameters and calls the right asic functions | |
365 | * to setup the page table using the DMA. | |
366 | */ | |
367 | static void radeon_vm_set_pages(struct radeon_device *rdev, | |
368 | struct radeon_ib *ib, | |
369 | uint64_t pe, | |
370 | uint64_t addr, unsigned count, | |
371 | uint32_t incr, uint32_t flags) | |
372 | { | |
373 | trace_radeon_vm_set_page(pe, addr, count, incr, flags); | |
374 | ||
375 | if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) { | |
376 | uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8; | |
377 | radeon_asic_vm_copy_pages(rdev, ib, pe, src, count); | |
378 | ||
379 | } else if ((flags & R600_PTE_SYSTEM) || (count < 3)) { | |
380 | radeon_asic_vm_write_pages(rdev, ib, pe, addr, | |
381 | count, incr, flags); | |
382 | ||
383 | } else { | |
384 | radeon_asic_vm_set_pages(rdev, ib, pe, addr, | |
385 | count, incr, flags); | |
386 | } | |
387 | } | |
388 | ||
6d2f2944 CK |
389 | /** |
390 | * radeon_vm_clear_bo - initially clear the page dir/table | |
391 | * | |
392 | * @rdev: radeon_device pointer | |
393 | * @bo: bo to clear | |
394 | */ | |
395 | static int radeon_vm_clear_bo(struct radeon_device *rdev, | |
396 | struct radeon_bo *bo) | |
397 | { | |
6d2f2944 CK |
398 | struct radeon_ib ib; |
399 | unsigned entries; | |
400 | uint64_t addr; | |
401 | int r; | |
402 | ||
587cdda8 CK |
403 | r = radeon_bo_reserve(bo, false); |
404 | if (r) | |
6d2f2944 CK |
405 | return r; |
406 | ||
587cdda8 CK |
407 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
408 | if (r) | |
409 | goto error_unreserve; | |
6d2f2944 CK |
410 | |
411 | addr = radeon_bo_gpu_offset(bo); | |
412 | entries = radeon_bo_size(bo) / 8; | |
413 | ||
cc6f3536 | 414 | r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, 256); |
6d2f2944 | 415 | if (r) |
587cdda8 | 416 | goto error_unreserve; |
6d2f2944 CK |
417 | |
418 | ib.length_dw = 0; | |
419 | ||
03f62abd CK |
420 | radeon_vm_set_pages(rdev, &ib, addr, 0, entries, 0, 0); |
421 | radeon_asic_vm_pad_ib(rdev, &ib); | |
cc6f3536 | 422 | WARN_ON(ib.length_dw > 64); |
6d2f2944 | 423 | |
1538a9e0 | 424 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
6d2f2944 | 425 | if (r) |
587cdda8 | 426 | goto error_free; |
6d2f2944 | 427 | |
ad1a58a4 | 428 | ib.fence->is_vm_update = true; |
587cdda8 | 429 | radeon_bo_fence(bo, ib.fence, false); |
6d2f2944 | 430 | |
587cdda8 CK |
431 | error_free: |
432 | radeon_ib_free(rdev, &ib); | |
6d2f2944 | 433 | |
587cdda8 CK |
434 | error_unreserve: |
435 | radeon_bo_unreserve(bo); | |
6d2f2944 CK |
436 | return r; |
437 | } | |
438 | ||
2280ab57 CK |
439 | /** |
440 | * radeon_vm_bo_set_addr - set bos virtual address inside a vm | |
441 | * | |
442 | * @rdev: radeon_device pointer | |
443 | * @bo_va: bo_va to store the address | |
444 | * @soffset: requested offset of the buffer in the VM address space | |
445 | * @flags: attributes of pages (read/write/valid/etc.) | |
446 | * | |
447 | * Set offset of @bo_va (cayman+). | |
448 | * Validate and set the offset requested within the vm address space. | |
449 | * Returns 0 for success, error for failure. | |
450 | * | |
85761f60 | 451 | * Object has to be reserved and gets unreserved by this function! |
2280ab57 CK |
452 | */ |
453 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, | |
454 | struct radeon_bo_va *bo_va, | |
455 | uint64_t soffset, | |
456 | uint32_t flags) | |
457 | { | |
458 | uint64_t size = radeon_bo_size(bo_va->bo); | |
2280ab57 | 459 | struct radeon_vm *vm = bo_va->vm; |
6d2f2944 | 460 | unsigned last_pfn, pt_idx; |
0aea5e4a | 461 | uint64_t eoffset; |
6d2f2944 | 462 | int r; |
2280ab57 CK |
463 | |
464 | if (soffset) { | |
465 | /* make sure object fit at this offset */ | |
466 | eoffset = soffset + size; | |
467 | if (soffset >= eoffset) { | |
468 | return -EINVAL; | |
469 | } | |
470 | ||
471 | last_pfn = eoffset / RADEON_GPU_PAGE_SIZE; | |
472 | if (last_pfn > rdev->vm_manager.max_pfn) { | |
473 | dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n", | |
474 | last_pfn, rdev->vm_manager.max_pfn); | |
475 | return -EINVAL; | |
476 | } | |
477 | ||
478 | } else { | |
479 | eoffset = last_pfn = 0; | |
480 | } | |
481 | ||
482 | mutex_lock(&vm->mutex); | |
0aea5e4a AD |
483 | if (bo_va->it.start || bo_va->it.last) { |
484 | if (bo_va->addr) { | |
485 | /* add a clone of the bo_va to clear the old address */ | |
486 | struct radeon_bo_va *tmp; | |
487 | tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); | |
68b1ea30 DC |
488 | if (!tmp) { |
489 | mutex_unlock(&vm->mutex); | |
490 | return -ENOMEM; | |
491 | } | |
0aea5e4a AD |
492 | tmp->it.start = bo_va->it.start; |
493 | tmp->it.last = bo_va->it.last; | |
494 | tmp->vm = vm; | |
495 | tmp->addr = bo_va->addr; | |
ee26d83f | 496 | tmp->bo = radeon_bo_ref(bo_va->bo); |
0aea5e4a | 497 | list_add(&tmp->vm_status, &vm->freed); |
2280ab57 CK |
498 | } |
499 | ||
0aea5e4a AD |
500 | interval_tree_remove(&bo_va->it, &vm->va); |
501 | bo_va->it.start = 0; | |
502 | bo_va->it.last = 0; | |
2280ab57 CK |
503 | } |
504 | ||
0aea5e4a AD |
505 | soffset /= RADEON_GPU_PAGE_SIZE; |
506 | eoffset /= RADEON_GPU_PAGE_SIZE; | |
507 | if (soffset || eoffset) { | |
508 | struct interval_tree_node *it; | |
509 | it = interval_tree_iter_first(&vm->va, soffset, eoffset - 1); | |
510 | if (it) { | |
511 | struct radeon_bo_va *tmp; | |
512 | tmp = container_of(it, struct radeon_bo_va, it); | |
513 | /* bo and tmp overlap, invalid offset */ | |
514 | dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with " | |
515 | "(bo %p 0x%010lx 0x%010lx)\n", bo_va->bo, | |
516 | soffset, tmp->bo, tmp->it.start, tmp->it.last); | |
5b753275 | 517 | mutex_unlock(&vm->mutex); |
0aea5e4a | 518 | return -EINVAL; |
5b753275 | 519 | } |
0aea5e4a AD |
520 | bo_va->it.start = soffset; |
521 | bo_va->it.last = eoffset - 1; | |
522 | interval_tree_insert(&bo_va->it, &vm->va); | |
036bf46a CK |
523 | } |
524 | ||
2280ab57 | 525 | bo_va->flags = flags; |
e31ad969 | 526 | bo_va->addr = 0; |
2280ab57 | 527 | |
0aea5e4a AD |
528 | soffset >>= radeon_vm_block_size; |
529 | eoffset >>= radeon_vm_block_size; | |
4510fb98 CK |
530 | |
531 | BUG_ON(eoffset >= radeon_vm_num_pdes(rdev)); | |
6d2f2944 CK |
532 | |
533 | if (eoffset > vm->max_pde_used) | |
534 | vm->max_pde_used = eoffset; | |
535 | ||
536 | radeon_bo_unreserve(bo_va->bo); | |
537 | ||
538 | /* walk over the address space and allocate the page tables */ | |
539 | for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) { | |
540 | struct radeon_bo *pt; | |
541 | ||
542 | if (vm->page_tables[pt_idx].bo) | |
543 | continue; | |
544 | ||
545 | /* drop mutex to allocate and clear page table */ | |
546 | mutex_unlock(&vm->mutex); | |
547 | ||
548 | r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8, | |
7dae77f8 | 549 | RADEON_GPU_PAGE_SIZE, true, |
831b6966 ML |
550 | RADEON_GEM_DOMAIN_VRAM, 0, |
551 | NULL, NULL, &pt); | |
6d2f2944 CK |
552 | if (r) |
553 | return r; | |
554 | ||
555 | r = radeon_vm_clear_bo(rdev, pt); | |
556 | if (r) { | |
557 | radeon_bo_unref(&pt); | |
558 | radeon_bo_reserve(bo_va->bo, false); | |
559 | return r; | |
560 | } | |
561 | ||
562 | /* aquire mutex again */ | |
563 | mutex_lock(&vm->mutex); | |
564 | if (vm->page_tables[pt_idx].bo) { | |
565 | /* someone else allocated the pt in the meantime */ | |
566 | mutex_unlock(&vm->mutex); | |
567 | radeon_bo_unref(&pt); | |
568 | mutex_lock(&vm->mutex); | |
569 | continue; | |
570 | } | |
571 | ||
572 | vm->page_tables[pt_idx].addr = 0; | |
573 | vm->page_tables[pt_idx].bo = pt; | |
574 | } | |
575 | ||
2280ab57 | 576 | mutex_unlock(&vm->mutex); |
85761f60 | 577 | return 0; |
2280ab57 CK |
578 | } |
579 | ||
580 | /** | |
581 | * radeon_vm_map_gart - get the physical address of a gart page | |
582 | * | |
583 | * @rdev: radeon_device pointer | |
584 | * @addr: the unmapped addr | |
585 | * | |
586 | * Look up the physical address of the page that the pte resolves | |
587 | * to (cayman+). | |
588 | * Returns the physical address of the page. | |
589 | */ | |
590 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr) | |
591 | { | |
592 | uint64_t result; | |
593 | ||
594 | /* page table offset */ | |
595 | result = rdev->gart.pages_addr[addr >> PAGE_SHIFT]; | |
596 | ||
597 | /* in case cpu page size != gpu page size*/ | |
598 | result |= addr & (~PAGE_MASK); | |
599 | ||
600 | return result; | |
601 | } | |
602 | ||
603 | /** | |
604 | * radeon_vm_page_flags - translate page flags to what the hw uses | |
605 | * | |
606 | * @flags: flags comming from userspace | |
607 | * | |
608 | * Translate the flags the userspace ABI uses to hw flags. | |
609 | */ | |
610 | static uint32_t radeon_vm_page_flags(uint32_t flags) | |
611 | { | |
612 | uint32_t hw_flags = 0; | |
613 | hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0; | |
614 | hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0; | |
615 | hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0; | |
616 | if (flags & RADEON_VM_PAGE_SYSTEM) { | |
617 | hw_flags |= R600_PTE_SYSTEM; | |
618 | hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0; | |
619 | } | |
620 | return hw_flags; | |
621 | } | |
622 | ||
623 | /** | |
624 | * radeon_vm_update_pdes - make sure that page directory is valid | |
625 | * | |
626 | * @rdev: radeon_device pointer | |
627 | * @vm: requested vm | |
628 | * @start: start of GPU address range | |
629 | * @end: end of GPU address range | |
630 | * | |
631 | * Allocates new page tables if necessary | |
632 | * and updates the page directory (cayman+). | |
633 | * Returns 0 for success, error for failure. | |
634 | * | |
635 | * Global and local mutex must be locked! | |
636 | */ | |
6d2f2944 CK |
637 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
638 | struct radeon_vm *vm) | |
2280ab57 | 639 | { |
37903b5e CK |
640 | struct radeon_bo *pd = vm->page_directory; |
641 | uint64_t pd_addr = radeon_bo_gpu_offset(pd); | |
4510fb98 | 642 | uint32_t incr = RADEON_VM_PTE_COUNT * 8; |
2280ab57 | 643 | uint64_t last_pde = ~0, last_pt = ~0; |
6d2f2944 CK |
644 | unsigned count = 0, pt_idx, ndw; |
645 | struct radeon_ib ib; | |
2280ab57 CK |
646 | int r; |
647 | ||
6d2f2944 CK |
648 | /* padding, etc. */ |
649 | ndw = 64; | |
650 | ||
651 | /* assume the worst case */ | |
cc6f3536 | 652 | ndw += vm->max_pde_used * 6; |
6d2f2944 CK |
653 | |
654 | /* update too big for an IB */ | |
655 | if (ndw > 0xfffff) | |
656 | return -ENOMEM; | |
657 | ||
658 | r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4); | |
659 | if (r) | |
660 | return r; | |
661 | ib.length_dw = 0; | |
2280ab57 CK |
662 | |
663 | /* walk over the address space and update the page directory */ | |
6d2f2944 CK |
664 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { |
665 | struct radeon_bo *bo = vm->page_tables[pt_idx].bo; | |
2280ab57 CK |
666 | uint64_t pde, pt; |
667 | ||
6d2f2944 | 668 | if (bo == NULL) |
2280ab57 CK |
669 | continue; |
670 | ||
6d2f2944 CK |
671 | pt = radeon_bo_gpu_offset(bo); |
672 | if (vm->page_tables[pt_idx].addr == pt) | |
673 | continue; | |
674 | vm->page_tables[pt_idx].addr = pt; | |
2280ab57 | 675 | |
6d2f2944 | 676 | pde = pd_addr + pt_idx * 8; |
2280ab57 CK |
677 | if (((last_pde + 8 * count) != pde) || |
678 | ((last_pt + incr * count) != pt)) { | |
679 | ||
680 | if (count) { | |
03f62abd CK |
681 | radeon_vm_set_pages(rdev, &ib, last_pde, |
682 | last_pt, count, incr, | |
683 | R600_PTE_VALID); | |
2280ab57 CK |
684 | } |
685 | ||
686 | count = 1; | |
687 | last_pde = pde; | |
688 | last_pt = pt; | |
689 | } else { | |
690 | ++count; | |
691 | } | |
692 | } | |
693 | ||
6d2f2944 | 694 | if (count) |
03f62abd CK |
695 | radeon_vm_set_pages(rdev, &ib, last_pde, last_pt, count, |
696 | incr, R600_PTE_VALID); | |
2280ab57 | 697 | |
6d2f2944 | 698 | if (ib.length_dw != 0) { |
03f62abd | 699 | radeon_asic_vm_pad_ib(rdev, &ib); |
f2c24b83 | 700 | |
975700d2 | 701 | radeon_sync_resv(rdev, &ib.sync, pd->tbo.resv, false); |
cc6f3536 | 702 | WARN_ON(ib.length_dw > ndw); |
1538a9e0 | 703 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
6d2f2944 CK |
704 | if (r) { |
705 | radeon_ib_free(rdev, &ib); | |
706 | return r; | |
707 | } | |
ad1a58a4 | 708 | ib.fence->is_vm_update = true; |
587cdda8 | 709 | radeon_bo_fence(pd, ib.fence, false); |
6d2f2944 CK |
710 | radeon_fence_unref(&vm->fence); |
711 | vm->fence = radeon_fence_ref(ib.fence); | |
2280ab57 | 712 | } |
6d2f2944 | 713 | radeon_ib_free(rdev, &ib); |
2280ab57 CK |
714 | |
715 | return 0; | |
716 | } | |
717 | ||
ec3dbbcb CK |
718 | /** |
719 | * radeon_vm_frag_ptes - add fragment information to PTEs | |
720 | * | |
721 | * @rdev: radeon_device pointer | |
722 | * @ib: IB for the update | |
723 | * @pe_start: first PTE to handle | |
724 | * @pe_end: last PTE to handle | |
725 | * @addr: addr those PTEs should point to | |
726 | * @flags: hw mapping flags | |
727 | * | |
728 | * Global and local mutex must be locked! | |
729 | */ | |
730 | static void radeon_vm_frag_ptes(struct radeon_device *rdev, | |
731 | struct radeon_ib *ib, | |
732 | uint64_t pe_start, uint64_t pe_end, | |
733 | uint64_t addr, uint32_t flags) | |
734 | { | |
735 | /** | |
736 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
737 | * field in the PTE. When this field is set to a non-zero value, page | |
738 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
739 | * flags are considered valid for all PTEs within the fragment range | |
740 | * and corresponding mappings are assumed to be physically contiguous. | |
741 | * | |
742 | * The L1 TLB can store a single PTE for the whole fragment, | |
743 | * significantly increasing the space available for translation | |
744 | * caching. This leads to large improvements in throughput when the | |
745 | * TLB is under pressure. | |
746 | * | |
747 | * The L2 TLB distributes small and large fragments into two | |
748 | * asymmetric partitions. The large fragment cache is significantly | |
749 | * larger. Thus, we try to use large fragments wherever possible. | |
750 | * Userspace can support this by aligning virtual base address and | |
751 | * allocation size to the fragment size. | |
752 | */ | |
753 | ||
754 | /* NI is optimized for 256KB fragments, SI and newer for 64KB */ | |
755 | uint64_t frag_flags = rdev->family == CHIP_CAYMAN ? | |
756 | R600_PTE_FRAG_256KB : R600_PTE_FRAG_64KB; | |
757 | uint64_t frag_align = rdev->family == CHIP_CAYMAN ? 0x200 : 0x80; | |
758 | ||
759 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
760 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
761 | ||
762 | unsigned count; | |
763 | ||
764 | /* system pages are non continuously */ | |
765 | if ((flags & R600_PTE_SYSTEM) || !(flags & R600_PTE_VALID) || | |
766 | (frag_start >= frag_end)) { | |
767 | ||
768 | count = (pe_end - pe_start) / 8; | |
03f62abd CK |
769 | radeon_vm_set_pages(rdev, ib, pe_start, addr, count, |
770 | RADEON_GPU_PAGE_SIZE, flags); | |
ec3dbbcb CK |
771 | return; |
772 | } | |
773 | ||
774 | /* handle the 4K area at the beginning */ | |
775 | if (pe_start != frag_start) { | |
776 | count = (frag_start - pe_start) / 8; | |
03f62abd CK |
777 | radeon_vm_set_pages(rdev, ib, pe_start, addr, count, |
778 | RADEON_GPU_PAGE_SIZE, flags); | |
ec3dbbcb CK |
779 | addr += RADEON_GPU_PAGE_SIZE * count; |
780 | } | |
781 | ||
782 | /* handle the area in the middle */ | |
783 | count = (frag_end - frag_start) / 8; | |
03f62abd CK |
784 | radeon_vm_set_pages(rdev, ib, frag_start, addr, count, |
785 | RADEON_GPU_PAGE_SIZE, flags | frag_flags); | |
ec3dbbcb CK |
786 | |
787 | /* handle the 4K area at the end */ | |
788 | if (frag_end != pe_end) { | |
789 | addr += RADEON_GPU_PAGE_SIZE * count; | |
790 | count = (pe_end - frag_end) / 8; | |
03f62abd CK |
791 | radeon_vm_set_pages(rdev, ib, frag_end, addr, count, |
792 | RADEON_GPU_PAGE_SIZE, flags); | |
ec3dbbcb CK |
793 | } |
794 | } | |
795 | ||
2280ab57 CK |
796 | /** |
797 | * radeon_vm_update_ptes - make sure that page tables are valid | |
798 | * | |
799 | * @rdev: radeon_device pointer | |
800 | * @vm: requested vm | |
801 | * @start: start of GPU address range | |
802 | * @end: end of GPU address range | |
803 | * @dst: destination address to map to | |
804 | * @flags: mapping flags | |
805 | * | |
806 | * Update the page tables in the range @start - @end (cayman+). | |
807 | * | |
808 | * Global and local mutex must be locked! | |
809 | */ | |
810 | static void radeon_vm_update_ptes(struct radeon_device *rdev, | |
811 | struct radeon_vm *vm, | |
812 | struct radeon_ib *ib, | |
813 | uint64_t start, uint64_t end, | |
814 | uint64_t dst, uint32_t flags) | |
815 | { | |
4510fb98 | 816 | uint64_t mask = RADEON_VM_PTE_COUNT - 1; |
2280ab57 CK |
817 | uint64_t last_pte = ~0, last_dst = ~0; |
818 | unsigned count = 0; | |
819 | uint64_t addr; | |
820 | ||
2280ab57 CK |
821 | /* walk over the address space and update the page tables */ |
822 | for (addr = start; addr < end; ) { | |
4510fb98 | 823 | uint64_t pt_idx = addr >> radeon_vm_block_size; |
37903b5e | 824 | struct radeon_bo *pt = vm->page_tables[pt_idx].bo; |
2280ab57 CK |
825 | unsigned nptes; |
826 | uint64_t pte; | |
827 | ||
975700d2 | 828 | radeon_sync_resv(rdev, &ib->sync, pt->tbo.resv, false); |
37903b5e | 829 | |
2280ab57 CK |
830 | if ((addr & ~mask) == (end & ~mask)) |
831 | nptes = end - addr; | |
832 | else | |
833 | nptes = RADEON_VM_PTE_COUNT - (addr & mask); | |
834 | ||
37903b5e | 835 | pte = radeon_bo_gpu_offset(pt); |
2280ab57 CK |
836 | pte += (addr & mask) * 8; |
837 | ||
838 | if ((last_pte + 8 * count) != pte) { | |
839 | ||
840 | if (count) { | |
ec3dbbcb CK |
841 | radeon_vm_frag_ptes(rdev, ib, last_pte, |
842 | last_pte + 8 * count, | |
843 | last_dst, flags); | |
2280ab57 CK |
844 | } |
845 | ||
846 | count = nptes; | |
847 | last_pte = pte; | |
848 | last_dst = dst; | |
849 | } else { | |
850 | count += nptes; | |
851 | } | |
852 | ||
853 | addr += nptes; | |
854 | dst += nptes * RADEON_GPU_PAGE_SIZE; | |
855 | } | |
856 | ||
857 | if (count) { | |
ec3dbbcb CK |
858 | radeon_vm_frag_ptes(rdev, ib, last_pte, |
859 | last_pte + 8 * count, | |
860 | last_dst, flags); | |
2280ab57 CK |
861 | } |
862 | } | |
863 | ||
587cdda8 CK |
864 | /** |
865 | * radeon_vm_fence_pts - fence page tables after an update | |
866 | * | |
867 | * @vm: requested vm | |
868 | * @start: start of GPU address range | |
869 | * @end: end of GPU address range | |
870 | * @fence: fence to use | |
871 | * | |
872 | * Fence the page tables in the range @start - @end (cayman+). | |
873 | * | |
874 | * Global and local mutex must be locked! | |
875 | */ | |
876 | static void radeon_vm_fence_pts(struct radeon_vm *vm, | |
877 | uint64_t start, uint64_t end, | |
878 | struct radeon_fence *fence) | |
879 | { | |
880 | unsigned i; | |
881 | ||
882 | start >>= radeon_vm_block_size; | |
883 | end >>= radeon_vm_block_size; | |
884 | ||
885 | for (i = start; i <= end; ++i) | |
886 | radeon_bo_fence(vm->page_tables[i].bo, fence, false); | |
887 | } | |
888 | ||
2280ab57 CK |
889 | /** |
890 | * radeon_vm_bo_update - map a bo into the vm page table | |
891 | * | |
892 | * @rdev: radeon_device pointer | |
893 | * @vm: requested vm | |
894 | * @bo: radeon buffer object | |
895 | * @mem: ttm mem | |
896 | * | |
897 | * Fill in the page table entries for @bo (cayman+). | |
898 | * Returns 0 for success, -EINVAL for failure. | |
899 | * | |
529364e0 | 900 | * Object have to be reserved and mutex must be locked! |
2280ab57 CK |
901 | */ |
902 | int radeon_vm_bo_update(struct radeon_device *rdev, | |
036bf46a | 903 | struct radeon_bo_va *bo_va, |
2280ab57 CK |
904 | struct ttm_mem_reg *mem) |
905 | { | |
036bf46a | 906 | struct radeon_vm *vm = bo_va->vm; |
2280ab57 | 907 | struct radeon_ib ib; |
cc6f3536 | 908 | unsigned nptes, ncmds, ndw; |
2280ab57 | 909 | uint64_t addr; |
cc6f3536 | 910 | uint32_t flags; |
2280ab57 CK |
911 | int r; |
912 | ||
0aea5e4a | 913 | if (!bo_va->it.start) { |
2280ab57 | 914 | dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n", |
036bf46a | 915 | bo_va->bo, vm); |
2280ab57 CK |
916 | return -EINVAL; |
917 | } | |
918 | ||
e31ad969 | 919 | list_del_init(&bo_va->vm_status); |
2280ab57 CK |
920 | |
921 | bo_va->flags &= ~RADEON_VM_PAGE_VALID; | |
922 | bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM; | |
02376d82 | 923 | bo_va->flags &= ~RADEON_VM_PAGE_SNOOPED; |
f72a113a CK |
924 | if (bo_va->bo && radeon_ttm_tt_is_readonly(bo_va->bo->tbo.ttm)) |
925 | bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE; | |
926 | ||
2280ab57 CK |
927 | if (mem) { |
928 | addr = mem->start << PAGE_SHIFT; | |
929 | if (mem->mem_type != TTM_PL_SYSTEM) { | |
930 | bo_va->flags |= RADEON_VM_PAGE_VALID; | |
2280ab57 CK |
931 | } |
932 | if (mem->mem_type == TTM_PL_TT) { | |
933 | bo_va->flags |= RADEON_VM_PAGE_SYSTEM; | |
02376d82 MD |
934 | if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC))) |
935 | bo_va->flags |= RADEON_VM_PAGE_SNOOPED; | |
936 | ||
2280ab57 CK |
937 | } else { |
938 | addr += rdev->vm_manager.vram_base_offset; | |
939 | } | |
940 | } else { | |
941 | addr = 0; | |
2280ab57 CK |
942 | } |
943 | ||
e31ad969 CK |
944 | if (addr == bo_va->addr) |
945 | return 0; | |
946 | bo_va->addr = addr; | |
947 | ||
2280ab57 CK |
948 | trace_radeon_vm_bo_update(bo_va); |
949 | ||
0aea5e4a | 950 | nptes = bo_va->it.last - bo_va->it.start + 1; |
2280ab57 | 951 | |
cc6f3536 CK |
952 | /* reserve space for one command every (1 << BLOCK_SIZE) entries |
953 | or 2k dwords (whatever is smaller) */ | |
954 | ncmds = (nptes >> min(radeon_vm_block_size, 11)) + 1; | |
955 | ||
2280ab57 CK |
956 | /* padding, etc. */ |
957 | ndw = 64; | |
958 | ||
cc6f3536 CK |
959 | flags = radeon_vm_page_flags(bo_va->flags); |
960 | if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) { | |
961 | /* only copy commands needed */ | |
962 | ndw += ncmds * 7; | |
963 | ||
964 | } else if (flags & R600_PTE_SYSTEM) { | |
965 | /* header for write data commands */ | |
966 | ndw += ncmds * 4; | |
967 | ||
968 | /* body of write data command */ | |
969 | ndw += nptes * 2; | |
2280ab57 | 970 | |
cc6f3536 CK |
971 | } else { |
972 | /* set page commands needed */ | |
973 | ndw += ncmds * 10; | |
974 | ||
975 | /* two extra commands for begin/end of fragment */ | |
976 | ndw += 2 * 10; | |
977 | } | |
2280ab57 | 978 | |
2280ab57 CK |
979 | /* update too big for an IB */ |
980 | if (ndw > 0xfffff) | |
981 | return -ENOMEM; | |
982 | ||
983 | r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4); | |
984 | if (r) | |
985 | return r; | |
986 | ib.length_dw = 0; | |
987 | ||
0aea5e4a AD |
988 | radeon_vm_update_ptes(rdev, vm, &ib, bo_va->it.start, |
989 | bo_va->it.last + 1, addr, | |
990 | radeon_vm_page_flags(bo_va->flags)); | |
2280ab57 | 991 | |
03f62abd | 992 | radeon_asic_vm_pad_ib(rdev, &ib); |
cc6f3536 CK |
993 | WARN_ON(ib.length_dw > ndw); |
994 | ||
1538a9e0 | 995 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
2280ab57 CK |
996 | if (r) { |
997 | radeon_ib_free(rdev, &ib); | |
998 | return r; | |
999 | } | |
ad1a58a4 | 1000 | ib.fence->is_vm_update = true; |
587cdda8 | 1001 | radeon_vm_fence_pts(vm, bo_va->it.start, bo_va->it.last + 1, ib.fence); |
2280ab57 CK |
1002 | radeon_fence_unref(&vm->fence); |
1003 | vm->fence = radeon_fence_ref(ib.fence); | |
1004 | radeon_ib_free(rdev, &ib); | |
2280ab57 CK |
1005 | |
1006 | return 0; | |
1007 | } | |
1008 | ||
036bf46a CK |
1009 | /** |
1010 | * radeon_vm_clear_freed - clear freed BOs in the PT | |
1011 | * | |
1012 | * @rdev: radeon_device pointer | |
1013 | * @vm: requested vm | |
1014 | * | |
1015 | * Make sure all freed BOs are cleared in the PT. | |
1016 | * Returns 0 for success. | |
1017 | * | |
1018 | * PTs have to be reserved and mutex must be locked! | |
1019 | */ | |
1020 | int radeon_vm_clear_freed(struct radeon_device *rdev, | |
1021 | struct radeon_vm *vm) | |
1022 | { | |
1023 | struct radeon_bo_va *bo_va, *tmp; | |
1024 | int r; | |
1025 | ||
1026 | list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) { | |
036bf46a | 1027 | r = radeon_vm_bo_update(rdev, bo_va, NULL); |
ee26d83f | 1028 | radeon_bo_unref(&bo_va->bo); |
036bf46a CK |
1029 | kfree(bo_va); |
1030 | if (r) | |
1031 | return r; | |
1032 | } | |
1033 | return 0; | |
1034 | ||
1035 | } | |
1036 | ||
e31ad969 CK |
1037 | /** |
1038 | * radeon_vm_clear_invalids - clear invalidated BOs in the PT | |
1039 | * | |
1040 | * @rdev: radeon_device pointer | |
1041 | * @vm: requested vm | |
1042 | * | |
1043 | * Make sure all invalidated BOs are cleared in the PT. | |
1044 | * Returns 0 for success. | |
1045 | * | |
1046 | * PTs have to be reserved and mutex must be locked! | |
1047 | */ | |
1048 | int radeon_vm_clear_invalids(struct radeon_device *rdev, | |
1049 | struct radeon_vm *vm) | |
1050 | { | |
1051 | struct radeon_bo_va *bo_va, *tmp; | |
1052 | int r; | |
1053 | ||
1054 | list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, vm_status) { | |
1055 | r = radeon_vm_bo_update(rdev, bo_va, NULL); | |
1056 | if (r) | |
1057 | return r; | |
1058 | } | |
1059 | return 0; | |
1060 | } | |
1061 | ||
2280ab57 CK |
1062 | /** |
1063 | * radeon_vm_bo_rmv - remove a bo to a specific vm | |
1064 | * | |
1065 | * @rdev: radeon_device pointer | |
1066 | * @bo_va: requested bo_va | |
1067 | * | |
1068 | * Remove @bo_va->bo from the requested vm (cayman+). | |
2280ab57 CK |
1069 | * |
1070 | * Object have to be reserved! | |
1071 | */ | |
036bf46a CK |
1072 | void radeon_vm_bo_rmv(struct radeon_device *rdev, |
1073 | struct radeon_bo_va *bo_va) | |
2280ab57 | 1074 | { |
036bf46a | 1075 | struct radeon_vm *vm = bo_va->vm; |
2280ab57 | 1076 | |
036bf46a | 1077 | list_del(&bo_va->bo_list); |
529364e0 | 1078 | |
036bf46a | 1079 | mutex_lock(&vm->mutex); |
0aea5e4a | 1080 | interval_tree_remove(&bo_va->it, &vm->va); |
e31ad969 | 1081 | list_del(&bo_va->vm_status); |
2280ab57 | 1082 | |
e31ad969 | 1083 | if (bo_va->addr) { |
ee26d83f | 1084 | bo_va->bo = radeon_bo_ref(bo_va->bo); |
036bf46a CK |
1085 | list_add(&bo_va->vm_status, &vm->freed); |
1086 | } else { | |
1087 | kfree(bo_va); | |
1088 | } | |
1089 | ||
1090 | mutex_unlock(&vm->mutex); | |
2280ab57 CK |
1091 | } |
1092 | ||
1093 | /** | |
1094 | * radeon_vm_bo_invalidate - mark the bo as invalid | |
1095 | * | |
1096 | * @rdev: radeon_device pointer | |
1097 | * @vm: requested vm | |
1098 | * @bo: radeon buffer object | |
1099 | * | |
1100 | * Mark @bo as invalid (cayman+). | |
1101 | */ | |
1102 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, | |
1103 | struct radeon_bo *bo) | |
1104 | { | |
1105 | struct radeon_bo_va *bo_va; | |
1106 | ||
1107 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
e31ad969 CK |
1108 | if (bo_va->addr) { |
1109 | mutex_lock(&bo_va->vm->mutex); | |
1110 | list_del(&bo_va->vm_status); | |
1111 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); | |
1112 | mutex_unlock(&bo_va->vm->mutex); | |
1113 | } | |
2280ab57 CK |
1114 | } |
1115 | } | |
1116 | ||
1117 | /** | |
1118 | * radeon_vm_init - initialize a vm instance | |
1119 | * | |
1120 | * @rdev: radeon_device pointer | |
1121 | * @vm: requested vm | |
1122 | * | |
1123 | * Init @vm fields (cayman+). | |
1124 | */ | |
6d2f2944 | 1125 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm) |
2280ab57 | 1126 | { |
1c89d27f CK |
1127 | const unsigned align = min(RADEON_VM_PTB_ALIGN_SIZE, |
1128 | RADEON_VM_PTE_COUNT * 8); | |
6d2f2944 | 1129 | unsigned pd_size, pd_entries, pts_size; |
7c42bc1a | 1130 | int i, r; |
6d2f2944 | 1131 | |
cc9e67e3 | 1132 | vm->ib_bo_va = NULL; |
2280ab57 | 1133 | vm->fence = NULL; |
7c42bc1a CK |
1134 | |
1135 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
1136 | vm->ids[i].id = 0; | |
1137 | vm->ids[i].flushed_updates = NULL; | |
1138 | vm->ids[i].last_id_use = NULL; | |
1139 | } | |
2280ab57 | 1140 | mutex_init(&vm->mutex); |
0aea5e4a | 1141 | vm->va = RB_ROOT; |
e31ad969 | 1142 | INIT_LIST_HEAD(&vm->invalidated); |
036bf46a | 1143 | INIT_LIST_HEAD(&vm->freed); |
6d2f2944 CK |
1144 | |
1145 | pd_size = radeon_vm_directory_size(rdev); | |
1146 | pd_entries = radeon_vm_num_pdes(rdev); | |
1147 | ||
1148 | /* allocate page table array */ | |
1149 | pts_size = pd_entries * sizeof(struct radeon_vm_pt); | |
1150 | vm->page_tables = kzalloc(pts_size, GFP_KERNEL); | |
1151 | if (vm->page_tables == NULL) { | |
1152 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1153 | return -ENOMEM; | |
1154 | } | |
1155 | ||
7dae77f8 | 1156 | r = radeon_bo_create(rdev, pd_size, align, true, |
02376d82 | 1157 | RADEON_GEM_DOMAIN_VRAM, 0, NULL, |
831b6966 | 1158 | NULL, &vm->page_directory); |
6d2f2944 CK |
1159 | if (r) |
1160 | return r; | |
1161 | ||
1162 | r = radeon_vm_clear_bo(rdev, vm->page_directory); | |
1163 | if (r) { | |
1164 | radeon_bo_unref(&vm->page_directory); | |
1165 | vm->page_directory = NULL; | |
1166 | return r; | |
1167 | } | |
1168 | ||
1169 | return 0; | |
2280ab57 CK |
1170 | } |
1171 | ||
1172 | /** | |
1173 | * radeon_vm_fini - tear down a vm instance | |
1174 | * | |
1175 | * @rdev: radeon_device pointer | |
1176 | * @vm: requested vm | |
1177 | * | |
1178 | * Tear down @vm (cayman+). | |
1179 | * Unbind the VM and remove all bos from the vm bo list | |
1180 | */ | |
1181 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm) | |
1182 | { | |
1183 | struct radeon_bo_va *bo_va, *tmp; | |
6d2f2944 | 1184 | int i, r; |
2280ab57 | 1185 | |
0aea5e4a | 1186 | if (!RB_EMPTY_ROOT(&vm->va)) { |
2280ab57 CK |
1187 | dev_err(rdev->dev, "still active bo inside vm\n"); |
1188 | } | |
0aea5e4a AD |
1189 | rbtree_postorder_for_each_entry_safe(bo_va, tmp, &vm->va, it.rb) { |
1190 | interval_tree_remove(&bo_va->it, &vm->va); | |
2280ab57 CK |
1191 | r = radeon_bo_reserve(bo_va->bo, false); |
1192 | if (!r) { | |
1193 | list_del_init(&bo_va->bo_list); | |
1194 | radeon_bo_unreserve(bo_va->bo); | |
1195 | kfree(bo_va); | |
1196 | } | |
1197 | } | |
ee26d83f CK |
1198 | list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) { |
1199 | radeon_bo_unref(&bo_va->bo); | |
036bf46a | 1200 | kfree(bo_va); |
ee26d83f | 1201 | } |
6d2f2944 CK |
1202 | |
1203 | for (i = 0; i < radeon_vm_num_pdes(rdev); i++) | |
1204 | radeon_bo_unref(&vm->page_tables[i].bo); | |
1205 | kfree(vm->page_tables); | |
1206 | ||
1207 | radeon_bo_unref(&vm->page_directory); | |
1208 | ||
2280ab57 | 1209 | radeon_fence_unref(&vm->fence); |
7c42bc1a CK |
1210 | |
1211 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
1212 | radeon_fence_unref(&vm->ids[i].flushed_updates); | |
1213 | radeon_fence_unref(&vm->ids[i].last_id_use); | |
1214 | } | |
6d2f2944 CK |
1215 | |
1216 | mutex_destroy(&vm->mutex); | |
2280ab57 | 1217 | } |