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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
c010f800 JG |
28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * | |
30 | * This file gather function specific to RS600 which is the IGP of | |
31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 | |
32 | * is the X1250/X1270 supporting AMD CPU). The display engine are | |
33 | * the avivo one, bios is an atombios, 3D block are the one of the | |
34 | * R4XX family. The GART is different from the RS400 one and is very | |
35 | * close to the one of the R600 family (R600 likely being an evolution | |
36 | * of the RS600 GART block). | |
37 | */ | |
771fe6b9 | 38 | #include "drmP.h" |
771fe6b9 | 39 | #include "radeon.h" |
c010f800 JG |
40 | #include "atom.h" |
41 | #include "rs600d.h" | |
771fe6b9 | 42 | |
3f7dc91a DA |
43 | #include "rs600_reg_safe.h" |
44 | ||
771fe6b9 JG |
45 | void rs600_gpu_init(struct radeon_device *rdev); |
46 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); | |
771fe6b9 | 47 | |
771fe6b9 JG |
48 | /* |
49 | * GART. | |
50 | */ | |
51 | void rs600_gart_tlb_flush(struct radeon_device *rdev) | |
52 | { | |
53 | uint32_t tmp; | |
54 | ||
c010f800 JG |
55 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
56 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; | |
57 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
771fe6b9 | 58 | |
c010f800 JG |
59 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
60 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); | |
61 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
771fe6b9 | 62 | |
c010f800 JG |
63 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
64 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; | |
65 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
66 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); | |
771fe6b9 JG |
67 | } |
68 | ||
4aac0473 | 69 | int rs600_gart_init(struct radeon_device *rdev) |
771fe6b9 | 70 | { |
771fe6b9 JG |
71 | int r; |
72 | ||
4aac0473 JG |
73 | if (rdev->gart.table.vram.robj) { |
74 | WARN(1, "RS600 GART already initialized.\n"); | |
75 | return 0; | |
76 | } | |
771fe6b9 JG |
77 | /* Initialize common gart structure */ |
78 | r = radeon_gart_init(rdev); | |
79 | if (r) { | |
80 | return r; | |
81 | } | |
82 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; | |
4aac0473 JG |
83 | return radeon_gart_table_vram_alloc(rdev); |
84 | } | |
85 | ||
86 | int rs600_gart_enable(struct radeon_device *rdev) | |
87 | { | |
c010f800 | 88 | u32 tmp; |
4aac0473 JG |
89 | int r, i; |
90 | ||
91 | if (rdev->gart.table.vram.robj == NULL) { | |
92 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
93 | return -EINVAL; | |
771fe6b9 | 94 | } |
4aac0473 JG |
95 | r = radeon_gart_table_vram_pin(rdev); |
96 | if (r) | |
97 | return r; | |
c010f800 JG |
98 | /* Enable bus master */ |
99 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; | |
100 | WREG32(R_00004C_BUS_CNTL, tmp); | |
771fe6b9 | 101 | /* FIXME: setup default page */ |
c010f800 JG |
102 | WREG32_MC(R_000100_MC_PT0_CNTL, |
103 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | | |
104 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); | |
771fe6b9 | 105 | for (i = 0; i < 19; i++) { |
c010f800 JG |
106 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
107 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | | |
108 | S_00016C_SYSTEM_ACCESS_MODE_MASK( | |
109 | V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) | | |
110 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( | |
111 | V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) | | |
112 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) | | |
113 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | | |
114 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1)); | |
771fe6b9 JG |
115 | } |
116 | ||
117 | /* System context map to GART space */ | |
c010f800 JG |
118 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start); |
119 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end); | |
771fe6b9 JG |
120 | |
121 | /* enable first context */ | |
c010f800 JG |
122 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
123 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); | |
124 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, | |
125 | S_000102_ENABLE_PAGE_TABLE(1) | | |
126 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); | |
771fe6b9 JG |
127 | /* disable all other contexts */ |
128 | for (i = 1; i < 8; i++) { | |
c010f800 | 129 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
771fe6b9 JG |
130 | } |
131 | ||
132 | /* setup the page table */ | |
c010f800 JG |
133 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
134 | rdev->gart.table_addr); | |
135 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); | |
771fe6b9 JG |
136 | |
137 | /* enable page tables */ | |
c010f800 JG |
138 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
139 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); | |
140 | tmp = RREG32_MC(R_000009_MC_CNTL1); | |
141 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); | |
771fe6b9 JG |
142 | rs600_gart_tlb_flush(rdev); |
143 | rdev->gart.ready = true; | |
144 | return 0; | |
145 | } | |
146 | ||
147 | void rs600_gart_disable(struct radeon_device *rdev) | |
148 | { | |
149 | uint32_t tmp; | |
150 | ||
151 | /* FIXME: disable out of gart access */ | |
c010f800 JG |
152 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
153 | tmp = RREG32_MC(R_000009_MC_CNTL1); | |
154 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); | |
4aac0473 JG |
155 | if (rdev->gart.table.vram.robj) { |
156 | radeon_object_kunmap(rdev->gart.table.vram.robj); | |
157 | radeon_object_unpin(rdev->gart.table.vram.robj); | |
158 | } | |
159 | } | |
160 | ||
161 | void rs600_gart_fini(struct radeon_device *rdev) | |
162 | { | |
163 | rs600_gart_disable(rdev); | |
164 | radeon_gart_table_vram_free(rdev); | |
165 | radeon_gart_fini(rdev); | |
771fe6b9 JG |
166 | } |
167 | ||
168 | #define R600_PTE_VALID (1 << 0) | |
169 | #define R600_PTE_SYSTEM (1 << 1) | |
170 | #define R600_PTE_SNOOPED (1 << 2) | |
171 | #define R600_PTE_READABLE (1 << 5) | |
172 | #define R600_PTE_WRITEABLE (1 << 6) | |
173 | ||
174 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |
175 | { | |
176 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; | |
177 | ||
178 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | |
179 | return -EINVAL; | |
180 | } | |
181 | addr = addr & 0xFFFFFFFFFFFFF000ULL; | |
182 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; | |
183 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; | |
184 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); | |
185 | return 0; | |
186 | } | |
187 | ||
7ed220d7 MD |
188 | int rs600_irq_set(struct radeon_device *rdev) |
189 | { | |
190 | uint32_t tmp = 0; | |
191 | uint32_t mode_int = 0; | |
192 | ||
193 | if (rdev->irq.sw_int) { | |
c010f800 | 194 | tmp |= S_000040_SW_INT_EN(1); |
7ed220d7 MD |
195 | } |
196 | if (rdev->irq.crtc_vblank_int[0]) { | |
c010f800 | 197 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
7ed220d7 MD |
198 | } |
199 | if (rdev->irq.crtc_vblank_int[1]) { | |
c010f800 | 200 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
7ed220d7 | 201 | } |
c010f800 JG |
202 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
203 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); | |
7ed220d7 MD |
204 | return 0; |
205 | } | |
206 | ||
207 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) | |
208 | { | |
01ceae8e JG |
209 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
210 | uint32_t irq_mask = ~C_000044_SW_INT; | |
c010f800 | 211 | |
01ceae8e | 212 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
c010f800 JG |
213 | *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
214 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { | |
215 | WREG32(R_006534_D1MODE_VBLANK_STATUS, | |
216 | S_006534_D1MODE_VBLANK_ACK(1)); | |
7ed220d7 | 217 | } |
c010f800 JG |
218 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
219 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, | |
220 | S_006D34_D2MODE_VBLANK_ACK(1)); | |
7ed220d7 MD |
221 | } |
222 | } else { | |
223 | *r500_disp_int = 0; | |
224 | } | |
225 | ||
226 | if (irqs) { | |
01ceae8e | 227 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
7ed220d7 MD |
228 | } |
229 | return irqs & irq_mask; | |
230 | } | |
231 | ||
ac447df4 JG |
232 | void rs600_irq_disable(struct radeon_device *rdev) |
233 | { | |
234 | u32 tmp; | |
235 | ||
236 | WREG32(R_000040_GEN_INT_CNTL, 0); | |
237 | WREG32(R_006540_DxMODE_INT_MASK, 0); | |
238 | /* Wait and acknowledge irq */ | |
239 | mdelay(1); | |
240 | rs600_irq_ack(rdev, &tmp); | |
241 | } | |
242 | ||
7ed220d7 MD |
243 | int rs600_irq_process(struct radeon_device *rdev) |
244 | { | |
3e5cb98d | 245 | uint32_t status, msi_rearm; |
7ed220d7 MD |
246 | uint32_t r500_disp_int; |
247 | ||
248 | status = rs600_irq_ack(rdev, &r500_disp_int); | |
249 | if (!status && !r500_disp_int) { | |
250 | return IRQ_NONE; | |
251 | } | |
252 | while (status || r500_disp_int) { | |
253 | /* SW interrupt */ | |
c010f800 | 254 | if (G_000040_SW_INT_EN(status)) |
7ed220d7 | 255 | radeon_fence_process(rdev); |
7ed220d7 | 256 | /* Vertical blank interrupts */ |
c010f800 | 257 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) |
7ed220d7 | 258 | drm_handle_vblank(rdev->ddev, 0); |
c010f800 | 259 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) |
7ed220d7 | 260 | drm_handle_vblank(rdev->ddev, 1); |
7ed220d7 MD |
261 | status = rs600_irq_ack(rdev, &r500_disp_int); |
262 | } | |
3e5cb98d AD |
263 | if (rdev->msi_enabled) { |
264 | switch (rdev->family) { | |
265 | case CHIP_RS600: | |
266 | case CHIP_RS690: | |
267 | case CHIP_RS740: | |
268 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; | |
269 | WREG32(RADEON_BUS_CNTL, msi_rearm); | |
270 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); | |
271 | break; | |
272 | default: | |
273 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; | |
274 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); | |
275 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); | |
276 | break; | |
277 | } | |
278 | } | |
7ed220d7 MD |
279 | return IRQ_HANDLED; |
280 | } | |
281 | ||
282 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
283 | { | |
284 | if (crtc == 0) | |
c010f800 | 285 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
7ed220d7 | 286 | else |
c010f800 | 287 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
7ed220d7 MD |
288 | } |
289 | ||
771fe6b9 JG |
290 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
291 | { | |
292 | unsigned i; | |
771fe6b9 JG |
293 | |
294 | for (i = 0; i < rdev->usec_timeout; i++) { | |
c010f800 | 295 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
771fe6b9 | 296 | return 0; |
c010f800 | 297 | udelay(1); |
771fe6b9 JG |
298 | } |
299 | return -1; | |
300 | } | |
301 | ||
771fe6b9 JG |
302 | void rs600_gpu_init(struct radeon_device *rdev) |
303 | { | |
304 | /* FIXME: HDP same place on rs600 ? */ | |
305 | r100_hdp_reset(rdev); | |
771fe6b9 JG |
306 | /* FIXME: is this correct ? */ |
307 | r420_pipes_init(rdev); | |
c010f800 JG |
308 | /* Wait for mc idle */ |
309 | if (rs600_mc_wait_for_idle(rdev)) | |
310 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
771fe6b9 JG |
311 | } |
312 | ||
771fe6b9 JG |
313 | void rs600_vram_info(struct radeon_device *rdev) |
314 | { | |
315 | /* FIXME: to do or is these values sane ? */ | |
316 | rdev->mc.vram_is_ddr = true; | |
317 | rdev->mc.vram_width = 128; | |
318 | } | |
319 | ||
c93bb85b JG |
320 | void rs600_bandwidth_update(struct radeon_device *rdev) |
321 | { | |
322 | /* FIXME: implement, should this be like rs690 ? */ | |
323 | } | |
324 | ||
771fe6b9 JG |
325 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
326 | { | |
c010f800 JG |
327 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
328 | S_000070_MC_IND_CITF_ARB0(1)); | |
329 | return RREG32(R_000074_MC_IND_DATA); | |
771fe6b9 JG |
330 | } |
331 | ||
332 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
333 | { | |
c010f800 JG |
334 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
335 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); | |
336 | WREG32(R_000074_MC_IND_DATA, v); | |
337 | } | |
338 | ||
339 | void rs600_debugfs(struct radeon_device *rdev) | |
340 | { | |
341 | if (r100_debugfs_rbbm_init(rdev)) | |
342 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
771fe6b9 | 343 | } |
3f7dc91a | 344 | |
3bc68535 | 345 | void rs600_set_safe_registers(struct radeon_device *rdev) |
3f7dc91a DA |
346 | { |
347 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; | |
348 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); | |
3bc68535 JG |
349 | } |
350 | ||
c010f800 JG |
351 | static void rs600_mc_program(struct radeon_device *rdev) |
352 | { | |
353 | struct rv515_mc_save save; | |
354 | ||
355 | /* Stops all mc clients */ | |
356 | rv515_mc_stop(rdev, &save); | |
357 | ||
358 | /* Wait for mc idle */ | |
359 | if (rs600_mc_wait_for_idle(rdev)) | |
360 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
361 | ||
362 | /* FIXME: What does AGP means for such chipset ? */ | |
363 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); | |
364 | WREG32_MC(R_000006_AGP_BASE, 0); | |
365 | WREG32_MC(R_000007_AGP_BASE_2, 0); | |
366 | /* Program MC */ | |
367 | WREG32_MC(R_000004_MC_FB_LOCATION, | |
368 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | | |
369 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
370 | WREG32(R_000134_HDP_FB_LOCATION, | |
371 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
372 | ||
373 | rv515_mc_resume(rdev, &save); | |
374 | } | |
375 | ||
376 | static int rs600_startup(struct radeon_device *rdev) | |
377 | { | |
378 | int r; | |
379 | ||
380 | rs600_mc_program(rdev); | |
381 | /* Resume clock */ | |
382 | rv515_clock_startup(rdev); | |
383 | /* Initialize GPU configuration (# pipes, ...) */ | |
384 | rs600_gpu_init(rdev); | |
385 | /* Initialize GART (initialize after TTM so we can allocate | |
386 | * memory through TTM but finalize after TTM) */ | |
387 | r = rs600_gart_enable(rdev); | |
388 | if (r) | |
389 | return r; | |
390 | /* Enable IRQ */ | |
391 | rdev->irq.sw_int = true; | |
392 | rs600_irq_set(rdev); | |
393 | /* 1M ring buffer */ | |
394 | r = r100_cp_init(rdev, 1024 * 1024); | |
395 | if (r) { | |
396 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
397 | return r; | |
398 | } | |
399 | r = r100_wb_init(rdev); | |
400 | if (r) | |
401 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
402 | r = r100_ib_init(rdev); | |
403 | if (r) { | |
404 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
405 | return r; | |
406 | } | |
407 | return 0; | |
408 | } | |
409 | ||
410 | int rs600_resume(struct radeon_device *rdev) | |
411 | { | |
412 | /* Make sur GART are not working */ | |
413 | rs600_gart_disable(rdev); | |
414 | /* Resume clock before doing reset */ | |
415 | rv515_clock_startup(rdev); | |
416 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
417 | if (radeon_gpu_reset(rdev)) { | |
418 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
419 | RREG32(R_000E40_RBBM_STATUS), | |
420 | RREG32(R_0007C0_CP_STAT)); | |
421 | } | |
422 | /* post */ | |
423 | atom_asic_init(rdev->mode_info.atom_context); | |
424 | /* Resume clock after posting */ | |
425 | rv515_clock_startup(rdev); | |
426 | return rs600_startup(rdev); | |
427 | } | |
428 | ||
429 | int rs600_suspend(struct radeon_device *rdev) | |
430 | { | |
431 | r100_cp_disable(rdev); | |
432 | r100_wb_disable(rdev); | |
ac447df4 | 433 | rs600_irq_disable(rdev); |
c010f800 JG |
434 | rs600_gart_disable(rdev); |
435 | return 0; | |
436 | } | |
437 | ||
438 | void rs600_fini(struct radeon_device *rdev) | |
439 | { | |
440 | rs600_suspend(rdev); | |
441 | r100_cp_fini(rdev); | |
442 | r100_wb_fini(rdev); | |
443 | r100_ib_fini(rdev); | |
444 | radeon_gem_fini(rdev); | |
445 | rs600_gart_fini(rdev); | |
446 | radeon_irq_kms_fini(rdev); | |
447 | radeon_fence_driver_fini(rdev); | |
448 | radeon_object_fini(rdev); | |
449 | radeon_atombios_fini(rdev); | |
450 | kfree(rdev->bios); | |
451 | rdev->bios = NULL; | |
452 | } | |
453 | ||
3bc68535 JG |
454 | int rs600_init(struct radeon_device *rdev) |
455 | { | |
c010f800 JG |
456 | int r; |
457 | ||
c010f800 JG |
458 | /* Disable VGA */ |
459 | rv515_vga_render_disable(rdev); | |
460 | /* Initialize scratch registers */ | |
461 | radeon_scratch_init(rdev); | |
462 | /* Initialize surface registers */ | |
463 | radeon_surface_init(rdev); | |
464 | /* BIOS */ | |
465 | if (!radeon_get_bios(rdev)) { | |
466 | if (ASIC_IS_AVIVO(rdev)) | |
467 | return -EINVAL; | |
468 | } | |
469 | if (rdev->is_atom_bios) { | |
470 | r = radeon_atombios_init(rdev); | |
471 | if (r) | |
472 | return r; | |
473 | } else { | |
474 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); | |
475 | return -EINVAL; | |
476 | } | |
477 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
478 | if (radeon_gpu_reset(rdev)) { | |
479 | dev_warn(rdev->dev, | |
480 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
481 | RREG32(R_000E40_RBBM_STATUS), | |
482 | RREG32(R_0007C0_CP_STAT)); | |
483 | } | |
484 | /* check if cards are posted or not */ | |
485 | if (!radeon_card_posted(rdev) && rdev->bios) { | |
486 | DRM_INFO("GPU not posted. posting now...\n"); | |
487 | atom_asic_init(rdev->mode_info.atom_context); | |
488 | } | |
489 | /* Initialize clocks */ | |
490 | radeon_get_clock_info(rdev->ddev); | |
491 | /* Get vram informations */ | |
492 | rs600_vram_info(rdev); | |
493 | /* Initialize memory controller (also test AGP) */ | |
494 | r = r420_mc_init(rdev); | |
495 | if (r) | |
496 | return r; | |
497 | rs600_debugfs(rdev); | |
498 | /* Fence driver */ | |
499 | r = radeon_fence_driver_init(rdev); | |
500 | if (r) | |
501 | return r; | |
502 | r = radeon_irq_kms_init(rdev); | |
503 | if (r) | |
504 | return r; | |
505 | /* Memory manager */ | |
506 | r = radeon_object_init(rdev); | |
507 | if (r) | |
508 | return r; | |
509 | r = rs600_gart_init(rdev); | |
510 | if (r) | |
511 | return r; | |
512 | rs600_set_safe_registers(rdev); | |
513 | rdev->accel_working = true; | |
514 | r = rs600_startup(rdev); | |
515 | if (r) { | |
516 | /* Somethings want wront with the accel init stop accel */ | |
517 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
518 | rs600_suspend(rdev); | |
519 | r100_cp_fini(rdev); | |
520 | r100_wb_fini(rdev); | |
521 | r100_ib_fini(rdev); | |
522 | rs600_gart_fini(rdev); | |
523 | radeon_irq_kms_fini(rdev); | |
524 | rdev->accel_working = false; | |
525 | } | |
3f7dc91a DA |
526 | return 0; |
527 | } |