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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
771fe6b9 | 29 | #include "radeon.h" |
e6990375 | 30 | #include "radeon_asic.h" |
c93bb85b | 31 | #include "atom.h" |
3bc68535 | 32 | #include "rs690d.h" |
771fe6b9 | 33 | |
3bc68535 | 34 | static int rs690_mc_wait_for_idle(struct radeon_device *rdev) |
771fe6b9 JG |
35 | { |
36 | unsigned i; | |
37 | uint32_t tmp; | |
38 | ||
39 | for (i = 0; i < rdev->usec_timeout; i++) { | |
40 | /* read MC_STATUS */ | |
3bc68535 JG |
41 | tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); |
42 | if (G_000090_MC_SYSTEM_IDLE(tmp)) | |
771fe6b9 | 43 | return 0; |
3bc68535 | 44 | udelay(1); |
771fe6b9 JG |
45 | } |
46 | return -1; | |
47 | } | |
48 | ||
3bc68535 | 49 | static void rs690_gpu_init(struct radeon_device *rdev) |
771fe6b9 | 50 | { |
771fe6b9 JG |
51 | /* FIXME: is this correct ? */ |
52 | r420_pipes_init(rdev); | |
53 | if (rs690_mc_wait_for_idle(rdev)) { | |
54 | printk(KERN_WARNING "Failed to wait MC idle while " | |
55 | "programming pipes. Bad things might happen.\n"); | |
56 | } | |
57 | } | |
58 | ||
a084e6ee AD |
59 | union igp_info { |
60 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; | |
61 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; | |
62 | }; | |
63 | ||
c93bb85b JG |
64 | void rs690_pm_info(struct radeon_device *rdev) |
65 | { | |
66 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
a084e6ee | 67 | union igp_info *info; |
c93bb85b JG |
68 | uint16_t data_offset; |
69 | uint8_t frev, crev; | |
70 | fixed20_12 tmp; | |
71 | ||
a084e6ee AD |
72 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, |
73 | &frev, &crev, &data_offset)) { | |
74 | info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); | |
75 | ||
76 | /* Get various system informations from bios */ | |
77 | switch (crev) { | |
78 | case 1: | |
68adac5e BS |
79 | tmp.full = dfixed_const(100); |
80 | rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock); | |
81 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); | |
f892034a AD |
82 | if (info->info.usK8MemoryClock) |
83 | rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); | |
84 | else if (rdev->clock.default_mclk) { | |
85 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); | |
86 | rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); | |
87 | } else | |
88 | rdev->pm.igp_system_mclk.full = dfixed_const(400); | |
68adac5e BS |
89 | rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); |
90 | rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); | |
a084e6ee AD |
91 | break; |
92 | case 2: | |
68adac5e BS |
93 | tmp.full = dfixed_const(100); |
94 | rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock); | |
95 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); | |
f892034a AD |
96 | if (info->info_v2.ulBootUpUMAClock) |
97 | rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock); | |
98 | else if (rdev->clock.default_mclk) | |
99 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); | |
100 | else | |
101 | rdev->pm.igp_system_mclk.full = dfixed_const(66700); | |
68adac5e BS |
102 | rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); |
103 | rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq); | |
104 | rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); | |
105 | rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); | |
a084e6ee AD |
106 | break; |
107 | default: | |
a084e6ee | 108 | /* We assume the slower possible clock ie worst case */ |
f892034a AD |
109 | rdev->pm.igp_sideport_mclk.full = dfixed_const(200); |
110 | rdev->pm.igp_system_mclk.full = dfixed_const(200); | |
111 | rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); | |
68adac5e | 112 | rdev->pm.igp_ht_link_width.full = dfixed_const(8); |
a084e6ee AD |
113 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
114 | break; | |
115 | } | |
116 | } else { | |
c93bb85b | 117 | /* We assume the slower possible clock ie worst case */ |
f892034a AD |
118 | rdev->pm.igp_sideport_mclk.full = dfixed_const(200); |
119 | rdev->pm.igp_system_mclk.full = dfixed_const(200); | |
120 | rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); | |
68adac5e | 121 | rdev->pm.igp_ht_link_width.full = dfixed_const(8); |
c93bb85b | 122 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
c93bb85b JG |
123 | } |
124 | /* Compute various bandwidth */ | |
125 | /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ | |
68adac5e BS |
126 | tmp.full = dfixed_const(4); |
127 | rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); | |
c93bb85b JG |
128 | /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 |
129 | * = ht_clk * ht_width / 5 | |
130 | */ | |
68adac5e BS |
131 | tmp.full = dfixed_const(5); |
132 | rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, | |
c93bb85b | 133 | rdev->pm.igp_ht_link_width); |
68adac5e | 134 | rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); |
c93bb85b JG |
135 | if (tmp.full < rdev->pm.max_bandwidth.full) { |
136 | /* HT link is a limiting factor */ | |
137 | rdev->pm.max_bandwidth.full = tmp.full; | |
138 | } | |
139 | /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 | |
140 | * = (sideport_clk * 14) / 10 | |
141 | */ | |
68adac5e BS |
142 | tmp.full = dfixed_const(14); |
143 | rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); | |
144 | tmp.full = dfixed_const(10); | |
145 | rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); | |
c93bb85b JG |
146 | } |
147 | ||
d594e46a | 148 | void rs690_mc_init(struct radeon_device *rdev) |
771fe6b9 | 149 | { |
d594e46a | 150 | u64 base; |
771fe6b9 JG |
151 | |
152 | rs400_gart_adjust_size(rdev); | |
771fe6b9 | 153 | rdev->mc.vram_is_ddr = true; |
722f2943 | 154 | rdev->mc.vram_width = 128; |
7a50f01a DA |
155 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
156 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
01d73a69 JC |
157 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
158 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
51e5fcd3 | 159 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a JG |
160 | base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); |
161 | base = G_000100_MC_FB_START(base) << 16; | |
c93bb85b | 162 | rs690_pm_info(rdev); |
06b6476d | 163 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
d594e46a JG |
164 | radeon_vram_location(rdev, &rdev->mc, base); |
165 | radeon_gtt_location(rdev, &rdev->mc); | |
f47299c5 | 166 | radeon_update_bandwidth_info(rdev); |
22dd5013 AD |
167 | } |
168 | ||
c93bb85b JG |
169 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
170 | struct drm_display_mode *mode1, | |
171 | struct drm_display_mode *mode2) | |
172 | { | |
173 | u32 tmp; | |
174 | ||
175 | /* | |
176 | * Line Buffer Setup | |
177 | * There is a single line buffer shared by both display controllers. | |
3bc68535 | 178 | * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between |
c93bb85b JG |
179 | * the display controllers. The paritioning can either be done |
180 | * manually or via one of four preset allocations specified in bits 1:0: | |
181 | * 0 - line buffer is divided in half and shared between crtc | |
182 | * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 | |
183 | * 2 - D1 gets the whole buffer | |
184 | * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 | |
3bc68535 | 185 | * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual |
c93bb85b JG |
186 | * allocation mode. In manual allocation mode, D1 always starts at 0, |
187 | * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. | |
188 | */ | |
3bc68535 JG |
189 | tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; |
190 | tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; | |
c93bb85b JG |
191 | /* auto */ |
192 | if (mode1 && mode2) { | |
193 | if (mode1->hdisplay > mode2->hdisplay) { | |
194 | if (mode1->hdisplay > 2560) | |
3bc68535 | 195 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; |
c93bb85b | 196 | else |
3bc68535 | 197 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
c93bb85b JG |
198 | } else if (mode2->hdisplay > mode1->hdisplay) { |
199 | if (mode2->hdisplay > 2560) | |
3bc68535 | 200 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
c93bb85b | 201 | else |
3bc68535 | 202 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
c93bb85b | 203 | } else |
3bc68535 | 204 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
c93bb85b | 205 | } else if (mode1) { |
3bc68535 | 206 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; |
c93bb85b | 207 | } else if (mode2) { |
3bc68535 | 208 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
c93bb85b | 209 | } |
3bc68535 | 210 | WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); |
771fe6b9 JG |
211 | } |
212 | ||
c93bb85b JG |
213 | struct rs690_watermark { |
214 | u32 lb_request_fifo_depth; | |
215 | fixed20_12 num_line_pair; | |
216 | fixed20_12 estimated_width; | |
217 | fixed20_12 worst_case_latency; | |
218 | fixed20_12 consumption_rate; | |
219 | fixed20_12 active_time; | |
220 | fixed20_12 dbpp; | |
221 | fixed20_12 priority_mark_max; | |
222 | fixed20_12 priority_mark; | |
223 | fixed20_12 sclk; | |
224 | }; | |
225 | ||
226 | void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, | |
227 | struct radeon_crtc *crtc, | |
228 | struct rs690_watermark *wm) | |
229 | { | |
230 | struct drm_display_mode *mode = &crtc->base.mode; | |
231 | fixed20_12 a, b, c; | |
232 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; | |
233 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; | |
c93bb85b JG |
234 | |
235 | if (!crtc->base.enabled) { | |
236 | /* FIXME: wouldn't it better to set priority mark to maximum */ | |
237 | wm->lb_request_fifo_depth = 4; | |
238 | return; | |
239 | } | |
240 | ||
68adac5e BS |
241 | if (crtc->vsc.full > dfixed_const(2)) |
242 | wm->num_line_pair.full = dfixed_const(2); | |
c93bb85b | 243 | else |
68adac5e BS |
244 | wm->num_line_pair.full = dfixed_const(1); |
245 | ||
246 | b.full = dfixed_const(mode->crtc_hdisplay); | |
247 | c.full = dfixed_const(256); | |
248 | a.full = dfixed_div(b, c); | |
249 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); | |
250 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); | |
251 | if (a.full < dfixed_const(4)) { | |
c93bb85b JG |
252 | wm->lb_request_fifo_depth = 4; |
253 | } else { | |
68adac5e | 254 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
c93bb85b JG |
255 | } |
256 | ||
257 | /* Determine consumption rate | |
258 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) | |
259 | * vtaps = number of vertical taps, | |
260 | * vsc = vertical scaling ratio, defined as source/destination | |
261 | * hsc = horizontal scaling ration, defined as source/destination | |
262 | */ | |
68adac5e BS |
263 | a.full = dfixed_const(mode->clock); |
264 | b.full = dfixed_const(1000); | |
265 | a.full = dfixed_div(a, b); | |
266 | pclk.full = dfixed_div(b, a); | |
c93bb85b | 267 | if (crtc->rmx_type != RMX_OFF) { |
68adac5e | 268 | b.full = dfixed_const(2); |
c93bb85b JG |
269 | if (crtc->vsc.full > b.full) |
270 | b.full = crtc->vsc.full; | |
68adac5e BS |
271 | b.full = dfixed_mul(b, crtc->hsc); |
272 | c.full = dfixed_const(2); | |
273 | b.full = dfixed_div(b, c); | |
274 | consumption_time.full = dfixed_div(pclk, b); | |
c93bb85b JG |
275 | } else { |
276 | consumption_time.full = pclk.full; | |
277 | } | |
68adac5e BS |
278 | a.full = dfixed_const(1); |
279 | wm->consumption_rate.full = dfixed_div(a, consumption_time); | |
c93bb85b JG |
280 | |
281 | ||
282 | /* Determine line time | |
283 | * LineTime = total time for one line of displayhtotal | |
284 | * LineTime = total number of horizontal pixels | |
285 | * pclk = pixel clock period(ns) | |
286 | */ | |
68adac5e BS |
287 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
288 | line_time.full = dfixed_mul(a, pclk); | |
c93bb85b JG |
289 | |
290 | /* Determine active time | |
291 | * ActiveTime = time of active region of display within one line, | |
292 | * hactive = total number of horizontal active pixels | |
293 | * htotal = total number of horizontal pixels | |
294 | */ | |
68adac5e BS |
295 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
296 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); | |
297 | wm->active_time.full = dfixed_mul(line_time, b); | |
298 | wm->active_time.full = dfixed_div(wm->active_time, a); | |
c93bb85b JG |
299 | |
300 | /* Maximun bandwidth is the minimun bandwidth of all component */ | |
301 | rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; | |
0888e883 | 302 | if (rdev->mc.igp_sideport_enabled) { |
c93bb85b JG |
303 | if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && |
304 | rdev->pm.sideport_bandwidth.full) | |
305 | rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; | |
68adac5e BS |
306 | read_delay_latency.full = dfixed_const(370 * 800 * 1000); |
307 | read_delay_latency.full = dfixed_div(read_delay_latency, | |
c93bb85b JG |
308 | rdev->pm.igp_sideport_mclk); |
309 | } else { | |
310 | if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && | |
311 | rdev->pm.k8_bandwidth.full) | |
312 | rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; | |
313 | if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && | |
314 | rdev->pm.ht_bandwidth.full) | |
315 | rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; | |
68adac5e | 316 | read_delay_latency.full = dfixed_const(5000); |
c93bb85b JG |
317 | } |
318 | ||
319 | /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ | |
68adac5e BS |
320 | a.full = dfixed_const(16); |
321 | rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a); | |
322 | a.full = dfixed_const(1000); | |
323 | rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk); | |
c93bb85b JG |
324 | /* Determine chunk time |
325 | * ChunkTime = the time it takes the DCP to send one chunk of data | |
326 | * to the LB which consists of pipeline delay and inter chunk gap | |
327 | * sclk = system clock(ns) | |
328 | */ | |
68adac5e BS |
329 | a.full = dfixed_const(256 * 13); |
330 | chunk_time.full = dfixed_mul(rdev->pm.sclk, a); | |
331 | a.full = dfixed_const(10); | |
332 | chunk_time.full = dfixed_div(chunk_time, a); | |
c93bb85b JG |
333 | |
334 | /* Determine the worst case latency | |
335 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) | |
336 | * WorstCaseLatency = worst case time from urgent to when the MC starts | |
337 | * to return data | |
338 | * READ_DELAY_IDLE_MAX = constant of 1us | |
339 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB | |
340 | * which consists of pipeline delay and inter chunk gap | |
341 | */ | |
68adac5e BS |
342 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
343 | a.full = dfixed_const(3); | |
344 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); | |
c93bb85b JG |
345 | wm->worst_case_latency.full += read_delay_latency.full; |
346 | } else { | |
68adac5e BS |
347 | a.full = dfixed_const(2); |
348 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); | |
c93bb85b JG |
349 | wm->worst_case_latency.full += read_delay_latency.full; |
350 | } | |
351 | ||
352 | /* Determine the tolerable latency | |
353 | * TolerableLatency = Any given request has only 1 line time | |
354 | * for the data to be returned | |
355 | * LBRequestFifoDepth = Number of chunk requests the LB can | |
356 | * put into the request FIFO for a display | |
357 | * LineTime = total time for one line of display | |
358 | * ChunkTime = the time it takes the DCP to send one chunk | |
359 | * of data to the LB which consists of | |
360 | * pipeline delay and inter chunk gap | |
361 | */ | |
68adac5e | 362 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
c93bb85b JG |
363 | tolerable_latency.full = line_time.full; |
364 | } else { | |
68adac5e | 365 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
c93bb85b | 366 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
68adac5e | 367 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
c93bb85b JG |
368 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
369 | } | |
370 | /* We assume worst case 32bits (4 bytes) */ | |
68adac5e | 371 | wm->dbpp.full = dfixed_const(4 * 8); |
c93bb85b JG |
372 | |
373 | /* Determine the maximum priority mark | |
374 | * width = viewport width in pixels | |
375 | */ | |
68adac5e BS |
376 | a.full = dfixed_const(16); |
377 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); | |
378 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); | |
379 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); | |
c93bb85b JG |
380 | |
381 | /* Determine estimated width */ | |
382 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; | |
68adac5e BS |
383 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
384 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | |
385 | wm->priority_mark.full = dfixed_const(10); | |
c93bb85b | 386 | } else { |
68adac5e BS |
387 | a.full = dfixed_const(16); |
388 | wm->priority_mark.full = dfixed_div(estimated_width, a); | |
389 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); | |
c93bb85b JG |
390 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
391 | } | |
392 | } | |
393 | ||
394 | void rs690_bandwidth_update(struct radeon_device *rdev) | |
395 | { | |
396 | struct drm_display_mode *mode0 = NULL; | |
397 | struct drm_display_mode *mode1 = NULL; | |
398 | struct rs690_watermark wm0; | |
399 | struct rs690_watermark wm1; | |
f46c0120 | 400 | u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
c93bb85b JG |
401 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
402 | fixed20_12 a, b; | |
403 | ||
f46c0120 AD |
404 | radeon_update_display_priority(rdev); |
405 | ||
c93bb85b JG |
406 | if (rdev->mode_info.crtcs[0]->base.enabled) |
407 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | |
408 | if (rdev->mode_info.crtcs[1]->base.enabled) | |
409 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | |
410 | /* | |
411 | * Set display0/1 priority up in the memory controller for | |
412 | * modes if the user specifies HIGH for displaypriority | |
413 | * option. | |
414 | */ | |
f46c0120 AD |
415 | if ((rdev->disp_priority == 2) && |
416 | ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { | |
3bc68535 JG |
417 | tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); |
418 | tmp &= C_000104_MC_DISP0R_INIT_LAT; | |
419 | tmp &= C_000104_MC_DISP1R_INIT_LAT; | |
c93bb85b | 420 | if (mode0) |
3bc68535 JG |
421 | tmp |= S_000104_MC_DISP0R_INIT_LAT(1); |
422 | if (mode1) | |
423 | tmp |= S_000104_MC_DISP1R_INIT_LAT(1); | |
424 | WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); | |
c93bb85b JG |
425 | } |
426 | rs690_line_buffer_adjust(rdev, mode0, mode1); | |
427 | ||
428 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) | |
3bc68535 | 429 | WREG32(R_006C9C_DCP_CONTROL, 0); |
c93bb85b | 430 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
3bc68535 | 431 | WREG32(R_006C9C_DCP_CONTROL, 2); |
c93bb85b JG |
432 | |
433 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); | |
434 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); | |
435 | ||
436 | tmp = (wm0.lb_request_fifo_depth - 1); | |
437 | tmp |= (wm1.lb_request_fifo_depth - 1) << 16; | |
3bc68535 | 438 | WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); |
c93bb85b JG |
439 | |
440 | if (mode0 && mode1) { | |
68adac5e BS |
441 | if (dfixed_trunc(wm0.dbpp) > 64) |
442 | a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); | |
c93bb85b JG |
443 | else |
444 | a.full = wm0.num_line_pair.full; | |
68adac5e BS |
445 | if (dfixed_trunc(wm1.dbpp) > 64) |
446 | b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); | |
c93bb85b JG |
447 | else |
448 | b.full = wm1.num_line_pair.full; | |
449 | a.full += b.full; | |
68adac5e | 450 | fill_rate.full = dfixed_div(wm0.sclk, a); |
c93bb85b JG |
451 | if (wm0.consumption_rate.full > fill_rate.full) { |
452 | b.full = wm0.consumption_rate.full - fill_rate.full; | |
68adac5e BS |
453 | b.full = dfixed_mul(b, wm0.active_time); |
454 | a.full = dfixed_mul(wm0.worst_case_latency, | |
c93bb85b JG |
455 | wm0.consumption_rate); |
456 | a.full = a.full + b.full; | |
68adac5e BS |
457 | b.full = dfixed_const(16 * 1000); |
458 | priority_mark02.full = dfixed_div(a, b); | |
c93bb85b | 459 | } else { |
68adac5e | 460 | a.full = dfixed_mul(wm0.worst_case_latency, |
c93bb85b | 461 | wm0.consumption_rate); |
68adac5e BS |
462 | b.full = dfixed_const(16 * 1000); |
463 | priority_mark02.full = dfixed_div(a, b); | |
c93bb85b JG |
464 | } |
465 | if (wm1.consumption_rate.full > fill_rate.full) { | |
466 | b.full = wm1.consumption_rate.full - fill_rate.full; | |
68adac5e BS |
467 | b.full = dfixed_mul(b, wm1.active_time); |
468 | a.full = dfixed_mul(wm1.worst_case_latency, | |
c93bb85b JG |
469 | wm1.consumption_rate); |
470 | a.full = a.full + b.full; | |
68adac5e BS |
471 | b.full = dfixed_const(16 * 1000); |
472 | priority_mark12.full = dfixed_div(a, b); | |
c93bb85b | 473 | } else { |
68adac5e | 474 | a.full = dfixed_mul(wm1.worst_case_latency, |
c93bb85b | 475 | wm1.consumption_rate); |
68adac5e BS |
476 | b.full = dfixed_const(16 * 1000); |
477 | priority_mark12.full = dfixed_div(a, b); | |
c93bb85b JG |
478 | } |
479 | if (wm0.priority_mark.full > priority_mark02.full) | |
480 | priority_mark02.full = wm0.priority_mark.full; | |
68adac5e | 481 | if (dfixed_trunc(priority_mark02) < 0) |
c93bb85b JG |
482 | priority_mark02.full = 0; |
483 | if (wm0.priority_mark_max.full > priority_mark02.full) | |
484 | priority_mark02.full = wm0.priority_mark_max.full; | |
485 | if (wm1.priority_mark.full > priority_mark12.full) | |
486 | priority_mark12.full = wm1.priority_mark.full; | |
68adac5e | 487 | if (dfixed_trunc(priority_mark12) < 0) |
c93bb85b JG |
488 | priority_mark12.full = 0; |
489 | if (wm1.priority_mark_max.full > priority_mark12.full) | |
490 | priority_mark12.full = wm1.priority_mark_max.full; | |
68adac5e BS |
491 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
492 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | |
f46c0120 AD |
493 | if (rdev->disp_priority == 2) { |
494 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); | |
495 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); | |
496 | } | |
497 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | |
498 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | |
499 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | |
500 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | |
c93bb85b | 501 | } else if (mode0) { |
68adac5e BS |
502 | if (dfixed_trunc(wm0.dbpp) > 64) |
503 | a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); | |
c93bb85b JG |
504 | else |
505 | a.full = wm0.num_line_pair.full; | |
68adac5e | 506 | fill_rate.full = dfixed_div(wm0.sclk, a); |
c93bb85b JG |
507 | if (wm0.consumption_rate.full > fill_rate.full) { |
508 | b.full = wm0.consumption_rate.full - fill_rate.full; | |
68adac5e BS |
509 | b.full = dfixed_mul(b, wm0.active_time); |
510 | a.full = dfixed_mul(wm0.worst_case_latency, | |
c93bb85b JG |
511 | wm0.consumption_rate); |
512 | a.full = a.full + b.full; | |
68adac5e BS |
513 | b.full = dfixed_const(16 * 1000); |
514 | priority_mark02.full = dfixed_div(a, b); | |
c93bb85b | 515 | } else { |
68adac5e | 516 | a.full = dfixed_mul(wm0.worst_case_latency, |
c93bb85b | 517 | wm0.consumption_rate); |
68adac5e BS |
518 | b.full = dfixed_const(16 * 1000); |
519 | priority_mark02.full = dfixed_div(a, b); | |
c93bb85b JG |
520 | } |
521 | if (wm0.priority_mark.full > priority_mark02.full) | |
522 | priority_mark02.full = wm0.priority_mark.full; | |
68adac5e | 523 | if (dfixed_trunc(priority_mark02) < 0) |
c93bb85b JG |
524 | priority_mark02.full = 0; |
525 | if (wm0.priority_mark_max.full > priority_mark02.full) | |
526 | priority_mark02.full = wm0.priority_mark_max.full; | |
68adac5e | 527 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
f46c0120 AD |
528 | if (rdev->disp_priority == 2) |
529 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); | |
530 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | |
531 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | |
3bc68535 JG |
532 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, |
533 | S_006D48_D2MODE_PRIORITY_A_OFF(1)); | |
534 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, | |
535 | S_006D4C_D2MODE_PRIORITY_B_OFF(1)); | |
c93bb85b | 536 | } else { |
68adac5e BS |
537 | if (dfixed_trunc(wm1.dbpp) > 64) |
538 | a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); | |
c93bb85b JG |
539 | else |
540 | a.full = wm1.num_line_pair.full; | |
68adac5e | 541 | fill_rate.full = dfixed_div(wm1.sclk, a); |
c93bb85b JG |
542 | if (wm1.consumption_rate.full > fill_rate.full) { |
543 | b.full = wm1.consumption_rate.full - fill_rate.full; | |
68adac5e BS |
544 | b.full = dfixed_mul(b, wm1.active_time); |
545 | a.full = dfixed_mul(wm1.worst_case_latency, | |
c93bb85b JG |
546 | wm1.consumption_rate); |
547 | a.full = a.full + b.full; | |
68adac5e BS |
548 | b.full = dfixed_const(16 * 1000); |
549 | priority_mark12.full = dfixed_div(a, b); | |
c93bb85b | 550 | } else { |
68adac5e | 551 | a.full = dfixed_mul(wm1.worst_case_latency, |
c93bb85b | 552 | wm1.consumption_rate); |
68adac5e BS |
553 | b.full = dfixed_const(16 * 1000); |
554 | priority_mark12.full = dfixed_div(a, b); | |
c93bb85b JG |
555 | } |
556 | if (wm1.priority_mark.full > priority_mark12.full) | |
557 | priority_mark12.full = wm1.priority_mark.full; | |
68adac5e | 558 | if (dfixed_trunc(priority_mark12) < 0) |
c93bb85b JG |
559 | priority_mark12.full = 0; |
560 | if (wm1.priority_mark_max.full > priority_mark12.full) | |
561 | priority_mark12.full = wm1.priority_mark_max.full; | |
68adac5e | 562 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
f46c0120 AD |
563 | if (rdev->disp_priority == 2) |
564 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); | |
3bc68535 JG |
565 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, |
566 | S_006548_D1MODE_PRIORITY_A_OFF(1)); | |
567 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, | |
568 | S_00654C_D1MODE_PRIORITY_B_OFF(1)); | |
f46c0120 AD |
569 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
570 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | |
c93bb85b JG |
571 | } |
572 | } | |
771fe6b9 | 573 | |
771fe6b9 JG |
574 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
575 | { | |
576 | uint32_t r; | |
577 | ||
3bc68535 JG |
578 | WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); |
579 | r = RREG32(R_00007C_MC_DATA); | |
580 | WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); | |
771fe6b9 JG |
581 | return r; |
582 | } | |
583 | ||
584 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
585 | { | |
3bc68535 JG |
586 | WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | |
587 | S_000078_MC_IND_WR_EN(1)); | |
588 | WREG32(R_00007C_MC_DATA, v); | |
589 | WREG32(R_000078_MC_INDEX, 0x7F); | |
590 | } | |
591 | ||
592 | void rs690_mc_program(struct radeon_device *rdev) | |
593 | { | |
594 | struct rv515_mc_save save; | |
595 | ||
596 | /* Stops all mc clients */ | |
597 | rv515_mc_stop(rdev, &save); | |
598 | ||
599 | /* Wait for mc idle */ | |
600 | if (rs690_mc_wait_for_idle(rdev)) | |
601 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
602 | /* Program MC, should be a 32bits limited address space */ | |
603 | WREG32_MC(R_000100_MCCFG_FB_LOCATION, | |
604 | S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | | |
605 | S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
606 | WREG32(R_000134_HDP_FB_LOCATION, | |
607 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
608 | ||
609 | rv515_mc_resume(rdev, &save); | |
610 | } | |
611 | ||
612 | static int rs690_startup(struct radeon_device *rdev) | |
613 | { | |
614 | int r; | |
615 | ||
616 | rs690_mc_program(rdev); | |
617 | /* Resume clock */ | |
618 | rv515_clock_startup(rdev); | |
619 | /* Initialize GPU configuration (# pipes, ...) */ | |
620 | rs690_gpu_init(rdev); | |
621 | /* Initialize GART (initialize after TTM so we can allocate | |
622 | * memory through TTM but finalize after TTM) */ | |
623 | r = rs400_gart_enable(rdev); | |
624 | if (r) | |
625 | return r; | |
626 | /* Enable IRQ */ | |
ac447df4 | 627 | rs600_irq_set(rdev); |
cafe6609 | 628 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
3bc68535 JG |
629 | /* 1M ring buffer */ |
630 | r = r100_cp_init(rdev, 1024 * 1024); | |
631 | if (r) { | |
632 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
633 | return r; | |
634 | } | |
635 | r = r100_wb_init(rdev); | |
636 | if (r) | |
637 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
638 | r = r100_ib_init(rdev); | |
639 | if (r) { | |
640 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
641 | return r; | |
642 | } | |
fe50ac78 RM |
643 | |
644 | r = r600_audio_init(rdev); | |
645 | if (r) { | |
646 | dev_err(rdev->dev, "failed initializing audio\n"); | |
647 | return r; | |
648 | } | |
649 | ||
3bc68535 JG |
650 | return 0; |
651 | } | |
652 | ||
653 | int rs690_resume(struct radeon_device *rdev) | |
654 | { | |
655 | /* Make sur GART are not working */ | |
656 | rs400_gart_disable(rdev); | |
657 | /* Resume clock before doing reset */ | |
658 | rv515_clock_startup(rdev); | |
659 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 660 | if (radeon_asic_reset(rdev)) { |
3bc68535 JG |
661 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
662 | RREG32(R_000E40_RBBM_STATUS), | |
663 | RREG32(R_0007C0_CP_STAT)); | |
664 | } | |
665 | /* post */ | |
666 | atom_asic_init(rdev->mode_info.atom_context); | |
667 | /* Resume clock after posting */ | |
668 | rv515_clock_startup(rdev); | |
550e2d92 DA |
669 | /* Initialize surface registers */ |
670 | radeon_surface_init(rdev); | |
3bc68535 JG |
671 | return rs690_startup(rdev); |
672 | } | |
673 | ||
674 | int rs690_suspend(struct radeon_device *rdev) | |
675 | { | |
fe50ac78 | 676 | r600_audio_fini(rdev); |
3bc68535 JG |
677 | r100_cp_disable(rdev); |
678 | r100_wb_disable(rdev); | |
ac447df4 | 679 | rs600_irq_disable(rdev); |
3bc68535 JG |
680 | rs400_gart_disable(rdev); |
681 | return 0; | |
682 | } | |
683 | ||
684 | void rs690_fini(struct radeon_device *rdev) | |
685 | { | |
fe50ac78 | 686 | r600_audio_fini(rdev); |
3bc68535 JG |
687 | r100_cp_fini(rdev); |
688 | r100_wb_fini(rdev); | |
689 | r100_ib_fini(rdev); | |
690 | radeon_gem_fini(rdev); | |
691 | rs400_gart_fini(rdev); | |
692 | radeon_irq_kms_fini(rdev); | |
693 | radeon_fence_driver_fini(rdev); | |
4c788679 | 694 | radeon_bo_fini(rdev); |
3bc68535 JG |
695 | radeon_atombios_fini(rdev); |
696 | kfree(rdev->bios); | |
697 | rdev->bios = NULL; | |
698 | } | |
699 | ||
700 | int rs690_init(struct radeon_device *rdev) | |
701 | { | |
702 | int r; | |
703 | ||
3bc68535 JG |
704 | /* Disable VGA */ |
705 | rv515_vga_render_disable(rdev); | |
706 | /* Initialize scratch registers */ | |
707 | radeon_scratch_init(rdev); | |
708 | /* Initialize surface registers */ | |
709 | radeon_surface_init(rdev); | |
4c712e6c DA |
710 | /* restore some register to sane defaults */ |
711 | r100_restore_sanity(rdev); | |
3bc68535 JG |
712 | /* TODO: disable VGA need to use VGA request */ |
713 | /* BIOS*/ | |
714 | if (!radeon_get_bios(rdev)) { | |
715 | if (ASIC_IS_AVIVO(rdev)) | |
716 | return -EINVAL; | |
717 | } | |
718 | if (rdev->is_atom_bios) { | |
719 | r = radeon_atombios_init(rdev); | |
720 | if (r) | |
721 | return r; | |
722 | } else { | |
723 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); | |
724 | return -EINVAL; | |
725 | } | |
726 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 727 | if (radeon_asic_reset(rdev)) { |
3bc68535 JG |
728 | dev_warn(rdev->dev, |
729 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
730 | RREG32(R_000E40_RBBM_STATUS), | |
731 | RREG32(R_0007C0_CP_STAT)); | |
732 | } | |
733 | /* check if cards are posted or not */ | |
72542d77 DA |
734 | if (radeon_boot_test_post_card(rdev) == false) |
735 | return -EINVAL; | |
736 | ||
3bc68535 JG |
737 | /* Initialize clocks */ |
738 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
739 | /* initialize memory controller */ |
740 | rs690_mc_init(rdev); | |
3bc68535 JG |
741 | rv515_debugfs(rdev); |
742 | /* Fence driver */ | |
743 | r = radeon_fence_driver_init(rdev); | |
744 | if (r) | |
745 | return r; | |
746 | r = radeon_irq_kms_init(rdev); | |
747 | if (r) | |
748 | return r; | |
749 | /* Memory manager */ | |
4c788679 | 750 | r = radeon_bo_init(rdev); |
3bc68535 JG |
751 | if (r) |
752 | return r; | |
753 | r = rs400_gart_init(rdev); | |
754 | if (r) | |
755 | return r; | |
756 | rs600_set_safe_registers(rdev); | |
757 | rdev->accel_working = true; | |
758 | r = rs690_startup(rdev); | |
759 | if (r) { | |
760 | /* Somethings want wront with the accel init stop accel */ | |
761 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
3bc68535 JG |
762 | r100_cp_fini(rdev); |
763 | r100_wb_fini(rdev); | |
764 | r100_ib_fini(rdev); | |
765 | rs400_gart_fini(rdev); | |
766 | radeon_irq_kms_fini(rdev); | |
767 | rdev->accel_working = false; | |
768 | } | |
769 | return 0; | |
771fe6b9 | 770 | } |