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UBUNTU: Ubuntu-5.11.0-22.23
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / radeon / rs780_dpm.c
CommitLineData
9d67006e
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
2ef79416 25#include <linux/pci.h>
c182615f
SR		 26#include <linux/seq_file.h>
27
c182615f
SR		 28#include "atom.h"
29#include "r600_dpm.h"
9d67006e 30#include "radeon.h"
01467a9b 31#include "radeon_asic.h"
9d67006e 32#include "rs780_dpm.h"
c182615f 33#include "rs780d.h"
9d67006e
AD		 34
35static struct igp_ps *rs780_get_ps(struct radeon_ps *rps)
36{
37 struct igp_ps *ps = rps->ps_priv;
38
39 return ps;
40}
41
42static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev)
43{
44 struct igp_power_info *pi = rdev->pm.dpm.priv;
45
46 return pi;
47}
48
49static void rs780_get_pm_mode_parameters(struct radeon_device *rdev)
50{
51 struct igp_power_info *pi = rs780_get_pi(rdev);
52 struct radeon_mode_info *minfo = &rdev->mode_info;
53 struct drm_crtc *crtc;
54 struct radeon_crtc *radeon_crtc;
55 int i;
56
57 /* defaults */
58 pi->crtc_id = 0;
59 pi->refresh_rate = 60;
60
61 for (i = 0; i < rdev->num_crtc; i++) {
62 crtc = (struct drm_crtc *)minfo->crtcs[i];
63 if (crtc && crtc->enabled) {
64 radeon_crtc = to_radeon_crtc(crtc);
65 pi->crtc_id = radeon_crtc->crtc_id;
66 if (crtc->mode.htotal && crtc->mode.vtotal)
c3eaa088 67 pi->refresh_rate = drm_mode_vrefresh(&crtc->mode);
9d67006e
AD		 68 break;
69 }
70 }
71}
72
73static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
74
f5d73a80
AD		 75static int rs780_initialize_dpm_power_state(struct radeon_device *rdev,
76 struct radeon_ps *boot_ps)
9d67006e
AD		 77{
78 struct atom_clock_dividers dividers;
f5d73a80 79 struct igp_ps *default_state = rs780_get_ps(boot_ps);
9d67006e
AD		 80 int i, ret;
81
82 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
83 default_state->sclk_low, false, &dividers);
84 if (ret)
85 return ret;
86
87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
90
91 if (dividers.enable_post_div)
92 r600_engine_clock_entry_enable_post_divider(rdev, 0, true);
93 else
94 r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
95
96 r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT);
97 r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
98
99 r600_engine_clock_entry_enable(rdev, 0, true);
100 for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++)
101 r600_engine_clock_entry_enable(rdev, i, false);
102
103 r600_enable_mclk_control(rdev, false);
104 r600_voltage_control_enable_pins(rdev, 0);
105
106 return 0;
107}
108
f5d73a80
AD		 109static int rs780_initialize_dpm_parameters(struct radeon_device *rdev,
110 struct radeon_ps *boot_ps)
9d67006e
AD		 111{
112 int ret = 0;
113 int i;
114
115 r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT);
116
117 r600_set_at(rdev, 0, 0, 0, 0);
118
119 r600_set_git(rdev, R600_GICST_DFLT);
120
121 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
122 r600_set_tc(rdev, i, 0, 0);
123
124 r600_select_td(rdev, R600_TD_DFLT);
125 r600_set_vrc(rdev, 0);
126
127 r600_set_tpu(rdev, R600_TPU_DFLT);
128 r600_set_tpc(rdev, R600_TPC_DFLT);
129
130 r600_set_sstu(rdev, R600_SSTU_DFLT);
131 r600_set_sst(rdev, R600_SST_DFLT);
132
133 r600_set_fctu(rdev, R600_FCTU_DFLT);
134 r600_set_fct(rdev, R600_FCT_DFLT);
135
136 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
137 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
138 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
139 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
140 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
141
142 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
143 r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
144 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
145
f5d73a80 146 ret = rs780_initialize_dpm_power_state(rdev, boot_ps);
9d67006e
AD		 147
148 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
149 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
150 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, 0);
151
152 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
153 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
154 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
155
156 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
157 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
158 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
159
160 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, R600_DISPLAY_WATERMARK_HIGH);
161 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);
162 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, R600_DISPLAY_WATERMARK_HIGH);
163
164 r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
165 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
166 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
167 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
168
169 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
170
171 r600_set_vrc(rdev, RS780_CGFTV_DFLT);
172
173 return ret;
174}
175
176static void rs780_start_dpm(struct radeon_device *rdev)
177{
178 r600_enable_sclk_control(rdev, false);
179 r600_enable_mclk_control(rdev, false);
180
181 r600_dynamicpm_enable(rdev, true);
182
183 radeon_wait_for_vblank(rdev, 0);
184 radeon_wait_for_vblank(rdev, 1);
185
186 r600_enable_spll_bypass(rdev, true);
187 r600_wait_for_spll_change(rdev);
188 r600_enable_spll_bypass(rdev, false);
189 r600_wait_for_spll_change(rdev);
190
191 r600_enable_spll_bypass(rdev, true);
192 r600_wait_for_spll_change(rdev);
193 r600_enable_spll_bypass(rdev, false);
194 r600_wait_for_spll_change(rdev);
195
196 r600_enable_sclk_control(rdev, true);
197}
198
199
200static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev)
201{
202 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
203 ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN);
204
205 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
206 RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT),
207 ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK);
208}
209
210static void rs780_preset_starting_fbdiv(struct radeon_device *rdev)
211{
212 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
213
214 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
215 ~STARTING_FEEDBACK_DIV_MASK);
216
217 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
218 ~FORCED_FEEDBACK_DIV_MASK);
219
220 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
221}
222
223static void rs780_voltage_scaling_init(struct radeon_device *rdev)
224{
225 struct igp_power_info *pi = rs780_get_pi(rdev);
226 struct drm_device *dev = rdev->ddev;
227 u32 fv_throt_pwm_fb_div_range[3];
228 u32 fv_throt_pwm_range[4];
229
230 if (dev->pdev->device == 0x9614) {
231 fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
232 fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
233 fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
234 } else if ((dev->pdev->device == 0x9714) ||
235 (dev->pdev->device == 0x9715)) {
236 fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
237 fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
238 fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
239 } else {
240 fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT;
241 fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT;
242 fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT;
243 }
244
245 if (pi->pwm_voltage_control) {
246 fv_throt_pwm_range[0] = pi->min_voltage;
247 fv_throt_pwm_range[1] = pi->min_voltage;
248 fv_throt_pwm_range[2] = pi->max_voltage;
249 fv_throt_pwm_range[3] = pi->max_voltage;
250 } else {
251 fv_throt_pwm_range[0] = pi->invert_pwm_required ?
252 RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT;
253 fv_throt_pwm_range[1] = pi->invert_pwm_required ?
254 RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT;
255 fv_throt_pwm_range[2] = pi->invert_pwm_required ?
256 RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT;
257 fv_throt_pwm_range[3] = pi->invert_pwm_required ?
258 RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT;
259 }
260
261 WREG32_P(FVTHROT_PWM_CTRL_REG0,
262 STARTING_PWM_HIGHTIME(pi->max_voltage),
263 ~STARTING_PWM_HIGHTIME_MASK);
264
265 WREG32_P(FVTHROT_PWM_CTRL_REG0,
266 NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),
267 ~NUMBER_OF_CYCLES_IN_PERIOD_MASK);
268
269 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
270 ~FORCE_STARTING_PWM_HIGHTIME);
271
272 if (pi->invert_pwm_required)
273 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
274 else
275 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
276
277 rs780_voltage_scaling_enable(rdev, true);
278
279 WREG32(FVTHROT_PWM_CTRL_REG1,
280 (MIN_PWM_HIGHTIME(pi->min_voltage) |
281 MAX_PWM_HIGHTIME(pi->max_voltage)));
282
283 WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
284 WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
285 WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
286 WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
287
288 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
289 RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]),
290 ~RANGE0_PWM_FEEDBACK_DIV_MASK);
291
292 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
293 (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) |
294 RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2])));
295
296 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
297 (RANGE0_PWM(fv_throt_pwm_range[1]) |
298 RANGE1_PWM(fv_throt_pwm_range[2])));
299 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
300 (RANGE2_PWM(fv_throt_pwm_range[1]) |
301 RANGE3_PWM(fv_throt_pwm_range[2])));
302}
303
304static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
305{
306 if (enable)
307 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,
308 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
309 else
310 WREG32_P(FVTHROT_CNTRL_REG, 0,
311 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
312}
313
314static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
315{
316 if (enable)
317 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
318 else
319 WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
320}
321
322static void rs780_set_engine_clock_wfc(struct radeon_device *rdev)
323{
324 WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
325 WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
326 WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
327 WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
328 WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
329
330 WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
331 WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
332 WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
333 WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
334 WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
335}
336
337static void rs780_set_engine_clock_sc(struct radeon_device *rdev)
338{
339 WREG32_P(FVTHROT_FBDIV_REG2,
340 FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT),
341 ~FB_DIV_TIMER_VAL_MASK);
342
343 WREG32_P(FVTHROT_CNTRL_REG,
344 REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf),
345 ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK));
346}
347
348static void rs780_set_engine_clock_tdc(struct radeon_device *rdev)
349{
350 WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));
351}
352
353static void rs780_set_engine_clock_ssc(struct radeon_device *rdev)
354{
355 WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
356 WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
357 WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
358 WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
359
360 WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
361}
362
363static void rs780_program_at(struct radeon_device *rdev)
364{
365 struct igp_power_info *pi = rs780_get_pi(rdev);
366
367 WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
368 WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
369 WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
370 WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
371 WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
372}
373
374static void rs780_disable_vbios_powersaving(struct radeon_device *rdev)
375{
376 WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
377}
378
63580c3e 379static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage)
9d67006e 380{
9d67006e
AD		 381 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
382
383 if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
384 (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
385 return;
386
387 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
388
389 udelay(1);
390
391 WREG32_P(FVTHROT_PWM_CTRL_REG0,
63580c3e 392 STARTING_PWM_HIGHTIME(voltage),
9d67006e
AD		 393 ~STARTING_PWM_HIGHTIME_MASK);
394
395 WREG32_P(FVTHROT_PWM_CTRL_REG0,
396 FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME);
397
398 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
399 ~RANGE_PWM_FEEDBACK_DIV_EN);
400
401 udelay(1);
402
403 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
404}
405
63580c3e
AB		 406static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)
407{
408 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
409
410 if (current_state->sclk_low == current_state->sclk_high)
411 return;
412
413 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
414
415 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
416 ~FORCED_FEEDBACK_DIV_MASK);
417 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
418 ~STARTING_FEEDBACK_DIV_MASK);
419 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
420
421 udelay(100);
422
423 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
424}
425
f5d73a80
AD		 426static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
427 struct radeon_ps *new_ps,
428 struct radeon_ps *old_ps)
9d67006e
AD		 429{
430 struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers;
f5d73a80
AD		 431 struct igp_ps *new_state = rs780_get_ps(new_ps);
432 struct igp_ps *old_state = rs780_get_ps(old_ps);
9d67006e
AD		 433 int ret;
434
435 if ((new_state->sclk_high == old_state->sclk_high) &&
436 (new_state->sclk_low == old_state->sclk_low))
437 return 0;
438
439 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
440 new_state->sclk_low, false, &min_dividers);
441 if (ret)
442 return ret;
443
444 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
445 new_state->sclk_high, false, &max_dividers);
446 if (ret)
447 return ret;
448
449 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
450 old_state->sclk_high, false, &current_max_dividers);
451 if (ret)
452 return ret;
453
ce7b30e0
AD		 454 if ((min_dividers.ref_div != max_dividers.ref_div) ||
455 (min_dividers.post_div != max_dividers.post_div) ||
456 (max_dividers.ref_div != current_max_dividers.ref_div) ||
457 (max_dividers.post_div != current_max_dividers.post_div))
458 return -EINVAL;
459
63580c3e 460 rs780_force_fbdiv(rdev, max_dividers.fb_div);
9d67006e
AD		 461
462 if (max_dividers.fb_div > min_dividers.fb_div) {
463 WREG32_P(FVTHROT_FBDIV_REG0,
464 MIN_FEEDBACK_DIV(min_dividers.fb_div) |
465 MAX_FEEDBACK_DIV(max_dividers.fb_div),
466 ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK));
467
468 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
469 }
470
471 return 0;
472}
473
f5d73a80
AD		 474static void rs780_set_engine_clock_spc(struct radeon_device *rdev,
475 struct radeon_ps *new_ps,
476 struct radeon_ps *old_ps)
9d67006e 477{
f5d73a80
AD		 478 struct igp_ps *new_state = rs780_get_ps(new_ps);
479 struct igp_ps *old_state = rs780_get_ps(old_ps);
9d67006e
AD		 480 struct igp_power_info *pi = rs780_get_pi(rdev);
481
482 if ((new_state->sclk_high == old_state->sclk_high) &&
483 (new_state->sclk_low == old_state->sclk_low))
484 return;
485
486 if (pi->crtc_id == 0)
487 WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
488 else
489 WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
490
491}
492
f5d73a80
AD		 493static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev,
494 struct radeon_ps *new_ps,
495 struct radeon_ps *old_ps)
9d67006e 496{
f5d73a80
AD		 497 struct igp_ps *new_state = rs780_get_ps(new_ps);
498 struct igp_ps *old_state = rs780_get_ps(old_ps);
9d67006e
AD		 499
500 if ((new_state->sclk_high == old_state->sclk_high) &&
501 (new_state->sclk_low == old_state->sclk_low))
502 return;
503
e40210cc
AD		 504 if (new_state->sclk_high == new_state->sclk_low)
505 return;
506
9d67006e
AD		 507 rs780_clk_scaling_enable(rdev, true);
508}
509
510static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,
511 enum rs780_vddc_level vddc)
512{
513 struct igp_power_info *pi = rs780_get_pi(rdev);
514
515 if (vddc == RS780_VDDC_LEVEL_HIGH)
516 return pi->max_voltage;
517 else if (vddc == RS780_VDDC_LEVEL_LOW)
518 return pi->min_voltage;
519 else
520 return pi->max_voltage;
521}
522
f5d73a80
AD		 523static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
524 struct radeon_ps *new_ps)
9d67006e 525{
f5d73a80 526 struct igp_ps *new_state = rs780_get_ps(new_ps);
9d67006e
AD		 527 struct igp_power_info *pi = rs780_get_pi(rdev);
528 enum rs780_vddc_level vddc_high, vddc_low;
529
530 udelay(100);
531
532 if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
533 (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
534 return;
535
536 vddc_high = rs780_get_voltage_for_vddc_level(rdev,
537 new_state->max_voltage);
538 vddc_low = rs780_get_voltage_for_vddc_level(rdev,
539 new_state->min_voltage);
540
541 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
542
543 udelay(1);
544 if (vddc_high > vddc_low) {
545 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
546 RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN);
547
548 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
549 } else if (vddc_high == vddc_low) {
550 if (pi->max_voltage != vddc_high) {
551 WREG32_P(FVTHROT_PWM_CTRL_REG0,
552 STARTING_PWM_HIGHTIME(vddc_high),
553 ~STARTING_PWM_HIGHTIME_MASK);
554
555 WREG32_P(FVTHROT_PWM_CTRL_REG0,
556 FORCE_STARTING_PWM_HIGHTIME,
557 ~FORCE_STARTING_PWM_HIGHTIME);
558 }
559 }
560
561 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
562}
563
915203c1
AD		 564static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
565 struct radeon_ps *new_ps,
566 struct radeon_ps *old_ps)
567{
568 struct igp_ps *new_state = rs780_get_ps(new_ps);
569 struct igp_ps *current_state = rs780_get_ps(old_ps);
570
571 if ((new_ps->vclk == old_ps->vclk) &&
572 (new_ps->dclk == old_ps->dclk))
573 return;
574
575 if (new_state->sclk_high >= current_state->sclk_high)
576 return;
577
578 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
579}
580
581static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
582 struct radeon_ps *new_ps,
583 struct radeon_ps *old_ps)
584{
585 struct igp_ps *new_state = rs780_get_ps(new_ps);
586 struct igp_ps *current_state = rs780_get_ps(old_ps);
587
588 if ((new_ps->vclk == old_ps->vclk) &&
589 (new_ps->dclk == old_ps->dclk))
590 return;
591
592 if (new_state->sclk_high < current_state->sclk_high)
593 return;
594
595 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
596}
597
9d67006e
AD		 598int rs780_dpm_enable(struct radeon_device *rdev)
599{
600 struct igp_power_info *pi = rs780_get_pi(rdev);
f5d73a80 601 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
a172230f 602 int ret;
9d67006e
AD		 603
604 rs780_get_pm_mode_parameters(rdev);
605 rs780_disable_vbios_powersaving(rdev);
606
607 if (r600_dynamicpm_enabled(rdev))
608 return -EINVAL;
a172230f
AD		 609 ret = rs780_initialize_dpm_parameters(rdev, boot_ps);
610 if (ret)
611 return ret;
9d67006e
AD		 612 rs780_start_dpm(rdev);
613
614 rs780_preset_ranges_slow_clk_fbdiv_en(rdev);
615 rs780_preset_starting_fbdiv(rdev);
616 if (pi->voltage_control)
617 rs780_voltage_scaling_init(rdev);
618 rs780_clk_scaling_enable(rdev, true);
619 rs780_set_engine_clock_sc(rdev);
620 rs780_set_engine_clock_wfc(rdev);
621 rs780_program_at(rdev);
622 rs780_set_engine_clock_tdc(rdev);
623 rs780_set_engine_clock_ssc(rdev);
624
625 if (pi->gfx_clock_gating)
626 r600_gfx_clockgating_enable(rdev, true);
627
628 return 0;
629}
630
631void rs780_dpm_disable(struct radeon_device *rdev)
632{
633 struct igp_power_info *pi = rs780_get_pi(rdev);
634
635 r600_dynamicpm_enable(rdev, false);
636
637 rs780_clk_scaling_enable(rdev, false);
638 rs780_voltage_scaling_enable(rdev, false);
639
640 if (pi->gfx_clock_gating)
641 r600_gfx_clockgating_enable(rdev, false);
4a6369e9
AD		 642
643 if (rdev->irq.installed &&
644 (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
645 rdev->irq.dpm_thermal = false;
646 radeon_irq_set(rdev);
647 }
9d67006e
AD		 648}
649
650int rs780_dpm_set_power_state(struct radeon_device *rdev)
651{
652 struct igp_power_info *pi = rs780_get_pi(rdev);
f5d73a80
AD		 653 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
654 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
a172230f 655 int ret;
9d67006e
AD		 656
657 rs780_get_pm_mode_parameters(rdev);
658
915203c1
AD		 659 rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
660
9d67006e 661 if (pi->voltage_control) {
63580c3e 662 rs780_force_voltage(rdev, pi->max_voltage);
9d67006e
AD		 663 mdelay(5);
664 }
665
a172230f
AD		 666 ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps);
667 if (ret)
668 return ret;
f5d73a80 669 rs780_set_engine_clock_spc(rdev, new_ps, old_ps);
9d67006e 670
f5d73a80 671 rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps);
9d67006e
AD		 672
673 if (pi->voltage_control)
f5d73a80 674 rs780_enable_voltage_scaling(rdev, new_ps);
9d67006e 675
915203c1
AD		 676 rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
677
9d67006e
AD		 678 return 0;
679}
680
681void rs780_dpm_setup_asic(struct radeon_device *rdev)
682{
683
684}
685
686void rs780_dpm_display_configuration_changed(struct radeon_device *rdev)
687{
688 rs780_get_pm_mode_parameters(rdev);
689 rs780_program_at(rdev);
690}
691
692union igp_info {
693 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
694 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
695};
696
697union power_info {
698 struct _ATOM_POWERPLAY_INFO info;
699 struct _ATOM_POWERPLAY_INFO_V2 info_2;
700 struct _ATOM_POWERPLAY_INFO_V3 info_3;
701 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
702 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
703 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
704};
705
706union pplib_clock_info {
707 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
708 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
709 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
710 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
711};
712
713union pplib_power_state {
714 struct _ATOM_PPLIB_STATE v1;
715 struct _ATOM_PPLIB_STATE_V2 v2;
716};
717
718static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
719 struct radeon_ps *rps,
720 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
721 u8 table_rev)
722{
723 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
724 rps->class = le16_to_cpu(non_clock_info->usClassification);
725 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
726
727 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
728 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
729 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
9d67006e
AD		 730 } else {
731 rps->vclk = 0;
732 rps->dclk = 0;
733 }
734
84f3d9f7
AD		 735 if (r600_is_uvd_state(rps->class, rps->class2)) {
736 if ((rps->vclk == 0) || (rps->dclk == 0)) {
737 rps->vclk = RS780_DEFAULT_VCLK_FREQ;
738 rps->dclk = RS780_DEFAULT_DCLK_FREQ;
739 }
740 }
741
9d67006e
AD		 742 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
743 rdev->pm.dpm.boot_ps = rps;
744 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
745 rdev->pm.dpm.uvd_ps = rps;
746}
747
748static void rs780_parse_pplib_clock_info(struct radeon_device *rdev,
749 struct radeon_ps *rps,
750 union pplib_clock_info *clock_info)
751{
752 struct igp_ps *ps = rs780_get_ps(rps);
753 u32 sclk;
754
755 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
756 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
757 ps->sclk_low = sclk;
758 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
759 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16;
760 ps->sclk_high = sclk;
761 switch (le16_to_cpu(clock_info->rs780.usVDDC)) {
762 case ATOM_PPLIB_RS780_VOLTAGE_NONE:
763 default:
764 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN;
765 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN;
766 break;
767 case ATOM_PPLIB_RS780_VOLTAGE_LOW:
768 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
769 ps->max_voltage = RS780_VDDC_LEVEL_LOW;
770 break;
771 case ATOM_PPLIB_RS780_VOLTAGE_HIGH:
772 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
773 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
774 break;
775 case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE:
776 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
777 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
778 break;
779 }
780 ps->flags = le32_to_cpu(clock_info->rs780.ulFlags);
781
782 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
783 ps->sclk_low = rdev->clock.default_sclk;
784 ps->sclk_high = rdev->clock.default_sclk;
785 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
786 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
787 }
788}
789
790static int rs780_parse_power_table(struct radeon_device *rdev)
791{
792 struct radeon_mode_info *mode_info = &rdev->mode_info;
793 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
794 union pplib_power_state *power_state;
795 int i;
796 union pplib_clock_info *clock_info;
797 union power_info *power_info;
798 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
3cf8bb1a 799 u16 data_offset;
9d67006e
AD		 800 u8 frev, crev;
801 struct igp_ps *ps;
802
803 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
804 &frev, &crev, &data_offset))
805 return -EINVAL;
806 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
807
6396bb22
KC		 808 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
809 sizeof(struct radeon_ps),
810 GFP_KERNEL);
9d67006e
AD		 811 if (!rdev->pm.dpm.ps)
812 return -ENOMEM;
9d67006e
AD		 813
814 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
815 power_state = (union pplib_power_state *)
816 (mode_info->atom_context->bios + data_offset +
817 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
818 i * power_info->pplib.ucStateEntrySize);
819 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
820 (mode_info->atom_context->bios + data_offset +
821 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
822 (power_state->v1.ucNonClockStateIndex *
823 power_info->pplib.ucNonClockSize));
824 if (power_info->pplib.ucStateEntrySize - 1) {
825 clock_info = (union pplib_clock_info *)
826 (mode_info->atom_context->bios + data_offset +
827 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
828 (power_state->v1.ucClockStateIndices[0] *
829 power_info->pplib.ucClockInfoSize));
830 ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL);
831 if (ps == NULL) {
832 kfree(rdev->pm.dpm.ps);
833 return -ENOMEM;
834 }
835 rdev->pm.dpm.ps[i].ps_priv = ps;
836 rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
837 non_clock_info,
838 power_info->pplib.ucNonClockSize);
839 rs780_parse_pplib_clock_info(rdev,
840 &rdev->pm.dpm.ps[i],
841 clock_info);
842 }
843 }
844 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
845 return 0;
846}
847
848int rs780_dpm_init(struct radeon_device *rdev)
849{
850 struct igp_power_info *pi;
851 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
852 union igp_info *info;
853 u16 data_offset;
854 u8 frev, crev;
855 int ret;
856
857 pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);
858 if (pi == NULL)
859 return -ENOMEM;
860 rdev->pm.dpm.priv = pi;
861
82f79cc5
AD		 862 ret = r600_get_platform_caps(rdev);
863 if (ret)
864 return ret;
865
9d67006e
AD		 866 ret = rs780_parse_power_table(rdev);
867 if (ret)
868 return ret;
869
870 pi->voltage_control = false;
871 pi->gfx_clock_gating = true;
872
873 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
874 &frev, &crev, &data_offset)) {
875 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
876
877 /* Get various system informations from bios */
878 switch (crev) {
879 case 1:
880 pi->num_of_cycles_in_period =
881 info->info.ucNumberOfCyclesInPeriod;
882 pi->num_of_cycles_in_period |=
883 info->info.ucNumberOfCyclesInPeriodHi << 8;
884 pi->invert_pwm_required =
885 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
886 pi->boot_voltage = info->info.ucStartingPWM_HighTime;
887 pi->max_voltage = info->info.ucMaxNBVoltage;
888 pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8;
889 pi->min_voltage = info->info.ucMinNBVoltage;
890 pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8;
891 pi->inter_voltage_low =
892 le16_to_cpu(info->info.usInterNBVoltageLow);
893 pi->inter_voltage_high =
894 le16_to_cpu(info->info.usInterNBVoltageHigh);
895 pi->voltage_control = true;
896 pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;
897 break;
898 case 2:
899 pi->num_of_cycles_in_period =
900 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod);
901 pi->invert_pwm_required =
902 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
903 pi->boot_voltage =
904 le16_to_cpu(info->info_2.usBootUpNBVoltage);
905 pi->max_voltage =
906 le16_to_cpu(info->info_2.usMaxNBVoltage);
907 pi->min_voltage =
908 le16_to_cpu(info->info_2.usMinNBVoltage);
909 pi->system_config =
910 le32_to_cpu(info->info_2.ulSystemConfig);
911 pi->pwm_voltage_control =
912 (pi->system_config & 0x4) ? true : false;
913 pi->voltage_control = true;
914 pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);
915 break;
916 default:
917 DRM_ERROR("No integrated system info for your GPU\n");
918 return -EINVAL;
919 }
920 if (pi->min_voltage > pi->max_voltage)
921 pi->voltage_control = false;
922 if (pi->pwm_voltage_control) {
923 if ((pi->num_of_cycles_in_period == 0) ||
924 (pi->max_voltage == 0) ||
925 (pi->min_voltage == 0))
926 pi->voltage_control = false;
927 } else {
928 if ((pi->num_of_cycles_in_period == 0) ||
929 (pi->max_voltage == 0))
930 pi->voltage_control = false;
931 }
932
933 return 0;
934 }
935 radeon_dpm_fini(rdev);
936 return -EINVAL;
937}
938
939void rs780_dpm_print_power_state(struct radeon_device *rdev,
940 struct radeon_ps *rps)
941{
942 struct igp_ps *ps = rs780_get_ps(rps);
943
944 r600_dpm_print_class_info(rps->class, rps->class2);
945 r600_dpm_print_cap_info(rps->caps);
946 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
947 printk("\t\tpower level 0 sclk: %u vddc_index: %d\n",
948 ps->sclk_low, ps->min_voltage);
949 printk("\t\tpower level 1 sclk: %u vddc_index: %d\n",
950 ps->sclk_high, ps->max_voltage);
951 r600_dpm_print_ps_status(rdev, rps);
952}
953
954void rs780_dpm_fini(struct radeon_device *rdev)
955{
956 int i;
957
958 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
959 kfree(rdev->pm.dpm.ps[i].ps_priv);
960 }
961 kfree(rdev->pm.dpm.ps);
962 kfree(rdev->pm.dpm.priv);
963}
964
965u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
966{
967 struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
968
969 if (low)
970 return requested_state->sclk_low;
971 else
972 return requested_state->sclk_high;
973}
974
975u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
976{
977 struct igp_power_info *pi = rs780_get_pi(rdev);
978
979 return pi->bootup_uma_clk;
980}
444bddc4
AD		 981
982void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
983 struct seq_file *m)
984{
985 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
986 struct igp_ps *ps = rs780_get_ps(rps);
987 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
988 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
989 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
990 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
991 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
992 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
993 (post_div * ref_div);
994
995 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
996
997 /* guess based on the current sclk */
998 if (sclk < (ps->sclk_low + 500))
999 seq_printf(m, "power level 0 sclk: %u vddc_index: %d\n",
1000 ps->sclk_low, ps->min_voltage);
1001 else
1002 seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n",
1003 ps->sclk_high, ps->max_voltage);
1004}
63580c3e 1005
3c94566c
AD		 1006/* get the current sclk in 10 khz units */
1007u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev)
1008{
1009 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
1010 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
1011 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
1012 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
1013 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
1014 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
1015 (post_div * ref_div);
1016
1017 return sclk;
1018}
1019
1020/* get the current mclk in 10 khz units */
1021u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev)
1022{
1023 struct igp_power_info *pi = rs780_get_pi(rdev);
1024
1025 return pi->bootup_uma_clk;
1026}
1027
63580c3e
AB		 1028int rs780_dpm_force_performance_level(struct radeon_device *rdev,
1029 enum radeon_dpm_forced_level level)
1030{
1031 struct igp_power_info *pi = rs780_get_pi(rdev);
1032 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1033 struct igp_ps *ps = rs780_get_ps(rps);
1034 struct atom_clock_dividers dividers;
1035 int ret;
1036
1037 rs780_clk_scaling_enable(rdev, false);
1038 rs780_voltage_scaling_enable(rdev, false);
1039
1040 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1041 if (pi->voltage_control)
1042 rs780_force_voltage(rdev, pi->max_voltage);
1043
1044 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1045 ps->sclk_high, false, &dividers);
1046 if (ret)
1047 return ret;
1048
1049 rs780_force_fbdiv(rdev, dividers.fb_div);
1050 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1051 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1052 ps->sclk_low, false, &dividers);
1053 if (ret)
1054 return ret;
1055
1056 rs780_force_fbdiv(rdev, dividers.fb_div);
1057
1058 if (pi->voltage_control)
1059 rs780_force_voltage(rdev, pi->min_voltage);
1060 } else {
1061 if (pi->voltage_control)
1062 rs780_force_voltage(rdev, pi->max_voltage);
1063
c2ee29d0
AD		 1064 if (ps->sclk_high != ps->sclk_low) {
1065 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
1066 rs780_clk_scaling_enable(rdev, true);
1067 }
63580c3e
AB		 1068
1069 if (pi->voltage_control) {
1070 rs780_voltage_scaling_enable(rdev, true);
1071 rs780_enable_voltage_scaling(rdev, rps);
1072 }
1073 }
1074
1075 rdev->pm.dpm.forced_level = level;
1076
1077 return 0;
1078}
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