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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
771fe6b9 | 30 | #include "drmP.h" |
3ce0a23d | 31 | #include "rv515d.h" |
771fe6b9 | 32 | #include "radeon.h" |
e6990375 | 33 | #include "radeon_asic.h" |
d39c3b89 | 34 | #include "atom.h" |
50f15303 | 35 | #include "rv515_reg_safe.h" |
d39c3b89 JG |
36 | |
37 | /* This files gather functions specifics to: rv515 */ | |
771fe6b9 JG |
38 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
39 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); | |
40 | void rv515_gpu_init(struct radeon_device *rdev); | |
41 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); | |
42 | ||
f0ed1f65 | 43 | void rv515_debugfs(struct radeon_device *rdev) |
771fe6b9 | 44 | { |
771fe6b9 JG |
45 | if (r100_debugfs_rbbm_init(rdev)) { |
46 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
47 | } | |
48 | if (rv515_debugfs_pipes_info_init(rdev)) { | |
49 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | |
50 | } | |
51 | if (rv515_debugfs_ga_info_init(rdev)) { | |
52 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | |
53 | } | |
771fe6b9 JG |
54 | } |
55 | ||
771fe6b9 JG |
56 | void rv515_ring_start(struct radeon_device *rdev) |
57 | { | |
771fe6b9 JG |
58 | int r; |
59 | ||
771fe6b9 JG |
60 | r = radeon_ring_lock(rdev, 64); |
61 | if (r) { | |
62 | return; | |
63 | } | |
c93bb85b | 64 | radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); |
771fe6b9 | 65 | radeon_ring_write(rdev, |
c93bb85b JG |
66 | ISYNC_ANY2D_IDLE3D | |
67 | ISYNC_ANY3D_IDLE2D | | |
68 | ISYNC_WAIT_IDLEGUI | | |
69 | ISYNC_CPSCRATCH_IDLEGUI); | |
70 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); | |
71 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); | |
771fe6b9 JG |
72 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
73 | radeon_ring_write(rdev, 1 << 31); | |
c93bb85b | 74 | radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); |
771fe6b9 | 75 | radeon_ring_write(rdev, 0); |
c93bb85b | 76 | radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); |
771fe6b9 JG |
77 | radeon_ring_write(rdev, 0); |
78 | radeon_ring_write(rdev, PACKET0(0x42C8, 0)); | |
79 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); | |
c93bb85b | 80 | radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); |
771fe6b9 | 81 | radeon_ring_write(rdev, 0); |
c93bb85b JG |
82 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
83 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); | |
84 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); | |
85 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); | |
86 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); | |
87 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); | |
88 | radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); | |
771fe6b9 | 89 | radeon_ring_write(rdev, 0); |
c93bb85b JG |
90 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
91 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); | |
92 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); | |
93 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); | |
94 | radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); | |
771fe6b9 | 95 | radeon_ring_write(rdev, |
c93bb85b JG |
96 | ((6 << MS_X0_SHIFT) | |
97 | (6 << MS_Y0_SHIFT) | | |
98 | (6 << MS_X1_SHIFT) | | |
99 | (6 << MS_Y1_SHIFT) | | |
100 | (6 << MS_X2_SHIFT) | | |
101 | (6 << MS_Y2_SHIFT) | | |
102 | (6 << MSBD0_Y_SHIFT) | | |
103 | (6 << MSBD0_X_SHIFT))); | |
104 | radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); | |
771fe6b9 | 105 | radeon_ring_write(rdev, |
c93bb85b JG |
106 | ((6 << MS_X3_SHIFT) | |
107 | (6 << MS_Y3_SHIFT) | | |
108 | (6 << MS_X4_SHIFT) | | |
109 | (6 << MS_Y4_SHIFT) | | |
110 | (6 << MS_X5_SHIFT) | | |
111 | (6 << MS_Y5_SHIFT) | | |
112 | (6 << MSBD1_SHIFT))); | |
113 | radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); | |
114 | radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); | |
115 | radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); | |
116 | radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); | |
117 | radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); | |
118 | radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); | |
068a117c JG |
119 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
120 | radeon_ring_write(rdev, 0); | |
771fe6b9 JG |
121 | radeon_ring_unlock_commit(rdev); |
122 | } | |
123 | ||
771fe6b9 JG |
124 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
125 | { | |
126 | unsigned i; | |
127 | uint32_t tmp; | |
128 | ||
129 | for (i = 0; i < rdev->usec_timeout; i++) { | |
130 | /* read MC_STATUS */ | |
c93bb85b JG |
131 | tmp = RREG32_MC(MC_STATUS); |
132 | if (tmp & MC_STATUS_IDLE) { | |
771fe6b9 JG |
133 | return 0; |
134 | } | |
135 | DRM_UDELAY(1); | |
136 | } | |
137 | return -1; | |
138 | } | |
139 | ||
d39c3b89 JG |
140 | void rv515_vga_render_disable(struct radeon_device *rdev) |
141 | { | |
142 | WREG32(R_000300_VGA_RENDER_CONTROL, | |
143 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); | |
144 | } | |
145 | ||
771fe6b9 JG |
146 | void rv515_gpu_init(struct radeon_device *rdev) |
147 | { | |
148 | unsigned pipe_select_current, gb_pipe_select, tmp; | |
149 | ||
771fe6b9 JG |
150 | if (r100_gui_wait_for_idle(rdev)) { |
151 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
152 | "reseting GPU. Bad things might happen.\n"); | |
153 | } | |
d39c3b89 | 154 | rv515_vga_render_disable(rdev); |
771fe6b9 JG |
155 | r420_pipes_init(rdev); |
156 | gb_pipe_select = RREG32(0x402C); | |
157 | tmp = RREG32(0x170C); | |
158 | pipe_select_current = (tmp >> 2) & 3; | |
159 | tmp = (1 << pipe_select_current) | | |
160 | (((gb_pipe_select >> 8) & 0xF) << 4); | |
161 | WREG32_PLL(0x000D, tmp); | |
162 | if (r100_gui_wait_for_idle(rdev)) { | |
163 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
164 | "reseting GPU. Bad things might happen.\n"); | |
165 | } | |
166 | if (rv515_mc_wait_for_idle(rdev)) { | |
167 | printk(KERN_WARNING "Failed to wait MC idle while " | |
168 | "programming pipes. Bad things might happen.\n"); | |
169 | } | |
170 | } | |
171 | ||
771fe6b9 JG |
172 | static void rv515_vram_get_type(struct radeon_device *rdev) |
173 | { | |
174 | uint32_t tmp; | |
175 | ||
176 | rdev->mc.vram_width = 128; | |
177 | rdev->mc.vram_is_ddr = true; | |
c93bb85b | 178 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
771fe6b9 JG |
179 | switch (tmp) { |
180 | case 0: | |
181 | rdev->mc.vram_width = 64; | |
182 | break; | |
183 | case 1: | |
184 | rdev->mc.vram_width = 128; | |
185 | break; | |
186 | default: | |
187 | rdev->mc.vram_width = 128; | |
188 | break; | |
189 | } | |
190 | } | |
191 | ||
d594e46a | 192 | void rv515_mc_init(struct radeon_device *rdev) |
771fe6b9 | 193 | { |
c93bb85b | 194 | |
771fe6b9 | 195 | rv515_vram_get_type(rdev); |
0924d942 | 196 | r100_vram_init_sizes(rdev); |
d594e46a JG |
197 | radeon_vram_location(rdev, &rdev->mc, 0); |
198 | if (!(rdev->flags & RADEON_IS_AGP)) | |
199 | radeon_gtt_location(rdev, &rdev->mc); | |
f47299c5 | 200 | radeon_update_bandwidth_info(rdev); |
771fe6b9 JG |
201 | } |
202 | ||
771fe6b9 JG |
203 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
204 | { | |
205 | uint32_t r; | |
206 | ||
c93bb85b JG |
207 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
208 | r = RREG32(MC_IND_DATA); | |
209 | WREG32(MC_IND_INDEX, 0); | |
771fe6b9 JG |
210 | return r; |
211 | } | |
212 | ||
213 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
214 | { | |
c93bb85b JG |
215 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
216 | WREG32(MC_IND_DATA, (v)); | |
217 | WREG32(MC_IND_INDEX, 0); | |
771fe6b9 JG |
218 | } |
219 | ||
771fe6b9 JG |
220 | #if defined(CONFIG_DEBUG_FS) |
221 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) | |
222 | { | |
223 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
224 | struct drm_device *dev = node->minor->dev; | |
225 | struct radeon_device *rdev = dev->dev_private; | |
226 | uint32_t tmp; | |
227 | ||
c93bb85b | 228 | tmp = RREG32(GB_PIPE_SELECT); |
771fe6b9 | 229 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
c93bb85b | 230 | tmp = RREG32(SU_REG_DEST); |
771fe6b9 | 231 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
c93bb85b | 232 | tmp = RREG32(GB_TILE_CONFIG); |
771fe6b9 | 233 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
c93bb85b | 234 | tmp = RREG32(DST_PIPE_CONFIG); |
771fe6b9 JG |
235 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
236 | return 0; | |
237 | } | |
238 | ||
239 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) | |
240 | { | |
241 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
242 | struct drm_device *dev = node->minor->dev; | |
243 | struct radeon_device *rdev = dev->dev_private; | |
244 | uint32_t tmp; | |
245 | ||
246 | tmp = RREG32(0x2140); | |
247 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); | |
a2d07b74 | 248 | radeon_asic_reset(rdev); |
771fe6b9 JG |
249 | tmp = RREG32(0x425C); |
250 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); | |
251 | return 0; | |
252 | } | |
253 | ||
254 | static struct drm_info_list rv515_pipes_info_list[] = { | |
255 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, | |
256 | }; | |
257 | ||
258 | static struct drm_info_list rv515_ga_info_list[] = { | |
259 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, | |
260 | }; | |
261 | #endif | |
262 | ||
263 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) | |
264 | { | |
265 | #if defined(CONFIG_DEBUG_FS) | |
266 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); | |
267 | #else | |
268 | return 0; | |
269 | #endif | |
270 | } | |
271 | ||
272 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev) | |
273 | { | |
274 | #if defined(CONFIG_DEBUG_FS) | |
275 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); | |
276 | #else | |
277 | return 0; | |
278 | #endif | |
279 | } | |
068a117c | 280 | |
d39c3b89 JG |
281 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
282 | { | |
283 | save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); | |
284 | save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); | |
285 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); | |
286 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); | |
287 | save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); | |
288 | save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); | |
289 | ||
290 | /* Stop all video */ | |
d39c3b89 JG |
291 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
292 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); | |
293 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); | |
294 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); | |
295 | WREG32(R_006080_D1CRTC_CONTROL, 0); | |
296 | WREG32(R_006880_D2CRTC_CONTROL, 0); | |
297 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); | |
298 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); | |
ef630627 DA |
299 | WREG32(R_000330_D1VGA_CONTROL, 0); |
300 | WREG32(R_000338_D2VGA_CONTROL, 0); | |
d39c3b89 JG |
301 | } |
302 | ||
303 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) | |
304 | { | |
305 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); | |
306 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); | |
307 | WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); | |
308 | WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); | |
309 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); | |
310 | /* Unlock host access */ | |
311 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); | |
312 | mdelay(1); | |
313 | /* Restore video state */ | |
ef630627 DA |
314 | WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); |
315 | WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); | |
d39c3b89 JG |
316 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
317 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); | |
318 | WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); | |
319 | WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); | |
320 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); | |
321 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); | |
d39c3b89 JG |
322 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
323 | } | |
324 | ||
325 | void rv515_mc_program(struct radeon_device *rdev) | |
326 | { | |
327 | struct rv515_mc_save save; | |
328 | ||
329 | /* Stops all mc clients */ | |
330 | rv515_mc_stop(rdev, &save); | |
331 | ||
332 | /* Wait for mc idle */ | |
333 | if (rv515_mc_wait_for_idle(rdev)) | |
334 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
335 | /* Write VRAM size in case we are limiting it */ | |
336 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
337 | /* Program MC, should be a 32bits limited address space */ | |
338 | WREG32_MC(R_000001_MC_FB_LOCATION, | |
339 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | | |
340 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
341 | WREG32(R_000134_HDP_FB_LOCATION, | |
342 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
343 | if (rdev->flags & RADEON_IS_AGP) { | |
344 | WREG32_MC(R_000002_MC_AGP_LOCATION, | |
345 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
346 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
347 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
348 | WREG32_MC(R_000004_MC_AGP_BASE_2, | |
349 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); | |
350 | } else { | |
351 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); | |
352 | WREG32_MC(R_000003_MC_AGP_BASE, 0); | |
353 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); | |
354 | } | |
355 | ||
356 | rv515_mc_resume(rdev, &save); | |
357 | } | |
358 | ||
359 | void rv515_clock_startup(struct radeon_device *rdev) | |
360 | { | |
361 | if (radeon_dynclks != -1 && radeon_dynclks) | |
362 | radeon_atom_set_clock_gating(rdev, 1); | |
363 | /* We need to force on some of the block */ | |
364 | WREG32_PLL(R_00000F_CP_DYN_CNTL, | |
365 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); | |
366 | WREG32_PLL(R_000011_E2_DYN_CNTL, | |
367 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); | |
368 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, | |
369 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); | |
370 | } | |
371 | ||
372 | static int rv515_startup(struct radeon_device *rdev) | |
373 | { | |
374 | int r; | |
375 | ||
376 | rv515_mc_program(rdev); | |
377 | /* Resume clock */ | |
378 | rv515_clock_startup(rdev); | |
379 | /* Initialize GPU configuration (# pipes, ...) */ | |
380 | rv515_gpu_init(rdev); | |
381 | /* Initialize GART (initialize after TTM so we can allocate | |
382 | * memory through TTM but finalize after TTM) */ | |
383 | if (rdev->flags & RADEON_IS_PCIE) { | |
384 | r = rv370_pcie_gart_enable(rdev); | |
385 | if (r) | |
386 | return r; | |
387 | } | |
388 | /* Enable IRQ */ | |
ac447df4 | 389 | rs600_irq_set(rdev); |
cafe6609 | 390 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
d39c3b89 JG |
391 | /* 1M ring buffer */ |
392 | r = r100_cp_init(rdev, 1024 * 1024); | |
393 | if (r) { | |
394 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
395 | return r; | |
396 | } | |
397 | r = r100_wb_init(rdev); | |
398 | if (r) | |
399 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
400 | r = r100_ib_init(rdev); | |
401 | if (r) { | |
402 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
403 | return r; | |
404 | } | |
405 | return 0; | |
406 | } | |
407 | ||
408 | int rv515_resume(struct radeon_device *rdev) | |
409 | { | |
410 | /* Make sur GART are not working */ | |
411 | if (rdev->flags & RADEON_IS_PCIE) | |
412 | rv370_pcie_gart_disable(rdev); | |
413 | /* Resume clock before doing reset */ | |
414 | rv515_clock_startup(rdev); | |
415 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 416 | if (radeon_asic_reset(rdev)) { |
d39c3b89 JG |
417 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
418 | RREG32(R_000E40_RBBM_STATUS), | |
419 | RREG32(R_0007C0_CP_STAT)); | |
420 | } | |
421 | /* post */ | |
422 | atom_asic_init(rdev->mode_info.atom_context); | |
423 | /* Resume clock after posting */ | |
424 | rv515_clock_startup(rdev); | |
550e2d92 DA |
425 | /* Initialize surface registers */ |
426 | radeon_surface_init(rdev); | |
d39c3b89 JG |
427 | return rv515_startup(rdev); |
428 | } | |
429 | ||
430 | int rv515_suspend(struct radeon_device *rdev) | |
431 | { | |
432 | r100_cp_disable(rdev); | |
433 | r100_wb_disable(rdev); | |
ac447df4 | 434 | rs600_irq_disable(rdev); |
d39c3b89 JG |
435 | if (rdev->flags & RADEON_IS_PCIE) |
436 | rv370_pcie_gart_disable(rdev); | |
437 | return 0; | |
438 | } | |
439 | ||
440 | void rv515_set_safe_registers(struct radeon_device *rdev) | |
068a117c | 441 | { |
50f15303 DA |
442 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
443 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); | |
d39c3b89 JG |
444 | } |
445 | ||
446 | void rv515_fini(struct radeon_device *rdev) | |
447 | { | |
29fb52ca | 448 | radeon_pm_fini(rdev); |
d39c3b89 JG |
449 | r100_cp_fini(rdev); |
450 | r100_wb_fini(rdev); | |
451 | r100_ib_fini(rdev); | |
452 | radeon_gem_fini(rdev); | |
4c788679 | 453 | rv370_pcie_gart_fini(rdev); |
d39c3b89 JG |
454 | radeon_agp_fini(rdev); |
455 | radeon_irq_kms_fini(rdev); | |
456 | radeon_fence_driver_fini(rdev); | |
4c788679 | 457 | radeon_bo_fini(rdev); |
d39c3b89 JG |
458 | radeon_atombios_fini(rdev); |
459 | kfree(rdev->bios); | |
460 | rdev->bios = NULL; | |
461 | } | |
462 | ||
463 | int rv515_init(struct radeon_device *rdev) | |
464 | { | |
465 | int r; | |
466 | ||
d39c3b89 JG |
467 | /* Initialize scratch registers */ |
468 | radeon_scratch_init(rdev); | |
469 | /* Initialize surface registers */ | |
470 | radeon_surface_init(rdev); | |
471 | /* TODO: disable VGA need to use VGA request */ | |
472 | /* BIOS*/ | |
473 | if (!radeon_get_bios(rdev)) { | |
474 | if (ASIC_IS_AVIVO(rdev)) | |
475 | return -EINVAL; | |
476 | } | |
477 | if (rdev->is_atom_bios) { | |
478 | r = radeon_atombios_init(rdev); | |
479 | if (r) | |
480 | return r; | |
481 | } else { | |
482 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); | |
483 | return -EINVAL; | |
484 | } | |
485 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 486 | if (radeon_asic_reset(rdev)) { |
d39c3b89 JG |
487 | dev_warn(rdev->dev, |
488 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
489 | RREG32(R_000E40_RBBM_STATUS), | |
490 | RREG32(R_0007C0_CP_STAT)); | |
491 | } | |
492 | /* check if cards are posted or not */ | |
72542d77 DA |
493 | if (radeon_boot_test_post_card(rdev) == false) |
494 | return -EINVAL; | |
d39c3b89 JG |
495 | /* Initialize clocks */ |
496 | radeon_get_clock_info(rdev->ddev); | |
7433874e RM |
497 | /* Initialize power management */ |
498 | radeon_pm_init(rdev); | |
d594e46a JG |
499 | /* initialize AGP */ |
500 | if (rdev->flags & RADEON_IS_AGP) { | |
501 | r = radeon_agp_init(rdev); | |
502 | if (r) { | |
503 | radeon_agp_disable(rdev); | |
504 | } | |
505 | } | |
506 | /* initialize memory controller */ | |
507 | rv515_mc_init(rdev); | |
d39c3b89 JG |
508 | rv515_debugfs(rdev); |
509 | /* Fence driver */ | |
510 | r = radeon_fence_driver_init(rdev); | |
511 | if (r) | |
512 | return r; | |
513 | r = radeon_irq_kms_init(rdev); | |
514 | if (r) | |
515 | return r; | |
516 | /* Memory manager */ | |
4c788679 | 517 | r = radeon_bo_init(rdev); |
d39c3b89 JG |
518 | if (r) |
519 | return r; | |
520 | r = rv370_pcie_gart_init(rdev); | |
521 | if (r) | |
522 | return r; | |
523 | rv515_set_safe_registers(rdev); | |
524 | rdev->accel_working = true; | |
525 | r = rv515_startup(rdev); | |
526 | if (r) { | |
527 | /* Somethings want wront with the accel init stop accel */ | |
528 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
d39c3b89 JG |
529 | r100_cp_fini(rdev); |
530 | r100_wb_fini(rdev); | |
531 | r100_ib_fini(rdev); | |
655efd3d | 532 | radeon_irq_kms_fini(rdev); |
d39c3b89 JG |
533 | rv370_pcie_gart_fini(rdev); |
534 | radeon_agp_fini(rdev); | |
d39c3b89 JG |
535 | rdev->accel_working = false; |
536 | } | |
068a117c JG |
537 | return 0; |
538 | } | |
c93bb85b | 539 | |
4ce001ab | 540 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
c93bb85b | 541 | { |
4ce001ab DA |
542 | int index_reg = 0x6578 + crtc->crtc_offset; |
543 | int data_reg = 0x657c + crtc->crtc_offset; | |
544 | ||
545 | WREG32(0x659C + crtc->crtc_offset, 0x0); | |
546 | WREG32(0x6594 + crtc->crtc_offset, 0x705); | |
547 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); | |
548 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); | |
549 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); | |
550 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); | |
551 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); | |
552 | WREG32(index_reg, 0x0); | |
553 | WREG32(data_reg, 0x841880A8); | |
554 | WREG32(index_reg, 0x1); | |
555 | WREG32(data_reg, 0x84208680); | |
556 | WREG32(index_reg, 0x2); | |
557 | WREG32(data_reg, 0xBFF880B0); | |
558 | WREG32(index_reg, 0x100); | |
559 | WREG32(data_reg, 0x83D88088); | |
560 | WREG32(index_reg, 0x101); | |
561 | WREG32(data_reg, 0x84608680); | |
562 | WREG32(index_reg, 0x102); | |
563 | WREG32(data_reg, 0xBFF080D0); | |
564 | WREG32(index_reg, 0x200); | |
565 | WREG32(data_reg, 0x83988068); | |
566 | WREG32(index_reg, 0x201); | |
567 | WREG32(data_reg, 0x84A08680); | |
568 | WREG32(index_reg, 0x202); | |
569 | WREG32(data_reg, 0xBFF080F8); | |
570 | WREG32(index_reg, 0x300); | |
571 | WREG32(data_reg, 0x83588058); | |
572 | WREG32(index_reg, 0x301); | |
573 | WREG32(data_reg, 0x84E08660); | |
574 | WREG32(index_reg, 0x302); | |
575 | WREG32(data_reg, 0xBFF88120); | |
576 | WREG32(index_reg, 0x400); | |
577 | WREG32(data_reg, 0x83188040); | |
578 | WREG32(index_reg, 0x401); | |
579 | WREG32(data_reg, 0x85008660); | |
580 | WREG32(index_reg, 0x402); | |
581 | WREG32(data_reg, 0xBFF88150); | |
582 | WREG32(index_reg, 0x500); | |
583 | WREG32(data_reg, 0x82D88030); | |
584 | WREG32(index_reg, 0x501); | |
585 | WREG32(data_reg, 0x85408640); | |
586 | WREG32(index_reg, 0x502); | |
587 | WREG32(data_reg, 0xBFF88180); | |
588 | WREG32(index_reg, 0x600); | |
589 | WREG32(data_reg, 0x82A08018); | |
590 | WREG32(index_reg, 0x601); | |
591 | WREG32(data_reg, 0x85808620); | |
592 | WREG32(index_reg, 0x602); | |
593 | WREG32(data_reg, 0xBFF081B8); | |
594 | WREG32(index_reg, 0x700); | |
595 | WREG32(data_reg, 0x82608010); | |
596 | WREG32(index_reg, 0x701); | |
597 | WREG32(data_reg, 0x85A08600); | |
598 | WREG32(index_reg, 0x702); | |
599 | WREG32(data_reg, 0x800081F0); | |
600 | WREG32(index_reg, 0x800); | |
601 | WREG32(data_reg, 0x8228BFF8); | |
602 | WREG32(index_reg, 0x801); | |
603 | WREG32(data_reg, 0x85E085E0); | |
604 | WREG32(index_reg, 0x802); | |
605 | WREG32(data_reg, 0xBFF88228); | |
606 | WREG32(index_reg, 0x10000); | |
607 | WREG32(data_reg, 0x82A8BF00); | |
608 | WREG32(index_reg, 0x10001); | |
609 | WREG32(data_reg, 0x82A08CC0); | |
610 | WREG32(index_reg, 0x10002); | |
611 | WREG32(data_reg, 0x8008BEF8); | |
612 | WREG32(index_reg, 0x10100); | |
613 | WREG32(data_reg, 0x81F0BF28); | |
614 | WREG32(index_reg, 0x10101); | |
615 | WREG32(data_reg, 0x83608CA0); | |
616 | WREG32(index_reg, 0x10102); | |
617 | WREG32(data_reg, 0x8018BED0); | |
618 | WREG32(index_reg, 0x10200); | |
619 | WREG32(data_reg, 0x8148BF38); | |
620 | WREG32(index_reg, 0x10201); | |
621 | WREG32(data_reg, 0x84408C80); | |
622 | WREG32(index_reg, 0x10202); | |
623 | WREG32(data_reg, 0x8008BEB8); | |
624 | WREG32(index_reg, 0x10300); | |
625 | WREG32(data_reg, 0x80B0BF78); | |
626 | WREG32(index_reg, 0x10301); | |
627 | WREG32(data_reg, 0x85008C20); | |
628 | WREG32(index_reg, 0x10302); | |
629 | WREG32(data_reg, 0x8020BEA0); | |
630 | WREG32(index_reg, 0x10400); | |
631 | WREG32(data_reg, 0x8028BF90); | |
632 | WREG32(index_reg, 0x10401); | |
633 | WREG32(data_reg, 0x85E08BC0); | |
634 | WREG32(index_reg, 0x10402); | |
635 | WREG32(data_reg, 0x8018BE90); | |
636 | WREG32(index_reg, 0x10500); | |
637 | WREG32(data_reg, 0xBFB8BFB0); | |
638 | WREG32(index_reg, 0x10501); | |
639 | WREG32(data_reg, 0x86C08B40); | |
640 | WREG32(index_reg, 0x10502); | |
641 | WREG32(data_reg, 0x8010BE90); | |
642 | WREG32(index_reg, 0x10600); | |
643 | WREG32(data_reg, 0xBF58BFC8); | |
644 | WREG32(index_reg, 0x10601); | |
645 | WREG32(data_reg, 0x87A08AA0); | |
646 | WREG32(index_reg, 0x10602); | |
647 | WREG32(data_reg, 0x8010BE98); | |
648 | WREG32(index_reg, 0x10700); | |
649 | WREG32(data_reg, 0xBF10BFF0); | |
650 | WREG32(index_reg, 0x10701); | |
651 | WREG32(data_reg, 0x886089E0); | |
652 | WREG32(index_reg, 0x10702); | |
653 | WREG32(data_reg, 0x8018BEB0); | |
654 | WREG32(index_reg, 0x10800); | |
655 | WREG32(data_reg, 0xBED8BFE8); | |
656 | WREG32(index_reg, 0x10801); | |
657 | WREG32(data_reg, 0x89408940); | |
658 | WREG32(index_reg, 0x10802); | |
659 | WREG32(data_reg, 0xBFE8BED8); | |
660 | WREG32(index_reg, 0x20000); | |
661 | WREG32(data_reg, 0x80008000); | |
662 | WREG32(index_reg, 0x20001); | |
663 | WREG32(data_reg, 0x90008000); | |
664 | WREG32(index_reg, 0x20002); | |
665 | WREG32(data_reg, 0x80008000); | |
666 | WREG32(index_reg, 0x20003); | |
667 | WREG32(data_reg, 0x80008000); | |
668 | WREG32(index_reg, 0x20100); | |
669 | WREG32(data_reg, 0x80108000); | |
670 | WREG32(index_reg, 0x20101); | |
671 | WREG32(data_reg, 0x8FE0BF70); | |
672 | WREG32(index_reg, 0x20102); | |
673 | WREG32(data_reg, 0xBFE880C0); | |
674 | WREG32(index_reg, 0x20103); | |
675 | WREG32(data_reg, 0x80008000); | |
676 | WREG32(index_reg, 0x20200); | |
677 | WREG32(data_reg, 0x8018BFF8); | |
678 | WREG32(index_reg, 0x20201); | |
679 | WREG32(data_reg, 0x8F80BF08); | |
680 | WREG32(index_reg, 0x20202); | |
681 | WREG32(data_reg, 0xBFD081A0); | |
682 | WREG32(index_reg, 0x20203); | |
683 | WREG32(data_reg, 0xBFF88000); | |
684 | WREG32(index_reg, 0x20300); | |
685 | WREG32(data_reg, 0x80188000); | |
686 | WREG32(index_reg, 0x20301); | |
687 | WREG32(data_reg, 0x8EE0BEC0); | |
688 | WREG32(index_reg, 0x20302); | |
689 | WREG32(data_reg, 0xBFB082A0); | |
690 | WREG32(index_reg, 0x20303); | |
691 | WREG32(data_reg, 0x80008000); | |
692 | WREG32(index_reg, 0x20400); | |
693 | WREG32(data_reg, 0x80188000); | |
694 | WREG32(index_reg, 0x20401); | |
695 | WREG32(data_reg, 0x8E00BEA0); | |
696 | WREG32(index_reg, 0x20402); | |
697 | WREG32(data_reg, 0xBF8883C0); | |
698 | WREG32(index_reg, 0x20403); | |
699 | WREG32(data_reg, 0x80008000); | |
700 | WREG32(index_reg, 0x20500); | |
701 | WREG32(data_reg, 0x80188000); | |
702 | WREG32(index_reg, 0x20501); | |
703 | WREG32(data_reg, 0x8D00BE90); | |
704 | WREG32(index_reg, 0x20502); | |
705 | WREG32(data_reg, 0xBF588500); | |
706 | WREG32(index_reg, 0x20503); | |
707 | WREG32(data_reg, 0x80008008); | |
708 | WREG32(index_reg, 0x20600); | |
709 | WREG32(data_reg, 0x80188000); | |
710 | WREG32(index_reg, 0x20601); | |
711 | WREG32(data_reg, 0x8BC0BE98); | |
712 | WREG32(index_reg, 0x20602); | |
713 | WREG32(data_reg, 0xBF308660); | |
714 | WREG32(index_reg, 0x20603); | |
715 | WREG32(data_reg, 0x80008008); | |
716 | WREG32(index_reg, 0x20700); | |
717 | WREG32(data_reg, 0x80108000); | |
718 | WREG32(index_reg, 0x20701); | |
719 | WREG32(data_reg, 0x8A80BEB0); | |
720 | WREG32(index_reg, 0x20702); | |
721 | WREG32(data_reg, 0xBF0087C0); | |
722 | WREG32(index_reg, 0x20703); | |
723 | WREG32(data_reg, 0x80008008); | |
724 | WREG32(index_reg, 0x20800); | |
725 | WREG32(data_reg, 0x80108000); | |
726 | WREG32(index_reg, 0x20801); | |
727 | WREG32(data_reg, 0x8920BED0); | |
728 | WREG32(index_reg, 0x20802); | |
729 | WREG32(data_reg, 0xBED08920); | |
730 | WREG32(index_reg, 0x20803); | |
731 | WREG32(data_reg, 0x80008010); | |
732 | WREG32(index_reg, 0x30000); | |
733 | WREG32(data_reg, 0x90008000); | |
734 | WREG32(index_reg, 0x30001); | |
735 | WREG32(data_reg, 0x80008000); | |
736 | WREG32(index_reg, 0x30100); | |
737 | WREG32(data_reg, 0x8FE0BF90); | |
738 | WREG32(index_reg, 0x30101); | |
739 | WREG32(data_reg, 0xBFF880A0); | |
740 | WREG32(index_reg, 0x30200); | |
741 | WREG32(data_reg, 0x8F60BF40); | |
742 | WREG32(index_reg, 0x30201); | |
743 | WREG32(data_reg, 0xBFE88180); | |
744 | WREG32(index_reg, 0x30300); | |
745 | WREG32(data_reg, 0x8EC0BF00); | |
746 | WREG32(index_reg, 0x30301); | |
747 | WREG32(data_reg, 0xBFC88280); | |
748 | WREG32(index_reg, 0x30400); | |
749 | WREG32(data_reg, 0x8DE0BEE0); | |
750 | WREG32(index_reg, 0x30401); | |
751 | WREG32(data_reg, 0xBFA083A0); | |
752 | WREG32(index_reg, 0x30500); | |
753 | WREG32(data_reg, 0x8CE0BED0); | |
754 | WREG32(index_reg, 0x30501); | |
755 | WREG32(data_reg, 0xBF7884E0); | |
756 | WREG32(index_reg, 0x30600); | |
757 | WREG32(data_reg, 0x8BA0BED8); | |
758 | WREG32(index_reg, 0x30601); | |
759 | WREG32(data_reg, 0xBF508640); | |
760 | WREG32(index_reg, 0x30700); | |
761 | WREG32(data_reg, 0x8A60BEE8); | |
762 | WREG32(index_reg, 0x30701); | |
763 | WREG32(data_reg, 0xBF2087A0); | |
764 | WREG32(index_reg, 0x30800); | |
765 | WREG32(data_reg, 0x8900BF00); | |
766 | WREG32(index_reg, 0x30801); | |
767 | WREG32(data_reg, 0xBF008900); | |
c93bb85b JG |
768 | } |
769 | ||
770 | struct rv515_watermark { | |
771 | u32 lb_request_fifo_depth; | |
772 | fixed20_12 num_line_pair; | |
773 | fixed20_12 estimated_width; | |
774 | fixed20_12 worst_case_latency; | |
775 | fixed20_12 consumption_rate; | |
776 | fixed20_12 active_time; | |
777 | fixed20_12 dbpp; | |
778 | fixed20_12 priority_mark_max; | |
779 | fixed20_12 priority_mark; | |
780 | fixed20_12 sclk; | |
781 | }; | |
782 | ||
783 | void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, | |
784 | struct radeon_crtc *crtc, | |
785 | struct rv515_watermark *wm) | |
786 | { | |
787 | struct drm_display_mode *mode = &crtc->base.mode; | |
788 | fixed20_12 a, b, c; | |
789 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; | |
790 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; | |
791 | ||
792 | if (!crtc->base.enabled) { | |
793 | /* FIXME: wouldn't it better to set priority mark to maximum */ | |
794 | wm->lb_request_fifo_depth = 4; | |
795 | return; | |
796 | } | |
797 | ||
798 | if (crtc->vsc.full > rfixed_const(2)) | |
799 | wm->num_line_pair.full = rfixed_const(2); | |
800 | else | |
801 | wm->num_line_pair.full = rfixed_const(1); | |
802 | ||
803 | b.full = rfixed_const(mode->crtc_hdisplay); | |
804 | c.full = rfixed_const(256); | |
69b3b5e5 AD |
805 | a.full = rfixed_div(b, c); |
806 | request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair); | |
807 | request_fifo_depth.full = rfixed_ceil(request_fifo_depth); | |
c93bb85b JG |
808 | if (a.full < rfixed_const(4)) { |
809 | wm->lb_request_fifo_depth = 4; | |
810 | } else { | |
811 | wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); | |
812 | } | |
813 | ||
814 | /* Determine consumption rate | |
815 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) | |
816 | * vtaps = number of vertical taps, | |
817 | * vsc = vertical scaling ratio, defined as source/destination | |
818 | * hsc = horizontal scaling ration, defined as source/destination | |
819 | */ | |
820 | a.full = rfixed_const(mode->clock); | |
821 | b.full = rfixed_const(1000); | |
822 | a.full = rfixed_div(a, b); | |
823 | pclk.full = rfixed_div(b, a); | |
824 | if (crtc->rmx_type != RMX_OFF) { | |
825 | b.full = rfixed_const(2); | |
826 | if (crtc->vsc.full > b.full) | |
827 | b.full = crtc->vsc.full; | |
828 | b.full = rfixed_mul(b, crtc->hsc); | |
829 | c.full = rfixed_const(2); | |
830 | b.full = rfixed_div(b, c); | |
831 | consumption_time.full = rfixed_div(pclk, b); | |
832 | } else { | |
833 | consumption_time.full = pclk.full; | |
834 | } | |
835 | a.full = rfixed_const(1); | |
836 | wm->consumption_rate.full = rfixed_div(a, consumption_time); | |
837 | ||
838 | ||
839 | /* Determine line time | |
840 | * LineTime = total time for one line of displayhtotal | |
841 | * LineTime = total number of horizontal pixels | |
842 | * pclk = pixel clock period(ns) | |
843 | */ | |
844 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); | |
845 | line_time.full = rfixed_mul(a, pclk); | |
846 | ||
847 | /* Determine active time | |
848 | * ActiveTime = time of active region of display within one line, | |
849 | * hactive = total number of horizontal active pixels | |
850 | * htotal = total number of horizontal pixels | |
851 | */ | |
852 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); | |
853 | b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | |
854 | wm->active_time.full = rfixed_mul(line_time, b); | |
855 | wm->active_time.full = rfixed_div(wm->active_time, a); | |
856 | ||
857 | /* Determine chunk time | |
858 | * ChunkTime = the time it takes the DCP to send one chunk of data | |
859 | * to the LB which consists of pipeline delay and inter chunk gap | |
860 | * sclk = system clock(Mhz) | |
861 | */ | |
862 | a.full = rfixed_const(600 * 1000); | |
863 | chunk_time.full = rfixed_div(a, rdev->pm.sclk); | |
864 | read_delay_latency.full = rfixed_const(1000); | |
865 | ||
866 | /* Determine the worst case latency | |
867 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) | |
868 | * WorstCaseLatency = worst case time from urgent to when the MC starts | |
869 | * to return data | |
870 | * READ_DELAY_IDLE_MAX = constant of 1us | |
871 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB | |
872 | * which consists of pipeline delay and inter chunk gap | |
873 | */ | |
874 | if (rfixed_trunc(wm->num_line_pair) > 1) { | |
875 | a.full = rfixed_const(3); | |
876 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); | |
877 | wm->worst_case_latency.full += read_delay_latency.full; | |
878 | } else { | |
879 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; | |
880 | } | |
881 | ||
882 | /* Determine the tolerable latency | |
883 | * TolerableLatency = Any given request has only 1 line time | |
884 | * for the data to be returned | |
885 | * LBRequestFifoDepth = Number of chunk requests the LB can | |
886 | * put into the request FIFO for a display | |
887 | * LineTime = total time for one line of display | |
888 | * ChunkTime = the time it takes the DCP to send one chunk | |
889 | * of data to the LB which consists of | |
890 | * pipeline delay and inter chunk gap | |
891 | */ | |
892 | if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { | |
893 | tolerable_latency.full = line_time.full; | |
894 | } else { | |
895 | tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); | |
896 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; | |
897 | tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); | |
898 | tolerable_latency.full = line_time.full - tolerable_latency.full; | |
899 | } | |
900 | /* We assume worst case 32bits (4 bytes) */ | |
901 | wm->dbpp.full = rfixed_const(2 * 16); | |
902 | ||
903 | /* Determine the maximum priority mark | |
904 | * width = viewport width in pixels | |
905 | */ | |
906 | a.full = rfixed_const(16); | |
907 | wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | |
908 | wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); | |
69b3b5e5 | 909 | wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max); |
c93bb85b JG |
910 | |
911 | /* Determine estimated width */ | |
912 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; | |
913 | estimated_width.full = rfixed_div(estimated_width, consumption_time); | |
914 | if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | |
69b3b5e5 | 915 | wm->priority_mark.full = wm->priority_mark_max.full; |
c93bb85b JG |
916 | } else { |
917 | a.full = rfixed_const(16); | |
918 | wm->priority_mark.full = rfixed_div(estimated_width, a); | |
69b3b5e5 | 919 | wm->priority_mark.full = rfixed_ceil(wm->priority_mark); |
c93bb85b JG |
920 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
921 | } | |
922 | } | |
923 | ||
924 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |
925 | { | |
926 | struct drm_display_mode *mode0 = NULL; | |
927 | struct drm_display_mode *mode1 = NULL; | |
928 | struct rv515_watermark wm0; | |
929 | struct rv515_watermark wm1; | |
f46c0120 | 930 | u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
c93bb85b JG |
931 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
932 | fixed20_12 a, b; | |
933 | ||
934 | if (rdev->mode_info.crtcs[0]->base.enabled) | |
935 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | |
936 | if (rdev->mode_info.crtcs[1]->base.enabled) | |
937 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | |
938 | rs690_line_buffer_adjust(rdev, mode0, mode1); | |
939 | ||
940 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); | |
941 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); | |
942 | ||
943 | tmp = wm0.lb_request_fifo_depth; | |
944 | tmp |= wm1.lb_request_fifo_depth << 16; | |
945 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); | |
946 | ||
947 | if (mode0 && mode1) { | |
948 | if (rfixed_trunc(wm0.dbpp) > 64) | |
949 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); | |
950 | else | |
951 | a.full = wm0.num_line_pair.full; | |
952 | if (rfixed_trunc(wm1.dbpp) > 64) | |
953 | b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); | |
954 | else | |
955 | b.full = wm1.num_line_pair.full; | |
956 | a.full += b.full; | |
957 | fill_rate.full = rfixed_div(wm0.sclk, a); | |
958 | if (wm0.consumption_rate.full > fill_rate.full) { | |
959 | b.full = wm0.consumption_rate.full - fill_rate.full; | |
960 | b.full = rfixed_mul(b, wm0.active_time); | |
961 | a.full = rfixed_const(16); | |
962 | b.full = rfixed_div(b, a); | |
963 | a.full = rfixed_mul(wm0.worst_case_latency, | |
964 | wm0.consumption_rate); | |
965 | priority_mark02.full = a.full + b.full; | |
966 | } else { | |
967 | a.full = rfixed_mul(wm0.worst_case_latency, | |
968 | wm0.consumption_rate); | |
969 | b.full = rfixed_const(16 * 1000); | |
970 | priority_mark02.full = rfixed_div(a, b); | |
971 | } | |
972 | if (wm1.consumption_rate.full > fill_rate.full) { | |
973 | b.full = wm1.consumption_rate.full - fill_rate.full; | |
974 | b.full = rfixed_mul(b, wm1.active_time); | |
975 | a.full = rfixed_const(16); | |
976 | b.full = rfixed_div(b, a); | |
977 | a.full = rfixed_mul(wm1.worst_case_latency, | |
978 | wm1.consumption_rate); | |
979 | priority_mark12.full = a.full + b.full; | |
980 | } else { | |
981 | a.full = rfixed_mul(wm1.worst_case_latency, | |
982 | wm1.consumption_rate); | |
983 | b.full = rfixed_const(16 * 1000); | |
984 | priority_mark12.full = rfixed_div(a, b); | |
985 | } | |
986 | if (wm0.priority_mark.full > priority_mark02.full) | |
987 | priority_mark02.full = wm0.priority_mark.full; | |
988 | if (rfixed_trunc(priority_mark02) < 0) | |
989 | priority_mark02.full = 0; | |
990 | if (wm0.priority_mark_max.full > priority_mark02.full) | |
991 | priority_mark02.full = wm0.priority_mark_max.full; | |
992 | if (wm1.priority_mark.full > priority_mark12.full) | |
993 | priority_mark12.full = wm1.priority_mark.full; | |
994 | if (rfixed_trunc(priority_mark12) < 0) | |
995 | priority_mark12.full = 0; | |
996 | if (wm1.priority_mark_max.full > priority_mark12.full) | |
997 | priority_mark12.full = wm1.priority_mark_max.full; | |
f46c0120 AD |
998 | d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); |
999 | d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); | |
1000 | if (rdev->disp_priority == 2) { | |
1001 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | |
1002 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | |
1003 | } | |
1004 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | |
1005 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | |
1006 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | |
1007 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | |
c93bb85b JG |
1008 | } else if (mode0) { |
1009 | if (rfixed_trunc(wm0.dbpp) > 64) | |
1010 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); | |
1011 | else | |
1012 | a.full = wm0.num_line_pair.full; | |
1013 | fill_rate.full = rfixed_div(wm0.sclk, a); | |
1014 | if (wm0.consumption_rate.full > fill_rate.full) { | |
1015 | b.full = wm0.consumption_rate.full - fill_rate.full; | |
1016 | b.full = rfixed_mul(b, wm0.active_time); | |
1017 | a.full = rfixed_const(16); | |
1018 | b.full = rfixed_div(b, a); | |
1019 | a.full = rfixed_mul(wm0.worst_case_latency, | |
1020 | wm0.consumption_rate); | |
1021 | priority_mark02.full = a.full + b.full; | |
1022 | } else { | |
1023 | a.full = rfixed_mul(wm0.worst_case_latency, | |
1024 | wm0.consumption_rate); | |
1025 | b.full = rfixed_const(16); | |
1026 | priority_mark02.full = rfixed_div(a, b); | |
1027 | } | |
1028 | if (wm0.priority_mark.full > priority_mark02.full) | |
1029 | priority_mark02.full = wm0.priority_mark.full; | |
1030 | if (rfixed_trunc(priority_mark02) < 0) | |
1031 | priority_mark02.full = 0; | |
1032 | if (wm0.priority_mark_max.full > priority_mark02.full) | |
1033 | priority_mark02.full = wm0.priority_mark_max.full; | |
f46c0120 AD |
1034 | d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); |
1035 | if (rdev->disp_priority == 2) | |
1036 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | |
1037 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | |
1038 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | |
c93bb85b JG |
1039 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
1040 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | |
1041 | } else { | |
1042 | if (rfixed_trunc(wm1.dbpp) > 64) | |
1043 | a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); | |
1044 | else | |
1045 | a.full = wm1.num_line_pair.full; | |
1046 | fill_rate.full = rfixed_div(wm1.sclk, a); | |
1047 | if (wm1.consumption_rate.full > fill_rate.full) { | |
1048 | b.full = wm1.consumption_rate.full - fill_rate.full; | |
1049 | b.full = rfixed_mul(b, wm1.active_time); | |
1050 | a.full = rfixed_const(16); | |
1051 | b.full = rfixed_div(b, a); | |
1052 | a.full = rfixed_mul(wm1.worst_case_latency, | |
1053 | wm1.consumption_rate); | |
1054 | priority_mark12.full = a.full + b.full; | |
1055 | } else { | |
1056 | a.full = rfixed_mul(wm1.worst_case_latency, | |
1057 | wm1.consumption_rate); | |
1058 | b.full = rfixed_const(16 * 1000); | |
1059 | priority_mark12.full = rfixed_div(a, b); | |
1060 | } | |
1061 | if (wm1.priority_mark.full > priority_mark12.full) | |
1062 | priority_mark12.full = wm1.priority_mark.full; | |
1063 | if (rfixed_trunc(priority_mark12) < 0) | |
1064 | priority_mark12.full = 0; | |
1065 | if (wm1.priority_mark_max.full > priority_mark12.full) | |
1066 | priority_mark12.full = wm1.priority_mark_max.full; | |
f46c0120 AD |
1067 | d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); |
1068 | if (rdev->disp_priority == 2) | |
1069 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | |
c93bb85b JG |
1070 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
1071 | WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | |
f46c0120 AD |
1072 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
1073 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | |
c93bb85b JG |
1074 | } |
1075 | } | |
1076 | ||
1077 | void rv515_bandwidth_update(struct radeon_device *rdev) | |
1078 | { | |
1079 | uint32_t tmp; | |
1080 | struct drm_display_mode *mode0 = NULL; | |
1081 | struct drm_display_mode *mode1 = NULL; | |
1082 | ||
f46c0120 AD |
1083 | radeon_update_display_priority(rdev); |
1084 | ||
c93bb85b JG |
1085 | if (rdev->mode_info.crtcs[0]->base.enabled) |
1086 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | |
1087 | if (rdev->mode_info.crtcs[1]->base.enabled) | |
1088 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | |
1089 | /* | |
1090 | * Set display0/1 priority up in the memory controller for | |
1091 | * modes if the user specifies HIGH for displaypriority | |
1092 | * option. | |
1093 | */ | |
f46c0120 AD |
1094 | if ((rdev->disp_priority == 2) && |
1095 | (rdev->family == CHIP_RV515)) { | |
c93bb85b JG |
1096 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
1097 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; | |
1098 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; | |
1099 | if (mode1) | |
1100 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); | |
1101 | if (mode0) | |
1102 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); | |
1103 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); | |
1104 | } | |
1105 | rv515_bandwidth_avivo_update(rdev); | |
1106 | } |