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drm/radeon/kms: add support for ss overrides on Fusion APUs
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / radeon / rv770.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/firmware.h>
29#include <linux/platform_device.h>
5a0e3ad6 30#include <linux/slab.h>
771fe6b9 31#include "drmP.h"
771fe6b9 32#include "radeon.h"
e6990375 33#include "radeon_asic.h"
4153e584 34#include "radeon_drm.h"
3ce0a23d 35#include "rv770d.h"
3ce0a23d 36#include "atom.h"
d39c3b89 37#include "avivod.h"
771fe6b9 38
3ce0a23d
JG		 39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
771fe6b9 41
3ce0a23d
JG		 42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
771fe6b9 44
21a8122a
AD		 45/* get temperature in millidegrees */
46u32 rv770_get_temp(struct radeon_device *rdev)
47{
48 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
49 ASIC_T_SHIFT;
50 u32 actual_temp = 0;
51
52 if ((temp >> 9) & 1)
53 actual_temp = 0;
54 else
55 actual_temp = (temp >> 1) & 0xff;
56
57 return actual_temp * 1000;
58}
59
49e02b73
AD		 60void rv770_pm_misc(struct radeon_device *rdev)
61{
a081a9d6
RM		 62 int req_ps_idx = rdev->pm.requested_power_state_index;
63 int req_cm_idx = rdev->pm.requested_clock_mode_index;
64 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
65 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
4d60173f
AD		 66
67 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
68 if (voltage->voltage != rdev->pm.current_vddc) {
69 radeon_atom_set_voltage(rdev, voltage->voltage);
70 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 71 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 72 }
73 }
49e02b73 74}
771fe6b9
JG		 75
76/*
3ce0a23d 77 * GART
771fe6b9 78 */
3ce0a23d 79int rv770_pcie_gart_enable(struct radeon_device *rdev)
771fe6b9 80{
3ce0a23d
JG		 81 u32 tmp;
82 int r, i;
771fe6b9 83
4aac0473
JG		 84 if (rdev->gart.table.vram.robj == NULL) {
85 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
86 return -EINVAL;
3ce0a23d 87 }
4aac0473
JG		 88 r = radeon_gart_table_vram_pin(rdev);
89 if (r)
3ce0a23d 90 return r;
82568565 91 radeon_gart_restore(rdev);
3ce0a23d
JG		 92 /* Setup L2 cache */
93 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
94 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
95 EFFECTIVE_L2_QUEUE_SIZE(7));
96 WREG32(VM_L2_CNTL2, 0);
97 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
98 /* Setup TLB control */
99 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
100 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
101 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
102 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
103 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
104 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
105 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
106 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
107 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
108 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
109 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
110 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 111 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 112 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
113 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
114 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
115 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
116 (u32)(rdev->dummy_page.addr >> 12));
117 for (i = 1; i < 7; i++)
118 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 119
3ce0a23d
JG		 120 r600_pcie_gart_tlb_flush(rdev);
121 rdev->gart.ready = true;
771fe6b9
JG		 122 return 0;
123}
124
3ce0a23d 125void rv770_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 126{
3ce0a23d 127 u32 tmp;
4c788679 128 int i, r;
3ce0a23d 129
3ce0a23d
JG		 130 /* Disable all tables */
131 for (i = 0; i < 7; i++)
132 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
133
134 /* Setup L2 cache */
135 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
136 EFFECTIVE_L2_QUEUE_SIZE(7));
137 WREG32(VM_L2_CNTL2, 0);
138 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
139 /* Setup TLB control */
140 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
141 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
142 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
143 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
144 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
145 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
146 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
147 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
4aac0473 148 if (rdev->gart.table.vram.robj) {
4c788679
JG		 149 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
150 if (likely(r == 0)) {
151 radeon_bo_kunmap(rdev->gart.table.vram.robj);
152 radeon_bo_unpin(rdev->gart.table.vram.robj);
153 radeon_bo_unreserve(rdev->gart.table.vram.robj);
154 }
4aac0473
JG		 155 }
156}
157
158void rv770_pcie_gart_fini(struct radeon_device *rdev)
159{
f9274562 160 radeon_gart_fini(rdev);
4aac0473
JG		 161 rv770_pcie_gart_disable(rdev);
162 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 163}
164
165
1a029b76
JG		 166void rv770_agp_enable(struct radeon_device *rdev)
167{
168 u32 tmp;
169 int i;
170
171 /* Setup L2 cache */
172 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
173 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
174 EFFECTIVE_L2_QUEUE_SIZE(7));
175 WREG32(VM_L2_CNTL2, 0);
176 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
177 /* Setup TLB control */
178 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
179 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
180 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
181 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
182 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
183 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
184 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
185 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
186 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
187 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
188 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
189 for (i = 0; i < 7; i++)
190 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
191}
192
a3c1945a 193static void rv770_mc_program(struct radeon_device *rdev)
771fe6b9 194{
a3c1945a 195 struct rv515_mc_save save;
3ce0a23d
JG		 196 u32 tmp;
197 int i, j;
198
199 /* Initialize HDP */
200 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
201 WREG32((0x2c14 + j), 0x00000000);
202 WREG32((0x2c18 + j), 0x00000000);
203 WREG32((0x2c1c + j), 0x00000000);
204 WREG32((0x2c20 + j), 0x00000000);
205 WREG32((0x2c24 + j), 0x00000000);
206 }
812d0469
AD		 207 /* r7xx hw bug. Read from HDP_DEBUG1 rather
208 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
209 */
210 tmp = RREG32(HDP_DEBUG1);
3ce0a23d 211
a3c1945a 212 rv515_mc_stop(rdev, &save);
3ce0a23d 213 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 214 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 215 }
3ce0a23d
JG		 216 /* Lockout access through VGA aperture*/
217 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 218 /* Update configuration */
1a029b76
JG		 219 if (rdev->flags & RADEON_IS_AGP) {
220 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
221 /* VRAM before AGP */
222 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
223 rdev->mc.vram_start >> 12);
224 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
225 rdev->mc.gtt_end >> 12);
226 } else {
227 /* VRAM after AGP */
228 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
229 rdev->mc.gtt_start >> 12);
230 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
231 rdev->mc.vram_end >> 12);
232 }
233 } else {
234 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
235 rdev->mc.vram_start >> 12);
236 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
237 rdev->mc.vram_end >> 12);
238 }
3ce0a23d 239 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 240 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 241 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
242 WREG32(MC_VM_FB_LOCATION, tmp);
243 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
244 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 245 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 246 if (rdev->flags & RADEON_IS_AGP) {
1a029b76 247 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
3ce0a23d
JG		 248 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
249 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
250 } else {
251 WREG32(MC_VM_AGP_BASE, 0);
252 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
253 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
254 }
3ce0a23d 255 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 256 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 257 }
a3c1945a 258 rv515_mc_resume(rdev, &save);
698443d9
DA		 259 /* we need to own VRAM, so turn off the VGA renderer here
260 * to stop it overwriting our objects */
d39c3b89 261 rv515_vga_render_disable(rdev);
771fe6b9
JG		 262}
263
3ce0a23d
JG		 264
265/*
266 * CP.
267 */
268void r700_cp_stop(struct radeon_device *rdev)
771fe6b9 269{
c919b371 270 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
3ce0a23d 271 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
724c80e1 272 WREG32(SCRATCH_UMSK, 0);
771fe6b9
JG		 273}
274
3ce0a23d 275static int rv770_cp_load_microcode(struct radeon_device *rdev)
771fe6b9 276{
3ce0a23d
JG		 277 const __be32 *fw_data;
278 int i;
279
280 if (!rdev->me_fw || !rdev->pfp_fw)
281 return -EINVAL;
282
283 r700_cp_stop(rdev);
284 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
285
286 /* Reset cp */
287 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
288 RREG32(GRBM_SOFT_RESET);
289 mdelay(15);
290 WREG32(GRBM_SOFT_RESET, 0);
291
292 fw_data = (const __be32 *)rdev->pfp_fw->data;
293 WREG32(CP_PFP_UCODE_ADDR, 0);
294 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
295 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
296 WREG32(CP_PFP_UCODE_ADDR, 0);
297
298 fw_data = (const __be32 *)rdev->me_fw->data;
299 WREG32(CP_ME_RAM_WADDR, 0);
300 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
301 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
302
303 WREG32(CP_PFP_UCODE_ADDR, 0);
304 WREG32(CP_ME_RAM_WADDR, 0);
305 WREG32(CP_ME_RAM_RADDR, 0);
306 return 0;
771fe6b9
JG		 307}
308
fe251e2f
AD		 309void r700_cp_fini(struct radeon_device *rdev)
310{
311 r700_cp_stop(rdev);
312 radeon_ring_fini(rdev);
313}
771fe6b9
JG		 314
315/*
3ce0a23d 316 * Core functions
771fe6b9 317 */
d03f5d59
AD		 318static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
319 u32 num_tile_pipes,
320 u32 num_backends,
321 u32 backend_disable_mask)
771fe6b9 322{
3ce0a23d
JG		 323 u32 backend_map = 0;
324 u32 enabled_backends_mask;
325 u32 enabled_backends_count;
326 u32 cur_pipe;
327 u32 swizzle_pipe[R7XX_MAX_PIPES];
328 u32 cur_backend;
329 u32 i;
d03f5d59 330 bool force_no_swizzle;
3ce0a23d
JG		 331
332 if (num_tile_pipes > R7XX_MAX_PIPES)
333 num_tile_pipes = R7XX_MAX_PIPES;
334 if (num_tile_pipes < 1)
335 num_tile_pipes = 1;
336 if (num_backends > R7XX_MAX_BACKENDS)
337 num_backends = R7XX_MAX_BACKENDS;
338 if (num_backends < 1)
339 num_backends = 1;
340
341 enabled_backends_mask = 0;
342 enabled_backends_count = 0;
343 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
344 if (((backend_disable_mask >> i) & 1) == 0) {
345 enabled_backends_mask |= (1 << i);
346 ++enabled_backends_count;
347 }
348 if (enabled_backends_count == num_backends)
349 break;
350 }
351
352 if (enabled_backends_count == 0) {
353 enabled_backends_mask = 1;
354 enabled_backends_count = 1;
355 }
356
357 if (enabled_backends_count != num_backends)
358 num_backends = enabled_backends_count;
359
d03f5d59
AD		 360 switch (rdev->family) {
361 case CHIP_RV770:
362 case CHIP_RV730:
363 force_no_swizzle = false;
364 break;
365 case CHIP_RV710:
366 case CHIP_RV740:
367 default:
368 force_no_swizzle = true;
369 break;
370 }
371
3ce0a23d
JG		 372 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
373 switch (num_tile_pipes) {
374 case 1:
375 swizzle_pipe[0] = 0;
376 break;
377 case 2:
378 swizzle_pipe[0] = 0;
379 swizzle_pipe[1] = 1;
380 break;
381 case 3:
d03f5d59
AD		 382 if (force_no_swizzle) {
383 swizzle_pipe[0] = 0;
384 swizzle_pipe[1] = 1;
385 swizzle_pipe[2] = 2;
386 } else {
387 swizzle_pipe[0] = 0;
388 swizzle_pipe[1] = 2;
389 swizzle_pipe[2] = 1;
390 }
3ce0a23d
JG		 391 break;
392 case 4:
d03f5d59
AD		 393 if (force_no_swizzle) {
394 swizzle_pipe[0] = 0;
395 swizzle_pipe[1] = 1;
396 swizzle_pipe[2] = 2;
397 swizzle_pipe[3] = 3;
398 } else {
399 swizzle_pipe[0] = 0;
400 swizzle_pipe[1] = 2;
401 swizzle_pipe[2] = 3;
402 swizzle_pipe[3] = 1;
403 }
3ce0a23d
JG		 404 break;
405 case 5:
d03f5d59
AD		 406 if (force_no_swizzle) {
407 swizzle_pipe[0] = 0;
408 swizzle_pipe[1] = 1;
409 swizzle_pipe[2] = 2;
410 swizzle_pipe[3] = 3;
411 swizzle_pipe[4] = 4;
412 } else {
413 swizzle_pipe[0] = 0;
414 swizzle_pipe[1] = 2;
415 swizzle_pipe[2] = 4;
416 swizzle_pipe[3] = 1;
417 swizzle_pipe[4] = 3;
418 }
3ce0a23d
JG		 419 break;
420 case 6:
d03f5d59
AD		 421 if (force_no_swizzle) {
422 swizzle_pipe[0] = 0;
423 swizzle_pipe[1] = 1;
424 swizzle_pipe[2] = 2;
425 swizzle_pipe[3] = 3;
426 swizzle_pipe[4] = 4;
427 swizzle_pipe[5] = 5;
428 } else {
429 swizzle_pipe[0] = 0;
430 swizzle_pipe[1] = 2;
431 swizzle_pipe[2] = 4;
432 swizzle_pipe[3] = 5;
433 swizzle_pipe[4] = 3;
434 swizzle_pipe[5] = 1;
435 }
3ce0a23d
JG		 436 break;
437 case 7:
d03f5d59
AD		 438 if (force_no_swizzle) {
439 swizzle_pipe[0] = 0;
440 swizzle_pipe[1] = 1;
441 swizzle_pipe[2] = 2;
442 swizzle_pipe[3] = 3;
443 swizzle_pipe[4] = 4;
444 swizzle_pipe[5] = 5;
445 swizzle_pipe[6] = 6;
446 } else {
447 swizzle_pipe[0] = 0;
448 swizzle_pipe[1] = 2;
449 swizzle_pipe[2] = 4;
450 swizzle_pipe[3] = 6;
451 swizzle_pipe[4] = 3;
452 swizzle_pipe[5] = 1;
453 swizzle_pipe[6] = 5;
454 }
3ce0a23d
JG		 455 break;
456 case 8:
d03f5d59
AD		 457 if (force_no_swizzle) {
458 swizzle_pipe[0] = 0;
459 swizzle_pipe[1] = 1;
460 swizzle_pipe[2] = 2;
461 swizzle_pipe[3] = 3;
462 swizzle_pipe[4] = 4;
463 swizzle_pipe[5] = 5;
464 swizzle_pipe[6] = 6;
465 swizzle_pipe[7] = 7;
466 } else {
467 swizzle_pipe[0] = 0;
468 swizzle_pipe[1] = 2;
469 swizzle_pipe[2] = 4;
470 swizzle_pipe[3] = 6;
471 swizzle_pipe[4] = 3;
472 swizzle_pipe[5] = 1;
473 swizzle_pipe[6] = 7;
474 swizzle_pipe[7] = 5;
475 }
3ce0a23d
JG		 476 break;
477 }
478
479 cur_backend = 0;
480 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
481 while (((1 << cur_backend) & enabled_backends_mask) == 0)
482 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
483
484 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
485
486 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
487 }
488
489 return backend_map;
771fe6b9
JG		 490}
491
9535ab73
AD		 492static void rv770_program_channel_remap(struct radeon_device *rdev)
493{
494 u32 tcp_chan_steer, mc_shared_chremap, tmp;
495 bool force_no_swizzle;
496
497 switch (rdev->family) {
498 case CHIP_RV770:
499 case CHIP_RV730:
500 force_no_swizzle = false;
501 break;
502 case CHIP_RV710:
503 case CHIP_RV740:
504 default:
505 force_no_swizzle = true;
506 break;
507 }
508
509 tmp = RREG32(MC_SHARED_CHMAP);
510 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
511 case 0:
512 case 1:
513 default:
514 /* default mapping */
515 mc_shared_chremap = 0x00fac688;
516 break;
517 case 2:
518 case 3:
519 if (force_no_swizzle)
520 mc_shared_chremap = 0x00fac688;
521 else
522 mc_shared_chremap = 0x00bbc298;
523 break;
524 }
525
526 if (rdev->family == CHIP_RV740)
527 tcp_chan_steer = 0x00ef2a60;
528 else
529 tcp_chan_steer = 0x00fac688;
530
531 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
532 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
533}
534
3ce0a23d 535static void rv770_gpu_init(struct radeon_device *rdev)
771fe6b9 536{
3ce0a23d 537 int i, j, num_qd_pipes;
d03f5d59 538 u32 ta_aux_cntl;
3ce0a23d
JG		 539 u32 sx_debug_1;
540 u32 smx_dc_ctl0;
d03f5d59 541 u32 db_debug3;
3ce0a23d
JG		 542 u32 num_gs_verts_per_thread;
543 u32 vgt_gs_per_es;
544 u32 gs_prim_buffer_depth = 0;
545 u32 sq_ms_fifo_sizes;
546 u32 sq_config;
547 u32 sq_thread_resource_mgmt;
548 u32 hdp_host_path_cntl;
549 u32 sq_dyn_gpr_size_simd_ab_0;
550 u32 backend_map;
551 u32 gb_tiling_config = 0;
552 u32 cc_rb_backend_disable = 0;
553 u32 cc_gc_shader_pipe_config = 0;
554 u32 mc_arb_ramcfg;
555 u32 db_debug4;
771fe6b9 556
3ce0a23d
JG		 557 /* setup chip specs */
558 switch (rdev->family) {
559 case CHIP_RV770:
560 rdev->config.rv770.max_pipes = 4;
561 rdev->config.rv770.max_tile_pipes = 8;
562 rdev->config.rv770.max_simds = 10;
563 rdev->config.rv770.max_backends = 4;
564 rdev->config.rv770.max_gprs = 256;
565 rdev->config.rv770.max_threads = 248;
566 rdev->config.rv770.max_stack_entries = 512;
567 rdev->config.rv770.max_hw_contexts = 8;
568 rdev->config.rv770.max_gs_threads = 16 * 2;
569 rdev->config.rv770.sx_max_export_size = 128;
570 rdev->config.rv770.sx_max_export_pos_size = 16;
571 rdev->config.rv770.sx_max_export_smx_size = 112;
572 rdev->config.rv770.sq_num_cf_insts = 2;
573
574 rdev->config.rv770.sx_num_of_sets = 7;
575 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
576 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
577 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
578 break;
579 case CHIP_RV730:
580 rdev->config.rv770.max_pipes = 2;
581 rdev->config.rv770.max_tile_pipes = 4;
582 rdev->config.rv770.max_simds = 8;
583 rdev->config.rv770.max_backends = 2;
584 rdev->config.rv770.max_gprs = 128;
585 rdev->config.rv770.max_threads = 248;
586 rdev->config.rv770.max_stack_entries = 256;
587 rdev->config.rv770.max_hw_contexts = 8;
588 rdev->config.rv770.max_gs_threads = 16 * 2;
589 rdev->config.rv770.sx_max_export_size = 256;
590 rdev->config.rv770.sx_max_export_pos_size = 32;
591 rdev->config.rv770.sx_max_export_smx_size = 224;
592 rdev->config.rv770.sq_num_cf_insts = 2;
593
594 rdev->config.rv770.sx_num_of_sets = 7;
595 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
596 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
597 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
598 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
599 rdev->config.rv770.sx_max_export_pos_size -= 16;
600 rdev->config.rv770.sx_max_export_smx_size += 16;
601 }
602 break;
603 case CHIP_RV710:
604 rdev->config.rv770.max_pipes = 2;
605 rdev->config.rv770.max_tile_pipes = 2;
606 rdev->config.rv770.max_simds = 2;
607 rdev->config.rv770.max_backends = 1;
608 rdev->config.rv770.max_gprs = 256;
609 rdev->config.rv770.max_threads = 192;
610 rdev->config.rv770.max_stack_entries = 256;
611 rdev->config.rv770.max_hw_contexts = 4;
612 rdev->config.rv770.max_gs_threads = 8 * 2;
613 rdev->config.rv770.sx_max_export_size = 128;
614 rdev->config.rv770.sx_max_export_pos_size = 16;
615 rdev->config.rv770.sx_max_export_smx_size = 112;
616 rdev->config.rv770.sq_num_cf_insts = 1;
617
618 rdev->config.rv770.sx_num_of_sets = 7;
619 rdev->config.rv770.sc_prim_fifo_size = 0x40;
620 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
621 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
622 break;
623 case CHIP_RV740:
624 rdev->config.rv770.max_pipes = 4;
625 rdev->config.rv770.max_tile_pipes = 4;
626 rdev->config.rv770.max_simds = 8;
627 rdev->config.rv770.max_backends = 4;
628 rdev->config.rv770.max_gprs = 256;
629 rdev->config.rv770.max_threads = 248;
630 rdev->config.rv770.max_stack_entries = 512;
631 rdev->config.rv770.max_hw_contexts = 8;
632 rdev->config.rv770.max_gs_threads = 16 * 2;
633 rdev->config.rv770.sx_max_export_size = 256;
634 rdev->config.rv770.sx_max_export_pos_size = 32;
635 rdev->config.rv770.sx_max_export_smx_size = 224;
636 rdev->config.rv770.sq_num_cf_insts = 2;
637
638 rdev->config.rv770.sx_num_of_sets = 7;
639 rdev->config.rv770.sc_prim_fifo_size = 0x100;
640 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
641 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
642
643 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
644 rdev->config.rv770.sx_max_export_pos_size -= 16;
645 rdev->config.rv770.sx_max_export_smx_size += 16;
646 }
647 break;
648 default:
649 break;
650 }
651
652 /* Initialize HDP */
653 j = 0;
654 for (i = 0; i < 32; i++) {
655 WREG32((0x2c14 + j), 0x00000000);
656 WREG32((0x2c18 + j), 0x00000000);
657 WREG32((0x2c1c + j), 0x00000000);
658 WREG32((0x2c20 + j), 0x00000000);
659 WREG32((0x2c24 + j), 0x00000000);
660 j += 0x18;
661 }
662
663 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
664
665 /* setup tiling, simd, pipe config */
666 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
667
668 switch (rdev->config.rv770.max_tile_pipes) {
669 case 1:
d03f5d59 670 default:
3ce0a23d
JG		 671 gb_tiling_config |= PIPE_TILING(0);
672 break;
673 case 2:
674 gb_tiling_config |= PIPE_TILING(1);
675 break;
676 case 4:
677 gb_tiling_config |= PIPE_TILING(2);
678 break;
679 case 8:
680 gb_tiling_config |= PIPE_TILING(3);
3ce0a23d
JG		 681 break;
682 }
d03f5d59 683 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
3ce0a23d
JG		 684
685 if (rdev->family == CHIP_RV770)
686 gb_tiling_config |= BANK_TILING(1);
687 else
e29649db 688 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
961fb597 689 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
881fe6c1
AD		 690 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
691 if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
692 rdev->config.rv770.tiling_group_size = 512;
693 else
694 rdev->config.rv770.tiling_group_size = 256;
e29649db 695 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
3ce0a23d
JG		 696 gb_tiling_config |= ROW_TILING(3);
697 gb_tiling_config |= SAMPLE_SPLIT(3);
698 } else {
699 gb_tiling_config |=
700 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
701 gb_tiling_config |=
702 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
703 }
704
705 gb_tiling_config |= BANK_SWAPS(1);
706
d03f5d59
AD		 707 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
708 cc_rb_backend_disable |=
709 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
3ce0a23d 710
d03f5d59
AD		 711 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
712 cc_gc_shader_pipe_config |=
3ce0a23d
JG		 713 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
714 cc_gc_shader_pipe_config |=
715 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
716
d03f5d59
AD		 717 if (rdev->family == CHIP_RV740)
718 backend_map = 0x28;
719 else
720 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
721 rdev->config.rv770.max_tile_pipes,
722 (R7XX_MAX_BACKENDS -
723 r600_count_pipe_bits((cc_rb_backend_disable &
724 R7XX_MAX_BACKENDS_MASK) >> 16)),
725 (cc_rb_backend_disable >> 16));
d03f5d59 726
e7aeeba6
AD		 727 rdev->config.rv770.tile_config = gb_tiling_config;
728 gb_tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 729
730 WREG32(GB_TILING_CONFIG, gb_tiling_config);
731 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
732 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
733
9535ab73
AD		 734 rv770_program_channel_remap(rdev);
735
3ce0a23d
JG		 736 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
737 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 738 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
d03f5d59 739 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
3ce0a23d 740
3ce0a23d
JG		 741 WREG32(CGTS_SYS_TCC_DISABLE, 0);
742 WREG32(CGTS_TCC_DISABLE, 0);
f867c60d
AD		 743 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
744 WREG32(CGTS_USER_TCC_DISABLE, 0);
3ce0a23d
JG		 745
746 num_qd_pipes =
d03f5d59 747 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 748 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
749 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
750
751 /* set HW defaults for 3D engine */
752 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
e29649db 753 ROQ_IB2_START(0x2b)));
3ce0a23d
JG		 754
755 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
756
d03f5d59
AD		 757 ta_aux_cntl = RREG32(TA_CNTL_AUX);
758 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
3ce0a23d
JG		 759
760 sx_debug_1 = RREG32(SX_DEBUG_1);
761 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
762 WREG32(SX_DEBUG_1, sx_debug_1);
763
764 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
765 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
766 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
767 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
768
d03f5d59
AD		 769 if (rdev->family != CHIP_RV740)
770 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
771 GS_FLUSH_CTL(4) |
772 ACK_FLUSH_CTL(3) |
773 SYNC_FLUSH_CTL));
3ce0a23d 774
d03f5d59
AD		 775 db_debug3 = RREG32(DB_DEBUG3);
776 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
777 switch (rdev->family) {
778 case CHIP_RV770:
779 case CHIP_RV740:
780 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
781 break;
782 case CHIP_RV710:
783 case CHIP_RV730:
784 default:
785 db_debug3 |= DB_CLK_OFF_DELAY(2);
786 break;
787 }
788 WREG32(DB_DEBUG3, db_debug3);
789
790 if (rdev->family != CHIP_RV770) {
3ce0a23d
JG		 791 db_debug4 = RREG32(DB_DEBUG4);
792 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
793 WREG32(DB_DEBUG4, db_debug4);
794 }
795
796 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
e29649db
AD		 797 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
798 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
3ce0a23d
JG		 799
800 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
e29649db
AD		 801 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
802 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
3ce0a23d
JG		 803
804 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
805
806 WREG32(VGT_NUM_INSTANCES, 1);
807
808 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
809
810 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
811
812 WREG32(CP_PERFMON_CNTL, 0);
813
814 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
815 DONE_FIFO_HIWATER(0xe0) |
816 ALU_UPDATE_FIFO_HIWATER(0x8));
817 switch (rdev->family) {
818 case CHIP_RV770:
3ce0a23d
JG		 819 case CHIP_RV730:
820 case CHIP_RV710:
d03f5d59
AD		 821 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
822 break;
3ce0a23d
JG		 823 case CHIP_RV740:
824 default:
825 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
826 break;
827 }
828 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
829
830 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
831 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
832 */
833 sq_config = RREG32(SQ_CONFIG);
834 sq_config &= ~(PS_PRIO(3) |
835 VS_PRIO(3) |
836 GS_PRIO(3) |
837 ES_PRIO(3));
838 sq_config |= (DX9_CONSTS |
839 VC_ENABLE |
840 EXPORT_SRC_C |
841 PS_PRIO(0) |
842 VS_PRIO(1) |
843 GS_PRIO(2) |
844 ES_PRIO(3));
845 if (rdev->family == CHIP_RV710)
846 /* no vertex cache */
847 sq_config &= ~VC_ENABLE;
848
849 WREG32(SQ_CONFIG, sq_config);
850
851 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
fe62e1a4
DA		 852 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
853 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
3ce0a23d
JG		 854
855 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
fe62e1a4 856 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
3ce0a23d
JG		 857
858 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
859 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
860 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
861 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
862 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
863 else
864 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
865 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
866
867 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
868 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
869
870 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
871 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
872
873 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
874 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
875 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
876 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
877
878 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
879 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
880 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
881 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
882 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
883 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
884 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
885 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
886
887 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
fe62e1a4 888 FORCE_EOV_MAX_REZ_CNT(255)));
3ce0a23d
JG		 889
890 if (rdev->family == CHIP_RV710)
891 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
fe62e1a4 892 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 893 else
894 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
fe62e1a4 895 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 896
897 switch (rdev->family) {
898 case CHIP_RV770:
899 case CHIP_RV730:
900 case CHIP_RV740:
901 gs_prim_buffer_depth = 384;
902 break;
903 case CHIP_RV710:
904 gs_prim_buffer_depth = 128;
905 break;
906 default:
907 break;
908 }
909
910 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
911 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
912 /* Max value for this is 256 */
913 if (vgt_gs_per_es > 256)
914 vgt_gs_per_es = 256;
915
916 WREG32(VGT_ES_PER_GS, 128);
917 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
918 WREG32(VGT_GS_PER_VS, 2);
919
920 /* more default values. 2D/3D driver should adjust as needed */
921 WREG32(VGT_GS_VERTEX_REUSE, 16);
922 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
923 WREG32(VGT_STRMOUT_EN, 0);
924 WREG32(SX_MISC, 0);
925 WREG32(PA_SC_MODE_CNTL, 0);
926 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
927 WREG32(PA_SC_AA_CONFIG, 0);
928 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
929 WREG32(PA_SC_LINE_STIPPLE, 0);
930 WREG32(SPI_INPUT_Z, 0);
931 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
932 WREG32(CB_COLOR7_FRAG, 0);
933
934 /* clear render buffer base addresses */
935 WREG32(CB_COLOR0_BASE, 0);
936 WREG32(CB_COLOR1_BASE, 0);
937 WREG32(CB_COLOR2_BASE, 0);
938 WREG32(CB_COLOR3_BASE, 0);
939 WREG32(CB_COLOR4_BASE, 0);
940 WREG32(CB_COLOR5_BASE, 0);
941 WREG32(CB_COLOR6_BASE, 0);
942 WREG32(CB_COLOR7_BASE, 0);
943
944 WREG32(TCP_CNTL, 0);
945
946 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
947 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
948
949 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
950
951 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
952 NUM_CLIP_SEQ(3)));
953
954}
955
87cbf8f2
AD		 956static int rv770_vram_scratch_init(struct radeon_device *rdev)
957{
958 int r;
959 u64 gpu_addr;
960
961 if (rdev->vram_scratch.robj == NULL) {
962 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
268b2510
AD		 963 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
964 &rdev->vram_scratch.robj);
87cbf8f2
AD		 965 if (r) {
966 return r;
967 }
968 }
969
970 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
971 if (unlikely(r != 0))
972 return r;
973 r = radeon_bo_pin(rdev->vram_scratch.robj,
974 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
975 if (r) {
976 radeon_bo_unreserve(rdev->vram_scratch.robj);
977 return r;
978 }
979 r = radeon_bo_kmap(rdev->vram_scratch.robj,
980 (void **)&rdev->vram_scratch.ptr);
981 if (r)
982 radeon_bo_unpin(rdev->vram_scratch.robj);
983 radeon_bo_unreserve(rdev->vram_scratch.robj);
984
985 return r;
986}
987
988static void rv770_vram_scratch_fini(struct radeon_device *rdev)
989{
990 int r;
991
992 if (rdev->vram_scratch.robj == NULL) {
993 return;
994 }
995 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
996 if (likely(r == 0)) {
997 radeon_bo_kunmap(rdev->vram_scratch.robj);
998 radeon_bo_unpin(rdev->vram_scratch.robj);
999 radeon_bo_unreserve(rdev->vram_scratch.robj);
1000 }
1001 radeon_bo_unref(&rdev->vram_scratch.robj);
1002}
1003
3ce0a23d
JG		 1004int rv770_mc_init(struct radeon_device *rdev)
1005{
3ce0a23d 1006 u32 tmp;
5885b7a9 1007 int chansize, numchan;
3ce0a23d
JG		 1008
1009 /* Get VRAM informations */
3ce0a23d 1010 rdev->mc.vram_is_ddr = true;
5885b7a9
AD		 1011 tmp = RREG32(MC_ARB_RAMCFG);
1012 if (tmp & CHANSIZE_OVERRIDE) {
1013 chansize = 16;
1014 } else if (tmp & CHANSIZE_MASK) {
1015 chansize = 64;
1016 } else {
1017 chansize = 32;
1018 }
1019 tmp = RREG32(MC_SHARED_CHMAP);
1020 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1021 case 0:
1022 default:
1023 numchan = 1;
1024 break;
1025 case 1:
1026 numchan = 2;
1027 break;
1028 case 2:
1029 numchan = 4;
1030 break;
1031 case 3:
1032 numchan = 8;
1033 break;
1034 }
1035 rdev->mc.vram_width = numchan * chansize;
771fe6b9 1036 /* Could aper size report 0 ? */
01d73a69
JC		 1037 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1038 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1039 /* Setup GPU memory space */
1040 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1041 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1042 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 1043 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
d594e46a 1044 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 1045 radeon_update_bandwidth_info(rdev);
1046
3ce0a23d
JG		 1047 return 0;
1048}
d594e46a 1049
fc30b8ef 1050static int rv770_startup(struct radeon_device *rdev)
3ce0a23d
JG		 1051{
1052 int r;
1053
779720a3
AD		 1054 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1055 r = r600_init_microcode(rdev);
1056 if (r) {
1057 DRM_ERROR("Failed to load firmware!\n");
1058 return r;
1059 }
1060 }
1061
a3c1945a 1062 rv770_mc_program(rdev);
1a029b76
JG		 1063 if (rdev->flags & RADEON_IS_AGP) {
1064 rv770_agp_enable(rdev);
1065 } else {
1066 r = rv770_pcie_gart_enable(rdev);
1067 if (r)
1068 return r;
1069 }
87cbf8f2
AD		 1070 r = rv770_vram_scratch_init(rdev);
1071 if (r)
1072 return r;
3ce0a23d 1073 rv770_gpu_init(rdev);
c38c7b64
JG		 1074 r = r600_blit_init(rdev);
1075 if (r) {
1076 r600_blit_fini(rdev);
1077 rdev->asic->copy = NULL;
1078 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1079 }
b70d6bb3 1080
724c80e1
AD		 1081 /* allocate wb buffer */
1082 r = radeon_wb_init(rdev);
1083 if (r)
1084 return r;
1085
d8f60cfc 1086 /* Enable IRQ */
d8f60cfc
AD		 1087 r = r600_irq_init(rdev);
1088 if (r) {
1089 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1090 radeon_irq_kms_fini(rdev);
1091 return r;
1092 }
1093 r600_irq_set(rdev);
1094
3ce0a23d
JG		 1095 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1096 if (r)
1097 return r;
1098 r = rv770_cp_load_microcode(rdev);
1099 if (r)
1100 return r;
1101 r = r600_cp_resume(rdev);
1102 if (r)
1103 return r;
724c80e1 1104
3ce0a23d
JG		 1105 return 0;
1106}
1107
fc30b8ef
DA		 1108int rv770_resume(struct radeon_device *rdev)
1109{
1110 int r;
1111
1a029b76
JG		 1112 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1113 * posting will perform necessary task to bring back GPU into good
1114 * shape.
1115 */
fc30b8ef 1116 /* post card */
e7d40b9a 1117 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 1118
1119 r = rv770_startup(rdev);
1120 if (r) {
1121 DRM_ERROR("r600 startup failed on resume\n");
1122 return r;
1123 }
1124
62a8ea3f 1125 r = r600_ib_test(rdev);
fc30b8ef
DA		 1126 if (r) {
1127 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1128 return r;
1129 }
8a8c6e7c
RM		 1130
1131 r = r600_audio_init(rdev);
1132 if (r) {
1133 dev_err(rdev->dev, "radeon: audio init failed\n");
1134 return r;
1135 }
1136
fc30b8ef
DA		 1137 return r;
1138
1139}
1140
3ce0a23d
JG		 1141int rv770_suspend(struct radeon_device *rdev)
1142{
4c788679
JG		 1143 int r;
1144
8a8c6e7c 1145 r600_audio_fini(rdev);
3ce0a23d
JG		 1146 /* FIXME: we should wait for ring to be empty */
1147 r700_cp_stop(rdev);
4153e584 1148 rdev->cp.ready = false;
0c45249f 1149 r600_irq_suspend(rdev);
724c80e1 1150 radeon_wb_disable(rdev);
4aac0473 1151 rv770_pcie_gart_disable(rdev);
4153e584 1152 /* unpin shaders bo */
30d2d9a5
JG		 1153 if (rdev->r600_blit.shader_obj) {
1154 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1155 if (likely(r == 0)) {
1156 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1157 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1158 }
4c788679 1159 }
3ce0a23d
JG		 1160 return 0;
1161}
1162
1163/* Plan is to move initialization in that function and use
1164 * helper function so that radeon_device_init pretty much
1165 * do nothing more than calling asic specific function. This
1166 * should also allow to remove a bunch of callback function
1167 * like vram_info.
1168 */
1169int rv770_init(struct radeon_device *rdev)
1170{
1171 int r;
1172
3ce0a23d
JG		 1173 r = radeon_dummy_page_init(rdev);
1174 if (r)
1175 return r;
1176 /* This don't do much */
1177 r = radeon_gem_init(rdev);
1178 if (r)
1179 return r;
1180 /* Read BIOS */
1181 if (!radeon_get_bios(rdev)) {
1182 if (ASIC_IS_AVIVO(rdev))
1183 return -EINVAL;
1184 }
1185 /* Must be an ATOMBIOS */
e7d40b9a
JG		 1186 if (!rdev->is_atom_bios) {
1187 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 1188 return -EINVAL;
e7d40b9a 1189 }
3ce0a23d
JG		 1190 r = radeon_atombios_init(rdev);
1191 if (r)
1192 return r;
1193 /* Post card if necessary */
72542d77
DA		 1194 if (!r600_card_posted(rdev)) {
1195 if (!rdev->bios) {
1196 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1197 return -EINVAL;
1198 }
3ce0a23d
JG		 1199 DRM_INFO("GPU not posted. posting now...\n");
1200 atom_asic_init(rdev->mode_info.atom_context);
1201 }
1202 /* Initialize scratch registers */
1203 r600_scratch_init(rdev);
1204 /* Initialize surface registers */
1205 radeon_surface_init(rdev);
7433874e 1206 /* Initialize clocks */
5e6dde7e 1207 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 1208 /* Fence driver */
1209 r = radeon_fence_driver_init(rdev);
1210 if (r)
1211 return r;
d594e46a 1212 /* initialize AGP */
700a0cc0
JG		 1213 if (rdev->flags & RADEON_IS_AGP) {
1214 r = radeon_agp_init(rdev);
1215 if (r)
1216 radeon_agp_disable(rdev);
1217 }
3ce0a23d 1218 r = rv770_mc_init(rdev);
b574f251 1219 if (r)
3ce0a23d 1220 return r;
3ce0a23d 1221 /* Memory manager */
4c788679 1222 r = radeon_bo_init(rdev);
3ce0a23d
JG		 1223 if (r)
1224 return r;
d8f60cfc
AD		 1225
1226 r = radeon_irq_kms_init(rdev);
1227 if (r)
1228 return r;
1229
3ce0a23d
JG		 1230 rdev->cp.ring_obj = NULL;
1231 r600_ring_init(rdev, 1024 * 1024);
1232
d8f60cfc
AD		 1233 rdev->ih.ring_obj = NULL;
1234 r600_ih_ring_init(rdev, 64 * 1024);
1235
4aac0473
JG		 1236 r = r600_pcie_gart_init(rdev);
1237 if (r)
1238 return r;
1239
779720a3 1240 rdev->accel_working = true;
fc30b8ef 1241 r = rv770_startup(rdev);
3ce0a23d 1242 if (r) {
655efd3d 1243 dev_err(rdev->dev, "disabling GPU acceleration\n");
fe251e2f 1244 r700_cp_fini(rdev);
655efd3d 1245 r600_irq_fini(rdev);
724c80e1 1246 radeon_wb_fini(rdev);
655efd3d 1247 radeon_irq_kms_fini(rdev);
75c81298 1248 rv770_pcie_gart_fini(rdev);
733289c2 1249 rdev->accel_working = false;
3ce0a23d 1250 }
733289c2 1251 if (rdev->accel_working) {
733289c2
JG		 1252 r = radeon_ib_pool_init(rdev);
1253 if (r) {
db96380e 1254 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 1255 rdev->accel_working = false;
db96380e
JG		 1256 } else {
1257 r = r600_ib_test(rdev);
1258 if (r) {
1259 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1260 rdev->accel_working = false;
1261 }
733289c2 1262 }
3ce0a23d 1263 }
8a8c6e7c
RM		 1264
1265 r = r600_audio_init(rdev);
1266 if (r) {
1267 dev_err(rdev->dev, "radeon: audio init failed\n");
1268 return r;
1269 }
1270
3ce0a23d
JG		 1271 return 0;
1272}
1273
1274void rv770_fini(struct radeon_device *rdev)
1275{
1276 r600_blit_fini(rdev);
fe251e2f 1277 r700_cp_fini(rdev);
d8f60cfc 1278 r600_irq_fini(rdev);
724c80e1 1279 radeon_wb_fini(rdev);
d8f60cfc 1280 radeon_irq_kms_fini(rdev);
4aac0473 1281 rv770_pcie_gart_fini(rdev);
87cbf8f2 1282 rv770_vram_scratch_fini(rdev);
3ce0a23d
JG		 1283 radeon_gem_fini(rdev);
1284 radeon_fence_driver_fini(rdev);
d0269ed8 1285 radeon_agp_fini(rdev);
4c788679 1286 radeon_bo_fini(rdev);
e7d40b9a 1287 radeon_atombios_fini(rdev);
3ce0a23d
JG		 1288 kfree(rdev->bios);
1289 rdev->bios = NULL;
1290 radeon_dummy_page_fini(rdev);
771fe6b9 1291}
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