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3ce0a23d JG |
1 | /* |
2 | * Copyright 2009 Advanced Micro Devices, Inc. | |
3 | * Copyright 2009 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | * Jerome Glisse | |
26 | */ | |
27 | #ifndef RV770_H | |
28 | #define RV770_H | |
29 | ||
30 | #define R7XX_MAX_SH_GPRS 256 | |
31 | #define R7XX_MAX_TEMP_GPRS 16 | |
32 | #define R7XX_MAX_SH_THREADS 256 | |
33 | #define R7XX_MAX_SH_STACK_ENTRIES 4096 | |
34 | #define R7XX_MAX_BACKENDS 8 | |
35 | #define R7XX_MAX_BACKENDS_MASK 0xff | |
36 | #define R7XX_MAX_SIMDS 16 | |
37 | #define R7XX_MAX_SIMDS_MASK 0xffff | |
38 | #define R7XX_MAX_PIPES 8 | |
39 | #define R7XX_MAX_PIPES_MASK 0xff | |
40 | ||
ef0e6e65 CK |
41 | /* discrete uvd clocks */ |
42 | #define CG_UPLL_FUNC_CNTL 0x718 | |
43 | # define UPLL_RESET_MASK 0x00000001 | |
44 | # define UPLL_SLEEP_MASK 0x00000002 | |
45 | # define UPLL_BYPASS_EN_MASK 0x00000004 | |
46 | # define UPLL_CTLREQ_MASK 0x00000008 | |
47 | # define UPLL_REF_DIV(x) ((x) << 16) | |
092fbc4c | 48 | # define UPLL_REF_DIV_MASK 0x003F0000 |
ef0e6e65 CK |
49 | # define UPLL_CTLACK_MASK 0x40000000 |
50 | # define UPLL_CTLACK2_MASK 0x80000000 | |
51 | #define CG_UPLL_FUNC_CNTL_2 0x71c | |
52 | # define UPLL_SW_HILEN(x) ((x) << 0) | |
53 | # define UPLL_SW_LOLEN(x) ((x) << 4) | |
54 | # define UPLL_SW_HILEN2(x) ((x) << 8) | |
55 | # define UPLL_SW_LOLEN2(x) ((x) << 12) | |
56 | # define UPLL_SW_MASK 0x0000FFFF | |
57 | # define VCLK_SRC_SEL(x) ((x) << 20) | |
58 | # define VCLK_SRC_SEL_MASK 0x01F00000 | |
59 | # define DCLK_SRC_SEL(x) ((x) << 25) | |
60 | # define DCLK_SRC_SEL_MASK 0x3E000000 | |
61 | #define CG_UPLL_FUNC_CNTL_3 0x720 | |
62 | # define UPLL_FB_DIV(x) ((x) << 0) | |
63 | # define UPLL_FB_DIV_MASK 0x01FFFFFF | |
64 | ||
66229b20 AD |
65 | /* pm registers */ |
66 | #define SMC_SRAM_ADDR 0x200 | |
67 | #define SMC_SRAM_AUTO_INC_DIS (1 << 16) | |
68 | #define SMC_SRAM_DATA 0x204 | |
69 | #define SMC_IO 0x208 | |
70 | #define SMC_RST_N (1 << 0) | |
71 | #define SMC_STOP_MODE (1 << 2) | |
72 | #define SMC_CLK_EN (1 << 11) | |
73 | #define SMC_MSG 0x20c | |
74 | #define HOST_SMC_MSG(x) ((x) << 0) | |
75 | #define HOST_SMC_MSG_MASK (0xff << 0) | |
76 | #define HOST_SMC_MSG_SHIFT 0 | |
77 | #define HOST_SMC_RESP(x) ((x) << 8) | |
78 | #define HOST_SMC_RESP_MASK (0xff << 8) | |
79 | #define HOST_SMC_RESP_SHIFT 8 | |
80 | #define SMC_HOST_MSG(x) ((x) << 16) | |
81 | #define SMC_HOST_MSG_MASK (0xff << 16) | |
82 | #define SMC_HOST_MSG_SHIFT 16 | |
83 | #define SMC_HOST_RESP(x) ((x) << 24) | |
84 | #define SMC_HOST_RESP_MASK (0xff << 24) | |
85 | #define SMC_HOST_RESP_SHIFT 24 | |
86 | ||
87 | #define SMC_ISR_FFD8_FFDB 0x218 | |
88 | ||
89 | #define CG_SPLL_FUNC_CNTL 0x600 | |
90 | #define SPLL_RESET (1 << 0) | |
91 | #define SPLL_SLEEP (1 << 1) | |
92 | #define SPLL_DIVEN (1 << 2) | |
93 | #define SPLL_BYPASS_EN (1 << 3) | |
94 | #define SPLL_REF_DIV(x) ((x) << 4) | |
95 | #define SPLL_REF_DIV_MASK (0x3f << 4) | |
96 | #define SPLL_HILEN(x) ((x) << 12) | |
97 | #define SPLL_HILEN_MASK (0xf << 12) | |
98 | #define SPLL_LOLEN(x) ((x) << 16) | |
99 | #define SPLL_LOLEN_MASK (0xf << 16) | |
100 | #define CG_SPLL_FUNC_CNTL_2 0x604 | |
101 | #define SCLK_MUX_SEL(x) ((x) << 0) | |
102 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) | |
de9ae744 | 103 | #define SCLK_MUX_UPDATE (1 << 26) |
66229b20 AD |
104 | #define CG_SPLL_FUNC_CNTL_3 0x608 |
105 | #define SPLL_FB_DIV(x) ((x) << 0) | |
106 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) | |
107 | #define SPLL_DITHEN (1 << 28) | |
de9ae744 AD |
108 | #define CG_SPLL_STATUS 0x60c |
109 | #define SPLL_CHG_STATUS (1 << 1) | |
66229b20 AD |
110 | |
111 | #define SPLL_CNTL_MODE 0x610 | |
112 | #define SPLL_DIV_SYNC (1 << 5) | |
113 | ||
de9ae744 AD |
114 | #define MPLL_CNTL_MODE 0x61c |
115 | # define MPLL_MCLK_SEL (1 << 11) | |
116 | # define RV730_MPLL_MCLK_SEL (1 << 25) | |
117 | ||
66229b20 AD |
118 | #define MPLL_AD_FUNC_CNTL 0x624 |
119 | #define CLKF(x) ((x) << 0) | |
120 | #define CLKF_MASK (0x7f << 0) | |
121 | #define CLKR(x) ((x) << 7) | |
122 | #define CLKR_MASK (0x1f << 7) | |
123 | #define CLKFRAC(x) ((x) << 12) | |
124 | #define CLKFRAC_MASK (0x1f << 12) | |
125 | #define YCLK_POST_DIV(x) ((x) << 17) | |
126 | #define YCLK_POST_DIV_MASK (3 << 17) | |
127 | #define IBIAS(x) ((x) << 20) | |
128 | #define IBIAS_MASK (0x3ff << 20) | |
129 | #define RESET (1 << 30) | |
130 | #define PDNB (1 << 31) | |
131 | #define MPLL_AD_FUNC_CNTL_2 0x628 | |
132 | #define BYPASS (1 << 19) | |
133 | #define BIAS_GEN_PDNB (1 << 24) | |
134 | #define RESET_EN (1 << 25) | |
135 | #define VCO_MODE (1 << 29) | |
136 | #define MPLL_DQ_FUNC_CNTL 0x62c | |
137 | #define MPLL_DQ_FUNC_CNTL_2 0x630 | |
138 | ||
139 | #define GENERAL_PWRMGT 0x63c | |
140 | # define GLOBAL_PWRMGT_EN (1 << 0) | |
141 | # define STATIC_PM_EN (1 << 1) | |
142 | # define THERMAL_PROTECTION_DIS (1 << 2) | |
143 | # define THERMAL_PROTECTION_TYPE (1 << 3) | |
144 | # define ENABLE_GEN2PCIE (1 << 4) | |
145 | # define ENABLE_GEN2XSP (1 << 5) | |
146 | # define SW_SMIO_INDEX(x) ((x) << 6) | |
147 | # define SW_SMIO_INDEX_MASK (3 << 6) | |
148 | # define SW_SMIO_INDEX_SHIFT 6 | |
149 | # define LOW_VOLT_D2_ACPI (1 << 8) | |
150 | # define LOW_VOLT_D3_ACPI (1 << 9) | |
151 | # define VOLT_PWRMGT_EN (1 << 10) | |
152 | # define BACKBIAS_PAD_EN (1 << 18) | |
153 | # define BACKBIAS_VALUE (1 << 19) | |
154 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) | |
155 | # define AC_DC_SW (1 << 24) | |
156 | ||
157 | #define CG_TPC 0x640 | |
158 | #define SCLK_PWRMGT_CNTL 0x644 | |
159 | # define SCLK_PWRMGT_OFF (1 << 0) | |
160 | # define SCLK_LOW_D1 (1 << 1) | |
161 | # define FIR_RESET (1 << 4) | |
162 | # define FIR_FORCE_TREND_SEL (1 << 5) | |
163 | # define FIR_TREND_MODE (1 << 6) | |
164 | # define DYN_GFX_CLK_OFF_EN (1 << 7) | |
165 | # define GFX_CLK_FORCE_ON (1 << 8) | |
166 | # define GFX_CLK_REQUEST_OFF (1 << 9) | |
167 | # define GFX_CLK_FORCE_OFF (1 << 10) | |
168 | # define GFX_CLK_OFF_ACPI_D1 (1 << 11) | |
169 | # define GFX_CLK_OFF_ACPI_D2 (1 << 12) | |
170 | # define GFX_CLK_OFF_ACPI_D3 (1 << 13) | |
171 | #define MCLK_PWRMGT_CNTL 0x648 | |
172 | # define DLL_SPEED(x) ((x) << 0) | |
173 | # define DLL_SPEED_MASK (0x1f << 0) | |
174 | # define MPLL_PWRMGT_OFF (1 << 5) | |
175 | # define DLL_READY (1 << 6) | |
176 | # define MC_INT_CNTL (1 << 7) | |
177 | # define MRDCKA0_SLEEP (1 << 8) | |
178 | # define MRDCKA1_SLEEP (1 << 9) | |
179 | # define MRDCKB0_SLEEP (1 << 10) | |
180 | # define MRDCKB1_SLEEP (1 << 11) | |
181 | # define MRDCKC0_SLEEP (1 << 12) | |
182 | # define MRDCKC1_SLEEP (1 << 13) | |
183 | # define MRDCKD0_SLEEP (1 << 14) | |
184 | # define MRDCKD1_SLEEP (1 << 15) | |
185 | # define MRDCKA0_RESET (1 << 16) | |
186 | # define MRDCKA1_RESET (1 << 17) | |
187 | # define MRDCKB0_RESET (1 << 18) | |
188 | # define MRDCKB1_RESET (1 << 19) | |
189 | # define MRDCKC0_RESET (1 << 20) | |
190 | # define MRDCKC1_RESET (1 << 21) | |
191 | # define MRDCKD0_RESET (1 << 22) | |
192 | # define MRDCKD1_RESET (1 << 23) | |
193 | # define DLL_READY_READ (1 << 24) | |
194 | # define USE_DISPLAY_GAP (1 << 25) | |
195 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) | |
196 | # define MPLL_TURNOFF_D2 (1 << 28) | |
197 | #define DLL_CNTL 0x64c | |
198 | # define MRDCKA0_BYPASS (1 << 24) | |
199 | # define MRDCKA1_BYPASS (1 << 25) | |
200 | # define MRDCKB0_BYPASS (1 << 26) | |
201 | # define MRDCKB1_BYPASS (1 << 27) | |
202 | # define MRDCKC0_BYPASS (1 << 28) | |
203 | # define MRDCKC1_BYPASS (1 << 29) | |
204 | # define MRDCKD0_BYPASS (1 << 30) | |
205 | # define MRDCKD1_BYPASS (1 << 31) | |
206 | ||
207 | #define MPLL_TIME 0x654 | |
208 | # define MPLL_LOCK_TIME(x) ((x) << 0) | |
209 | # define MPLL_LOCK_TIME_MASK (0xffff << 0) | |
210 | # define MPLL_RESET_TIME(x) ((x) << 16) | |
211 | # define MPLL_RESET_TIME_MASK (0xffff << 16) | |
212 | ||
213 | #define CG_CLKPIN_CNTL 0x660 | |
214 | # define MUX_TCLK_TO_XCLK (1 << 8) | |
215 | # define XTALIN_DIVIDE (1 << 9) | |
216 | ||
bd210d11 AD |
217 | #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c |
218 | # define CURRENT_PROFILE_INDEX_MASK (0xf << 4) | |
219 | # define CURRENT_PROFILE_INDEX_SHIFT 4 | |
220 | ||
66229b20 AD |
221 | #define S0_VID_LOWER_SMIO_CNTL 0x678 |
222 | #define S1_VID_LOWER_SMIO_CNTL 0x67c | |
223 | #define S2_VID_LOWER_SMIO_CNTL 0x680 | |
224 | #define S3_VID_LOWER_SMIO_CNTL 0x684 | |
225 | ||
226 | #define CG_FTV 0x690 | |
227 | #define CG_FFCT_0 0x694 | |
228 | # define UTC_0(x) ((x) << 0) | |
229 | # define UTC_0_MASK (0x3ff << 0) | |
230 | # define DTC_0(x) ((x) << 10) | |
231 | # define DTC_0_MASK (0x3ff << 10) | |
232 | ||
233 | #define CG_BSP 0x6d0 | |
234 | # define BSP(x) ((x) << 0) | |
235 | # define BSP_MASK (0xffff << 0) | |
236 | # define BSU(x) ((x) << 16) | |
237 | # define BSU_MASK (0xf << 16) | |
238 | #define CG_AT 0x6d4 | |
239 | # define CG_R(x) ((x) << 0) | |
240 | # define CG_R_MASK (0xffff << 0) | |
241 | # define CG_L(x) ((x) << 16) | |
242 | # define CG_L_MASK (0xffff << 16) | |
243 | #define CG_GIT 0x6d8 | |
244 | # define CG_GICST(x) ((x) << 0) | |
245 | # define CG_GICST_MASK (0xffff << 0) | |
246 | # define CG_GIPOT(x) ((x) << 16) | |
247 | # define CG_GIPOT_MASK (0xffff << 16) | |
248 | ||
249 | #define CG_SSP 0x6e8 | |
250 | # define SST(x) ((x) << 0) | |
251 | # define SST_MASK (0xffff << 0) | |
252 | # define SSTU(x) ((x) << 16) | |
253 | # define SSTU_MASK (0xf << 16) | |
254 | ||
255 | #define CG_DISPLAY_GAP_CNTL 0x714 | |
256 | # define DISP1_GAP(x) ((x) << 0) | |
257 | # define DISP1_GAP_MASK (3 << 0) | |
258 | # define DISP2_GAP(x) ((x) << 2) | |
259 | # define DISP2_GAP_MASK (3 << 2) | |
260 | # define VBI_TIMER_COUNT(x) ((x) << 4) | |
261 | # define VBI_TIMER_COUNT_MASK (0x3fff << 4) | |
262 | # define VBI_TIMER_UNIT(x) ((x) << 20) | |
263 | # define VBI_TIMER_UNIT_MASK (7 << 20) | |
264 | # define DISP1_GAP_MCHG(x) ((x) << 24) | |
265 | # define DISP1_GAP_MCHG_MASK (3 << 24) | |
266 | # define DISP2_GAP_MCHG(x) ((x) << 26) | |
267 | # define DISP2_GAP_MCHG_MASK (3 << 26) | |
268 | ||
269 | #define CG_SPLL_SPREAD_SPECTRUM 0x790 | |
270 | #define SSEN (1 << 0) | |
271 | #define CLKS(x) ((x) << 4) | |
272 | #define CLKS_MASK (0xfff << 4) | |
273 | #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 | |
274 | #define CLKV(x) ((x) << 0) | |
275 | #define CLKV_MASK (0x3ffffff << 0) | |
276 | #define CG_MPLL_SPREAD_SPECTRUM 0x798 | |
277 | #define CG_UPLL_SPREAD_SPECTRUM 0x79c | |
278 | # define SSEN_MASK 0x00000001 | |
279 | ||
280 | #define CG_CGTT_LOCAL_0 0x7d0 | |
281 | #define CG_CGTT_LOCAL_1 0x7d4 | |
282 | ||
283 | #define BIOS_SCRATCH_4 0x1734 | |
284 | ||
285 | #define MC_SEQ_MISC0 0x2a00 | |
286 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 | |
287 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 | |
288 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 | |
289 | ||
290 | #define MC_ARB_SQM_RATIO 0x2770 | |
291 | #define STATE0(x) ((x) << 0) | |
292 | #define STATE0_MASK (0xff << 0) | |
293 | #define STATE1(x) ((x) << 8) | |
294 | #define STATE1_MASK (0xff << 8) | |
295 | #define STATE2(x) ((x) << 16) | |
296 | #define STATE2_MASK (0xff << 16) | |
297 | #define STATE3(x) ((x) << 24) | |
298 | #define STATE3_MASK (0xff << 24) | |
299 | ||
300 | #define MC_ARB_RFSH_RATE 0x27b0 | |
301 | #define POWERMODE0(x) ((x) << 0) | |
302 | #define POWERMODE0_MASK (0xff << 0) | |
303 | #define POWERMODE1(x) ((x) << 8) | |
304 | #define POWERMODE1_MASK (0xff << 8) | |
305 | #define POWERMODE2(x) ((x) << 16) | |
306 | #define POWERMODE2_MASK (0xff << 16) | |
307 | #define POWERMODE3(x) ((x) << 24) | |
308 | #define POWERMODE3_MASK (0xff << 24) | |
309 | ||
310 | #define CGTS_SM_CTRL_REG 0x9150 | |
311 | ||
3ce0a23d JG |
312 | /* Registers */ |
313 | #define CB_COLOR0_BASE 0x28040 | |
314 | #define CB_COLOR1_BASE 0x28044 | |
315 | #define CB_COLOR2_BASE 0x28048 | |
316 | #define CB_COLOR3_BASE 0x2804C | |
317 | #define CB_COLOR4_BASE 0x28050 | |
318 | #define CB_COLOR5_BASE 0x28054 | |
319 | #define CB_COLOR6_BASE 0x28058 | |
320 | #define CB_COLOR7_BASE 0x2805C | |
321 | #define CB_COLOR7_FRAG 0x280FC | |
322 | ||
323 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 | |
324 | #define CC_RB_BACKEND_DISABLE 0x98F4 | |
325 | #define BACKEND_DISABLE(x) ((x) << 16) | |
326 | #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 | |
327 | ||
328 | #define CGTS_SYS_TCC_DISABLE 0x3F90 | |
329 | #define CGTS_TCC_DISABLE 0x9148 | |
330 | #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 | |
331 | #define CGTS_USER_TCC_DISABLE 0x914C | |
332 | ||
333 | #define CONFIG_MEMSIZE 0x5428 | |
334 | ||
335 | #define CP_ME_CNTL 0x86D8 | |
66229b20 AD |
336 | #define CP_ME_HALT (1 << 28) |
337 | #define CP_PFP_HALT (1 << 26) | |
3ce0a23d JG |
338 | #define CP_ME_RAM_DATA 0xC160 |
339 | #define CP_ME_RAM_RADDR 0xC158 | |
340 | #define CP_ME_RAM_WADDR 0xC15C | |
341 | #define CP_MEQ_THRESHOLDS 0x8764 | |
342 | #define STQ_SPLIT(x) ((x) << 0) | |
343 | #define CP_PERFMON_CNTL 0x87FC | |
344 | #define CP_PFP_UCODE_ADDR 0xC150 | |
345 | #define CP_PFP_UCODE_DATA 0xC154 | |
346 | #define CP_QUEUE_THRESHOLDS 0x8760 | |
347 | #define ROQ_IB1_START(x) ((x) << 0) | |
348 | #define ROQ_IB2_START(x) ((x) << 8) | |
349 | #define CP_RB_CNTL 0xC104 | |
4eace7fd CC |
350 | #define RB_BUFSZ(x) ((x) << 0) |
351 | #define RB_BLKSZ(x) ((x) << 8) | |
352 | #define RB_NO_UPDATE (1 << 27) | |
353 | #define RB_RPTR_WR_ENA (1 << 31) | |
3ce0a23d JG |
354 | #define BUF_SWAP_32BIT (2 << 16) |
355 | #define CP_RB_RPTR 0x8700 | |
356 | #define CP_RB_RPTR_ADDR 0xC10C | |
357 | #define CP_RB_RPTR_ADDR_HI 0xC110 | |
358 | #define CP_RB_RPTR_WR 0xC108 | |
359 | #define CP_RB_WPTR 0xC114 | |
360 | #define CP_RB_WPTR_ADDR 0xC118 | |
361 | #define CP_RB_WPTR_ADDR_HI 0xC11C | |
362 | #define CP_RB_WPTR_DELAY 0x8704 | |
363 | #define CP_SEM_WAIT_TIMER 0x85BC | |
364 | ||
365 | #define DB_DEBUG3 0x98B0 | |
366 | #define DB_CLK_OFF_DELAY(x) ((x) << 11) | |
367 | #define DB_DEBUG4 0x9B8C | |
368 | #define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) | |
369 | ||
370 | #define DCP_TILING_CONFIG 0x6CA0 | |
371 | #define PIPE_TILING(x) ((x) << 1) | |
372 | #define BANK_TILING(x) ((x) << 4) | |
373 | #define GROUP_SIZE(x) ((x) << 6) | |
374 | #define ROW_TILING(x) ((x) << 8) | |
375 | #define BANK_SWAPS(x) ((x) << 11) | |
376 | #define SAMPLE_SPLIT(x) ((x) << 14) | |
377 | #define BACKEND_MAP(x) ((x) << 16) | |
378 | ||
379 | #define GB_TILING_CONFIG 0x98F0 | |
416a2bd2 AD |
380 | #define PIPE_TILING__SHIFT 1 |
381 | #define PIPE_TILING__MASK 0x0000000e | |
3ce0a23d | 382 | |
4d75658b AD |
383 | #define DMA_TILING_CONFIG 0x3ec8 |
384 | #define DMA_TILING_CONFIG2 0xd0b8 | |
385 | ||
9a21059d CK |
386 | /* RV730 only */ |
387 | #define UVD_UDEC_TILING_CONFIG 0xef40 | |
388 | #define UVD_UDEC_DB_TILING_CONFIG 0xef44 | |
389 | #define UVD_UDEC_DBW_TILING_CONFIG 0xef48 | |
70a033d2 | 390 | #define UVD_NO_OP 0xeffc |
9a21059d | 391 | |
3ce0a23d JG |
392 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
393 | #define INACTIVE_QD_PIPES(x) ((x) << 8) | |
394 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 | |
416a2bd2 | 395 | #define INACTIVE_QD_PIPES_SHIFT 8 |
3ce0a23d JG |
396 | #define INACTIVE_SIMDS(x) ((x) << 16) |
397 | #define INACTIVE_SIMDS_MASK 0x00FF0000 | |
398 | ||
399 | #define GRBM_CNTL 0x8000 | |
400 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | |
401 | #define GRBM_SOFT_RESET 0x8020 | |
402 | #define SOFT_RESET_CP (1<<0) | |
403 | #define GRBM_STATUS 0x8010 | |
404 | #define CMDFIFO_AVAIL_MASK 0x0000000F | |
405 | #define GUI_ACTIVE (1<<31) | |
406 | #define GRBM_STATUS2 0x8014 | |
407 | ||
66229b20 AD |
408 | #define CG_THERMAL_CTRL 0x72C |
409 | #define DPM_EVENT_SRC(x) ((x) << 0) | |
410 | #define DPM_EVENT_SRC_MASK (7 << 0) | |
411 | #define DIG_THERM_DPM(x) ((x) << 14) | |
412 | #define DIG_THERM_DPM_MASK 0x003FC000 | |
413 | #define DIG_THERM_DPM_SHIFT 14 | |
414 | ||
415 | #define CG_THERMAL_INT 0x734 | |
416 | #define DIG_THERM_INTH(x) ((x) << 8) | |
417 | #define DIG_THERM_INTH_MASK 0x0000FF00 | |
418 | #define DIG_THERM_INTH_SHIFT 8 | |
419 | #define DIG_THERM_INTL(x) ((x) << 16) | |
420 | #define DIG_THERM_INTL_MASK 0x00FF0000 | |
421 | #define DIG_THERM_INTL_SHIFT 16 | |
422 | #define THERM_INT_MASK_HIGH (1 << 24) | |
423 | #define THERM_INT_MASK_LOW (1 << 25) | |
454d2e2a | 424 | |
21a8122a AD |
425 | #define CG_MULT_THERMAL_STATUS 0x740 |
426 | #define ASIC_T(x) ((x) << 16) | |
427 | #define ASIC_T_MASK 0x3FF0000 | |
428 | #define ASIC_T_SHIFT 16 | |
429 | ||
3ce0a23d JG |
430 | #define HDP_HOST_PATH_CNTL 0x2C00 |
431 | #define HDP_NONSURFACE_BASE 0x2C04 | |
432 | #define HDP_NONSURFACE_INFO 0x2C08 | |
433 | #define HDP_NONSURFACE_SIZE 0x2C0C | |
434 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 | |
435 | #define HDP_TILING_CONFIG 0x2F3C | |
812d0469 | 436 | #define HDP_DEBUG1 0x2F34 |
3ce0a23d | 437 | |
5885b7a9 AD |
438 | #define MC_SHARED_CHMAP 0x2004 |
439 | #define NOOFCHAN_SHIFT 12 | |
440 | #define NOOFCHAN_MASK 0x00003000 | |
9535ab73 | 441 | #define MC_SHARED_CHREMAP 0x2008 |
5885b7a9 | 442 | |
3ce0a23d JG |
443 | #define MC_ARB_RAMCFG 0x2760 |
444 | #define NOOFBANK_SHIFT 0 | |
445 | #define NOOFBANK_MASK 0x00000003 | |
446 | #define NOOFRANK_SHIFT 2 | |
447 | #define NOOFRANK_MASK 0x00000004 | |
448 | #define NOOFROWS_SHIFT 3 | |
449 | #define NOOFROWS_MASK 0x00000038 | |
450 | #define NOOFCOLS_SHIFT 6 | |
451 | #define NOOFCOLS_MASK 0x000000C0 | |
452 | #define CHANSIZE_SHIFT 8 | |
453 | #define CHANSIZE_MASK 0x00000100 | |
454 | #define BURSTLENGTH_SHIFT 9 | |
455 | #define BURSTLENGTH_MASK 0x00000200 | |
5885b7a9 | 456 | #define CHANSIZE_OVERRIDE (1 << 11) |
3ce0a23d JG |
457 | #define MC_VM_AGP_TOP 0x2028 |
458 | #define MC_VM_AGP_BOT 0x202C | |
459 | #define MC_VM_AGP_BASE 0x2030 | |
460 | #define MC_VM_FB_LOCATION 0x2024 | |
461 | #define MC_VM_MB_L1_TLB0_CNTL 0x2234 | |
462 | #define MC_VM_MB_L1_TLB1_CNTL 0x2238 | |
463 | #define MC_VM_MB_L1_TLB2_CNTL 0x223C | |
464 | #define MC_VM_MB_L1_TLB3_CNTL 0x2240 | |
465 | #define ENABLE_L1_TLB (1 << 0) | |
466 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) | |
467 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) | |
468 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) | |
469 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) | |
470 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) | |
471 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) | |
472 | #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) | |
473 | #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) | |
474 | #define MC_VM_MD_L1_TLB0_CNTL 0x2654 | |
475 | #define MC_VM_MD_L1_TLB1_CNTL 0x2658 | |
476 | #define MC_VM_MD_L1_TLB2_CNTL 0x265C | |
0b8c30bc | 477 | #define MC_VM_MD_L1_TLB3_CNTL 0x2698 |
3ce0a23d JG |
478 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C |
479 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 | |
480 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 | |
481 | ||
482 | #define PA_CL_ENHANCE 0x8A14 | |
483 | #define CLIP_VTX_REORDER_ENA (1 << 0) | |
484 | #define NUM_CLIP_SEQ(x) ((x) << 1) | |
485 | #define PA_SC_AA_CONFIG 0x28C04 | |
486 | #define PA_SC_CLIPRECT_RULE 0x2820C | |
487 | #define PA_SC_EDGERULE 0x28230 | |
488 | #define PA_SC_FIFO_SIZE 0x8BCC | |
489 | #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) | |
490 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) | |
491 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 | |
492 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) | |
493 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) | |
494 | #define PA_SC_LINE_STIPPLE 0x28A0C | |
495 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 | |
496 | #define PA_SC_MODE_CNTL 0x28A4C | |
497 | #define PA_SC_MULTI_CHIP_CNTL 0x8B20 | |
498 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) | |
499 | ||
500 | #define SCRATCH_REG0 0x8500 | |
501 | #define SCRATCH_REG1 0x8504 | |
502 | #define SCRATCH_REG2 0x8508 | |
503 | #define SCRATCH_REG3 0x850C | |
504 | #define SCRATCH_REG4 0x8510 | |
505 | #define SCRATCH_REG5 0x8514 | |
506 | #define SCRATCH_REG6 0x8518 | |
507 | #define SCRATCH_REG7 0x851C | |
508 | #define SCRATCH_UMSK 0x8540 | |
509 | #define SCRATCH_ADDR 0x8544 | |
510 | ||
b866d133 | 511 | #define SMX_SAR_CTL0 0xA008 |
3ce0a23d JG |
512 | #define SMX_DC_CTL0 0xA020 |
513 | #define USE_HASH_FUNCTION (1 << 0) | |
514 | #define CACHE_DEPTH(x) ((x) << 1) | |
515 | #define FLUSH_ALL_ON_EVENT (1 << 10) | |
516 | #define STALL_ON_EVENT (1 << 11) | |
517 | #define SMX_EVENT_CTL 0xA02C | |
518 | #define ES_FLUSH_CTL(x) ((x) << 0) | |
519 | #define GS_FLUSH_CTL(x) ((x) << 3) | |
520 | #define ACK_FLUSH_CTL(x) ((x) << 6) | |
521 | #define SYNC_FLUSH_CTL (1 << 8) | |
522 | ||
523 | #define SPI_CONFIG_CNTL 0x9100 | |
524 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) | |
525 | #define DISABLE_INTERP_1 (1 << 5) | |
526 | #define SPI_CONFIG_CNTL_1 0x913C | |
527 | #define VTX_DONE_DELAY(x) ((x) << 0) | |
528 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) | |
529 | #define SPI_INPUT_Z 0x286D8 | |
530 | #define SPI_PS_IN_CONTROL_0 0x286CC | |
531 | #define NUM_INTERP(x) ((x)<<0) | |
532 | #define POSITION_ENA (1<<8) | |
533 | #define POSITION_CENTROID (1<<9) | |
534 | #define POSITION_ADDR(x) ((x)<<10) | |
535 | #define PARAM_GEN(x) ((x)<<15) | |
536 | #define PARAM_GEN_ADDR(x) ((x)<<19) | |
537 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) | |
538 | #define PERSP_GRADIENT_ENA (1<<28) | |
539 | #define LINEAR_GRADIENT_ENA (1<<29) | |
540 | #define POSITION_SAMPLE (1<<30) | |
541 | #define BARYC_AT_SAMPLE_ENA (1<<31) | |
542 | ||
543 | #define SQ_CONFIG 0x8C00 | |
544 | #define VC_ENABLE (1 << 0) | |
545 | #define EXPORT_SRC_C (1 << 1) | |
546 | #define DX9_CONSTS (1 << 2) | |
547 | #define ALU_INST_PREFER_VECTOR (1 << 3) | |
548 | #define DX10_CLAMP (1 << 4) | |
549 | #define CLAUSE_SEQ_PRIO(x) ((x) << 8) | |
550 | #define PS_PRIO(x) ((x) << 24) | |
551 | #define VS_PRIO(x) ((x) << 26) | |
552 | #define GS_PRIO(x) ((x) << 28) | |
553 | #define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 | |
554 | #define SIMDA_RING0(x) ((x)<<0) | |
555 | #define SIMDA_RING1(x) ((x)<<8) | |
556 | #define SIMDB_RING0(x) ((x)<<16) | |
557 | #define SIMDB_RING1(x) ((x)<<24) | |
558 | #define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 | |
559 | #define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 | |
560 | #define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC | |
561 | #define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 | |
562 | #define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 | |
563 | #define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 | |
564 | #define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC | |
565 | #define ES_PRIO(x) ((x) << 30) | |
566 | #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 | |
567 | #define NUM_PS_GPRS(x) ((x) << 0) | |
568 | #define NUM_VS_GPRS(x) ((x) << 16) | |
569 | #define DYN_GPR_ENABLE (1 << 27) | |
570 | #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) | |
571 | #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 | |
572 | #define NUM_GS_GPRS(x) ((x) << 0) | |
573 | #define NUM_ES_GPRS(x) ((x) << 16) | |
574 | #define SQ_MS_FIFO_SIZES 0x8CF0 | |
575 | #define CACHE_FIFO_SIZE(x) ((x) << 0) | |
576 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) | |
577 | #define DONE_FIFO_HIWATER(x) ((x) << 16) | |
578 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) | |
579 | #define SQ_STACK_RESOURCE_MGMT_1 0x8C10 | |
580 | #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) | |
581 | #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) | |
582 | #define SQ_STACK_RESOURCE_MGMT_2 0x8C14 | |
583 | #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) | |
584 | #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) | |
585 | #define SQ_THREAD_RESOURCE_MGMT 0x8C0C | |
586 | #define NUM_PS_THREADS(x) ((x) << 0) | |
587 | #define NUM_VS_THREADS(x) ((x) << 8) | |
588 | #define NUM_GS_THREADS(x) ((x) << 16) | |
589 | #define NUM_ES_THREADS(x) ((x) << 24) | |
590 | ||
591 | #define SX_DEBUG_1 0x9058 | |
592 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) | |
593 | #define SX_EXPORT_BUFFER_SIZES 0x900C | |
594 | #define COLOR_BUFFER_SIZE(x) ((x) << 0) | |
595 | #define POSITION_BUFFER_SIZE(x) ((x) << 8) | |
596 | #define SMX_BUFFER_SIZE(x) ((x) << 16) | |
597 | #define SX_MISC 0x28350 | |
598 | ||
599 | #define TA_CNTL_AUX 0x9508 | |
600 | #define DISABLE_CUBE_WRAP (1 << 0) | |
601 | #define DISABLE_CUBE_ANISO (1 << 1) | |
602 | #define SYNC_GRADIENT (1 << 24) | |
603 | #define SYNC_WALKER (1 << 25) | |
604 | #define SYNC_ALIGNER (1 << 26) | |
605 | #define BILINEAR_PRECISION_6_BIT (0 << 31) | |
606 | #define BILINEAR_PRECISION_8_BIT (1 << 31) | |
607 | ||
608 | #define TCP_CNTL 0x9610 | |
9535ab73 | 609 | #define TCP_CHAN_STEER 0x9614 |
3ce0a23d | 610 | |
b866d133 AD |
611 | #define VC_ENHANCE 0x9714 |
612 | ||
3ce0a23d JG |
613 | #define VGT_CACHE_INVALIDATION 0x88C4 |
614 | #define CACHE_INVALIDATION(x) ((x)<<0) | |
615 | #define VC_ONLY 0 | |
616 | #define TC_ONLY 1 | |
617 | #define VC_AND_TC 2 | |
618 | #define AUTO_INVLD_EN(x) ((x) << 6) | |
619 | #define NO_AUTO 0 | |
620 | #define ES_AUTO 1 | |
621 | #define GS_AUTO 2 | |
622 | #define ES_AND_GS_AUTO 3 | |
623 | #define VGT_ES_PER_GS 0x88CC | |
624 | #define VGT_GS_PER_ES 0x88C8 | |
625 | #define VGT_GS_PER_VS 0x88E8 | |
626 | #define VGT_GS_VERTEX_REUSE 0x88D4 | |
627 | #define VGT_NUM_INSTANCES 0x8974 | |
628 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C | |
629 | #define DEALLOC_DIST_MASK 0x0000007F | |
630 | #define VGT_STRMOUT_EN 0x28AB0 | |
631 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 | |
632 | #define VTX_REUSE_DEPTH_MASK 0x000000FF | |
633 | ||
634 | #define VM_CONTEXT0_CNTL 0x1410 | |
635 | #define ENABLE_CONTEXT (1 << 0) | |
636 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) | |
637 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) | |
638 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C | |
639 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C | |
640 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C | |
641 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 | |
642 | #define VM_L2_CNTL 0x1400 | |
643 | #define ENABLE_L2_CACHE (1 << 0) | |
644 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) | |
645 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) | |
646 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) | |
647 | #define VM_L2_CNTL2 0x1404 | |
648 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) | |
649 | #define INVALIDATE_L2_CACHE (1 << 1) | |
650 | #define VM_L2_CNTL3 0x1408 | |
651 | #define BANK_SELECT(x) ((x) << 0) | |
652 | #define CACHE_UPDATE_MODE(x) ((x) << 6) | |
653 | #define VM_L2_STATUS 0x140C | |
654 | #define L2_BUSY (1 << 0) | |
655 | ||
656 | #define WAIT_UNTIL 0x8040 | |
657 | ||
4d75658b AD |
658 | /* async DMA */ |
659 | #define DMA_RB_RPTR 0xd008 | |
660 | #define DMA_RB_WPTR 0xd00c | |
661 | ||
662 | /* async DMA packets */ | |
663 | #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ | |
664 | (((t) & 0x1) << 23) | \ | |
665 | (((s) & 0x1) << 22) | \ | |
666 | (((n) & 0xFFFF) << 0)) | |
667 | /* async DMA Packet types */ | |
668 | #define DMA_PACKET_WRITE 0x2 | |
669 | #define DMA_PACKET_COPY 0x3 | |
670 | #define DMA_PACKET_INDIRECT_BUFFER 0x4 | |
671 | #define DMA_PACKET_SEMAPHORE 0x5 | |
672 | #define DMA_PACKET_FENCE 0x6 | |
673 | #define DMA_PACKET_TRAP 0x7 | |
674 | #define DMA_PACKET_CONSTANT_FILL 0xd | |
675 | #define DMA_PACKET_NOP 0xf | |
676 | ||
677 | ||
bcc1c2a1 AD |
678 | #define SRBM_STATUS 0x0E50 |
679 | ||
3a2a67aa AD |
680 | /* DCE 3.2 HDMI */ |
681 | #define HDMI_CONTROL 0x7400 | |
682 | # define HDMI_KEEPOUT_MODE (1 << 0) | |
683 | # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ | |
684 | # define HDMI_ERROR_ACK (1 << 8) | |
685 | # define HDMI_ERROR_MASK (1 << 9) | |
686 | #define HDMI_STATUS 0x7404 | |
687 | # define HDMI_ACTIVE_AVMUTE (1 << 0) | |
688 | # define HDMI_AUDIO_PACKET_ERROR (1 << 16) | |
689 | # define HDMI_VBI_PACKET_ERROR (1 << 20) | |
690 | #define HDMI_AUDIO_PACKET_CONTROL 0x7408 | |
691 | # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) | |
692 | # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) | |
693 | #define HDMI_ACR_PACKET_CONTROL 0x740c | |
694 | # define HDMI_ACR_SEND (1 << 0) | |
695 | # define HDMI_ACR_CONT (1 << 1) | |
696 | # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) | |
697 | # define HDMI_ACR_HW 0 | |
698 | # define HDMI_ACR_32 1 | |
699 | # define HDMI_ACR_44 2 | |
700 | # define HDMI_ACR_48 3 | |
701 | # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ | |
702 | # define HDMI_ACR_AUTO_SEND (1 << 12) | |
703 | #define HDMI_VBI_PACKET_CONTROL 0x7410 | |
704 | # define HDMI_NULL_SEND (1 << 0) | |
705 | # define HDMI_GC_SEND (1 << 4) | |
706 | # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ | |
707 | #define HDMI_INFOFRAME_CONTROL0 0x7414 | |
708 | # define HDMI_AVI_INFO_SEND (1 << 0) | |
709 | # define HDMI_AVI_INFO_CONT (1 << 1) | |
710 | # define HDMI_AUDIO_INFO_SEND (1 << 4) | |
711 | # define HDMI_AUDIO_INFO_CONT (1 << 5) | |
712 | # define HDMI_MPEG_INFO_SEND (1 << 8) | |
713 | # define HDMI_MPEG_INFO_CONT (1 << 9) | |
714 | #define HDMI_INFOFRAME_CONTROL1 0x7418 | |
715 | # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) | |
716 | # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) | |
717 | # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) | |
718 | #define HDMI_GENERIC_PACKET_CONTROL 0x741c | |
719 | # define HDMI_GENERIC0_SEND (1 << 0) | |
720 | # define HDMI_GENERIC0_CONT (1 << 1) | |
721 | # define HDMI_GENERIC1_SEND (1 << 4) | |
722 | # define HDMI_GENERIC1_CONT (1 << 5) | |
723 | # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) | |
724 | # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) | |
725 | #define HDMI_GC 0x7428 | |
726 | # define HDMI_GC_AVMUTE (1 << 0) | |
727 | #define AFMT_AUDIO_PACKET_CONTROL2 0x742c | |
728 | # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) | |
729 | # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) | |
730 | # define AFMT_60958_CS_SOURCE (1 << 4) | |
731 | # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) | |
732 | # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) | |
733 | #define AFMT_AVI_INFO0 0x7454 | |
734 | # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
735 | # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) | |
736 | # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) | |
737 | # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) | |
738 | # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) | |
739 | # define AFMT_AVI_INFO_Y_RGB 0 | |
740 | # define AFMT_AVI_INFO_Y_YCBCR422 1 | |
741 | # define AFMT_AVI_INFO_Y_YCBCR444 2 | |
742 | # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) | |
743 | # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) | |
744 | # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) | |
745 | # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) | |
746 | # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) | |
747 | # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) | |
748 | # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) | |
749 | # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) | |
750 | # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) | |
751 | # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) | |
752 | #define AFMT_AVI_INFO1 0x7458 | |
753 | # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ | |
754 | # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ | |
755 | # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) | |
756 | #define AFMT_AVI_INFO2 0x745c | |
757 | # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) | |
758 | # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) | |
759 | #define AFMT_AVI_INFO3 0x7460 | |
760 | # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) | |
761 | # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) | |
762 | #define AFMT_MPEG_INFO0 0x7464 | |
763 | # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
764 | # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) | |
765 | # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) | |
766 | # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) | |
767 | #define AFMT_MPEG_INFO1 0x7468 | |
768 | # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) | |
769 | # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) | |
770 | # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) | |
771 | #define AFMT_GENERIC0_HDR 0x746c | |
772 | #define AFMT_GENERIC0_0 0x7470 | |
773 | #define AFMT_GENERIC0_1 0x7474 | |
774 | #define AFMT_GENERIC0_2 0x7478 | |
775 | #define AFMT_GENERIC0_3 0x747c | |
776 | #define AFMT_GENERIC0_4 0x7480 | |
777 | #define AFMT_GENERIC0_5 0x7484 | |
778 | #define AFMT_GENERIC0_6 0x7488 | |
779 | #define AFMT_GENERIC1_HDR 0x748c | |
780 | #define AFMT_GENERIC1_0 0x7490 | |
781 | #define AFMT_GENERIC1_1 0x7494 | |
782 | #define AFMT_GENERIC1_2 0x7498 | |
783 | #define AFMT_GENERIC1_3 0x749c | |
784 | #define AFMT_GENERIC1_4 0x74a0 | |
785 | #define AFMT_GENERIC1_5 0x74a4 | |
786 | #define AFMT_GENERIC1_6 0x74a8 | |
787 | #define HDMI_ACR_32_0 0x74ac | |
788 | # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) | |
789 | #define HDMI_ACR_32_1 0x74b0 | |
790 | # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) | |
791 | #define HDMI_ACR_44_0 0x74b4 | |
792 | # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) | |
793 | #define HDMI_ACR_44_1 0x74b8 | |
794 | # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) | |
795 | #define HDMI_ACR_48_0 0x74bc | |
796 | # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) | |
797 | #define HDMI_ACR_48_1 0x74c0 | |
798 | # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) | |
799 | #define HDMI_ACR_STATUS_0 0x74c4 | |
800 | #define HDMI_ACR_STATUS_1 0x74c8 | |
801 | #define AFMT_AUDIO_INFO0 0x74cc | |
802 | # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
803 | # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) | |
804 | # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) | |
805 | #define AFMT_AUDIO_INFO1 0x74d0 | |
806 | # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) | |
807 | # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) | |
808 | # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) | |
809 | # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) | |
810 | #define AFMT_60958_0 0x74d4 | |
811 | # define AFMT_60958_CS_A(x) (((x) & 1) << 0) | |
812 | # define AFMT_60958_CS_B(x) (((x) & 1) << 1) | |
813 | # define AFMT_60958_CS_C(x) (((x) & 1) << 2) | |
814 | # define AFMT_60958_CS_D(x) (((x) & 3) << 3) | |
815 | # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) | |
816 | # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) | |
817 | # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) | |
818 | # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) | |
819 | # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) | |
820 | # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) | |
821 | #define AFMT_60958_1 0x74d8 | |
822 | # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) | |
823 | # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) | |
824 | # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) | |
825 | # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) | |
826 | # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) | |
827 | #define AFMT_AUDIO_CRC_CONTROL 0x74dc | |
828 | # define AFMT_AUDIO_CRC_EN (1 << 0) | |
829 | #define AFMT_RAMP_CONTROL0 0x74e0 | |
830 | # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) | |
831 | # define AFMT_RAMP_DATA_SIGN (1 << 31) | |
832 | #define AFMT_RAMP_CONTROL1 0x74e4 | |
833 | # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) | |
834 | # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) | |
835 | #define AFMT_RAMP_CONTROL2 0x74e8 | |
836 | # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) | |
837 | #define AFMT_RAMP_CONTROL3 0x74ec | |
838 | # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) | |
839 | #define AFMT_60958_2 0x74f0 | |
840 | # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) | |
841 | # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) | |
842 | # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) | |
843 | # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) | |
844 | # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) | |
845 | # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) | |
846 | #define AFMT_STATUS 0x7600 | |
847 | # define AFMT_AUDIO_ENABLE (1 << 4) | |
848 | # define AFMT_AZ_FORMAT_WTRIG (1 << 28) | |
849 | # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) | |
850 | # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) | |
851 | #define AFMT_AUDIO_PACKET_CONTROL 0x7604 | |
852 | # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) | |
853 | # define AFMT_AUDIO_TEST_EN (1 << 12) | |
854 | # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) | |
855 | # define AFMT_60958_CS_UPDATE (1 << 26) | |
856 | # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) | |
857 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) | |
858 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) | |
859 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) | |
860 | #define AFMT_VBI_PACKET_CONTROL 0x7608 | |
861 | # define AFMT_GENERIC0_UPDATE (1 << 2) | |
862 | #define AFMT_INFOFRAME_CONTROL0 0x760c | |
d592fca9 | 863 | # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */ |
3a2a67aa AD |
864 | # define AFMT_AUDIO_INFO_UPDATE (1 << 7) |
865 | # define AFMT_MPEG_INFO_UPDATE (1 << 10) | |
866 | #define AFMT_GENERIC0_7 0x7610 | |
867 | /* second instance starts at 0x7800 */ | |
868 | #define HDMI_OFFSET0 (0x7400 - 0x7400) | |
869 | #define HDMI_OFFSET1 (0x7800 - 0x7400) | |
870 | ||
fbed600a AD |
871 | /* DCE3.2 ELD audio interface */ |
872 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */ | |
873 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */ | |
874 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */ | |
875 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */ | |
876 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */ | |
877 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */ | |
878 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */ | |
879 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */ | |
880 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */ | |
881 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */ | |
882 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */ | |
883 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */ | |
884 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */ | |
885 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */ | |
886 | # define MAX_CHANNELS(x) (((x) & 0x7) << 0) | |
887 | /* max channels minus one. 7 = 8 channels */ | |
888 | # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) | |
889 | # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) | |
890 | # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ | |
891 | /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO | |
892 | * bit0 = 32 kHz | |
893 | * bit1 = 44.1 kHz | |
894 | * bit2 = 48 kHz | |
895 | * bit3 = 88.2 kHz | |
896 | * bit4 = 96 kHz | |
897 | * bit5 = 176.4 kHz | |
898 | * bit6 = 192 kHz | |
899 | */ | |
900 | ||
901 | #define AZ_HOT_PLUG_CONTROL 0x7300 | |
902 | # define AZ_FORCE_CODEC_WAKE (1 << 0) | |
903 | # define PIN0_JACK_DETECTION_ENABLE (1 << 4) | |
904 | # define PIN1_JACK_DETECTION_ENABLE (1 << 5) | |
905 | # define PIN2_JACK_DETECTION_ENABLE (1 << 6) | |
906 | # define PIN3_JACK_DETECTION_ENABLE (1 << 7) | |
907 | # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) | |
908 | # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) | |
909 | # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) | |
910 | # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) | |
911 | # define CODEC_HOT_PLUG_ENABLE (1 << 12) | |
912 | # define PIN0_AUDIO_ENABLED (1 << 24) | |
913 | # define PIN1_AUDIO_ENABLED (1 << 25) | |
914 | # define PIN2_AUDIO_ENABLED (1 << 26) | |
915 | # define PIN3_AUDIO_ENABLED (1 << 27) | |
916 | # define AUDIO_ENABLED (1 << 31) | |
917 | ||
918 | ||
6f34be50 AD |
919 | #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 |
920 | #define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 | |
921 | #define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 | |
922 | #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 | |
923 | #define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c | |
924 | #define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c | |
925 | ||
66229b20 AD |
926 | /* PCIE indirect regs */ |
927 | #define PCIE_P_CNTL 0x40 | |
928 | # define P_PLL_PWRDN_IN_L1L23 (1 << 3) | |
929 | # define P_PLL_BUF_PDNB (1 << 4) | |
930 | # define P_PLL_PDNB (1 << 9) | |
931 | # define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12) | |
932 | /* PCIE PORT regs */ | |
933 | #define PCIE_LC_CNTL 0xa0 | |
934 | # define LC_L0S_INACTIVITY(x) ((x) << 8) | |
935 | # define LC_L0S_INACTIVITY_MASK (0xf << 8) | |
936 | # define LC_L0S_INACTIVITY_SHIFT 8 | |
937 | # define LC_L1_INACTIVITY(x) ((x) << 12) | |
938 | # define LC_L1_INACTIVITY_MASK (0xf << 12) | |
939 | # define LC_L1_INACTIVITY_SHIFT 12 | |
940 | # define LC_PMI_TO_L1_DIS (1 << 16) | |
941 | # define LC_ASPM_TO_L1_DIS (1 << 24) | |
9e46a48d AD |
942 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
943 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ | |
944 | # define LC_LINK_WIDTH_SHIFT 0 | |
945 | # define LC_LINK_WIDTH_MASK 0x7 | |
946 | # define LC_LINK_WIDTH_X0 0 | |
947 | # define LC_LINK_WIDTH_X1 1 | |
948 | # define LC_LINK_WIDTH_X2 2 | |
949 | # define LC_LINK_WIDTH_X4 3 | |
950 | # define LC_LINK_WIDTH_X8 4 | |
951 | # define LC_LINK_WIDTH_X16 6 | |
952 | # define LC_LINK_WIDTH_RD_SHIFT 4 | |
953 | # define LC_LINK_WIDTH_RD_MASK 0x70 | |
954 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) | |
955 | # define LC_RECONFIG_NOW (1 << 8) | |
956 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) | |
957 | # define LC_RENEGOTIATE_EN (1 << 10) | |
958 | # define LC_SHORT_RECONFIG_EN (1 << 11) | |
959 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) | |
960 | # define LC_UPCONFIGURE_DIS (1 << 13) | |
961 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ | |
962 | # define LC_GEN2_EN_STRAP (1 << 0) | |
963 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) | |
964 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) | |
965 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) | |
966 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) | |
967 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 | |
968 | # define LC_CURRENT_DATA_RATE (1 << 11) | |
66229b20 AD |
969 | # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) |
970 | # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) | |
971 | # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 | |
9e46a48d AD |
972 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
973 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) | |
974 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) | |
975 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) | |
976 | #define MM_CFGREGS_CNTL 0x544c | |
977 | # define MM_WR_TO_CFG_EN (1 << 3) | |
978 | #define LINK_CNTL2 0x88 /* F0 */ | |
979 | # define TARGET_LINK_SPEED_MASK (0xf << 0) | |
980 | # define SELECTABLE_DEEMPHASIS (1 << 6) | |
981 | ||
e409b128 CK |
982 | /* |
983 | * PM4 | |
984 | */ | |
985 | #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ | |
986 | (((reg) >> 2) & 0xFFFF) | \ | |
987 | ((n) & 0x3FFF) << 16) | |
988 | #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ | |
989 | (((op) & 0xFF) << 8) | \ | |
990 | ((n) & 0x3FFF) << 16) | |
991 | ||
f2ba57b5 | 992 | /* UVD */ |
013ead48 CK |
993 | #define UVD_SEMA_ADDR_LOW 0xef00 |
994 | #define UVD_SEMA_ADDR_HIGH 0xef04 | |
995 | #define UVD_SEMA_CMD 0xef08 | |
e409b128 CK |
996 | #define UVD_GPCOM_VCPU_CMD 0xef0c |
997 | #define UVD_GPCOM_VCPU_DATA0 0xef10 | |
998 | #define UVD_GPCOM_VCPU_DATA1 0xef14 | |
999 | ||
f2ba57b5 CK |
1000 | #define UVD_LMI_EXT40_ADDR 0xf498 |
1001 | #define UVD_VCPU_CHIP_ID 0xf4d4 | |
1002 | #define UVD_VCPU_CACHE_OFFSET0 0xf4d8 | |
1003 | #define UVD_VCPU_CACHE_SIZE0 0xf4dc | |
1004 | #define UVD_VCPU_CACHE_OFFSET1 0xf4e0 | |
1005 | #define UVD_VCPU_CACHE_SIZE1 0xf4e4 | |
1006 | #define UVD_VCPU_CACHE_OFFSET2 0xf4e8 | |
1007 | #define UVD_VCPU_CACHE_SIZE2 0xf4ec | |
1008 | #define UVD_LMI_ADDR_EXT 0xf594 | |
1009 | ||
1010 | #define UVD_RBC_RB_RPTR 0xf690 | |
1011 | #define UVD_RBC_RB_WPTR 0xf694 | |
1012 | ||
e409b128 CK |
1013 | #define UVD_CONTEXT_ID 0xf6f4 |
1014 | ||
3ce0a23d | 1015 | #endif |