]>
Commit | Line | Data |
---|---|---|
43b3cd99 AD |
1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #ifndef SI_H | |
25 | #define SI_H | |
26 | ||
1a8ca750 AD |
27 | #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 |
28 | ||
29 | #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 | |
30 | #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 | |
31 | ||
2539eb02 CK |
32 | /* discrete uvd clocks */ |
33 | #define CG_UPLL_FUNC_CNTL 0x634 | |
34 | # define UPLL_RESET_MASK 0x00000001 | |
35 | # define UPLL_SLEEP_MASK 0x00000002 | |
36 | # define UPLL_BYPASS_EN_MASK 0x00000004 | |
37 | # define UPLL_CTLREQ_MASK 0x00000008 | |
38 | # define UPLL_VCO_MODE_MASK 0x00000600 | |
39 | # define UPLL_REF_DIV_MASK 0x001F0000 | |
40 | # define UPLL_CTLACK_MASK 0x40000000 | |
41 | # define UPLL_CTLACK2_MASK 0x80000000 | |
42 | #define CG_UPLL_FUNC_CNTL_2 0x638 | |
43 | # define UPLL_PDIV_A(x) ((x) << 0) | |
44 | # define UPLL_PDIV_A_MASK 0x0000007F | |
45 | # define UPLL_PDIV_B(x) ((x) << 8) | |
46 | # define UPLL_PDIV_B_MASK 0x00007F00 | |
47 | # define VCLK_SRC_SEL(x) ((x) << 20) | |
48 | # define VCLK_SRC_SEL_MASK 0x01F00000 | |
49 | # define DCLK_SRC_SEL(x) ((x) << 25) | |
50 | # define DCLK_SRC_SEL_MASK 0x3E000000 | |
51 | #define CG_UPLL_FUNC_CNTL_3 0x63C | |
52 | # define UPLL_FB_DIV(x) ((x) << 0) | |
53 | # define UPLL_FB_DIV_MASK 0x01FFFFFF | |
54 | #define CG_UPLL_FUNC_CNTL_4 0x644 | |
55 | # define UPLL_SPARE_ISPARE9 0x00020000 | |
56 | #define CG_UPLL_FUNC_CNTL_5 0x648 | |
57 | # define RESET_ANTI_MUX_MASK 0x00000200 | |
58 | #define CG_UPLL_SPREAD_SPECTRUM 0x650 | |
59 | # define SSEN_MASK 0x00000001 | |
60 | ||
1bd47d2e AD |
61 | #define CG_MULT_THERMAL_STATUS 0x714 |
62 | #define ASIC_MAX_TEMP(x) ((x) << 0) | |
63 | #define ASIC_MAX_TEMP_MASK 0x000001ff | |
64 | #define ASIC_MAX_TEMP_SHIFT 0 | |
65 | #define CTF_TEMP(x) ((x) << 9) | |
66 | #define CTF_TEMP_MASK 0x0003fe00 | |
67 | #define CTF_TEMP_SHIFT 9 | |
68 | ||
0a96d72b AD |
69 | #define SI_MAX_SH_GPRS 256 |
70 | #define SI_MAX_TEMP_GPRS 16 | |
71 | #define SI_MAX_SH_THREADS 256 | |
72 | #define SI_MAX_SH_STACK_ENTRIES 4096 | |
73 | #define SI_MAX_FRC_EOV_CNT 16384 | |
74 | #define SI_MAX_BACKENDS 8 | |
75 | #define SI_MAX_BACKENDS_MASK 0xFF | |
76 | #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F | |
77 | #define SI_MAX_SIMDS 12 | |
78 | #define SI_MAX_SIMDS_MASK 0x0FFF | |
79 | #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF | |
80 | #define SI_MAX_PIPES 8 | |
81 | #define SI_MAX_PIPES_MASK 0xFF | |
82 | #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F | |
83 | #define SI_MAX_LDS_NUM 0xFFFF | |
84 | #define SI_MAX_TCC 16 | |
85 | #define SI_MAX_TCC_MASK 0xFFFF | |
86 | ||
d2800ee5 AD |
87 | #define VGA_HDP_CONTROL 0x328 |
88 | #define VGA_MEMORY_DISABLE (1 << 4) | |
89 | ||
454d2e2a AD |
90 | #define CG_CLKPIN_CNTL 0x660 |
91 | # define XTALIN_DIVIDE (1 << 1) | |
92 | #define CG_CLKPIN_CNTL_2 0x664 | |
93 | # define MUX_TCLK_TO_XCLK (1 << 8) | |
94 | ||
0a96d72b AD |
95 | #define DMIF_ADDR_CONFIG 0xBD4 |
96 | ||
7c1c7c18 AD |
97 | #define DMIF_ADDR_CALC 0xC00 |
98 | ||
c476dde2 | 99 | #define SRBM_STATUS 0xE50 |
014bb209 AD |
100 | #define GRBM_RQ_PENDING (1 << 5) |
101 | #define VMC_BUSY (1 << 8) | |
102 | #define MCB_BUSY (1 << 9) | |
103 | #define MCB_NON_DISPLAY_BUSY (1 << 10) | |
104 | #define MCC_BUSY (1 << 11) | |
105 | #define MCD_BUSY (1 << 12) | |
106 | #define SEM_BUSY (1 << 14) | |
107 | #define IH_BUSY (1 << 17) | |
c476dde2 | 108 | |
64c56e8c JG |
109 | #define SRBM_SOFT_RESET 0x0E60 |
110 | #define SOFT_RESET_BIF (1 << 1) | |
111 | #define SOFT_RESET_DC (1 << 5) | |
112 | #define SOFT_RESET_DMA1 (1 << 6) | |
113 | #define SOFT_RESET_GRBM (1 << 8) | |
114 | #define SOFT_RESET_HDP (1 << 9) | |
115 | #define SOFT_RESET_IH (1 << 10) | |
116 | #define SOFT_RESET_MC (1 << 11) | |
117 | #define SOFT_RESET_ROM (1 << 14) | |
118 | #define SOFT_RESET_SEM (1 << 15) | |
119 | #define SOFT_RESET_VMC (1 << 17) | |
120 | #define SOFT_RESET_DMA (1 << 20) | |
121 | #define SOFT_RESET_TST (1 << 21) | |
122 | #define SOFT_RESET_REGBB (1 << 22) | |
123 | #define SOFT_RESET_ORB (1 << 23) | |
124 | ||
0a96d72b AD |
125 | #define CC_SYS_RB_BACKEND_DISABLE 0xe80 |
126 | #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 | |
127 | ||
014bb209 AD |
128 | #define SRBM_STATUS2 0x0EC4 |
129 | #define DMA_BUSY (1 << 5) | |
130 | #define DMA1_BUSY (1 << 6) | |
131 | ||
d2800ee5 AD |
132 | #define VM_L2_CNTL 0x1400 |
133 | #define ENABLE_L2_CACHE (1 << 0) | |
134 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) | |
135 | #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) | |
136 | #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) | |
137 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) | |
138 | #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) | |
139 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) | |
140 | #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) | |
141 | #define VM_L2_CNTL2 0x1404 | |
142 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) | |
143 | #define INVALIDATE_L2_CACHE (1 << 1) | |
144 | #define INVALIDATE_CACHE_MODE(x) ((x) << 26) | |
145 | #define INVALIDATE_PTE_AND_PDE_CACHES 0 | |
146 | #define INVALIDATE_ONLY_PTE_CACHES 1 | |
147 | #define INVALIDATE_ONLY_PDE_CACHES 2 | |
148 | #define VM_L2_CNTL3 0x1408 | |
149 | #define BANK_SELECT(x) ((x) << 0) | |
150 | #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) | |
151 | #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) | |
152 | #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) | |
153 | #define VM_L2_STATUS 0x140C | |
154 | #define L2_BUSY (1 << 0) | |
155 | #define VM_CONTEXT0_CNTL 0x1410 | |
156 | #define ENABLE_CONTEXT (1 << 0) | |
157 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) | |
ae133a11 | 158 | #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) |
d2800ee5 | 159 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
ae133a11 CK |
160 | #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) |
161 | #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) | |
162 | #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) | |
163 | #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) | |
164 | #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) | |
165 | #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) | |
166 | #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) | |
167 | #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) | |
168 | #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) | |
169 | #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) | |
d2800ee5 AD |
170 | #define VM_CONTEXT1_CNTL 0x1414 |
171 | #define VM_CONTEXT0_CNTL2 0x1430 | |
172 | #define VM_CONTEXT1_CNTL2 0x1434 | |
173 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 | |
174 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c | |
175 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 | |
176 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 | |
177 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 | |
178 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c | |
179 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 | |
180 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 | |
181 | ||
ae133a11 CK |
182 | #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC |
183 | #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC | |
184 | ||
d2800ee5 AD |
185 | #define VM_INVALIDATE_REQUEST 0x1478 |
186 | #define VM_INVALIDATE_RESPONSE 0x147c | |
187 | ||
188 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 | |
189 | #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c | |
190 | ||
191 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c | |
192 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 | |
193 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 | |
194 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 | |
195 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c | |
196 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 | |
197 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 | |
198 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 | |
199 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c | |
200 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 | |
201 | ||
202 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C | |
203 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 | |
204 | ||
43b3cd99 AD |
205 | #define MC_SHARED_CHMAP 0x2004 |
206 | #define NOOFCHAN_SHIFT 12 | |
207 | #define NOOFCHAN_MASK 0x0000f000 | |
0a96d72b AD |
208 | #define MC_SHARED_CHREMAP 0x2008 |
209 | ||
d2800ee5 AD |
210 | #define MC_VM_FB_LOCATION 0x2024 |
211 | #define MC_VM_AGP_TOP 0x2028 | |
212 | #define MC_VM_AGP_BOT 0x202C | |
213 | #define MC_VM_AGP_BASE 0x2030 | |
214 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 | |
215 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 | |
216 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C | |
217 | ||
218 | #define MC_VM_MX_L1_TLB_CNTL 0x2064 | |
219 | #define ENABLE_L1_TLB (1 << 0) | |
220 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) | |
221 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) | |
222 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) | |
223 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) | |
224 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) | |
225 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) | |
226 | #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) | |
227 | ||
8b074dd6 AD |
228 | #define MC_SHARED_BLACKOUT_CNTL 0x20ac |
229 | ||
0a96d72b AD |
230 | #define MC_ARB_RAMCFG 0x2760 |
231 | #define NOOFBANK_SHIFT 0 | |
232 | #define NOOFBANK_MASK 0x00000003 | |
233 | #define NOOFRANK_SHIFT 2 | |
234 | #define NOOFRANK_MASK 0x00000004 | |
235 | #define NOOFROWS_SHIFT 3 | |
236 | #define NOOFROWS_MASK 0x00000038 | |
237 | #define NOOFCOLS_SHIFT 6 | |
238 | #define NOOFCOLS_MASK 0x000000C0 | |
239 | #define CHANSIZE_SHIFT 8 | |
240 | #define CHANSIZE_MASK 0x00000100 | |
d2800ee5 | 241 | #define CHANSIZE_OVERRIDE (1 << 11) |
0a96d72b AD |
242 | #define NOOFGROUPS_SHIFT 12 |
243 | #define NOOFGROUPS_MASK 0x00001000 | |
244 | ||
8b074dd6 AD |
245 | #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 |
246 | #define TRAIN_DONE_D0 (1 << 30) | |
247 | #define TRAIN_DONE_D1 (1 << 31) | |
248 | ||
249 | #define MC_SEQ_SUP_CNTL 0x28c8 | |
250 | #define RUN_MASK (1 << 0) | |
251 | #define MC_SEQ_SUP_PGM 0x28cc | |
252 | ||
253 | #define MC_IO_PAD_CNTL_D0 0x29d0 | |
254 | #define MEM_FALL_OUT_CMD (1 << 8) | |
255 | ||
256 | #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 | |
257 | #define MC_SEQ_IO_DEBUG_DATA 0x2a48 | |
258 | ||
0a96d72b | 259 | #define HDP_HOST_PATH_CNTL 0x2C00 |
d2800ee5 AD |
260 | #define HDP_NONSURFACE_BASE 0x2C04 |
261 | #define HDP_NONSURFACE_INFO 0x2C08 | |
262 | #define HDP_NONSURFACE_SIZE 0x2C0C | |
0a96d72b AD |
263 | |
264 | #define HDP_ADDR_CONFIG 0x2F48 | |
265 | #define HDP_MISC_CNTL 0x2F4C | |
266 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) | |
267 | ||
25a857fb AD |
268 | #define IH_RB_CNTL 0x3e00 |
269 | # define IH_RB_ENABLE (1 << 0) | |
270 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ | |
271 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) | |
272 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) | |
273 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ | |
274 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) | |
275 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) | |
276 | #define IH_RB_BASE 0x3e04 | |
277 | #define IH_RB_RPTR 0x3e08 | |
278 | #define IH_RB_WPTR 0x3e0c | |
279 | # define RB_OVERFLOW (1 << 0) | |
280 | # define WPTR_OFFSET_MASK 0x3fffc | |
281 | #define IH_RB_WPTR_ADDR_HI 0x3e10 | |
282 | #define IH_RB_WPTR_ADDR_LO 0x3e14 | |
283 | #define IH_CNTL 0x3e18 | |
284 | # define ENABLE_INTR (1 << 0) | |
285 | # define IH_MC_SWAP(x) ((x) << 1) | |
286 | # define IH_MC_SWAP_NONE 0 | |
287 | # define IH_MC_SWAP_16BIT 1 | |
288 | # define IH_MC_SWAP_32BIT 2 | |
289 | # define IH_MC_SWAP_64BIT 3 | |
290 | # define RPTR_REARM (1 << 4) | |
291 | # define MC_WRREQ_CREDIT(x) ((x) << 15) | |
292 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) | |
293 | # define MC_VMID(x) ((x) << 25) | |
294 | ||
d2800ee5 AD |
295 | #define CONFIG_MEMSIZE 0x5428 |
296 | ||
25a857fb AD |
297 | #define INTERRUPT_CNTL 0x5468 |
298 | # define IH_DUMMY_RD_OVERRIDE (1 << 0) | |
299 | # define IH_DUMMY_RD_EN (1 << 1) | |
300 | # define IH_REQ_NONSNOOP_EN (1 << 3) | |
301 | # define GEN_IH_INT_EN (1 << 8) | |
302 | #define INTERRUPT_CNTL2 0x546c | |
303 | ||
d2800ee5 AD |
304 | #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
305 | ||
0a96d72b AD |
306 | #define BIF_FB_EN 0x5490 |
307 | #define FB_READ_EN (1 << 0) | |
308 | #define FB_WRITE_EN (1 << 1) | |
43b3cd99 | 309 | |
d2800ee5 AD |
310 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
311 | ||
43b3cd99 AD |
312 | #define DC_LB_MEMORY_SPLIT 0x6b0c |
313 | #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) | |
314 | ||
315 | #define PRIORITY_A_CNT 0x6b18 | |
316 | #define PRIORITY_MARK_MASK 0x7fff | |
317 | #define PRIORITY_OFF (1 << 16) | |
318 | #define PRIORITY_ALWAYS_ON (1 << 20) | |
319 | #define PRIORITY_B_CNT 0x6b1c | |
320 | ||
321 | #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 | |
322 | # define LATENCY_WATERMARK_MASK(x) ((x) << 16) | |
323 | #define DPG_PIPE_LATENCY_CONTROL 0x6ccc | |
324 | # define LATENCY_LOW_WATERMARK(x) ((x) << 0) | |
325 | # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) | |
326 | ||
25a857fb AD |
327 | /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ |
328 | #define VLINE_STATUS 0x6bb8 | |
329 | # define VLINE_OCCURRED (1 << 0) | |
330 | # define VLINE_ACK (1 << 4) | |
331 | # define VLINE_STAT (1 << 12) | |
332 | # define VLINE_INTERRUPT (1 << 16) | |
333 | # define VLINE_INTERRUPT_TYPE (1 << 17) | |
334 | /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ | |
335 | #define VBLANK_STATUS 0x6bbc | |
336 | # define VBLANK_OCCURRED (1 << 0) | |
337 | # define VBLANK_ACK (1 << 4) | |
338 | # define VBLANK_STAT (1 << 12) | |
339 | # define VBLANK_INTERRUPT (1 << 16) | |
340 | # define VBLANK_INTERRUPT_TYPE (1 << 17) | |
341 | ||
342 | /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ | |
343 | #define INT_MASK 0x6b40 | |
344 | # define VBLANK_INT_MASK (1 << 0) | |
345 | # define VLINE_INT_MASK (1 << 4) | |
346 | ||
347 | #define DISP_INTERRUPT_STATUS 0x60f4 | |
348 | # define LB_D1_VLINE_INTERRUPT (1 << 2) | |
349 | # define LB_D1_VBLANK_INTERRUPT (1 << 3) | |
350 | # define DC_HPD1_INTERRUPT (1 << 17) | |
351 | # define DC_HPD1_RX_INTERRUPT (1 << 18) | |
352 | # define DACA_AUTODETECT_INTERRUPT (1 << 22) | |
353 | # define DACB_AUTODETECT_INTERRUPT (1 << 23) | |
354 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) | |
355 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) | |
356 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 | |
357 | # define LB_D2_VLINE_INTERRUPT (1 << 2) | |
358 | # define LB_D2_VBLANK_INTERRUPT (1 << 3) | |
359 | # define DC_HPD2_INTERRUPT (1 << 17) | |
360 | # define DC_HPD2_RX_INTERRUPT (1 << 18) | |
361 | # define DISP_TIMER_INTERRUPT (1 << 24) | |
362 | #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc | |
363 | # define LB_D3_VLINE_INTERRUPT (1 << 2) | |
364 | # define LB_D3_VBLANK_INTERRUPT (1 << 3) | |
365 | # define DC_HPD3_INTERRUPT (1 << 17) | |
366 | # define DC_HPD3_RX_INTERRUPT (1 << 18) | |
367 | #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 | |
368 | # define LB_D4_VLINE_INTERRUPT (1 << 2) | |
369 | # define LB_D4_VBLANK_INTERRUPT (1 << 3) | |
370 | # define DC_HPD4_INTERRUPT (1 << 17) | |
371 | # define DC_HPD4_RX_INTERRUPT (1 << 18) | |
372 | #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c | |
373 | # define LB_D5_VLINE_INTERRUPT (1 << 2) | |
374 | # define LB_D5_VBLANK_INTERRUPT (1 << 3) | |
375 | # define DC_HPD5_INTERRUPT (1 << 17) | |
376 | # define DC_HPD5_RX_INTERRUPT (1 << 18) | |
377 | #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 | |
378 | # define LB_D6_VLINE_INTERRUPT (1 << 2) | |
379 | # define LB_D6_VBLANK_INTERRUPT (1 << 3) | |
380 | # define DC_HPD6_INTERRUPT (1 << 17) | |
381 | # define DC_HPD6_RX_INTERRUPT (1 << 18) | |
382 | ||
383 | /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ | |
384 | #define GRPH_INT_STATUS 0x6858 | |
385 | # define GRPH_PFLIP_INT_OCCURRED (1 << 0) | |
386 | # define GRPH_PFLIP_INT_CLEAR (1 << 8) | |
387 | /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ | |
388 | #define GRPH_INT_CONTROL 0x685c | |
389 | # define GRPH_PFLIP_INT_MASK (1 << 0) | |
390 | # define GRPH_PFLIP_INT_TYPE (1 << 8) | |
391 | ||
392 | #define DACA_AUTODETECT_INT_CONTROL 0x66c8 | |
393 | ||
394 | #define DC_HPD1_INT_STATUS 0x601c | |
395 | #define DC_HPD2_INT_STATUS 0x6028 | |
396 | #define DC_HPD3_INT_STATUS 0x6034 | |
397 | #define DC_HPD4_INT_STATUS 0x6040 | |
398 | #define DC_HPD5_INT_STATUS 0x604c | |
399 | #define DC_HPD6_INT_STATUS 0x6058 | |
400 | # define DC_HPDx_INT_STATUS (1 << 0) | |
401 | # define DC_HPDx_SENSE (1 << 1) | |
402 | # define DC_HPDx_RX_INT_STATUS (1 << 8) | |
403 | ||
404 | #define DC_HPD1_INT_CONTROL 0x6020 | |
405 | #define DC_HPD2_INT_CONTROL 0x602c | |
406 | #define DC_HPD3_INT_CONTROL 0x6038 | |
407 | #define DC_HPD4_INT_CONTROL 0x6044 | |
408 | #define DC_HPD5_INT_CONTROL 0x6050 | |
409 | #define DC_HPD6_INT_CONTROL 0x605c | |
410 | # define DC_HPDx_INT_ACK (1 << 0) | |
411 | # define DC_HPDx_INT_POLARITY (1 << 8) | |
412 | # define DC_HPDx_INT_EN (1 << 16) | |
413 | # define DC_HPDx_RX_INT_ACK (1 << 20) | |
414 | # define DC_HPDx_RX_INT_EN (1 << 24) | |
415 | ||
416 | #define DC_HPD1_CONTROL 0x6024 | |
417 | #define DC_HPD2_CONTROL 0x6030 | |
418 | #define DC_HPD3_CONTROL 0x603c | |
419 | #define DC_HPD4_CONTROL 0x6048 | |
420 | #define DC_HPD5_CONTROL 0x6054 | |
421 | #define DC_HPD6_CONTROL 0x6060 | |
422 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) | |
423 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) | |
424 | # define DC_HPDx_EN (1 << 28) | |
425 | ||
426 | /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ | |
427 | #define CRTC_STATUS_FRAME_COUNT 0x6e98 | |
428 | ||
0a96d72b AD |
429 | #define GRBM_CNTL 0x8000 |
430 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | |
431 | ||
c476dde2 AD |
432 | #define GRBM_STATUS2 0x8008 |
433 | #define RLC_RQ_PENDING (1 << 0) | |
434 | #define RLC_BUSY (1 << 8) | |
435 | #define TC_BUSY (1 << 9) | |
436 | ||
437 | #define GRBM_STATUS 0x8010 | |
438 | #define CMDFIFO_AVAIL_MASK 0x0000000F | |
439 | #define RING2_RQ_PENDING (1 << 4) | |
440 | #define SRBM_RQ_PENDING (1 << 5) | |
441 | #define RING1_RQ_PENDING (1 << 6) | |
442 | #define CF_RQ_PENDING (1 << 7) | |
443 | #define PF_RQ_PENDING (1 << 8) | |
444 | #define GDS_DMA_RQ_PENDING (1 << 9) | |
445 | #define GRBM_EE_BUSY (1 << 10) | |
446 | #define DB_CLEAN (1 << 12) | |
447 | #define CB_CLEAN (1 << 13) | |
448 | #define TA_BUSY (1 << 14) | |
449 | #define GDS_BUSY (1 << 15) | |
450 | #define VGT_BUSY (1 << 17) | |
451 | #define IA_BUSY_NO_DMA (1 << 18) | |
452 | #define IA_BUSY (1 << 19) | |
453 | #define SX_BUSY (1 << 20) | |
454 | #define SPI_BUSY (1 << 22) | |
455 | #define BCI_BUSY (1 << 23) | |
456 | #define SC_BUSY (1 << 24) | |
457 | #define PA_BUSY (1 << 25) | |
458 | #define DB_BUSY (1 << 26) | |
459 | #define CP_COHERENCY_BUSY (1 << 28) | |
460 | #define CP_BUSY (1 << 29) | |
461 | #define CB_BUSY (1 << 30) | |
462 | #define GUI_ACTIVE (1 << 31) | |
463 | #define GRBM_STATUS_SE0 0x8014 | |
464 | #define GRBM_STATUS_SE1 0x8018 | |
465 | #define SE_DB_CLEAN (1 << 1) | |
466 | #define SE_CB_CLEAN (1 << 2) | |
467 | #define SE_BCI_BUSY (1 << 22) | |
468 | #define SE_VGT_BUSY (1 << 23) | |
469 | #define SE_PA_BUSY (1 << 24) | |
470 | #define SE_TA_BUSY (1 << 25) | |
471 | #define SE_SX_BUSY (1 << 26) | |
472 | #define SE_SPI_BUSY (1 << 27) | |
473 | #define SE_SC_BUSY (1 << 29) | |
474 | #define SE_DB_BUSY (1 << 30) | |
475 | #define SE_CB_BUSY (1 << 31) | |
476 | ||
477 | #define GRBM_SOFT_RESET 0x8020 | |
478 | #define SOFT_RESET_CP (1 << 0) | |
479 | #define SOFT_RESET_CB (1 << 1) | |
480 | #define SOFT_RESET_RLC (1 << 2) | |
481 | #define SOFT_RESET_DB (1 << 3) | |
482 | #define SOFT_RESET_GDS (1 << 4) | |
483 | #define SOFT_RESET_PA (1 << 5) | |
484 | #define SOFT_RESET_SC (1 << 6) | |
485 | #define SOFT_RESET_BCI (1 << 7) | |
486 | #define SOFT_RESET_SPI (1 << 8) | |
487 | #define SOFT_RESET_SX (1 << 10) | |
488 | #define SOFT_RESET_TC (1 << 11) | |
489 | #define SOFT_RESET_TA (1 << 12) | |
490 | #define SOFT_RESET_VGT (1 << 14) | |
491 | #define SOFT_RESET_IA (1 << 15) | |
492 | ||
498dd8b3 | 493 | #define GRBM_GFX_INDEX 0x802C |
1a8ca750 AD |
494 | #define INSTANCE_INDEX(x) ((x) << 0) |
495 | #define SH_INDEX(x) ((x) << 8) | |
496 | #define SE_INDEX(x) ((x) << 16) | |
497 | #define SH_BROADCAST_WRITES (1 << 29) | |
498 | #define INSTANCE_BROADCAST_WRITES (1 << 30) | |
499 | #define SE_BROADCAST_WRITES (1 << 31) | |
498dd8b3 | 500 | |
25a857fb AD |
501 | #define GRBM_INT_CNTL 0x8060 |
502 | # define RDERR_INT_ENABLE (1 << 0) | |
503 | # define GUI_IDLE_INT_ENABLE (1 << 19) | |
504 | ||
f418b88a | 505 | #define CP_STRMOUT_CNTL 0x84FC |
48c0c902 AD |
506 | #define SCRATCH_REG0 0x8500 |
507 | #define SCRATCH_REG1 0x8504 | |
508 | #define SCRATCH_REG2 0x8508 | |
509 | #define SCRATCH_REG3 0x850C | |
510 | #define SCRATCH_REG4 0x8510 | |
511 | #define SCRATCH_REG5 0x8514 | |
512 | #define SCRATCH_REG6 0x8518 | |
513 | #define SCRATCH_REG7 0x851C | |
514 | ||
515 | #define SCRATCH_UMSK 0x8540 | |
516 | #define SCRATCH_ADDR 0x8544 | |
517 | ||
518 | #define CP_SEM_WAIT_TIMER 0x85BC | |
519 | ||
520 | #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 | |
521 | ||
c476dde2 AD |
522 | #define CP_ME_CNTL 0x86D8 |
523 | #define CP_CE_HALT (1 << 24) | |
524 | #define CP_PFP_HALT (1 << 26) | |
525 | #define CP_ME_HALT (1 << 28) | |
526 | ||
2ece2e8b AD |
527 | #define CP_COHER_CNTL2 0x85E8 |
528 | ||
48c0c902 AD |
529 | #define CP_RB2_RPTR 0x86f8 |
530 | #define CP_RB1_RPTR 0x86fc | |
c476dde2 | 531 | #define CP_RB0_RPTR 0x8700 |
48c0c902 | 532 | #define CP_RB_WPTR_DELAY 0x8704 |
c476dde2 | 533 | |
0a96d72b AD |
534 | #define CP_QUEUE_THRESHOLDS 0x8760 |
535 | #define ROQ_IB1_START(x) ((x) << 0) | |
536 | #define ROQ_IB2_START(x) ((x) << 8) | |
537 | #define CP_MEQ_THRESHOLDS 0x8764 | |
538 | #define MEQ1_START(x) ((x) << 0) | |
539 | #define MEQ2_START(x) ((x) << 8) | |
540 | ||
541 | #define CP_PERFMON_CNTL 0x87FC | |
542 | ||
498dd8b3 AD |
543 | #define VGT_VTX_VECT_EJECT_REG 0x88B0 |
544 | ||
0a96d72b AD |
545 | #define VGT_CACHE_INVALIDATION 0x88C4 |
546 | #define CACHE_INVALIDATION(x) ((x) << 0) | |
547 | #define VC_ONLY 0 | |
548 | #define TC_ONLY 1 | |
549 | #define VC_AND_TC 2 | |
550 | #define AUTO_INVLD_EN(x) ((x) << 6) | |
551 | #define NO_AUTO 0 | |
552 | #define ES_AUTO 1 | |
553 | #define GS_AUTO 2 | |
554 | #define ES_AND_GS_AUTO 3 | |
498dd8b3 AD |
555 | #define VGT_ESGS_RING_SIZE 0x88C8 |
556 | #define VGT_GSVS_RING_SIZE 0x88CC | |
0a96d72b AD |
557 | |
558 | #define VGT_GS_VERTEX_REUSE 0x88D4 | |
559 | ||
498dd8b3 AD |
560 | #define VGT_PRIMITIVE_TYPE 0x8958 |
561 | #define VGT_INDEX_TYPE 0x895C | |
562 | ||
563 | #define VGT_NUM_INDICES 0x8970 | |
0a96d72b AD |
564 | #define VGT_NUM_INSTANCES 0x8974 |
565 | ||
498dd8b3 AD |
566 | #define VGT_TF_RING_SIZE 0x8988 |
567 | ||
568 | #define VGT_HS_OFFCHIP_PARAM 0x89B0 | |
569 | ||
570 | #define VGT_TF_MEMORY_BASE 0x89B8 | |
571 | ||
0a96d72b | 572 | #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc |
1a8ca750 AD |
573 | #define INACTIVE_CUS_MASK 0xFFFF0000 |
574 | #define INACTIVE_CUS_SHIFT 16 | |
0a96d72b AD |
575 | #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 |
576 | ||
577 | #define PA_CL_ENHANCE 0x8A14 | |
578 | #define CLIP_VTX_REORDER_ENA (1 << 0) | |
579 | #define NUM_CLIP_SEQ(x) ((x) << 1) | |
580 | ||
498dd8b3 AD |
581 | #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 |
582 | ||
0a96d72b AD |
583 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 |
584 | ||
585 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 | |
586 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) | |
587 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) | |
588 | ||
589 | #define PA_SC_FIFO_SIZE 0x8BCC | |
590 | #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) | |
591 | #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) | |
592 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) | |
593 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) | |
594 | ||
498dd8b3 AD |
595 | #define PA_SC_ENHANCE 0x8BF0 |
596 | ||
0a96d72b AD |
597 | #define SQ_CONFIG 0x8C00 |
598 | ||
498dd8b3 AD |
599 | #define SQC_CACHES 0x8C08 |
600 | ||
0a96d72b AD |
601 | #define SX_DEBUG_1 0x9060 |
602 | ||
498dd8b3 AD |
603 | #define SPI_STATIC_THREAD_MGMT_1 0x90E0 |
604 | #define SPI_STATIC_THREAD_MGMT_2 0x90E4 | |
605 | #define SPI_STATIC_THREAD_MGMT_3 0x90E8 | |
606 | #define SPI_PS_MAX_WAVE_ID 0x90EC | |
607 | ||
608 | #define SPI_CONFIG_CNTL 0x9100 | |
609 | ||
0a96d72b AD |
610 | #define SPI_CONFIG_CNTL_1 0x913C |
611 | #define VTX_DONE_DELAY(x) ((x) << 0) | |
612 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) | |
613 | ||
614 | #define CGTS_TCC_DISABLE 0x9148 | |
615 | #define CGTS_USER_TCC_DISABLE 0x914C | |
616 | #define TCC_DISABLE_MASK 0xFFFF0000 | |
617 | #define TCC_DISABLE_SHIFT 16 | |
618 | ||
498dd8b3 AD |
619 | #define TA_CNTL_AUX 0x9508 |
620 | ||
0a96d72b AD |
621 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
622 | #define BACKEND_DISABLE(x) ((x) << 16) | |
623 | #define GB_ADDR_CONFIG 0x98F8 | |
624 | #define NUM_PIPES(x) ((x) << 0) | |
625 | #define NUM_PIPES_MASK 0x00000007 | |
626 | #define NUM_PIPES_SHIFT 0 | |
627 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) | |
628 | #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 | |
629 | #define PIPE_INTERLEAVE_SIZE_SHIFT 4 | |
630 | #define NUM_SHADER_ENGINES(x) ((x) << 12) | |
631 | #define NUM_SHADER_ENGINES_MASK 0x00003000 | |
632 | #define NUM_SHADER_ENGINES_SHIFT 12 | |
633 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) | |
634 | #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 | |
635 | #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 | |
636 | #define NUM_GPUS(x) ((x) << 20) | |
637 | #define NUM_GPUS_MASK 0x00700000 | |
638 | #define NUM_GPUS_SHIFT 20 | |
639 | #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) | |
640 | #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 | |
641 | #define MULTI_GPU_TILE_SIZE_SHIFT 24 | |
642 | #define ROW_SIZE(x) ((x) << 28) | |
643 | #define ROW_SIZE_MASK 0x30000000 | |
644 | #define ROW_SIZE_SHIFT 28 | |
645 | ||
646 | #define GB_TILE_MODE0 0x9910 | |
647 | # define MICRO_TILE_MODE(x) ((x) << 0) | |
648 | # define ADDR_SURF_DISPLAY_MICRO_TILING 0 | |
649 | # define ADDR_SURF_THIN_MICRO_TILING 1 | |
650 | # define ADDR_SURF_DEPTH_MICRO_TILING 2 | |
651 | # define ARRAY_MODE(x) ((x) << 2) | |
652 | # define ARRAY_LINEAR_GENERAL 0 | |
653 | # define ARRAY_LINEAR_ALIGNED 1 | |
654 | # define ARRAY_1D_TILED_THIN1 2 | |
655 | # define ARRAY_2D_TILED_THIN1 4 | |
656 | # define PIPE_CONFIG(x) ((x) << 6) | |
657 | # define ADDR_SURF_P2 0 | |
658 | # define ADDR_SURF_P4_8x16 4 | |
659 | # define ADDR_SURF_P4_16x16 5 | |
660 | # define ADDR_SURF_P4_16x32 6 | |
661 | # define ADDR_SURF_P4_32x32 7 | |
662 | # define ADDR_SURF_P8_16x16_8x16 8 | |
663 | # define ADDR_SURF_P8_16x32_8x16 9 | |
664 | # define ADDR_SURF_P8_32x32_8x16 10 | |
665 | # define ADDR_SURF_P8_16x32_16x16 11 | |
666 | # define ADDR_SURF_P8_32x32_16x16 12 | |
667 | # define ADDR_SURF_P8_32x32_16x32 13 | |
668 | # define ADDR_SURF_P8_32x64_32x32 14 | |
669 | # define TILE_SPLIT(x) ((x) << 11) | |
670 | # define ADDR_SURF_TILE_SPLIT_64B 0 | |
671 | # define ADDR_SURF_TILE_SPLIT_128B 1 | |
672 | # define ADDR_SURF_TILE_SPLIT_256B 2 | |
673 | # define ADDR_SURF_TILE_SPLIT_512B 3 | |
674 | # define ADDR_SURF_TILE_SPLIT_1KB 4 | |
675 | # define ADDR_SURF_TILE_SPLIT_2KB 5 | |
676 | # define ADDR_SURF_TILE_SPLIT_4KB 6 | |
677 | # define BANK_WIDTH(x) ((x) << 14) | |
678 | # define ADDR_SURF_BANK_WIDTH_1 0 | |
679 | # define ADDR_SURF_BANK_WIDTH_2 1 | |
680 | # define ADDR_SURF_BANK_WIDTH_4 2 | |
681 | # define ADDR_SURF_BANK_WIDTH_8 3 | |
682 | # define BANK_HEIGHT(x) ((x) << 16) | |
683 | # define ADDR_SURF_BANK_HEIGHT_1 0 | |
684 | # define ADDR_SURF_BANK_HEIGHT_2 1 | |
685 | # define ADDR_SURF_BANK_HEIGHT_4 2 | |
686 | # define ADDR_SURF_BANK_HEIGHT_8 3 | |
687 | # define MACRO_TILE_ASPECT(x) ((x) << 18) | |
688 | # define ADDR_SURF_MACRO_ASPECT_1 0 | |
689 | # define ADDR_SURF_MACRO_ASPECT_2 1 | |
690 | # define ADDR_SURF_MACRO_ASPECT_4 2 | |
691 | # define ADDR_SURF_MACRO_ASPECT_8 3 | |
692 | # define NUM_BANKS(x) ((x) << 20) | |
693 | # define ADDR_SURF_2_BANK 0 | |
694 | # define ADDR_SURF_4_BANK 1 | |
695 | # define ADDR_SURF_8_BANK 2 | |
696 | # define ADDR_SURF_16_BANK 3 | |
697 | ||
698 | #define CB_PERFCOUNTER0_SELECT0 0x9a20 | |
699 | #define CB_PERFCOUNTER0_SELECT1 0x9a24 | |
700 | #define CB_PERFCOUNTER1_SELECT0 0x9a28 | |
701 | #define CB_PERFCOUNTER1_SELECT1 0x9a2c | |
702 | #define CB_PERFCOUNTER2_SELECT0 0x9a30 | |
703 | #define CB_PERFCOUNTER2_SELECT1 0x9a34 | |
704 | #define CB_PERFCOUNTER3_SELECT0 0x9a38 | |
705 | #define CB_PERFCOUNTER3_SELECT1 0x9a3c | |
706 | ||
707 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C | |
708 | #define BACKEND_DISABLE_MASK 0x00FF0000 | |
709 | #define BACKEND_DISABLE_SHIFT 16 | |
710 | ||
711 | #define TCP_CHAN_STEER_LO 0xac0c | |
712 | #define TCP_CHAN_STEER_HI 0xac10 | |
713 | ||
48c0c902 AD |
714 | #define CP_RB0_BASE 0xC100 |
715 | #define CP_RB0_CNTL 0xC104 | |
716 | #define RB_BUFSZ(x) ((x) << 0) | |
717 | #define RB_BLKSZ(x) ((x) << 8) | |
718 | #define BUF_SWAP_32BIT (2 << 16) | |
719 | #define RB_NO_UPDATE (1 << 27) | |
720 | #define RB_RPTR_WR_ENA (1 << 31) | |
721 | ||
722 | #define CP_RB0_RPTR_ADDR 0xC10C | |
723 | #define CP_RB0_RPTR_ADDR_HI 0xC110 | |
724 | #define CP_RB0_WPTR 0xC114 | |
725 | ||
726 | #define CP_PFP_UCODE_ADDR 0xC150 | |
727 | #define CP_PFP_UCODE_DATA 0xC154 | |
728 | #define CP_ME_RAM_RADDR 0xC158 | |
729 | #define CP_ME_RAM_WADDR 0xC15C | |
730 | #define CP_ME_RAM_DATA 0xC160 | |
731 | ||
732 | #define CP_CE_UCODE_ADDR 0xC168 | |
733 | #define CP_CE_UCODE_DATA 0xC16C | |
734 | ||
735 | #define CP_RB1_BASE 0xC180 | |
736 | #define CP_RB1_CNTL 0xC184 | |
737 | #define CP_RB1_RPTR_ADDR 0xC188 | |
738 | #define CP_RB1_RPTR_ADDR_HI 0xC18C | |
739 | #define CP_RB1_WPTR 0xC190 | |
740 | #define CP_RB2_BASE 0xC194 | |
741 | #define CP_RB2_CNTL 0xC198 | |
742 | #define CP_RB2_RPTR_ADDR 0xC19C | |
743 | #define CP_RB2_RPTR_ADDR_HI 0xC1A0 | |
744 | #define CP_RB2_WPTR 0xC1A4 | |
25a857fb AD |
745 | #define CP_INT_CNTL_RING0 0xC1A8 |
746 | #define CP_INT_CNTL_RING1 0xC1AC | |
747 | #define CP_INT_CNTL_RING2 0xC1B0 | |
748 | # define CNTX_BUSY_INT_ENABLE (1 << 19) | |
749 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) | |
750 | # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) | |
751 | # define TIME_STAMP_INT_ENABLE (1 << 26) | |
752 | # define CP_RINGID2_INT_ENABLE (1 << 29) | |
753 | # define CP_RINGID1_INT_ENABLE (1 << 30) | |
754 | # define CP_RINGID0_INT_ENABLE (1 << 31) | |
755 | #define CP_INT_STATUS_RING0 0xC1B4 | |
756 | #define CP_INT_STATUS_RING1 0xC1B8 | |
757 | #define CP_INT_STATUS_RING2 0xC1BC | |
758 | # define WAIT_MEM_SEM_INT_STAT (1 << 21) | |
759 | # define TIME_STAMP_INT_STAT (1 << 26) | |
760 | # define CP_RINGID2_INT_STAT (1 << 29) | |
761 | # define CP_RINGID1_INT_STAT (1 << 30) | |
762 | # define CP_RINGID0_INT_STAT (1 << 31) | |
48c0c902 AD |
763 | |
764 | #define CP_DEBUG 0xC1FC | |
765 | ||
347e7592 AD |
766 | #define RLC_CNTL 0xC300 |
767 | # define RLC_ENABLE (1 << 0) | |
768 | #define RLC_RL_BASE 0xC304 | |
769 | #define RLC_RL_SIZE 0xC308 | |
770 | #define RLC_LB_CNTL 0xC30C | |
771 | #define RLC_SAVE_AND_RESTORE_BASE 0xC310 | |
772 | #define RLC_LB_CNTR_MAX 0xC314 | |
773 | #define RLC_LB_CNTR_INIT 0xC318 | |
774 | ||
775 | #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 | |
776 | ||
777 | #define RLC_UCODE_ADDR 0xC32C | |
778 | #define RLC_UCODE_DATA 0xC330 | |
779 | ||
6759a0a7 MO |
780 | #define RLC_GPU_CLOCK_COUNT_LSB 0xC338 |
781 | #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C | |
782 | #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340 | |
347e7592 AD |
783 | #define RLC_MC_CNTL 0xC344 |
784 | #define RLC_UCODE_CNTL 0xC348 | |
785 | ||
1a8ca750 AD |
786 | #define PA_SC_RASTER_CONFIG 0x28350 |
787 | # define RASTER_CONFIG_RB_MAP_0 0 | |
788 | # define RASTER_CONFIG_RB_MAP_1 1 | |
789 | # define RASTER_CONFIG_RB_MAP_2 2 | |
790 | # define RASTER_CONFIG_RB_MAP_3 3 | |
791 | ||
2ece2e8b AD |
792 | #define VGT_EVENT_INITIATOR 0x28a90 |
793 | # define SAMPLE_STREAMOUTSTATS1 (1 << 0) | |
794 | # define SAMPLE_STREAMOUTSTATS2 (2 << 0) | |
795 | # define SAMPLE_STREAMOUTSTATS3 (3 << 0) | |
796 | # define CACHE_FLUSH_TS (4 << 0) | |
797 | # define CACHE_FLUSH (6 << 0) | |
798 | # define CS_PARTIAL_FLUSH (7 << 0) | |
799 | # define VGT_STREAMOUT_RESET (10 << 0) | |
800 | # define END_OF_PIPE_INCR_DE (11 << 0) | |
801 | # define END_OF_PIPE_IB_END (12 << 0) | |
802 | # define RST_PIX_CNT (13 << 0) | |
803 | # define VS_PARTIAL_FLUSH (15 << 0) | |
804 | # define PS_PARTIAL_FLUSH (16 << 0) | |
805 | # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) | |
806 | # define ZPASS_DONE (21 << 0) | |
807 | # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) | |
808 | # define PERFCOUNTER_START (23 << 0) | |
809 | # define PERFCOUNTER_STOP (24 << 0) | |
810 | # define PIPELINESTAT_START (25 << 0) | |
811 | # define PIPELINESTAT_STOP (26 << 0) | |
812 | # define PERFCOUNTER_SAMPLE (27 << 0) | |
813 | # define SAMPLE_PIPELINESTAT (30 << 0) | |
814 | # define SAMPLE_STREAMOUTSTATS (32 << 0) | |
815 | # define RESET_VTX_CNT (33 << 0) | |
816 | # define VGT_FLUSH (36 << 0) | |
817 | # define BOTTOM_OF_PIPE_TS (40 << 0) | |
818 | # define DB_CACHE_FLUSH_AND_INV (42 << 0) | |
819 | # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) | |
820 | # define FLUSH_AND_INV_DB_META (44 << 0) | |
821 | # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) | |
822 | # define FLUSH_AND_INV_CB_META (46 << 0) | |
823 | # define CS_DONE (47 << 0) | |
824 | # define PS_DONE (48 << 0) | |
825 | # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) | |
826 | # define THREAD_TRACE_START (51 << 0) | |
827 | # define THREAD_TRACE_STOP (52 << 0) | |
828 | # define THREAD_TRACE_FLUSH (54 << 0) | |
829 | # define THREAD_TRACE_FINISH (55 << 0) | |
830 | ||
f2ba57b5 CK |
831 | /* |
832 | * UVD | |
833 | */ | |
834 | #define UVD_RBC_RB_RPTR 0xF690 | |
835 | #define UVD_RBC_RB_WPTR 0xF694 | |
836 | ||
d2800ee5 AD |
837 | /* |
838 | * PM4 | |
839 | */ | |
4e872ae2 | 840 | #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ |
d2800ee5 AD |
841 | (((reg) >> 2) & 0xFFFF) | \ |
842 | ((n) & 0x3FFF) << 16) | |
843 | #define CP_PACKET2 0x80000000 | |
844 | #define PACKET2_PAD_SHIFT 0 | |
845 | #define PACKET2_PAD_MASK (0x3fffffff << 0) | |
846 | ||
847 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) | |
848 | ||
4e872ae2 | 849 | #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ |
d2800ee5 AD |
850 | (((op) & 0xFF) << 8) | \ |
851 | ((n) & 0x3FFF) << 16) | |
852 | ||
48c0c902 AD |
853 | #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) |
854 | ||
d2800ee5 AD |
855 | /* Packet 3 types */ |
856 | #define PACKET3_NOP 0x10 | |
857 | #define PACKET3_SET_BASE 0x11 | |
858 | #define PACKET3_BASE_INDEX(x) ((x) << 0) | |
859 | #define GDS_PARTITION_BASE 2 | |
860 | #define CE_PARTITION_BASE 3 | |
861 | #define PACKET3_CLEAR_STATE 0x12 | |
862 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 | |
863 | #define PACKET3_DISPATCH_DIRECT 0x15 | |
864 | #define PACKET3_DISPATCH_INDIRECT 0x16 | |
865 | #define PACKET3_ALLOC_GDS 0x1B | |
866 | #define PACKET3_WRITE_GDS_RAM 0x1C | |
867 | #define PACKET3_ATOMIC_GDS 0x1D | |
868 | #define PACKET3_ATOMIC 0x1E | |
869 | #define PACKET3_OCCLUSION_QUERY 0x1F | |
870 | #define PACKET3_SET_PREDICATION 0x20 | |
871 | #define PACKET3_REG_RMW 0x21 | |
872 | #define PACKET3_COND_EXEC 0x22 | |
873 | #define PACKET3_PRED_EXEC 0x23 | |
874 | #define PACKET3_DRAW_INDIRECT 0x24 | |
875 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 | |
876 | #define PACKET3_INDEX_BASE 0x26 | |
877 | #define PACKET3_DRAW_INDEX_2 0x27 | |
878 | #define PACKET3_CONTEXT_CONTROL 0x28 | |
879 | #define PACKET3_INDEX_TYPE 0x2A | |
880 | #define PACKET3_DRAW_INDIRECT_MULTI 0x2C | |
881 | #define PACKET3_DRAW_INDEX_AUTO 0x2D | |
882 | #define PACKET3_DRAW_INDEX_IMMD 0x2E | |
883 | #define PACKET3_NUM_INSTANCES 0x2F | |
884 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 | |
885 | #define PACKET3_INDIRECT_BUFFER_CONST 0x31 | |
886 | #define PACKET3_INDIRECT_BUFFER 0x32 | |
887 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 | |
888 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 | |
889 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 | |
890 | #define PACKET3_WRITE_DATA 0x37 | |
76c44f2c AD |
891 | #define WRITE_DATA_DST_SEL(x) ((x) << 8) |
892 | /* 0 - register | |
893 | * 1 - memory (sync - via GRBM) | |
894 | * 2 - tc/l2 | |
895 | * 3 - gds | |
896 | * 4 - reserved | |
897 | * 5 - memory (async - direct) | |
898 | */ | |
899 | #define WR_ONE_ADDR (1 << 16) | |
900 | #define WR_CONFIRM (1 << 20) | |
901 | #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) | |
902 | /* 0 - me | |
903 | * 1 - pfp | |
904 | * 2 - ce | |
905 | */ | |
d2800ee5 AD |
906 | #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 |
907 | #define PACKET3_MEM_SEMAPHORE 0x39 | |
908 | #define PACKET3_MPEG_INDEX 0x3A | |
909 | #define PACKET3_COPY_DW 0x3B | |
910 | #define PACKET3_WAIT_REG_MEM 0x3C | |
911 | #define PACKET3_MEM_WRITE 0x3D | |
912 | #define PACKET3_COPY_DATA 0x40 | |
b997a8ba AD |
913 | #define PACKET3_CP_DMA 0x41 |
914 | /* 1. header | |
915 | * 2. SRC_ADDR_LO or DATA [31:0] | |
916 | * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | | |
917 | * SRC_ADDR_HI [7:0] | |
918 | * 4. DST_ADDR_LO [31:0] | |
919 | * 5. DST_ADDR_HI [7:0] | |
920 | * 6. COMMAND [30:21] | BYTE_COUNT [20:0] | |
921 | */ | |
922 | # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) | |
923 | /* 0 - SRC_ADDR | |
924 | * 1 - GDS | |
925 | */ | |
926 | # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) | |
927 | /* 0 - ME | |
928 | * 1 - PFP | |
929 | */ | |
930 | # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) | |
931 | /* 0 - SRC_ADDR | |
932 | * 1 - GDS | |
933 | * 2 - DATA | |
934 | */ | |
935 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) | |
936 | /* COMMAND */ | |
937 | # define PACKET3_CP_DMA_DIS_WC (1 << 21) | |
938 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) | |
939 | /* 0 - none | |
940 | * 1 - 8 in 16 | |
941 | * 2 - 8 in 32 | |
942 | * 3 - 8 in 64 | |
943 | */ | |
944 | # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) | |
945 | /* 0 - none | |
946 | * 1 - 8 in 16 | |
947 | * 2 - 8 in 32 | |
948 | * 3 - 8 in 64 | |
949 | */ | |
950 | # define PACKET3_CP_DMA_CMD_SAS (1 << 26) | |
951 | /* 0 - memory | |
952 | * 1 - register | |
953 | */ | |
954 | # define PACKET3_CP_DMA_CMD_DAS (1 << 27) | |
955 | /* 0 - memory | |
956 | * 1 - register | |
957 | */ | |
958 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) | |
959 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) | |
960 | # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) | |
d2800ee5 AD |
961 | #define PACKET3_PFP_SYNC_ME 0x42 |
962 | #define PACKET3_SURFACE_SYNC 0x43 | |
963 | # define PACKET3_DEST_BASE_0_ENA (1 << 0) | |
964 | # define PACKET3_DEST_BASE_1_ENA (1 << 1) | |
965 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | |
966 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) | |
967 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) | |
968 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) | |
969 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) | |
970 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) | |
971 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) | |
972 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) | |
973 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) | |
974 | # define PACKET3_DEST_BASE_2_ENA (1 << 19) | |
975 | # define PACKET3_DEST_BASE_3_ENA (1 << 21) | |
976 | # define PACKET3_TCL1_ACTION_ENA (1 << 22) | |
977 | # define PACKET3_TC_ACTION_ENA (1 << 23) | |
978 | # define PACKET3_CB_ACTION_ENA (1 << 25) | |
979 | # define PACKET3_DB_ACTION_ENA (1 << 26) | |
980 | # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) | |
981 | # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) | |
982 | #define PACKET3_ME_INITIALIZE 0x44 | |
983 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) | |
984 | #define PACKET3_COND_WRITE 0x45 | |
985 | #define PACKET3_EVENT_WRITE 0x46 | |
2ece2e8b AD |
986 | #define EVENT_TYPE(x) ((x) << 0) |
987 | #define EVENT_INDEX(x) ((x) << 8) | |
988 | /* 0 - any non-TS event | |
989 | * 1 - ZPASS_DONE | |
990 | * 2 - SAMPLE_PIPELINESTAT | |
991 | * 3 - SAMPLE_STREAMOUTSTAT* | |
992 | * 4 - *S_PARTIAL_FLUSH | |
993 | * 5 - EOP events | |
994 | * 6 - EOS events | |
995 | * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT | |
996 | */ | |
997 | #define INV_L2 (1 << 20) | |
998 | /* INV TC L2 cache when EVENT_INDEX = 7 */ | |
d2800ee5 | 999 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
2ece2e8b AD |
1000 | #define DATA_SEL(x) ((x) << 29) |
1001 | /* 0 - discard | |
1002 | * 1 - send low 32bit data | |
1003 | * 2 - send 64bit data | |
1004 | * 3 - send 64bit counter value | |
1005 | */ | |
1006 | #define INT_SEL(x) ((x) << 24) | |
1007 | /* 0 - none | |
1008 | * 1 - interrupt only (DATA_SEL = 0) | |
1009 | * 2 - interrupt when data write is confirmed | |
1010 | */ | |
d2800ee5 AD |
1011 | #define PACKET3_EVENT_WRITE_EOS 0x48 |
1012 | #define PACKET3_PREAMBLE_CNTL 0x4A | |
1013 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) | |
1014 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) | |
1015 | #define PACKET3_ONE_REG_WRITE 0x57 | |
1016 | #define PACKET3_LOAD_CONFIG_REG 0x5F | |
1017 | #define PACKET3_LOAD_CONTEXT_REG 0x60 | |
1018 | #define PACKET3_LOAD_SH_REG 0x61 | |
1019 | #define PACKET3_SET_CONFIG_REG 0x68 | |
1020 | #define PACKET3_SET_CONFIG_REG_START 0x00008000 | |
1021 | #define PACKET3_SET_CONFIG_REG_END 0x0000b000 | |
1022 | #define PACKET3_SET_CONTEXT_REG 0x69 | |
1023 | #define PACKET3_SET_CONTEXT_REG_START 0x00028000 | |
1024 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 | |
1025 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 | |
1026 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74 | |
1027 | #define PACKET3_SET_SH_REG 0x76 | |
1028 | #define PACKET3_SET_SH_REG_START 0x0000b000 | |
1029 | #define PACKET3_SET_SH_REG_END 0x0000c000 | |
1030 | #define PACKET3_SET_SH_REG_OFFSET 0x77 | |
1031 | #define PACKET3_ME_WRITE 0x7A | |
1032 | #define PACKET3_SCRATCH_RAM_WRITE 0x7D | |
1033 | #define PACKET3_SCRATCH_RAM_READ 0x7E | |
1034 | #define PACKET3_CE_WRITE 0x7F | |
1035 | #define PACKET3_LOAD_CONST_RAM 0x80 | |
1036 | #define PACKET3_WRITE_CONST_RAM 0x81 | |
1037 | #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 | |
1038 | #define PACKET3_DUMP_CONST_RAM 0x83 | |
1039 | #define PACKET3_INCREMENT_CE_COUNTER 0x84 | |
1040 | #define PACKET3_INCREMENT_DE_COUNTER 0x85 | |
1041 | #define PACKET3_WAIT_ON_CE_COUNTER 0x86 | |
1042 | #define PACKET3_WAIT_ON_DE_COUNTER 0x87 | |
1043 | #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 | |
1044 | #define PACKET3_SET_CE_DE_COUNTERS 0x89 | |
1045 | #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A | |
a85a7da4 | 1046 | #define PACKET3_SWITCH_BUFFER 0x8B |
0a96d72b | 1047 | |
8c5fd7ef AD |
1048 | /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ |
1049 | #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ | |
1050 | #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ | |
1051 | ||
1052 | #define DMA_RB_CNTL 0xd000 | |
1053 | # define DMA_RB_ENABLE (1 << 0) | |
1054 | # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ | |
1055 | # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ | |
1056 | # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) | |
1057 | # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ | |
1058 | # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ | |
1059 | #define DMA_RB_BASE 0xd004 | |
1060 | #define DMA_RB_RPTR 0xd008 | |
1061 | #define DMA_RB_WPTR 0xd00c | |
1062 | ||
1063 | #define DMA_RB_RPTR_ADDR_HI 0xd01c | |
1064 | #define DMA_RB_RPTR_ADDR_LO 0xd020 | |
1065 | ||
1066 | #define DMA_IB_CNTL 0xd024 | |
1067 | # define DMA_IB_ENABLE (1 << 0) | |
1068 | # define DMA_IB_SWAP_ENABLE (1 << 4) | |
1069 | #define DMA_IB_RPTR 0xd028 | |
1070 | #define DMA_CNTL 0xd02c | |
1071 | # define TRAP_ENABLE (1 << 0) | |
1072 | # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) | |
1073 | # define SEM_WAIT_INT_ENABLE (1 << 2) | |
1074 | # define DATA_SWAP_ENABLE (1 << 3) | |
1075 | # define FENCE_SWAP_ENABLE (1 << 4) | |
1076 | # define CTXEMPTY_INT_ENABLE (1 << 28) | |
eaaa6983 JG |
1077 | #define DMA_STATUS_REG 0xd034 |
1078 | # define DMA_IDLE (1 << 0) | |
8c5fd7ef AD |
1079 | #define DMA_TILING_CONFIG 0xd0b8 |
1080 | ||
1081 | #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ | |
1082 | (((b) & 0x1) << 26) | \ | |
1083 | (((t) & 0x1) << 23) | \ | |
1084 | (((s) & 0x1) << 22) | \ | |
1085 | (((n) & 0xFFFFF) << 0)) | |
deab48f1 AD |
1086 | |
1087 | #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ | |
1088 | (((vmid) & 0xF) << 20) | \ | |
1089 | (((n) & 0xFFFFF) << 0)) | |
1090 | ||
1091 | #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ | |
1092 | (1 << 26) | \ | |
1093 | (1 << 21) | \ | |
1094 | (((n) & 0xFFFFF) << 0)) | |
1095 | ||
8c5fd7ef AD |
1096 | /* async DMA Packet types */ |
1097 | #define DMA_PACKET_WRITE 0x2 | |
1098 | #define DMA_PACKET_COPY 0x3 | |
1099 | #define DMA_PACKET_INDIRECT_BUFFER 0x4 | |
1100 | #define DMA_PACKET_SEMAPHORE 0x5 | |
1101 | #define DMA_PACKET_FENCE 0x6 | |
1102 | #define DMA_PACKET_TRAP 0x7 | |
1103 | #define DMA_PACKET_SRBM_WRITE 0x9 | |
1104 | #define DMA_PACKET_CONSTANT_FILL 0xd | |
1105 | #define DMA_PACKET_NOP 0xf | |
1106 | ||
43b3cd99 | 1107 | #endif |