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Commit | Line | Data |
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2048e328 MY |
1 | /* |
2 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd | |
3 | * Author:Mark Yao <mark.yao@rock-chips.com> | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <drm/drm.h> | |
16 | #include <drm/drmP.h> | |
63ebb9fa | 17 | #include <drm/drm_atomic.h> |
2048e328 MY |
18 | #include <drm/drm_crtc.h> |
19 | #include <drm/drm_crtc_helper.h> | |
20 | #include <drm/drm_plane_helper.h> | |
21 | ||
22 | #include <linux/kernel.h> | |
00fe6148 | 23 | #include <linux/module.h> |
2048e328 MY |
24 | #include <linux/platform_device.h> |
25 | #include <linux/clk.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/component.h> | |
30 | ||
31 | #include <linux/reset.h> | |
32 | #include <linux/delay.h> | |
33 | ||
34 | #include "rockchip_drm_drv.h" | |
35 | #include "rockchip_drm_gem.h" | |
36 | #include "rockchip_drm_fb.h" | |
37 | #include "rockchip_drm_vop.h" | |
38 | ||
2048e328 MY |
39 | #define __REG_SET_RELAXED(x, off, mask, shift, v) \ |
40 | vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) | |
41 | #define __REG_SET_NORMAL(x, off, mask, shift, v) \ | |
42 | vop_mask_write(x, off, (mask) << shift, (v) << shift) | |
43 | ||
44 | #define REG_SET(x, base, reg, v, mode) \ | |
45 | __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) | |
dbb3d944 MY |
46 | #define REG_SET_MASK(x, base, reg, v, mode) \ |
47 | __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) | |
2048e328 MY |
48 | |
49 | #define VOP_WIN_SET(x, win, name, v) \ | |
50 | REG_SET(x, win->base, win->phy->name, v, RELAXED) | |
4c156c21 MY |
51 | #define VOP_SCL_SET(x, win, name, v) \ |
52 | REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) | |
2048e328 MY |
53 | #define VOP_CTRL_SET(x, name, v) \ |
54 | REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) | |
55 | ||
dbb3d944 MY |
56 | #define VOP_INTR_GET(vop, name) \ |
57 | vop_read_reg(vop, 0, &vop->data->ctrl->name) | |
58 | ||
59 | #define VOP_INTR_SET(vop, name, v) \ | |
60 | REG_SET(vop, 0, vop->data->intr->name, v, NORMAL) | |
61 | #define VOP_INTR_SET_TYPE(vop, name, type, v) \ | |
62 | do { \ | |
63 | int i, reg = 0; \ | |
64 | for (i = 0; i < vop->data->intr->nintrs; i++) { \ | |
65 | if (vop->data->intr->intrs[i] & type) \ | |
66 | reg |= (v) << i; \ | |
67 | } \ | |
68 | VOP_INTR_SET(vop, name, reg); \ | |
69 | } while (0) | |
70 | #define VOP_INTR_GET_TYPE(vop, name, type) \ | |
71 | vop_get_intr_type(vop, &vop->data->intr->name, type) | |
72 | ||
2048e328 MY |
73 | #define VOP_WIN_GET(x, win, name) \ |
74 | vop_read_reg(x, win->base, &win->phy->name) | |
75 | ||
76 | #define VOP_WIN_GET_YRGBADDR(vop, win) \ | |
77 | vop_readl(vop, win->base + win->phy->yrgb_mst.offset) | |
78 | ||
79 | #define to_vop(x) container_of(x, struct vop, crtc) | |
80 | #define to_vop_win(x) container_of(x, struct vop_win, base) | |
63ebb9fa | 81 | #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) |
2048e328 | 82 | |
63ebb9fa MY |
83 | struct vop_plane_state { |
84 | struct drm_plane_state base; | |
85 | int format; | |
86 | struct drm_rect src; | |
87 | struct drm_rect dest; | |
2048e328 | 88 | dma_addr_t yrgb_mst; |
63ebb9fa | 89 | bool enable; |
2048e328 MY |
90 | }; |
91 | ||
92 | struct vop_win { | |
93 | struct drm_plane base; | |
94 | const struct vop_win_data *data; | |
95 | struct vop *vop; | |
96 | ||
63ebb9fa | 97 | struct vop_plane_state state; |
2048e328 MY |
98 | }; |
99 | ||
100 | struct vop { | |
101 | struct drm_crtc crtc; | |
102 | struct device *dev; | |
103 | struct drm_device *drm_dev; | |
31e980c5 | 104 | bool is_enabled; |
2048e328 | 105 | |
2048e328 MY |
106 | /* mutex vsync_ work */ |
107 | struct mutex vsync_mutex; | |
108 | bool vsync_work_pending; | |
1067219b | 109 | struct completion dsp_hold_completion; |
63ebb9fa MY |
110 | struct completion wait_update_complete; |
111 | struct drm_pending_vblank_event *event; | |
2048e328 MY |
112 | |
113 | const struct vop_data *data; | |
114 | ||
115 | uint32_t *regsbak; | |
116 | void __iomem *regs; | |
117 | ||
118 | /* physical map length of vop register */ | |
119 | uint32_t len; | |
120 | ||
121 | /* one time only one process allowed to config the register */ | |
122 | spinlock_t reg_lock; | |
123 | /* lock vop irq reg */ | |
124 | spinlock_t irq_lock; | |
125 | ||
126 | unsigned int irq; | |
127 | ||
128 | /* vop AHP clk */ | |
129 | struct clk *hclk; | |
130 | /* vop dclk */ | |
131 | struct clk *dclk; | |
132 | /* vop share memory frequency */ | |
133 | struct clk *aclk; | |
134 | ||
135 | /* vop dclk reset */ | |
136 | struct reset_control *dclk_rst; | |
137 | ||
2048e328 MY |
138 | struct vop_win win[]; |
139 | }; | |
140 | ||
2048e328 MY |
141 | static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) |
142 | { | |
143 | writel(v, vop->regs + offset); | |
144 | vop->regsbak[offset >> 2] = v; | |
145 | } | |
146 | ||
147 | static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) | |
148 | { | |
149 | return readl(vop->regs + offset); | |
150 | } | |
151 | ||
152 | static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, | |
153 | const struct vop_reg *reg) | |
154 | { | |
155 | return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; | |
156 | } | |
157 | ||
2048e328 MY |
158 | static inline void vop_mask_write(struct vop *vop, uint32_t offset, |
159 | uint32_t mask, uint32_t v) | |
160 | { | |
161 | if (mask) { | |
162 | uint32_t cached_val = vop->regsbak[offset >> 2]; | |
163 | ||
164 | cached_val = (cached_val & ~mask) | v; | |
165 | writel(cached_val, vop->regs + offset); | |
166 | vop->regsbak[offset >> 2] = cached_val; | |
167 | } | |
168 | } | |
169 | ||
170 | static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, | |
171 | uint32_t mask, uint32_t v) | |
172 | { | |
173 | if (mask) { | |
174 | uint32_t cached_val = vop->regsbak[offset >> 2]; | |
175 | ||
176 | cached_val = (cached_val & ~mask) | v; | |
177 | writel_relaxed(cached_val, vop->regs + offset); | |
178 | vop->regsbak[offset >> 2] = cached_val; | |
179 | } | |
180 | } | |
181 | ||
dbb3d944 MY |
182 | static inline uint32_t vop_get_intr_type(struct vop *vop, |
183 | const struct vop_reg *reg, int type) | |
184 | { | |
185 | uint32_t i, ret = 0; | |
186 | uint32_t regs = vop_read_reg(vop, 0, reg); | |
187 | ||
188 | for (i = 0; i < vop->data->intr->nintrs; i++) { | |
189 | if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) | |
190 | ret |= vop->data->intr->intrs[i]; | |
191 | } | |
192 | ||
193 | return ret; | |
194 | } | |
195 | ||
0cf33fe3 MY |
196 | static inline void vop_cfg_done(struct vop *vop) |
197 | { | |
198 | VOP_CTRL_SET(vop, cfg_done, 1); | |
199 | } | |
200 | ||
85a359f2 TF |
201 | static bool has_rb_swapped(uint32_t format) |
202 | { | |
203 | switch (format) { | |
204 | case DRM_FORMAT_XBGR8888: | |
205 | case DRM_FORMAT_ABGR8888: | |
206 | case DRM_FORMAT_BGR888: | |
207 | case DRM_FORMAT_BGR565: | |
208 | return true; | |
209 | default: | |
210 | return false; | |
211 | } | |
212 | } | |
213 | ||
2048e328 MY |
214 | static enum vop_data_format vop_convert_format(uint32_t format) |
215 | { | |
216 | switch (format) { | |
217 | case DRM_FORMAT_XRGB8888: | |
218 | case DRM_FORMAT_ARGB8888: | |
85a359f2 TF |
219 | case DRM_FORMAT_XBGR8888: |
220 | case DRM_FORMAT_ABGR8888: | |
2048e328 MY |
221 | return VOP_FMT_ARGB8888; |
222 | case DRM_FORMAT_RGB888: | |
85a359f2 | 223 | case DRM_FORMAT_BGR888: |
2048e328 MY |
224 | return VOP_FMT_RGB888; |
225 | case DRM_FORMAT_RGB565: | |
85a359f2 | 226 | case DRM_FORMAT_BGR565: |
2048e328 MY |
227 | return VOP_FMT_RGB565; |
228 | case DRM_FORMAT_NV12: | |
229 | return VOP_FMT_YUV420SP; | |
230 | case DRM_FORMAT_NV16: | |
231 | return VOP_FMT_YUV422SP; | |
232 | case DRM_FORMAT_NV24: | |
233 | return VOP_FMT_YUV444SP; | |
234 | default: | |
235 | DRM_ERROR("unsupport format[%08x]\n", format); | |
236 | return -EINVAL; | |
237 | } | |
238 | } | |
239 | ||
84c7f8ca MY |
240 | static bool is_yuv_support(uint32_t format) |
241 | { | |
242 | switch (format) { | |
243 | case DRM_FORMAT_NV12: | |
244 | case DRM_FORMAT_NV16: | |
245 | case DRM_FORMAT_NV24: | |
246 | return true; | |
247 | default: | |
248 | return false; | |
249 | } | |
250 | } | |
251 | ||
2048e328 MY |
252 | static bool is_alpha_support(uint32_t format) |
253 | { | |
254 | switch (format) { | |
255 | case DRM_FORMAT_ARGB8888: | |
85a359f2 | 256 | case DRM_FORMAT_ABGR8888: |
2048e328 MY |
257 | return true; |
258 | default: | |
259 | return false; | |
260 | } | |
261 | } | |
262 | ||
4c156c21 MY |
263 | static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, |
264 | uint32_t dst, bool is_horizontal, | |
265 | int vsu_mode, int *vskiplines) | |
266 | { | |
267 | uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; | |
268 | ||
269 | if (is_horizontal) { | |
270 | if (mode == SCALE_UP) | |
271 | val = GET_SCL_FT_BIC(src, dst); | |
272 | else if (mode == SCALE_DOWN) | |
273 | val = GET_SCL_FT_BILI_DN(src, dst); | |
274 | } else { | |
275 | if (mode == SCALE_UP) { | |
276 | if (vsu_mode == SCALE_UP_BIL) | |
277 | val = GET_SCL_FT_BILI_UP(src, dst); | |
278 | else | |
279 | val = GET_SCL_FT_BIC(src, dst); | |
280 | } else if (mode == SCALE_DOWN) { | |
281 | if (vskiplines) { | |
282 | *vskiplines = scl_get_vskiplines(src, dst); | |
283 | val = scl_get_bili_dn_vskip(src, dst, | |
284 | *vskiplines); | |
285 | } else { | |
286 | val = GET_SCL_FT_BILI_DN(src, dst); | |
287 | } | |
288 | } | |
289 | } | |
290 | ||
291 | return val; | |
292 | } | |
293 | ||
294 | static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, | |
295 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, | |
296 | uint32_t dst_h, uint32_t pixel_format) | |
297 | { | |
298 | uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; | |
299 | uint16_t cbcr_hor_scl_mode = SCALE_NONE; | |
300 | uint16_t cbcr_ver_scl_mode = SCALE_NONE; | |
301 | int hsub = drm_format_horz_chroma_subsampling(pixel_format); | |
302 | int vsub = drm_format_vert_chroma_subsampling(pixel_format); | |
303 | bool is_yuv = is_yuv_support(pixel_format); | |
304 | uint16_t cbcr_src_w = src_w / hsub; | |
305 | uint16_t cbcr_src_h = src_h / vsub; | |
306 | uint16_t vsu_mode; | |
307 | uint16_t lb_mode; | |
308 | uint32_t val; | |
309 | int vskiplines; | |
310 | ||
311 | if (dst_w > 3840) { | |
312 | DRM_ERROR("Maximum destination width (3840) exceeded\n"); | |
313 | return; | |
314 | } | |
315 | ||
316 | yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); | |
317 | yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); | |
318 | ||
319 | if (is_yuv) { | |
320 | cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); | |
321 | cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); | |
322 | if (cbcr_hor_scl_mode == SCALE_DOWN) | |
323 | lb_mode = scl_vop_cal_lb_mode(dst_w, true); | |
324 | else | |
325 | lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); | |
326 | } else { | |
327 | if (yrgb_hor_scl_mode == SCALE_DOWN) | |
328 | lb_mode = scl_vop_cal_lb_mode(dst_w, false); | |
329 | else | |
330 | lb_mode = scl_vop_cal_lb_mode(src_w, false); | |
331 | } | |
332 | ||
333 | VOP_SCL_SET(vop, win, lb_mode, lb_mode); | |
334 | if (lb_mode == LB_RGB_3840X2) { | |
335 | if (yrgb_ver_scl_mode != SCALE_NONE) { | |
336 | DRM_ERROR("ERROR : not allow yrgb ver scale\n"); | |
337 | return; | |
338 | } | |
339 | if (cbcr_ver_scl_mode != SCALE_NONE) { | |
340 | DRM_ERROR("ERROR : not allow cbcr ver scale\n"); | |
341 | return; | |
342 | } | |
343 | vsu_mode = SCALE_UP_BIL; | |
344 | } else if (lb_mode == LB_RGB_2560X4) { | |
345 | vsu_mode = SCALE_UP_BIL; | |
346 | } else { | |
347 | vsu_mode = SCALE_UP_BIC; | |
348 | } | |
349 | ||
350 | val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, | |
351 | true, 0, NULL); | |
352 | VOP_SCL_SET(vop, win, scale_yrgb_x, val); | |
353 | val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, | |
354 | false, vsu_mode, &vskiplines); | |
355 | VOP_SCL_SET(vop, win, scale_yrgb_y, val); | |
356 | ||
357 | VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4); | |
358 | VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2); | |
359 | ||
360 | VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); | |
361 | VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); | |
362 | VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); | |
363 | VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); | |
364 | VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode); | |
365 | if (is_yuv) { | |
366 | val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, | |
367 | dst_w, true, 0, NULL); | |
368 | VOP_SCL_SET(vop, win, scale_cbcr_x, val); | |
369 | val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, | |
370 | dst_h, false, vsu_mode, &vskiplines); | |
371 | VOP_SCL_SET(vop, win, scale_cbcr_y, val); | |
372 | ||
373 | VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4); | |
374 | VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2); | |
375 | VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); | |
376 | VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); | |
377 | VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); | |
378 | VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); | |
379 | VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode); | |
380 | } | |
381 | } | |
382 | ||
1067219b MY |
383 | static void vop_dsp_hold_valid_irq_enable(struct vop *vop) |
384 | { | |
385 | unsigned long flags; | |
386 | ||
387 | if (WARN_ON(!vop->is_enabled)) | |
388 | return; | |
389 | ||
390 | spin_lock_irqsave(&vop->irq_lock, flags); | |
391 | ||
dbb3d944 | 392 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); |
1067219b MY |
393 | |
394 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
395 | } | |
396 | ||
397 | static void vop_dsp_hold_valid_irq_disable(struct vop *vop) | |
398 | { | |
399 | unsigned long flags; | |
400 | ||
401 | if (WARN_ON(!vop->is_enabled)) | |
402 | return; | |
403 | ||
404 | spin_lock_irqsave(&vop->irq_lock, flags); | |
405 | ||
dbb3d944 | 406 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); |
1067219b MY |
407 | |
408 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
409 | } | |
410 | ||
63ebb9fa | 411 | static void vop_enable(struct drm_crtc *crtc) |
2048e328 MY |
412 | { |
413 | struct vop *vop = to_vop(crtc); | |
414 | int ret; | |
415 | ||
31e980c5 MY |
416 | if (vop->is_enabled) |
417 | return; | |
418 | ||
5d82d1a7 MY |
419 | ret = pm_runtime_get_sync(vop->dev); |
420 | if (ret < 0) { | |
421 | dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); | |
422 | return; | |
423 | } | |
424 | ||
2048e328 MY |
425 | ret = clk_enable(vop->hclk); |
426 | if (ret < 0) { | |
427 | dev_err(vop->dev, "failed to enable hclk - %d\n", ret); | |
428 | return; | |
429 | } | |
430 | ||
431 | ret = clk_enable(vop->dclk); | |
432 | if (ret < 0) { | |
433 | dev_err(vop->dev, "failed to enable dclk - %d\n", ret); | |
434 | goto err_disable_hclk; | |
435 | } | |
436 | ||
437 | ret = clk_enable(vop->aclk); | |
438 | if (ret < 0) { | |
439 | dev_err(vop->dev, "failed to enable aclk - %d\n", ret); | |
440 | goto err_disable_dclk; | |
441 | } | |
442 | ||
443 | /* | |
444 | * Slave iommu shares power, irq and clock with vop. It was associated | |
445 | * automatically with this master device via common driver code. | |
446 | * Now that we have enabled the clock we attach it to the shared drm | |
447 | * mapping. | |
448 | */ | |
449 | ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); | |
450 | if (ret) { | |
451 | dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); | |
452 | goto err_disable_aclk; | |
453 | } | |
454 | ||
77faa161 | 455 | memcpy(vop->regs, vop->regsbak, vop->len); |
52ab7891 MY |
456 | /* |
457 | * At here, vop clock & iommu is enable, R/W vop regs would be safe. | |
458 | */ | |
459 | vop->is_enabled = true; | |
460 | ||
2048e328 MY |
461 | spin_lock(&vop->reg_lock); |
462 | ||
463 | VOP_CTRL_SET(vop, standby, 0); | |
464 | ||
465 | spin_unlock(&vop->reg_lock); | |
466 | ||
467 | enable_irq(vop->irq); | |
468 | ||
b5f7b755 | 469 | drm_crtc_vblank_on(crtc); |
2048e328 MY |
470 | |
471 | return; | |
472 | ||
473 | err_disable_aclk: | |
474 | clk_disable(vop->aclk); | |
475 | err_disable_dclk: | |
476 | clk_disable(vop->dclk); | |
477 | err_disable_hclk: | |
478 | clk_disable(vop->hclk); | |
479 | } | |
480 | ||
0ad3675d | 481 | static void vop_crtc_disable(struct drm_crtc *crtc) |
2048e328 MY |
482 | { |
483 | struct vop *vop = to_vop(crtc); | |
484 | ||
31e980c5 MY |
485 | if (!vop->is_enabled) |
486 | return; | |
487 | ||
b5f7b755 | 488 | drm_crtc_vblank_off(crtc); |
2048e328 | 489 | |
2048e328 | 490 | /* |
1067219b MY |
491 | * Vop standby will take effect at end of current frame, |
492 | * if dsp hold valid irq happen, it means standby complete. | |
493 | * | |
494 | * we must wait standby complete when we want to disable aclk, | |
495 | * if not, memory bus maybe dead. | |
2048e328 | 496 | */ |
1067219b MY |
497 | reinit_completion(&vop->dsp_hold_completion); |
498 | vop_dsp_hold_valid_irq_enable(vop); | |
499 | ||
2048e328 MY |
500 | spin_lock(&vop->reg_lock); |
501 | ||
502 | VOP_CTRL_SET(vop, standby, 1); | |
503 | ||
504 | spin_unlock(&vop->reg_lock); | |
52ab7891 | 505 | |
1067219b MY |
506 | wait_for_completion(&vop->dsp_hold_completion); |
507 | ||
508 | vop_dsp_hold_valid_irq_disable(vop); | |
509 | ||
510 | disable_irq(vop->irq); | |
511 | ||
52ab7891 | 512 | vop->is_enabled = false; |
1067219b | 513 | |
2048e328 | 514 | /* |
1067219b | 515 | * vop standby complete, so iommu detach is safe. |
2048e328 | 516 | */ |
2048e328 MY |
517 | rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); |
518 | ||
1067219b | 519 | clk_disable(vop->dclk); |
2048e328 MY |
520 | clk_disable(vop->aclk); |
521 | clk_disable(vop->hclk); | |
5d82d1a7 | 522 | pm_runtime_put(vop->dev); |
2048e328 MY |
523 | } |
524 | ||
63ebb9fa | 525 | static void vop_plane_destroy(struct drm_plane *plane) |
2048e328 | 526 | { |
63ebb9fa | 527 | drm_plane_cleanup(plane); |
2048e328 MY |
528 | } |
529 | ||
63ebb9fa MY |
530 | static int vop_plane_atomic_check(struct drm_plane *plane, |
531 | struct drm_plane_state *state) | |
2048e328 | 532 | { |
63ebb9fa MY |
533 | struct drm_crtc *crtc = state->crtc; |
534 | struct drm_framebuffer *fb = state->fb; | |
2048e328 | 535 | struct vop_win *vop_win = to_vop_win(plane); |
63ebb9fa | 536 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); |
2048e328 | 537 | const struct vop_win_data *win = vop_win->data; |
2048e328 MY |
538 | bool visible; |
539 | int ret; | |
63ebb9fa MY |
540 | struct drm_rect *dest = &vop_plane_state->dest; |
541 | struct drm_rect *src = &vop_plane_state->src; | |
542 | struct drm_rect clip; | |
4c156c21 MY |
543 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : |
544 | DRM_PLANE_HELPER_NO_SCALING; | |
545 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : | |
546 | DRM_PLANE_HELPER_NO_SCALING; | |
2048e328 | 547 | |
63ebb9fa MY |
548 | crtc = crtc ? crtc : plane->state->crtc; |
549 | /* | |
550 | * Both crtc or plane->state->crtc can be null. | |
551 | */ | |
552 | if (!crtc || !fb) | |
553 | goto out_disable; | |
554 | src->x1 = state->src_x; | |
555 | src->y1 = state->src_y; | |
556 | src->x2 = state->src_x + state->src_w; | |
557 | src->y2 = state->src_y + state->src_h; | |
558 | dest->x1 = state->crtc_x; | |
559 | dest->y1 = state->crtc_y; | |
560 | dest->x2 = state->crtc_x + state->crtc_w; | |
561 | dest->y2 = state->crtc_y + state->crtc_h; | |
562 | ||
563 | clip.x1 = 0; | |
564 | clip.y1 = 0; | |
565 | clip.x2 = crtc->mode.hdisplay; | |
566 | clip.y2 = crtc->mode.vdisplay; | |
567 | ||
568 | ret = drm_plane_helper_check_update(plane, crtc, state->fb, | |
569 | src, dest, &clip, | |
4c156c21 MY |
570 | min_scale, |
571 | max_scale, | |
63ebb9fa | 572 | true, true, &visible); |
2048e328 MY |
573 | if (ret) |
574 | return ret; | |
575 | ||
576 | if (!visible) | |
63ebb9fa | 577 | goto out_disable; |
2048e328 | 578 | |
63ebb9fa MY |
579 | vop_plane_state->format = vop_convert_format(fb->pixel_format); |
580 | if (vop_plane_state->format < 0) | |
581 | return vop_plane_state->format; | |
84c7f8ca | 582 | |
63ebb9fa MY |
583 | /* |
584 | * Src.x1 can be odd when do clip, but yuv plane start point | |
585 | * need align with 2 pixel. | |
586 | */ | |
587 | if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) | |
2048e328 | 588 | return -EINVAL; |
2048e328 | 589 | |
63ebb9fa | 590 | vop_plane_state->enable = true; |
2048e328 | 591 | |
63ebb9fa | 592 | return 0; |
84c7f8ca | 593 | |
63ebb9fa MY |
594 | out_disable: |
595 | vop_plane_state->enable = false; | |
596 | return 0; | |
597 | } | |
2048e328 | 598 | |
63ebb9fa MY |
599 | static void vop_plane_atomic_disable(struct drm_plane *plane, |
600 | struct drm_plane_state *old_state) | |
601 | { | |
602 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); | |
603 | struct vop_win *vop_win = to_vop_win(plane); | |
604 | const struct vop_win_data *win = vop_win->data; | |
605 | struct vop *vop = to_vop(old_state->crtc); | |
2048e328 | 606 | |
63ebb9fa MY |
607 | if (!old_state->crtc) |
608 | return; | |
2048e328 | 609 | |
63ebb9fa | 610 | spin_lock(&vop->reg_lock); |
2048e328 | 611 | |
63ebb9fa | 612 | VOP_WIN_SET(vop, win, enable, 0); |
84c7f8ca | 613 | |
63ebb9fa | 614 | spin_unlock(&vop->reg_lock); |
84c7f8ca | 615 | |
63ebb9fa MY |
616 | vop_plane_state->enable = false; |
617 | } | |
84c7f8ca | 618 | |
63ebb9fa MY |
619 | static void vop_plane_atomic_update(struct drm_plane *plane, |
620 | struct drm_plane_state *old_state) | |
621 | { | |
622 | struct drm_plane_state *state = plane->state; | |
623 | struct drm_crtc *crtc = state->crtc; | |
624 | struct vop_win *vop_win = to_vop_win(plane); | |
625 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); | |
626 | const struct vop_win_data *win = vop_win->data; | |
627 | struct vop *vop = to_vop(state->crtc); | |
628 | struct drm_framebuffer *fb = state->fb; | |
629 | unsigned int actual_w, actual_h; | |
630 | unsigned int dsp_stx, dsp_sty; | |
631 | uint32_t act_info, dsp_info, dsp_st; | |
632 | struct drm_rect *src = &vop_plane_state->src; | |
633 | struct drm_rect *dest = &vop_plane_state->dest; | |
634 | struct drm_gem_object *obj, *uv_obj; | |
635 | struct rockchip_gem_object *rk_obj, *rk_uv_obj; | |
636 | unsigned long offset; | |
637 | dma_addr_t dma_addr; | |
638 | uint32_t val; | |
639 | bool rb_swap; | |
84c7f8ca | 640 | |
2048e328 | 641 | /* |
63ebb9fa | 642 | * can't update plane when vop is disabled. |
2048e328 | 643 | */ |
63ebb9fa MY |
644 | if (!crtc) |
645 | return; | |
2048e328 | 646 | |
63ebb9fa MY |
647 | if (WARN_ON(!vop->is_enabled)) |
648 | return; | |
2048e328 | 649 | |
63ebb9fa MY |
650 | if (!vop_plane_state->enable) { |
651 | vop_plane_atomic_disable(plane, old_state); | |
652 | return; | |
2048e328 | 653 | } |
63ebb9fa MY |
654 | |
655 | obj = rockchip_fb_get_gem_obj(fb, 0); | |
656 | rk_obj = to_rockchip_obj(obj); | |
657 | ||
658 | actual_w = drm_rect_width(src) >> 16; | |
659 | actual_h = drm_rect_height(src) >> 16; | |
660 | act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); | |
661 | ||
662 | dsp_info = (drm_rect_height(dest) - 1) << 16; | |
663 | dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; | |
664 | ||
665 | dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; | |
666 | dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; | |
667 | dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); | |
668 | ||
669 | offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); | |
670 | offset += (src->y1 >> 16) * fb->pitches[0]; | |
671 | vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; | |
2048e328 MY |
672 | |
673 | spin_lock(&vop->reg_lock); | |
674 | ||
63ebb9fa MY |
675 | VOP_WIN_SET(vop, win, format, vop_plane_state->format); |
676 | VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); | |
677 | VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); | |
678 | if (is_yuv_support(fb->pixel_format)) { | |
679 | int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); | |
680 | int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); | |
681 | int bpp = drm_format_plane_cpp(fb->pixel_format, 1); | |
682 | ||
683 | uv_obj = rockchip_fb_get_gem_obj(fb, 1); | |
684 | rk_uv_obj = to_rockchip_obj(uv_obj); | |
685 | ||
686 | offset = (src->x1 >> 16) * bpp / hsub; | |
687 | offset += (src->y1 >> 16) * fb->pitches[1] / vsub; | |
688 | ||
689 | dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; | |
690 | VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); | |
691 | VOP_WIN_SET(vop, win, uv_mst, dma_addr); | |
84c7f8ca | 692 | } |
4c156c21 MY |
693 | |
694 | if (win->phy->scl) | |
695 | scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, | |
63ebb9fa | 696 | drm_rect_width(dest), drm_rect_height(dest), |
4c156c21 MY |
697 | fb->pixel_format); |
698 | ||
63ebb9fa MY |
699 | VOP_WIN_SET(vop, win, act_info, act_info); |
700 | VOP_WIN_SET(vop, win, dsp_info, dsp_info); | |
701 | VOP_WIN_SET(vop, win, dsp_st, dsp_st); | |
4c156c21 | 702 | |
63ebb9fa | 703 | rb_swap = has_rb_swapped(fb->pixel_format); |
85a359f2 | 704 | VOP_WIN_SET(vop, win, rb_swap, rb_swap); |
2048e328 | 705 | |
63ebb9fa | 706 | if (is_alpha_support(fb->pixel_format)) { |
2048e328 MY |
707 | VOP_WIN_SET(vop, win, dst_alpha_ctl, |
708 | DST_FACTOR_M0(ALPHA_SRC_INVERSE)); | |
709 | val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | | |
710 | SRC_ALPHA_M0(ALPHA_STRAIGHT) | | |
711 | SRC_BLEND_M0(ALPHA_PER_PIX) | | |
712 | SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | | |
713 | SRC_FACTOR_M0(ALPHA_ONE); | |
714 | VOP_WIN_SET(vop, win, src_alpha_ctl, val); | |
715 | } else { | |
716 | VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); | |
717 | } | |
718 | ||
719 | VOP_WIN_SET(vop, win, enable, 1); | |
2048e328 | 720 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
721 | } |
722 | ||
63ebb9fa MY |
723 | static const struct drm_plane_helper_funcs plane_helper_funcs = { |
724 | .atomic_check = vop_plane_atomic_check, | |
725 | .atomic_update = vop_plane_atomic_update, | |
726 | .atomic_disable = vop_plane_atomic_disable, | |
727 | }; | |
2048e328 | 728 | |
63ebb9fa | 729 | void vop_atomic_plane_reset(struct drm_plane *plane) |
2048e328 | 730 | { |
63ebb9fa MY |
731 | struct vop_plane_state *vop_plane_state = |
732 | to_vop_plane_state(plane->state); | |
2048e328 | 733 | |
63ebb9fa MY |
734 | if (plane->state && plane->state->fb) |
735 | drm_framebuffer_unreference(plane->state->fb); | |
736 | ||
737 | kfree(vop_plane_state); | |
738 | vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); | |
739 | if (!vop_plane_state) | |
740 | return; | |
2048e328 | 741 | |
63ebb9fa MY |
742 | plane->state = &vop_plane_state->base; |
743 | plane->state->plane = plane; | |
2048e328 MY |
744 | } |
745 | ||
63ebb9fa MY |
746 | struct drm_plane_state * |
747 | vop_atomic_plane_duplicate_state(struct drm_plane *plane) | |
2048e328 | 748 | { |
63ebb9fa MY |
749 | struct vop_plane_state *old_vop_plane_state; |
750 | struct vop_plane_state *vop_plane_state; | |
2048e328 | 751 | |
63ebb9fa MY |
752 | if (WARN_ON(!plane->state)) |
753 | return NULL; | |
2048e328 | 754 | |
63ebb9fa MY |
755 | old_vop_plane_state = to_vop_plane_state(plane->state); |
756 | vop_plane_state = kmemdup(old_vop_plane_state, | |
757 | sizeof(*vop_plane_state), GFP_KERNEL); | |
758 | if (!vop_plane_state) | |
759 | return NULL; | |
2048e328 | 760 | |
63ebb9fa MY |
761 | __drm_atomic_helper_plane_duplicate_state(plane, |
762 | &vop_plane_state->base); | |
2048e328 | 763 | |
63ebb9fa | 764 | return &vop_plane_state->base; |
2048e328 MY |
765 | } |
766 | ||
63ebb9fa MY |
767 | static void vop_atomic_plane_destroy_state(struct drm_plane *plane, |
768 | struct drm_plane_state *state) | |
2048e328 | 769 | { |
63ebb9fa MY |
770 | struct vop_plane_state *vop_state = to_vop_plane_state(state); |
771 | ||
772 | __drm_atomic_helper_plane_destroy_state(plane, state); | |
773 | ||
774 | kfree(vop_state); | |
2048e328 MY |
775 | } |
776 | ||
777 | static const struct drm_plane_funcs vop_plane_funcs = { | |
63ebb9fa MY |
778 | .update_plane = drm_atomic_helper_update_plane, |
779 | .disable_plane = drm_atomic_helper_disable_plane, | |
2048e328 | 780 | .destroy = vop_plane_destroy, |
63ebb9fa MY |
781 | .reset = vop_atomic_plane_reset, |
782 | .atomic_duplicate_state = vop_atomic_plane_duplicate_state, | |
783 | .atomic_destroy_state = vop_atomic_plane_destroy_state, | |
2048e328 MY |
784 | }; |
785 | ||
786 | int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, | |
787 | int connector_type, | |
788 | int out_mode) | |
789 | { | |
790 | struct vop *vop = to_vop(crtc); | |
791 | ||
d0e20d0e MY |
792 | if (WARN_ON(!vop->is_enabled)) |
793 | return -EINVAL; | |
794 | ||
795 | switch (connector_type) { | |
796 | case DRM_MODE_CONNECTOR_LVDS: | |
797 | VOP_CTRL_SET(vop, rgb_en, 1); | |
798 | break; | |
799 | case DRM_MODE_CONNECTOR_eDP: | |
800 | VOP_CTRL_SET(vop, edp_en, 1); | |
801 | break; | |
802 | case DRM_MODE_CONNECTOR_HDMIA: | |
803 | VOP_CTRL_SET(vop, hdmi_en, 1); | |
804 | break; | |
805 | default: | |
806 | DRM_ERROR("unsupport connector_type[%d]\n", connector_type); | |
807 | return -EINVAL; | |
808 | }; | |
809 | VOP_CTRL_SET(vop, out_mode, out_mode); | |
2048e328 MY |
810 | |
811 | return 0; | |
812 | } | |
f66a1627 | 813 | EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config); |
2048e328 MY |
814 | |
815 | static int vop_crtc_enable_vblank(struct drm_crtc *crtc) | |
816 | { | |
817 | struct vop *vop = to_vop(crtc); | |
818 | unsigned long flags; | |
819 | ||
63ebb9fa | 820 | if (WARN_ON(!vop->is_enabled)) |
2048e328 MY |
821 | return -EPERM; |
822 | ||
823 | spin_lock_irqsave(&vop->irq_lock, flags); | |
824 | ||
dbb3d944 | 825 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); |
2048e328 MY |
826 | |
827 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
828 | ||
829 | return 0; | |
830 | } | |
831 | ||
832 | static void vop_crtc_disable_vblank(struct drm_crtc *crtc) | |
833 | { | |
834 | struct vop *vop = to_vop(crtc); | |
835 | unsigned long flags; | |
836 | ||
63ebb9fa | 837 | if (WARN_ON(!vop->is_enabled)) |
2048e328 | 838 | return; |
31e980c5 | 839 | |
2048e328 | 840 | spin_lock_irqsave(&vop->irq_lock, flags); |
dbb3d944 MY |
841 | |
842 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); | |
843 | ||
2048e328 MY |
844 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
845 | } | |
846 | ||
63ebb9fa MY |
847 | static void vop_crtc_wait_for_update(struct drm_crtc *crtc) |
848 | { | |
849 | struct vop *vop = to_vop(crtc); | |
850 | ||
851 | reinit_completion(&vop->wait_update_complete); | |
852 | WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); | |
853 | } | |
854 | ||
2048e328 MY |
855 | static const struct rockchip_crtc_funcs private_crtc_funcs = { |
856 | .enable_vblank = vop_crtc_enable_vblank, | |
857 | .disable_vblank = vop_crtc_disable_vblank, | |
63ebb9fa | 858 | .wait_for_update = vop_crtc_wait_for_update, |
2048e328 MY |
859 | }; |
860 | ||
2048e328 MY |
861 | static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, |
862 | const struct drm_display_mode *mode, | |
863 | struct drm_display_mode *adjusted_mode) | |
864 | { | |
865 | if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0) | |
866 | return false; | |
867 | ||
868 | return true; | |
869 | } | |
870 | ||
63ebb9fa | 871 | static void vop_crtc_enable(struct drm_crtc *crtc) |
2048e328 MY |
872 | { |
873 | struct vop *vop = to_vop(crtc); | |
63ebb9fa | 874 | struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; |
2048e328 MY |
875 | u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; |
876 | u16 hdisplay = adjusted_mode->hdisplay; | |
877 | u16 htotal = adjusted_mode->htotal; | |
878 | u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; | |
879 | u16 hact_end = hact_st + hdisplay; | |
880 | u16 vdisplay = adjusted_mode->vdisplay; | |
881 | u16 vtotal = adjusted_mode->vtotal; | |
882 | u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | |
883 | u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; | |
884 | u16 vact_end = vact_st + vdisplay; | |
2048e328 MY |
885 | uint32_t val; |
886 | ||
63ebb9fa | 887 | vop_enable(crtc); |
2048e328 | 888 | /* |
ce3887ed MY |
889 | * If dclk rate is zero, mean that scanout is stop, |
890 | * we don't need wait any more. | |
2048e328 | 891 | */ |
ce3887ed MY |
892 | if (clk_get_rate(vop->dclk)) { |
893 | /* | |
894 | * Rk3288 vop timing register is immediately, when configure | |
895 | * display timing on display time, may cause tearing. | |
896 | * | |
897 | * Vop standby will take effect at end of current frame, | |
898 | * if dsp hold valid irq happen, it means standby complete. | |
899 | * | |
900 | * mode set: | |
901 | * standby and wait complete --> |---- | |
902 | * | display time | |
903 | * |---- | |
904 | * |---> dsp hold irq | |
905 | * configure display timing --> | | |
906 | * standby exit | | |
907 | * | new frame start. | |
908 | */ | |
909 | ||
910 | reinit_completion(&vop->dsp_hold_completion); | |
911 | vop_dsp_hold_valid_irq_enable(vop); | |
912 | ||
913 | spin_lock(&vop->reg_lock); | |
914 | ||
915 | VOP_CTRL_SET(vop, standby, 1); | |
916 | ||
917 | spin_unlock(&vop->reg_lock); | |
918 | ||
919 | wait_for_completion(&vop->dsp_hold_completion); | |
920 | ||
921 | vop_dsp_hold_valid_irq_disable(vop); | |
922 | } | |
2048e328 | 923 | |
2048e328 | 924 | val = 0x8; |
44ddb7ef MY |
925 | val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; |
926 | val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); | |
2048e328 MY |
927 | VOP_CTRL_SET(vop, pin_pol, val); |
928 | ||
929 | VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); | |
930 | val = hact_st << 16; | |
931 | val |= hact_end; | |
932 | VOP_CTRL_SET(vop, hact_st_end, val); | |
933 | VOP_CTRL_SET(vop, hpost_st_end, val); | |
934 | ||
935 | VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); | |
936 | val = vact_st << 16; | |
937 | val |= vact_end; | |
938 | VOP_CTRL_SET(vop, vact_st_end, val); | |
939 | VOP_CTRL_SET(vop, vpost_st_end, val); | |
940 | ||
2048e328 | 941 | clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); |
ce3887ed MY |
942 | |
943 | VOP_CTRL_SET(vop, standby, 0); | |
2048e328 MY |
944 | } |
945 | ||
63ebb9fa MY |
946 | static void vop_crtc_atomic_flush(struct drm_crtc *crtc, |
947 | struct drm_crtc_state *old_crtc_state) | |
2048e328 MY |
948 | { |
949 | struct vop *vop = to_vop(crtc); | |
2048e328 | 950 | |
63ebb9fa MY |
951 | if (WARN_ON(!vop->is_enabled)) |
952 | return; | |
2048e328 | 953 | |
63ebb9fa | 954 | spin_lock(&vop->reg_lock); |
2048e328 | 955 | |
63ebb9fa | 956 | vop_cfg_done(vop); |
2048e328 | 957 | |
63ebb9fa | 958 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
959 | } |
960 | ||
63ebb9fa MY |
961 | static void vop_crtc_atomic_begin(struct drm_crtc *crtc, |
962 | struct drm_crtc_state *old_crtc_state) | |
2048e328 | 963 | { |
63ebb9fa | 964 | struct vop *vop = to_vop(crtc); |
2048e328 | 965 | |
63ebb9fa MY |
966 | if (crtc->state->event) { |
967 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
2048e328 | 968 | |
63ebb9fa MY |
969 | vop->event = crtc->state->event; |
970 | crtc->state->event = NULL; | |
971 | } | |
2048e328 MY |
972 | } |
973 | ||
63ebb9fa MY |
974 | static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { |
975 | .enable = vop_crtc_enable, | |
976 | .disable = vop_crtc_disable, | |
977 | .mode_fixup = vop_crtc_mode_fixup, | |
978 | .atomic_flush = vop_crtc_atomic_flush, | |
979 | .atomic_begin = vop_crtc_atomic_begin, | |
980 | }; | |
981 | ||
2048e328 MY |
982 | static void vop_crtc_destroy(struct drm_crtc *crtc) |
983 | { | |
984 | drm_crtc_cleanup(crtc); | |
985 | } | |
986 | ||
987 | static const struct drm_crtc_funcs vop_crtc_funcs = { | |
63ebb9fa MY |
988 | .set_config = drm_atomic_helper_set_config, |
989 | .page_flip = drm_atomic_helper_page_flip, | |
2048e328 | 990 | .destroy = vop_crtc_destroy, |
63ebb9fa MY |
991 | .reset = drm_atomic_helper_crtc_reset, |
992 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
993 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
2048e328 MY |
994 | }; |
995 | ||
63ebb9fa | 996 | static bool vop_win_pending_is_complete(struct vop_win *vop_win) |
2048e328 | 997 | { |
63ebb9fa MY |
998 | struct drm_plane *plane = &vop_win->base; |
999 | struct vop_plane_state *state = to_vop_plane_state(plane->state); | |
1000 | dma_addr_t yrgb_mst; | |
2048e328 | 1001 | |
63ebb9fa MY |
1002 | if (!state->enable) |
1003 | return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; | |
2048e328 | 1004 | |
63ebb9fa | 1005 | yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); |
2048e328 | 1006 | |
63ebb9fa | 1007 | return yrgb_mst == state->yrgb_mst; |
2048e328 MY |
1008 | } |
1009 | ||
63ebb9fa | 1010 | static void vop_handle_vblank(struct vop *vop) |
2048e328 | 1011 | { |
63ebb9fa MY |
1012 | struct drm_device *drm = vop->drm_dev; |
1013 | struct drm_crtc *crtc = &vop->crtc; | |
1014 | unsigned long flags; | |
1015 | int i; | |
2048e328 | 1016 | |
63ebb9fa MY |
1017 | for (i = 0; i < vop->data->win_size; i++) { |
1018 | if (!vop_win_pending_is_complete(&vop->win[i])) | |
1019 | return; | |
2048e328 MY |
1020 | } |
1021 | ||
63ebb9fa MY |
1022 | if (vop->event) { |
1023 | spin_lock_irqsave(&drm->event_lock, flags); | |
2048e328 | 1024 | |
63ebb9fa MY |
1025 | drm_crtc_send_vblank_event(crtc, vop->event); |
1026 | drm_crtc_vblank_put(crtc); | |
1027 | vop->event = NULL; | |
2048e328 | 1028 | |
63ebb9fa | 1029 | spin_unlock_irqrestore(&drm->event_lock, flags); |
2048e328 | 1030 | } |
63ebb9fa MY |
1031 | if (!completion_done(&vop->wait_update_complete)) |
1032 | complete(&vop->wait_update_complete); | |
2048e328 MY |
1033 | } |
1034 | ||
1035 | static irqreturn_t vop_isr(int irq, void *data) | |
1036 | { | |
1037 | struct vop *vop = data; | |
b5f7b755 | 1038 | struct drm_crtc *crtc = &vop->crtc; |
dbb3d944 | 1039 | uint32_t active_irqs; |
2048e328 | 1040 | unsigned long flags; |
1067219b | 1041 | int ret = IRQ_NONE; |
2048e328 MY |
1042 | |
1043 | /* | |
dbb3d944 | 1044 | * interrupt register has interrupt status, enable and clear bits, we |
2048e328 MY |
1045 | * must hold irq_lock to avoid a race with enable/disable_vblank(). |
1046 | */ | |
1047 | spin_lock_irqsave(&vop->irq_lock, flags); | |
dbb3d944 MY |
1048 | |
1049 | active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); | |
2048e328 MY |
1050 | /* Clear all active interrupt sources */ |
1051 | if (active_irqs) | |
dbb3d944 MY |
1052 | VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); |
1053 | ||
2048e328 MY |
1054 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
1055 | ||
1056 | /* This is expected for vop iommu irqs, since the irq is shared */ | |
1057 | if (!active_irqs) | |
1058 | return IRQ_NONE; | |
1059 | ||
1067219b MY |
1060 | if (active_irqs & DSP_HOLD_VALID_INTR) { |
1061 | complete(&vop->dsp_hold_completion); | |
1062 | active_irqs &= ~DSP_HOLD_VALID_INTR; | |
1063 | ret = IRQ_HANDLED; | |
2048e328 MY |
1064 | } |
1065 | ||
1067219b | 1066 | if (active_irqs & FS_INTR) { |
b5f7b755 | 1067 | drm_crtc_handle_vblank(crtc); |
63ebb9fa | 1068 | vop_handle_vblank(vop); |
1067219b | 1069 | active_irqs &= ~FS_INTR; |
63ebb9fa | 1070 | ret = IRQ_HANDLED; |
1067219b | 1071 | } |
2048e328 | 1072 | |
1067219b MY |
1073 | /* Unhandled irqs are spurious. */ |
1074 | if (active_irqs) | |
1075 | DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); | |
1076 | ||
1077 | return ret; | |
2048e328 MY |
1078 | } |
1079 | ||
1080 | static int vop_create_crtc(struct vop *vop) | |
1081 | { | |
1082 | const struct vop_data *vop_data = vop->data; | |
1083 | struct device *dev = vop->dev; | |
1084 | struct drm_device *drm_dev = vop->drm_dev; | |
1085 | struct drm_plane *primary = NULL, *cursor = NULL, *plane; | |
1086 | struct drm_crtc *crtc = &vop->crtc; | |
1087 | struct device_node *port; | |
1088 | int ret; | |
1089 | int i; | |
1090 | ||
1091 | /* | |
1092 | * Create drm_plane for primary and cursor planes first, since we need | |
1093 | * to pass them to drm_crtc_init_with_planes, which sets the | |
1094 | * "possible_crtcs" to the newly initialized crtc. | |
1095 | */ | |
1096 | for (i = 0; i < vop_data->win_size; i++) { | |
1097 | struct vop_win *vop_win = &vop->win[i]; | |
1098 | const struct vop_win_data *win_data = vop_win->data; | |
1099 | ||
1100 | if (win_data->type != DRM_PLANE_TYPE_PRIMARY && | |
1101 | win_data->type != DRM_PLANE_TYPE_CURSOR) | |
1102 | continue; | |
1103 | ||
1104 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1105 | 0, &vop_plane_funcs, | |
1106 | win_data->phy->data_formats, | |
1107 | win_data->phy->nformats, | |
b0b3b795 | 1108 | win_data->type, NULL); |
2048e328 MY |
1109 | if (ret) { |
1110 | DRM_ERROR("failed to initialize plane\n"); | |
1111 | goto err_cleanup_planes; | |
1112 | } | |
1113 | ||
1114 | plane = &vop_win->base; | |
63ebb9fa | 1115 | drm_plane_helper_add(plane, &plane_helper_funcs); |
2048e328 MY |
1116 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
1117 | primary = plane; | |
1118 | else if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
1119 | cursor = plane; | |
1120 | } | |
1121 | ||
1122 | ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, | |
f9882876 | 1123 | &vop_crtc_funcs, NULL); |
2048e328 MY |
1124 | if (ret) |
1125 | return ret; | |
1126 | ||
1127 | drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); | |
1128 | ||
1129 | /* | |
1130 | * Create drm_planes for overlay windows with possible_crtcs restricted | |
1131 | * to the newly created crtc. | |
1132 | */ | |
1133 | for (i = 0; i < vop_data->win_size; i++) { | |
1134 | struct vop_win *vop_win = &vop->win[i]; | |
1135 | const struct vop_win_data *win_data = vop_win->data; | |
1136 | unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); | |
1137 | ||
1138 | if (win_data->type != DRM_PLANE_TYPE_OVERLAY) | |
1139 | continue; | |
1140 | ||
1141 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1142 | possible_crtcs, | |
1143 | &vop_plane_funcs, | |
1144 | win_data->phy->data_formats, | |
1145 | win_data->phy->nformats, | |
b0b3b795 | 1146 | win_data->type, NULL); |
2048e328 MY |
1147 | if (ret) { |
1148 | DRM_ERROR("failed to initialize overlay plane\n"); | |
1149 | goto err_cleanup_crtc; | |
1150 | } | |
63ebb9fa | 1151 | drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); |
2048e328 MY |
1152 | } |
1153 | ||
1154 | port = of_get_child_by_name(dev->of_node, "port"); | |
1155 | if (!port) { | |
1156 | DRM_ERROR("no port node found in %s\n", | |
1157 | dev->of_node->full_name); | |
1158 | goto err_cleanup_crtc; | |
1159 | } | |
1160 | ||
1067219b | 1161 | init_completion(&vop->dsp_hold_completion); |
63ebb9fa | 1162 | init_completion(&vop->wait_update_complete); |
2048e328 | 1163 | crtc->port = port; |
b5f7b755 | 1164 | rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); |
2048e328 MY |
1165 | |
1166 | return 0; | |
1167 | ||
1168 | err_cleanup_crtc: | |
1169 | drm_crtc_cleanup(crtc); | |
1170 | err_cleanup_planes: | |
1171 | list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head) | |
1172 | drm_plane_cleanup(plane); | |
1173 | return ret; | |
1174 | } | |
1175 | ||
1176 | static void vop_destroy_crtc(struct vop *vop) | |
1177 | { | |
1178 | struct drm_crtc *crtc = &vop->crtc; | |
1179 | ||
b5f7b755 | 1180 | rockchip_unregister_crtc_funcs(crtc); |
2048e328 MY |
1181 | of_node_put(crtc->port); |
1182 | drm_crtc_cleanup(crtc); | |
1183 | } | |
1184 | ||
1185 | static int vop_initial(struct vop *vop) | |
1186 | { | |
1187 | const struct vop_data *vop_data = vop->data; | |
1188 | const struct vop_reg_data *init_table = vop_data->init_table; | |
1189 | struct reset_control *ahb_rst; | |
1190 | int i, ret; | |
1191 | ||
1192 | vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); | |
1193 | if (IS_ERR(vop->hclk)) { | |
1194 | dev_err(vop->dev, "failed to get hclk source\n"); | |
1195 | return PTR_ERR(vop->hclk); | |
1196 | } | |
1197 | vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); | |
1198 | if (IS_ERR(vop->aclk)) { | |
1199 | dev_err(vop->dev, "failed to get aclk source\n"); | |
1200 | return PTR_ERR(vop->aclk); | |
1201 | } | |
1202 | vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); | |
1203 | if (IS_ERR(vop->dclk)) { | |
1204 | dev_err(vop->dev, "failed to get dclk source\n"); | |
1205 | return PTR_ERR(vop->dclk); | |
1206 | } | |
1207 | ||
2048e328 MY |
1208 | ret = clk_prepare(vop->dclk); |
1209 | if (ret < 0) { | |
1210 | dev_err(vop->dev, "failed to prepare dclk\n"); | |
d7b53fd9 | 1211 | return ret; |
2048e328 MY |
1212 | } |
1213 | ||
d7b53fd9 SS |
1214 | /* Enable both the hclk and aclk to setup the vop */ |
1215 | ret = clk_prepare_enable(vop->hclk); | |
2048e328 | 1216 | if (ret < 0) { |
d7b53fd9 | 1217 | dev_err(vop->dev, "failed to prepare/enable hclk\n"); |
2048e328 MY |
1218 | goto err_unprepare_dclk; |
1219 | } | |
1220 | ||
d7b53fd9 | 1221 | ret = clk_prepare_enable(vop->aclk); |
2048e328 | 1222 | if (ret < 0) { |
d7b53fd9 SS |
1223 | dev_err(vop->dev, "failed to prepare/enable aclk\n"); |
1224 | goto err_disable_hclk; | |
2048e328 | 1225 | } |
d7b53fd9 | 1226 | |
2048e328 MY |
1227 | /* |
1228 | * do hclk_reset, reset all vop registers. | |
1229 | */ | |
1230 | ahb_rst = devm_reset_control_get(vop->dev, "ahb"); | |
1231 | if (IS_ERR(ahb_rst)) { | |
1232 | dev_err(vop->dev, "failed to get ahb reset\n"); | |
1233 | ret = PTR_ERR(ahb_rst); | |
d7b53fd9 | 1234 | goto err_disable_aclk; |
2048e328 MY |
1235 | } |
1236 | reset_control_assert(ahb_rst); | |
1237 | usleep_range(10, 20); | |
1238 | reset_control_deassert(ahb_rst); | |
1239 | ||
1240 | memcpy(vop->regsbak, vop->regs, vop->len); | |
1241 | ||
1242 | for (i = 0; i < vop_data->table_size; i++) | |
1243 | vop_writel(vop, init_table[i].offset, init_table[i].value); | |
1244 | ||
1245 | for (i = 0; i < vop_data->win_size; i++) { | |
1246 | const struct vop_win_data *win = &vop_data->win[i]; | |
1247 | ||
1248 | VOP_WIN_SET(vop, win, enable, 0); | |
1249 | } | |
1250 | ||
1251 | vop_cfg_done(vop); | |
1252 | ||
1253 | /* | |
1254 | * do dclk_reset, let all config take affect. | |
1255 | */ | |
1256 | vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); | |
1257 | if (IS_ERR(vop->dclk_rst)) { | |
1258 | dev_err(vop->dev, "failed to get dclk reset\n"); | |
1259 | ret = PTR_ERR(vop->dclk_rst); | |
d7b53fd9 | 1260 | goto err_disable_aclk; |
2048e328 MY |
1261 | } |
1262 | reset_control_assert(vop->dclk_rst); | |
1263 | usleep_range(10, 20); | |
1264 | reset_control_deassert(vop->dclk_rst); | |
1265 | ||
1266 | clk_disable(vop->hclk); | |
d7b53fd9 | 1267 | clk_disable(vop->aclk); |
2048e328 | 1268 | |
31e980c5 | 1269 | vop->is_enabled = false; |
2048e328 MY |
1270 | |
1271 | return 0; | |
1272 | ||
d7b53fd9 SS |
1273 | err_disable_aclk: |
1274 | clk_disable_unprepare(vop->aclk); | |
2048e328 | 1275 | err_disable_hclk: |
d7b53fd9 | 1276 | clk_disable_unprepare(vop->hclk); |
2048e328 MY |
1277 | err_unprepare_dclk: |
1278 | clk_unprepare(vop->dclk); | |
2048e328 MY |
1279 | return ret; |
1280 | } | |
1281 | ||
1282 | /* | |
1283 | * Initialize the vop->win array elements. | |
1284 | */ | |
1285 | static void vop_win_init(struct vop *vop) | |
1286 | { | |
1287 | const struct vop_data *vop_data = vop->data; | |
1288 | unsigned int i; | |
1289 | ||
1290 | for (i = 0; i < vop_data->win_size; i++) { | |
1291 | struct vop_win *vop_win = &vop->win[i]; | |
1292 | const struct vop_win_data *win_data = &vop_data->win[i]; | |
1293 | ||
1294 | vop_win->data = win_data; | |
1295 | vop_win->vop = vop; | |
2048e328 MY |
1296 | } |
1297 | } | |
1298 | ||
1299 | static int vop_bind(struct device *dev, struct device *master, void *data) | |
1300 | { | |
1301 | struct platform_device *pdev = to_platform_device(dev); | |
2048e328 MY |
1302 | const struct vop_data *vop_data; |
1303 | struct drm_device *drm_dev = data; | |
1304 | struct vop *vop; | |
1305 | struct resource *res; | |
1306 | size_t alloc_size; | |
3ea68922 | 1307 | int ret, irq; |
2048e328 | 1308 | |
a67719d1 | 1309 | vop_data = of_device_get_match_data(dev); |
2048e328 MY |
1310 | if (!vop_data) |
1311 | return -ENODEV; | |
1312 | ||
1313 | /* Allocate vop struct and its vop_win array */ | |
1314 | alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; | |
1315 | vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); | |
1316 | if (!vop) | |
1317 | return -ENOMEM; | |
1318 | ||
1319 | vop->dev = dev; | |
1320 | vop->data = vop_data; | |
1321 | vop->drm_dev = drm_dev; | |
1322 | dev_set_drvdata(dev, vop); | |
1323 | ||
1324 | vop_win_init(vop); | |
1325 | ||
1326 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1327 | vop->len = resource_size(res); | |
1328 | vop->regs = devm_ioremap_resource(dev, res); | |
1329 | if (IS_ERR(vop->regs)) | |
1330 | return PTR_ERR(vop->regs); | |
1331 | ||
1332 | vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); | |
1333 | if (!vop->regsbak) | |
1334 | return -ENOMEM; | |
1335 | ||
1336 | ret = vop_initial(vop); | |
1337 | if (ret < 0) { | |
1338 | dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); | |
1339 | return ret; | |
1340 | } | |
1341 | ||
3ea68922 HS |
1342 | irq = platform_get_irq(pdev, 0); |
1343 | if (irq < 0) { | |
2048e328 | 1344 | dev_err(dev, "cannot find irq for vop\n"); |
3ea68922 | 1345 | return irq; |
2048e328 | 1346 | } |
3ea68922 | 1347 | vop->irq = (unsigned int)irq; |
2048e328 MY |
1348 | |
1349 | spin_lock_init(&vop->reg_lock); | |
1350 | spin_lock_init(&vop->irq_lock); | |
1351 | ||
1352 | mutex_init(&vop->vsync_mutex); | |
1353 | ||
63ebb9fa MY |
1354 | ret = devm_request_irq(dev, vop->irq, vop_isr, |
1355 | IRQF_SHARED, dev_name(dev), vop); | |
2048e328 MY |
1356 | if (ret) |
1357 | return ret; | |
1358 | ||
1359 | /* IRQ is initially disabled; it gets enabled in power_on */ | |
1360 | disable_irq(vop->irq); | |
1361 | ||
1362 | ret = vop_create_crtc(vop); | |
1363 | if (ret) | |
1364 | return ret; | |
1365 | ||
1366 | pm_runtime_enable(&pdev->dev); | |
1367 | return 0; | |
1368 | } | |
1369 | ||
1370 | static void vop_unbind(struct device *dev, struct device *master, void *data) | |
1371 | { | |
1372 | struct vop *vop = dev_get_drvdata(dev); | |
1373 | ||
1374 | pm_runtime_disable(dev); | |
1375 | vop_destroy_crtc(vop); | |
1376 | } | |
1377 | ||
a67719d1 | 1378 | const struct component_ops vop_component_ops = { |
2048e328 MY |
1379 | .bind = vop_bind, |
1380 | .unbind = vop_unbind, | |
1381 | }; |