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Commit | Line | Data |
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2048e328 MY |
1 | /* |
2 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd | |
3 | * Author:Mark Yao <mark.yao@rock-chips.com> | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <drm/drm.h> | |
16 | #include <drm/drmP.h> | |
63ebb9fa | 17 | #include <drm/drm_atomic.h> |
2048e328 MY |
18 | #include <drm/drm_crtc.h> |
19 | #include <drm/drm_crtc_helper.h> | |
20 | #include <drm/drm_plane_helper.h> | |
21 | ||
22 | #include <linux/kernel.h> | |
00fe6148 | 23 | #include <linux/module.h> |
2048e328 MY |
24 | #include <linux/platform_device.h> |
25 | #include <linux/clk.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/component.h> | |
30 | ||
31 | #include <linux/reset.h> | |
32 | #include <linux/delay.h> | |
33 | ||
34 | #include "rockchip_drm_drv.h" | |
35 | #include "rockchip_drm_gem.h" | |
36 | #include "rockchip_drm_fb.h" | |
37 | #include "rockchip_drm_vop.h" | |
38 | ||
2048e328 MY |
39 | #define __REG_SET_RELAXED(x, off, mask, shift, v) \ |
40 | vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) | |
41 | #define __REG_SET_NORMAL(x, off, mask, shift, v) \ | |
42 | vop_mask_write(x, off, (mask) << shift, (v) << shift) | |
43 | ||
44 | #define REG_SET(x, base, reg, v, mode) \ | |
45 | __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) | |
c7647f86 JK |
46 | #define REG_SET_MASK(x, base, reg, mask, v, mode) \ |
47 | __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) | |
2048e328 MY |
48 | |
49 | #define VOP_WIN_SET(x, win, name, v) \ | |
50 | REG_SET(x, win->base, win->phy->name, v, RELAXED) | |
4c156c21 MY |
51 | #define VOP_SCL_SET(x, win, name, v) \ |
52 | REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) | |
1194fffb MY |
53 | #define VOP_SCL_SET_EXT(x, win, name, v) \ |
54 | REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) | |
2048e328 MY |
55 | #define VOP_CTRL_SET(x, name, v) \ |
56 | REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) | |
57 | ||
dbb3d944 MY |
58 | #define VOP_INTR_GET(vop, name) \ |
59 | vop_read_reg(vop, 0, &vop->data->ctrl->name) | |
60 | ||
c7647f86 JK |
61 | #define VOP_INTR_SET(vop, name, mask, v) \ |
62 | REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) | |
dbb3d944 MY |
63 | #define VOP_INTR_SET_TYPE(vop, name, type, v) \ |
64 | do { \ | |
c7647f86 | 65 | int i, reg = 0, mask = 0; \ |
dbb3d944 | 66 | for (i = 0; i < vop->data->intr->nintrs; i++) { \ |
c7647f86 | 67 | if (vop->data->intr->intrs[i] & type) { \ |
dbb3d944 | 68 | reg |= (v) << i; \ |
c7647f86 JK |
69 | mask |= 1 << i; \ |
70 | } \ | |
dbb3d944 | 71 | } \ |
c7647f86 | 72 | VOP_INTR_SET(vop, name, mask, reg); \ |
dbb3d944 MY |
73 | } while (0) |
74 | #define VOP_INTR_GET_TYPE(vop, name, type) \ | |
75 | vop_get_intr_type(vop, &vop->data->intr->name, type) | |
76 | ||
2048e328 MY |
77 | #define VOP_WIN_GET(x, win, name) \ |
78 | vop_read_reg(x, win->base, &win->phy->name) | |
79 | ||
80 | #define VOP_WIN_GET_YRGBADDR(vop, win) \ | |
81 | vop_readl(vop, win->base + win->phy->yrgb_mst.offset) | |
82 | ||
83 | #define to_vop(x) container_of(x, struct vop, crtc) | |
84 | #define to_vop_win(x) container_of(x, struct vop_win, base) | |
63ebb9fa | 85 | #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) |
2048e328 | 86 | |
63ebb9fa MY |
87 | struct vop_plane_state { |
88 | struct drm_plane_state base; | |
89 | int format; | |
2048e328 | 90 | dma_addr_t yrgb_mst; |
63ebb9fa | 91 | bool enable; |
2048e328 MY |
92 | }; |
93 | ||
94 | struct vop_win { | |
95 | struct drm_plane base; | |
96 | const struct vop_win_data *data; | |
97 | struct vop *vop; | |
98 | ||
4f9d39a7 DV |
99 | /* protected by dev->event_lock */ |
100 | bool enable; | |
101 | dma_addr_t yrgb_mst; | |
2048e328 MY |
102 | }; |
103 | ||
104 | struct vop { | |
105 | struct drm_crtc crtc; | |
106 | struct device *dev; | |
107 | struct drm_device *drm_dev; | |
31e980c5 | 108 | bool is_enabled; |
2048e328 | 109 | |
2048e328 MY |
110 | /* mutex vsync_ work */ |
111 | struct mutex vsync_mutex; | |
112 | bool vsync_work_pending; | |
1067219b | 113 | struct completion dsp_hold_completion; |
63ebb9fa | 114 | struct completion wait_update_complete; |
4f9d39a7 DV |
115 | |
116 | /* protected by dev->event_lock */ | |
63ebb9fa | 117 | struct drm_pending_vblank_event *event; |
2048e328 MY |
118 | |
119 | const struct vop_data *data; | |
120 | ||
121 | uint32_t *regsbak; | |
122 | void __iomem *regs; | |
123 | ||
124 | /* physical map length of vop register */ | |
125 | uint32_t len; | |
126 | ||
127 | /* one time only one process allowed to config the register */ | |
128 | spinlock_t reg_lock; | |
129 | /* lock vop irq reg */ | |
130 | spinlock_t irq_lock; | |
131 | ||
132 | unsigned int irq; | |
133 | ||
134 | /* vop AHP clk */ | |
135 | struct clk *hclk; | |
136 | /* vop dclk */ | |
137 | struct clk *dclk; | |
138 | /* vop share memory frequency */ | |
139 | struct clk *aclk; | |
140 | ||
141 | /* vop dclk reset */ | |
142 | struct reset_control *dclk_rst; | |
143 | ||
2048e328 MY |
144 | struct vop_win win[]; |
145 | }; | |
146 | ||
2048e328 MY |
147 | static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) |
148 | { | |
149 | writel(v, vop->regs + offset); | |
150 | vop->regsbak[offset >> 2] = v; | |
151 | } | |
152 | ||
153 | static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) | |
154 | { | |
155 | return readl(vop->regs + offset); | |
156 | } | |
157 | ||
158 | static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, | |
159 | const struct vop_reg *reg) | |
160 | { | |
161 | return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; | |
162 | } | |
163 | ||
2048e328 MY |
164 | static inline void vop_mask_write(struct vop *vop, uint32_t offset, |
165 | uint32_t mask, uint32_t v) | |
166 | { | |
167 | if (mask) { | |
168 | uint32_t cached_val = vop->regsbak[offset >> 2]; | |
169 | ||
170 | cached_val = (cached_val & ~mask) | v; | |
171 | writel(cached_val, vop->regs + offset); | |
172 | vop->regsbak[offset >> 2] = cached_val; | |
173 | } | |
174 | } | |
175 | ||
176 | static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, | |
177 | uint32_t mask, uint32_t v) | |
178 | { | |
179 | if (mask) { | |
180 | uint32_t cached_val = vop->regsbak[offset >> 2]; | |
181 | ||
182 | cached_val = (cached_val & ~mask) | v; | |
183 | writel_relaxed(cached_val, vop->regs + offset); | |
184 | vop->regsbak[offset >> 2] = cached_val; | |
185 | } | |
186 | } | |
187 | ||
dbb3d944 MY |
188 | static inline uint32_t vop_get_intr_type(struct vop *vop, |
189 | const struct vop_reg *reg, int type) | |
190 | { | |
191 | uint32_t i, ret = 0; | |
192 | uint32_t regs = vop_read_reg(vop, 0, reg); | |
193 | ||
194 | for (i = 0; i < vop->data->intr->nintrs; i++) { | |
195 | if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) | |
196 | ret |= vop->data->intr->intrs[i]; | |
197 | } | |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
0cf33fe3 MY |
202 | static inline void vop_cfg_done(struct vop *vop) |
203 | { | |
204 | VOP_CTRL_SET(vop, cfg_done, 1); | |
205 | } | |
206 | ||
85a359f2 TF |
207 | static bool has_rb_swapped(uint32_t format) |
208 | { | |
209 | switch (format) { | |
210 | case DRM_FORMAT_XBGR8888: | |
211 | case DRM_FORMAT_ABGR8888: | |
212 | case DRM_FORMAT_BGR888: | |
213 | case DRM_FORMAT_BGR565: | |
214 | return true; | |
215 | default: | |
216 | return false; | |
217 | } | |
218 | } | |
219 | ||
2048e328 MY |
220 | static enum vop_data_format vop_convert_format(uint32_t format) |
221 | { | |
222 | switch (format) { | |
223 | case DRM_FORMAT_XRGB8888: | |
224 | case DRM_FORMAT_ARGB8888: | |
85a359f2 TF |
225 | case DRM_FORMAT_XBGR8888: |
226 | case DRM_FORMAT_ABGR8888: | |
2048e328 MY |
227 | return VOP_FMT_ARGB8888; |
228 | case DRM_FORMAT_RGB888: | |
85a359f2 | 229 | case DRM_FORMAT_BGR888: |
2048e328 MY |
230 | return VOP_FMT_RGB888; |
231 | case DRM_FORMAT_RGB565: | |
85a359f2 | 232 | case DRM_FORMAT_BGR565: |
2048e328 MY |
233 | return VOP_FMT_RGB565; |
234 | case DRM_FORMAT_NV12: | |
235 | return VOP_FMT_YUV420SP; | |
236 | case DRM_FORMAT_NV16: | |
237 | return VOP_FMT_YUV422SP; | |
238 | case DRM_FORMAT_NV24: | |
239 | return VOP_FMT_YUV444SP; | |
240 | default: | |
241 | DRM_ERROR("unsupport format[%08x]\n", format); | |
242 | return -EINVAL; | |
243 | } | |
244 | } | |
245 | ||
84c7f8ca MY |
246 | static bool is_yuv_support(uint32_t format) |
247 | { | |
248 | switch (format) { | |
249 | case DRM_FORMAT_NV12: | |
250 | case DRM_FORMAT_NV16: | |
251 | case DRM_FORMAT_NV24: | |
252 | return true; | |
253 | default: | |
254 | return false; | |
255 | } | |
256 | } | |
257 | ||
2048e328 MY |
258 | static bool is_alpha_support(uint32_t format) |
259 | { | |
260 | switch (format) { | |
261 | case DRM_FORMAT_ARGB8888: | |
85a359f2 | 262 | case DRM_FORMAT_ABGR8888: |
2048e328 MY |
263 | return true; |
264 | default: | |
265 | return false; | |
266 | } | |
267 | } | |
268 | ||
4c156c21 MY |
269 | static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, |
270 | uint32_t dst, bool is_horizontal, | |
271 | int vsu_mode, int *vskiplines) | |
272 | { | |
273 | uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; | |
274 | ||
275 | if (is_horizontal) { | |
276 | if (mode == SCALE_UP) | |
277 | val = GET_SCL_FT_BIC(src, dst); | |
278 | else if (mode == SCALE_DOWN) | |
279 | val = GET_SCL_FT_BILI_DN(src, dst); | |
280 | } else { | |
281 | if (mode == SCALE_UP) { | |
282 | if (vsu_mode == SCALE_UP_BIL) | |
283 | val = GET_SCL_FT_BILI_UP(src, dst); | |
284 | else | |
285 | val = GET_SCL_FT_BIC(src, dst); | |
286 | } else if (mode == SCALE_DOWN) { | |
287 | if (vskiplines) { | |
288 | *vskiplines = scl_get_vskiplines(src, dst); | |
289 | val = scl_get_bili_dn_vskip(src, dst, | |
290 | *vskiplines); | |
291 | } else { | |
292 | val = GET_SCL_FT_BILI_DN(src, dst); | |
293 | } | |
294 | } | |
295 | } | |
296 | ||
297 | return val; | |
298 | } | |
299 | ||
300 | static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, | |
301 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, | |
302 | uint32_t dst_h, uint32_t pixel_format) | |
303 | { | |
304 | uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; | |
305 | uint16_t cbcr_hor_scl_mode = SCALE_NONE; | |
306 | uint16_t cbcr_ver_scl_mode = SCALE_NONE; | |
307 | int hsub = drm_format_horz_chroma_subsampling(pixel_format); | |
308 | int vsub = drm_format_vert_chroma_subsampling(pixel_format); | |
309 | bool is_yuv = is_yuv_support(pixel_format); | |
310 | uint16_t cbcr_src_w = src_w / hsub; | |
311 | uint16_t cbcr_src_h = src_h / vsub; | |
312 | uint16_t vsu_mode; | |
313 | uint16_t lb_mode; | |
314 | uint32_t val; | |
2db00cf5 | 315 | int vskiplines = 0; |
4c156c21 MY |
316 | |
317 | if (dst_w > 3840) { | |
318 | DRM_ERROR("Maximum destination width (3840) exceeded\n"); | |
319 | return; | |
320 | } | |
321 | ||
1194fffb MY |
322 | if (!win->phy->scl->ext) { |
323 | VOP_SCL_SET(vop, win, scale_yrgb_x, | |
324 | scl_cal_scale2(src_w, dst_w)); | |
325 | VOP_SCL_SET(vop, win, scale_yrgb_y, | |
326 | scl_cal_scale2(src_h, dst_h)); | |
327 | if (is_yuv) { | |
328 | VOP_SCL_SET(vop, win, scale_cbcr_x, | |
ee8662fc | 329 | scl_cal_scale2(cbcr_src_w, dst_w)); |
1194fffb | 330 | VOP_SCL_SET(vop, win, scale_cbcr_y, |
ee8662fc | 331 | scl_cal_scale2(cbcr_src_h, dst_h)); |
1194fffb MY |
332 | } |
333 | return; | |
334 | } | |
335 | ||
4c156c21 MY |
336 | yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); |
337 | yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); | |
338 | ||
339 | if (is_yuv) { | |
340 | cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); | |
341 | cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); | |
342 | if (cbcr_hor_scl_mode == SCALE_DOWN) | |
343 | lb_mode = scl_vop_cal_lb_mode(dst_w, true); | |
344 | else | |
345 | lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); | |
346 | } else { | |
347 | if (yrgb_hor_scl_mode == SCALE_DOWN) | |
348 | lb_mode = scl_vop_cal_lb_mode(dst_w, false); | |
349 | else | |
350 | lb_mode = scl_vop_cal_lb_mode(src_w, false); | |
351 | } | |
352 | ||
1194fffb | 353 | VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); |
4c156c21 MY |
354 | if (lb_mode == LB_RGB_3840X2) { |
355 | if (yrgb_ver_scl_mode != SCALE_NONE) { | |
356 | DRM_ERROR("ERROR : not allow yrgb ver scale\n"); | |
357 | return; | |
358 | } | |
359 | if (cbcr_ver_scl_mode != SCALE_NONE) { | |
360 | DRM_ERROR("ERROR : not allow cbcr ver scale\n"); | |
361 | return; | |
362 | } | |
363 | vsu_mode = SCALE_UP_BIL; | |
364 | } else if (lb_mode == LB_RGB_2560X4) { | |
365 | vsu_mode = SCALE_UP_BIL; | |
366 | } else { | |
367 | vsu_mode = SCALE_UP_BIC; | |
368 | } | |
369 | ||
370 | val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, | |
371 | true, 0, NULL); | |
372 | VOP_SCL_SET(vop, win, scale_yrgb_x, val); | |
373 | val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, | |
374 | false, vsu_mode, &vskiplines); | |
375 | VOP_SCL_SET(vop, win, scale_yrgb_y, val); | |
376 | ||
1194fffb MY |
377 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); |
378 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); | |
4c156c21 | 379 | |
1194fffb MY |
380 | VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); |
381 | VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); | |
382 | VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); | |
383 | VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); | |
384 | VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); | |
4c156c21 MY |
385 | if (is_yuv) { |
386 | val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, | |
387 | dst_w, true, 0, NULL); | |
388 | VOP_SCL_SET(vop, win, scale_cbcr_x, val); | |
389 | val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, | |
390 | dst_h, false, vsu_mode, &vskiplines); | |
391 | VOP_SCL_SET(vop, win, scale_cbcr_y, val); | |
392 | ||
1194fffb MY |
393 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); |
394 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); | |
395 | VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); | |
396 | VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); | |
397 | VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); | |
398 | VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); | |
399 | VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); | |
4c156c21 MY |
400 | } |
401 | } | |
402 | ||
1067219b MY |
403 | static void vop_dsp_hold_valid_irq_enable(struct vop *vop) |
404 | { | |
405 | unsigned long flags; | |
406 | ||
407 | if (WARN_ON(!vop->is_enabled)) | |
408 | return; | |
409 | ||
410 | spin_lock_irqsave(&vop->irq_lock, flags); | |
411 | ||
dbb3d944 | 412 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); |
1067219b MY |
413 | |
414 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
415 | } | |
416 | ||
417 | static void vop_dsp_hold_valid_irq_disable(struct vop *vop) | |
418 | { | |
419 | unsigned long flags; | |
420 | ||
421 | if (WARN_ON(!vop->is_enabled)) | |
422 | return; | |
423 | ||
424 | spin_lock_irqsave(&vop->irq_lock, flags); | |
425 | ||
dbb3d944 | 426 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); |
1067219b MY |
427 | |
428 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
429 | } | |
430 | ||
63ebb9fa | 431 | static void vop_enable(struct drm_crtc *crtc) |
2048e328 MY |
432 | { |
433 | struct vop *vop = to_vop(crtc); | |
434 | int ret; | |
435 | ||
5d82d1a7 MY |
436 | ret = pm_runtime_get_sync(vop->dev); |
437 | if (ret < 0) { | |
438 | dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); | |
439 | return; | |
440 | } | |
441 | ||
2048e328 MY |
442 | ret = clk_enable(vop->hclk); |
443 | if (ret < 0) { | |
444 | dev_err(vop->dev, "failed to enable hclk - %d\n", ret); | |
445 | return; | |
446 | } | |
447 | ||
448 | ret = clk_enable(vop->dclk); | |
449 | if (ret < 0) { | |
450 | dev_err(vop->dev, "failed to enable dclk - %d\n", ret); | |
451 | goto err_disable_hclk; | |
452 | } | |
453 | ||
454 | ret = clk_enable(vop->aclk); | |
455 | if (ret < 0) { | |
456 | dev_err(vop->dev, "failed to enable aclk - %d\n", ret); | |
457 | goto err_disable_dclk; | |
458 | } | |
459 | ||
460 | /* | |
461 | * Slave iommu shares power, irq and clock with vop. It was associated | |
462 | * automatically with this master device via common driver code. | |
463 | * Now that we have enabled the clock we attach it to the shared drm | |
464 | * mapping. | |
465 | */ | |
466 | ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); | |
467 | if (ret) { | |
468 | dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); | |
469 | goto err_disable_aclk; | |
470 | } | |
471 | ||
77faa161 | 472 | memcpy(vop->regs, vop->regsbak, vop->len); |
52ab7891 MY |
473 | /* |
474 | * At here, vop clock & iommu is enable, R/W vop regs would be safe. | |
475 | */ | |
476 | vop->is_enabled = true; | |
477 | ||
2048e328 MY |
478 | spin_lock(&vop->reg_lock); |
479 | ||
480 | VOP_CTRL_SET(vop, standby, 0); | |
481 | ||
482 | spin_unlock(&vop->reg_lock); | |
483 | ||
484 | enable_irq(vop->irq); | |
485 | ||
b5f7b755 | 486 | drm_crtc_vblank_on(crtc); |
2048e328 MY |
487 | |
488 | return; | |
489 | ||
490 | err_disable_aclk: | |
491 | clk_disable(vop->aclk); | |
492 | err_disable_dclk: | |
493 | clk_disable(vop->dclk); | |
494 | err_disable_hclk: | |
495 | clk_disable(vop->hclk); | |
496 | } | |
497 | ||
0ad3675d | 498 | static void vop_crtc_disable(struct drm_crtc *crtc) |
2048e328 MY |
499 | { |
500 | struct vop *vop = to_vop(crtc); | |
3ed6c649 | 501 | int i; |
2048e328 | 502 | |
893b6cad DV |
503 | WARN_ON(vop->event); |
504 | ||
3ed6c649 TV |
505 | /* |
506 | * We need to make sure that all windows are disabled before we | |
507 | * disable that crtc. Otherwise we might try to scan from a destroyed | |
508 | * buffer later. | |
509 | */ | |
510 | for (i = 0; i < vop->data->win_size; i++) { | |
511 | struct vop_win *vop_win = &vop->win[i]; | |
512 | const struct vop_win_data *win = vop_win->data; | |
513 | ||
514 | spin_lock(&vop->reg_lock); | |
515 | VOP_WIN_SET(vop, win, enable, 0); | |
516 | spin_unlock(&vop->reg_lock); | |
517 | } | |
518 | ||
b5f7b755 | 519 | drm_crtc_vblank_off(crtc); |
2048e328 | 520 | |
2048e328 | 521 | /* |
1067219b MY |
522 | * Vop standby will take effect at end of current frame, |
523 | * if dsp hold valid irq happen, it means standby complete. | |
524 | * | |
525 | * we must wait standby complete when we want to disable aclk, | |
526 | * if not, memory bus maybe dead. | |
2048e328 | 527 | */ |
1067219b MY |
528 | reinit_completion(&vop->dsp_hold_completion); |
529 | vop_dsp_hold_valid_irq_enable(vop); | |
530 | ||
2048e328 MY |
531 | spin_lock(&vop->reg_lock); |
532 | ||
533 | VOP_CTRL_SET(vop, standby, 1); | |
534 | ||
535 | spin_unlock(&vop->reg_lock); | |
52ab7891 | 536 | |
1067219b MY |
537 | wait_for_completion(&vop->dsp_hold_completion); |
538 | ||
539 | vop_dsp_hold_valid_irq_disable(vop); | |
540 | ||
541 | disable_irq(vop->irq); | |
542 | ||
52ab7891 | 543 | vop->is_enabled = false; |
1067219b | 544 | |
2048e328 | 545 | /* |
1067219b | 546 | * vop standby complete, so iommu detach is safe. |
2048e328 | 547 | */ |
2048e328 MY |
548 | rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); |
549 | ||
1067219b | 550 | clk_disable(vop->dclk); |
2048e328 MY |
551 | clk_disable(vop->aclk); |
552 | clk_disable(vop->hclk); | |
5d82d1a7 | 553 | pm_runtime_put(vop->dev); |
893b6cad DV |
554 | |
555 | if (crtc->state->event && !crtc->state->active) { | |
556 | spin_lock_irq(&crtc->dev->event_lock); | |
557 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
558 | spin_unlock_irq(&crtc->dev->event_lock); | |
559 | ||
560 | crtc->state->event = NULL; | |
561 | } | |
2048e328 MY |
562 | } |
563 | ||
63ebb9fa | 564 | static void vop_plane_destroy(struct drm_plane *plane) |
2048e328 | 565 | { |
63ebb9fa | 566 | drm_plane_cleanup(plane); |
2048e328 MY |
567 | } |
568 | ||
44d0237a MY |
569 | static int vop_plane_prepare_fb(struct drm_plane *plane, |
570 | const struct drm_plane_state *new_state) | |
571 | { | |
572 | if (plane->state->fb) | |
573 | drm_framebuffer_reference(plane->state->fb); | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static void vop_plane_cleanup_fb(struct drm_plane *plane, | |
579 | const struct drm_plane_state *old_state) | |
580 | { | |
581 | if (old_state->fb) | |
582 | drm_framebuffer_unreference(old_state->fb); | |
583 | } | |
584 | ||
63ebb9fa MY |
585 | static int vop_plane_atomic_check(struct drm_plane *plane, |
586 | struct drm_plane_state *state) | |
2048e328 | 587 | { |
63ebb9fa | 588 | struct drm_crtc *crtc = state->crtc; |
92915da6 | 589 | struct drm_crtc_state *crtc_state; |
63ebb9fa | 590 | struct drm_framebuffer *fb = state->fb; |
2048e328 | 591 | struct vop_win *vop_win = to_vop_win(plane); |
63ebb9fa | 592 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); |
2048e328 | 593 | const struct vop_win_data *win = vop_win->data; |
2048e328 MY |
594 | bool visible; |
595 | int ret; | |
ac92028e VS |
596 | struct drm_rect *dest = &state->dst; |
597 | struct drm_rect *src = &state->src; | |
63ebb9fa | 598 | struct drm_rect clip; |
4c156c21 MY |
599 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : |
600 | DRM_PLANE_HELPER_NO_SCALING; | |
601 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : | |
602 | DRM_PLANE_HELPER_NO_SCALING; | |
2048e328 | 603 | |
63ebb9fa MY |
604 | if (!crtc || !fb) |
605 | goto out_disable; | |
92915da6 JK |
606 | |
607 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); | |
608 | if (WARN_ON(!crtc_state)) | |
609 | return -EINVAL; | |
610 | ||
63ebb9fa MY |
611 | src->x1 = state->src_x; |
612 | src->y1 = state->src_y; | |
613 | src->x2 = state->src_x + state->src_w; | |
614 | src->y2 = state->src_y + state->src_h; | |
615 | dest->x1 = state->crtc_x; | |
616 | dest->y1 = state->crtc_y; | |
617 | dest->x2 = state->crtc_x + state->crtc_w; | |
618 | dest->y2 = state->crtc_y + state->crtc_h; | |
619 | ||
620 | clip.x1 = 0; | |
621 | clip.y1 = 0; | |
92915da6 JK |
622 | clip.x2 = crtc_state->adjusted_mode.hdisplay; |
623 | clip.y2 = crtc_state->adjusted_mode.vdisplay; | |
63ebb9fa MY |
624 | |
625 | ret = drm_plane_helper_check_update(plane, crtc, state->fb, | |
626 | src, dest, &clip, | |
9b8b013d | 627 | state->rotation, |
4c156c21 MY |
628 | min_scale, |
629 | max_scale, | |
63ebb9fa | 630 | true, true, &visible); |
2048e328 MY |
631 | if (ret) |
632 | return ret; | |
633 | ||
634 | if (!visible) | |
63ebb9fa | 635 | goto out_disable; |
2048e328 | 636 | |
63ebb9fa MY |
637 | vop_plane_state->format = vop_convert_format(fb->pixel_format); |
638 | if (vop_plane_state->format < 0) | |
639 | return vop_plane_state->format; | |
84c7f8ca | 640 | |
63ebb9fa MY |
641 | /* |
642 | * Src.x1 can be odd when do clip, but yuv plane start point | |
643 | * need align with 2 pixel. | |
644 | */ | |
645 | if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) | |
2048e328 | 646 | return -EINVAL; |
2048e328 | 647 | |
63ebb9fa | 648 | vop_plane_state->enable = true; |
2048e328 | 649 | |
63ebb9fa | 650 | return 0; |
84c7f8ca | 651 | |
63ebb9fa MY |
652 | out_disable: |
653 | vop_plane_state->enable = false; | |
654 | return 0; | |
655 | } | |
2048e328 | 656 | |
63ebb9fa MY |
657 | static void vop_plane_atomic_disable(struct drm_plane *plane, |
658 | struct drm_plane_state *old_state) | |
659 | { | |
660 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); | |
661 | struct vop_win *vop_win = to_vop_win(plane); | |
662 | const struct vop_win_data *win = vop_win->data; | |
663 | struct vop *vop = to_vop(old_state->crtc); | |
2048e328 | 664 | |
63ebb9fa MY |
665 | if (!old_state->crtc) |
666 | return; | |
2048e328 | 667 | |
4f9d39a7 DV |
668 | spin_lock_irq(&plane->dev->event_lock); |
669 | vop_win->enable = false; | |
670 | vop_win->yrgb_mst = 0; | |
671 | spin_unlock_irq(&plane->dev->event_lock); | |
672 | ||
63ebb9fa | 673 | spin_lock(&vop->reg_lock); |
2048e328 | 674 | |
63ebb9fa | 675 | VOP_WIN_SET(vop, win, enable, 0); |
84c7f8ca | 676 | |
63ebb9fa | 677 | spin_unlock(&vop->reg_lock); |
84c7f8ca | 678 | |
63ebb9fa MY |
679 | vop_plane_state->enable = false; |
680 | } | |
84c7f8ca | 681 | |
63ebb9fa MY |
682 | static void vop_plane_atomic_update(struct drm_plane *plane, |
683 | struct drm_plane_state *old_state) | |
684 | { | |
685 | struct drm_plane_state *state = plane->state; | |
686 | struct drm_crtc *crtc = state->crtc; | |
687 | struct vop_win *vop_win = to_vop_win(plane); | |
688 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); | |
689 | const struct vop_win_data *win = vop_win->data; | |
690 | struct vop *vop = to_vop(state->crtc); | |
691 | struct drm_framebuffer *fb = state->fb; | |
692 | unsigned int actual_w, actual_h; | |
693 | unsigned int dsp_stx, dsp_sty; | |
694 | uint32_t act_info, dsp_info, dsp_st; | |
ac92028e VS |
695 | struct drm_rect *src = &state->src; |
696 | struct drm_rect *dest = &state->dst; | |
63ebb9fa MY |
697 | struct drm_gem_object *obj, *uv_obj; |
698 | struct rockchip_gem_object *rk_obj, *rk_uv_obj; | |
699 | unsigned long offset; | |
700 | dma_addr_t dma_addr; | |
701 | uint32_t val; | |
702 | bool rb_swap; | |
84c7f8ca | 703 | |
2048e328 | 704 | /* |
63ebb9fa | 705 | * can't update plane when vop is disabled. |
2048e328 | 706 | */ |
4f9d39a7 | 707 | if (WARN_ON(!crtc)) |
63ebb9fa | 708 | return; |
2048e328 | 709 | |
63ebb9fa MY |
710 | if (WARN_ON(!vop->is_enabled)) |
711 | return; | |
2048e328 | 712 | |
63ebb9fa MY |
713 | if (!vop_plane_state->enable) { |
714 | vop_plane_atomic_disable(plane, old_state); | |
715 | return; | |
2048e328 | 716 | } |
63ebb9fa MY |
717 | |
718 | obj = rockchip_fb_get_gem_obj(fb, 0); | |
719 | rk_obj = to_rockchip_obj(obj); | |
720 | ||
721 | actual_w = drm_rect_width(src) >> 16; | |
722 | actual_h = drm_rect_height(src) >> 16; | |
723 | act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); | |
724 | ||
725 | dsp_info = (drm_rect_height(dest) - 1) << 16; | |
726 | dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; | |
727 | ||
728 | dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; | |
729 | dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; | |
730 | dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); | |
731 | ||
732 | offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); | |
733 | offset += (src->y1 >> 16) * fb->pitches[0]; | |
734 | vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; | |
2048e328 | 735 | |
4f9d39a7 DV |
736 | spin_lock_irq(&plane->dev->event_lock); |
737 | vop_win->enable = true; | |
738 | vop_win->yrgb_mst = vop_plane_state->yrgb_mst; | |
739 | spin_unlock_irq(&plane->dev->event_lock); | |
740 | ||
2048e328 MY |
741 | spin_lock(&vop->reg_lock); |
742 | ||
63ebb9fa MY |
743 | VOP_WIN_SET(vop, win, format, vop_plane_state->format); |
744 | VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); | |
745 | VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); | |
746 | if (is_yuv_support(fb->pixel_format)) { | |
747 | int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); | |
748 | int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); | |
749 | int bpp = drm_format_plane_cpp(fb->pixel_format, 1); | |
750 | ||
751 | uv_obj = rockchip_fb_get_gem_obj(fb, 1); | |
752 | rk_uv_obj = to_rockchip_obj(uv_obj); | |
753 | ||
754 | offset = (src->x1 >> 16) * bpp / hsub; | |
755 | offset += (src->y1 >> 16) * fb->pitches[1] / vsub; | |
756 | ||
757 | dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; | |
758 | VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); | |
759 | VOP_WIN_SET(vop, win, uv_mst, dma_addr); | |
84c7f8ca | 760 | } |
4c156c21 MY |
761 | |
762 | if (win->phy->scl) | |
763 | scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, | |
63ebb9fa | 764 | drm_rect_width(dest), drm_rect_height(dest), |
4c156c21 MY |
765 | fb->pixel_format); |
766 | ||
63ebb9fa MY |
767 | VOP_WIN_SET(vop, win, act_info, act_info); |
768 | VOP_WIN_SET(vop, win, dsp_info, dsp_info); | |
769 | VOP_WIN_SET(vop, win, dsp_st, dsp_st); | |
4c156c21 | 770 | |
63ebb9fa | 771 | rb_swap = has_rb_swapped(fb->pixel_format); |
85a359f2 | 772 | VOP_WIN_SET(vop, win, rb_swap, rb_swap); |
2048e328 | 773 | |
63ebb9fa | 774 | if (is_alpha_support(fb->pixel_format)) { |
2048e328 MY |
775 | VOP_WIN_SET(vop, win, dst_alpha_ctl, |
776 | DST_FACTOR_M0(ALPHA_SRC_INVERSE)); | |
777 | val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | | |
778 | SRC_ALPHA_M0(ALPHA_STRAIGHT) | | |
779 | SRC_BLEND_M0(ALPHA_PER_PIX) | | |
780 | SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | | |
781 | SRC_FACTOR_M0(ALPHA_ONE); | |
782 | VOP_WIN_SET(vop, win, src_alpha_ctl, val); | |
783 | } else { | |
784 | VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); | |
785 | } | |
786 | ||
787 | VOP_WIN_SET(vop, win, enable, 1); | |
2048e328 | 788 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
789 | } |
790 | ||
63ebb9fa | 791 | static const struct drm_plane_helper_funcs plane_helper_funcs = { |
44d0237a MY |
792 | .prepare_fb = vop_plane_prepare_fb, |
793 | .cleanup_fb = vop_plane_cleanup_fb, | |
63ebb9fa MY |
794 | .atomic_check = vop_plane_atomic_check, |
795 | .atomic_update = vop_plane_atomic_update, | |
796 | .atomic_disable = vop_plane_atomic_disable, | |
797 | }; | |
2048e328 | 798 | |
8ff490ae | 799 | static void vop_atomic_plane_reset(struct drm_plane *plane) |
2048e328 | 800 | { |
63ebb9fa MY |
801 | struct vop_plane_state *vop_plane_state = |
802 | to_vop_plane_state(plane->state); | |
2048e328 | 803 | |
63ebb9fa MY |
804 | if (plane->state && plane->state->fb) |
805 | drm_framebuffer_unreference(plane->state->fb); | |
806 | ||
807 | kfree(vop_plane_state); | |
808 | vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); | |
809 | if (!vop_plane_state) | |
810 | return; | |
2048e328 | 811 | |
63ebb9fa MY |
812 | plane->state = &vop_plane_state->base; |
813 | plane->state->plane = plane; | |
2048e328 MY |
814 | } |
815 | ||
8ff490ae | 816 | static struct drm_plane_state * |
63ebb9fa | 817 | vop_atomic_plane_duplicate_state(struct drm_plane *plane) |
2048e328 | 818 | { |
63ebb9fa MY |
819 | struct vop_plane_state *old_vop_plane_state; |
820 | struct vop_plane_state *vop_plane_state; | |
2048e328 | 821 | |
63ebb9fa MY |
822 | if (WARN_ON(!plane->state)) |
823 | return NULL; | |
2048e328 | 824 | |
63ebb9fa MY |
825 | old_vop_plane_state = to_vop_plane_state(plane->state); |
826 | vop_plane_state = kmemdup(old_vop_plane_state, | |
827 | sizeof(*vop_plane_state), GFP_KERNEL); | |
828 | if (!vop_plane_state) | |
829 | return NULL; | |
2048e328 | 830 | |
63ebb9fa MY |
831 | __drm_atomic_helper_plane_duplicate_state(plane, |
832 | &vop_plane_state->base); | |
2048e328 | 833 | |
63ebb9fa | 834 | return &vop_plane_state->base; |
2048e328 MY |
835 | } |
836 | ||
63ebb9fa MY |
837 | static void vop_atomic_plane_destroy_state(struct drm_plane *plane, |
838 | struct drm_plane_state *state) | |
2048e328 | 839 | { |
63ebb9fa MY |
840 | struct vop_plane_state *vop_state = to_vop_plane_state(state); |
841 | ||
2f701695 | 842 | __drm_atomic_helper_plane_destroy_state(state); |
63ebb9fa MY |
843 | |
844 | kfree(vop_state); | |
2048e328 MY |
845 | } |
846 | ||
847 | static const struct drm_plane_funcs vop_plane_funcs = { | |
63ebb9fa MY |
848 | .update_plane = drm_atomic_helper_update_plane, |
849 | .disable_plane = drm_atomic_helper_disable_plane, | |
2048e328 | 850 | .destroy = vop_plane_destroy, |
63ebb9fa MY |
851 | .reset = vop_atomic_plane_reset, |
852 | .atomic_duplicate_state = vop_atomic_plane_duplicate_state, | |
853 | .atomic_destroy_state = vop_atomic_plane_destroy_state, | |
2048e328 MY |
854 | }; |
855 | ||
2048e328 MY |
856 | static int vop_crtc_enable_vblank(struct drm_crtc *crtc) |
857 | { | |
858 | struct vop *vop = to_vop(crtc); | |
859 | unsigned long flags; | |
860 | ||
63ebb9fa | 861 | if (WARN_ON(!vop->is_enabled)) |
2048e328 MY |
862 | return -EPERM; |
863 | ||
864 | spin_lock_irqsave(&vop->irq_lock, flags); | |
865 | ||
dbb3d944 | 866 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); |
2048e328 MY |
867 | |
868 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | static void vop_crtc_disable_vblank(struct drm_crtc *crtc) | |
874 | { | |
875 | struct vop *vop = to_vop(crtc); | |
876 | unsigned long flags; | |
877 | ||
63ebb9fa | 878 | if (WARN_ON(!vop->is_enabled)) |
2048e328 | 879 | return; |
31e980c5 | 880 | |
2048e328 | 881 | spin_lock_irqsave(&vop->irq_lock, flags); |
dbb3d944 MY |
882 | |
883 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); | |
884 | ||
2048e328 MY |
885 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
886 | } | |
887 | ||
63ebb9fa MY |
888 | static void vop_crtc_wait_for_update(struct drm_crtc *crtc) |
889 | { | |
890 | struct vop *vop = to_vop(crtc); | |
891 | ||
892 | reinit_completion(&vop->wait_update_complete); | |
893 | WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); | |
894 | } | |
895 | ||
2048e328 MY |
896 | static const struct rockchip_crtc_funcs private_crtc_funcs = { |
897 | .enable_vblank = vop_crtc_enable_vblank, | |
898 | .disable_vblank = vop_crtc_disable_vblank, | |
63ebb9fa | 899 | .wait_for_update = vop_crtc_wait_for_update, |
2048e328 MY |
900 | }; |
901 | ||
2048e328 MY |
902 | static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, |
903 | const struct drm_display_mode *mode, | |
904 | struct drm_display_mode *adjusted_mode) | |
905 | { | |
b59b8de3 CZ |
906 | struct vop *vop = to_vop(crtc); |
907 | ||
b59b8de3 CZ |
908 | adjusted_mode->clock = |
909 | clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; | |
910 | ||
2048e328 MY |
911 | return true; |
912 | } | |
913 | ||
63ebb9fa | 914 | static void vop_crtc_enable(struct drm_crtc *crtc) |
2048e328 MY |
915 | { |
916 | struct vop *vop = to_vop(crtc); | |
4e257d9e | 917 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); |
63ebb9fa | 918 | struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; |
2048e328 MY |
919 | u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; |
920 | u16 hdisplay = adjusted_mode->hdisplay; | |
921 | u16 htotal = adjusted_mode->htotal; | |
922 | u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; | |
923 | u16 hact_end = hact_st + hdisplay; | |
924 | u16 vdisplay = adjusted_mode->vdisplay; | |
925 | u16 vtotal = adjusted_mode->vtotal; | |
926 | u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | |
927 | u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; | |
928 | u16 vact_end = vact_st + vdisplay; | |
2048e328 MY |
929 | uint32_t val; |
930 | ||
893b6cad DV |
931 | WARN_ON(vop->event); |
932 | ||
63ebb9fa | 933 | vop_enable(crtc); |
2048e328 | 934 | /* |
ce3887ed MY |
935 | * If dclk rate is zero, mean that scanout is stop, |
936 | * we don't need wait any more. | |
2048e328 | 937 | */ |
ce3887ed MY |
938 | if (clk_get_rate(vop->dclk)) { |
939 | /* | |
940 | * Rk3288 vop timing register is immediately, when configure | |
941 | * display timing on display time, may cause tearing. | |
942 | * | |
943 | * Vop standby will take effect at end of current frame, | |
944 | * if dsp hold valid irq happen, it means standby complete. | |
945 | * | |
946 | * mode set: | |
947 | * standby and wait complete --> |---- | |
948 | * | display time | |
949 | * |---- | |
950 | * |---> dsp hold irq | |
951 | * configure display timing --> | | |
952 | * standby exit | | |
953 | * | new frame start. | |
954 | */ | |
955 | ||
956 | reinit_completion(&vop->dsp_hold_completion); | |
957 | vop_dsp_hold_valid_irq_enable(vop); | |
958 | ||
959 | spin_lock(&vop->reg_lock); | |
960 | ||
961 | VOP_CTRL_SET(vop, standby, 1); | |
962 | ||
963 | spin_unlock(&vop->reg_lock); | |
964 | ||
965 | wait_for_completion(&vop->dsp_hold_completion); | |
966 | ||
967 | vop_dsp_hold_valid_irq_disable(vop); | |
968 | } | |
2048e328 | 969 | |
2048e328 | 970 | val = 0x8; |
44ddb7ef MY |
971 | val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; |
972 | val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); | |
2048e328 | 973 | VOP_CTRL_SET(vop, pin_pol, val); |
4e257d9e MY |
974 | switch (s->output_type) { |
975 | case DRM_MODE_CONNECTOR_LVDS: | |
976 | VOP_CTRL_SET(vop, rgb_en, 1); | |
977 | break; | |
978 | case DRM_MODE_CONNECTOR_eDP: | |
979 | VOP_CTRL_SET(vop, edp_en, 1); | |
980 | break; | |
981 | case DRM_MODE_CONNECTOR_HDMIA: | |
982 | VOP_CTRL_SET(vop, hdmi_en, 1); | |
983 | break; | |
984 | case DRM_MODE_CONNECTOR_DSI: | |
985 | VOP_CTRL_SET(vop, mipi_en, 1); | |
986 | break; | |
987 | default: | |
988 | DRM_ERROR("unsupport connector_type[%d]\n", s->output_type); | |
989 | } | |
990 | VOP_CTRL_SET(vop, out_mode, s->output_mode); | |
2048e328 MY |
991 | |
992 | VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); | |
993 | val = hact_st << 16; | |
994 | val |= hact_end; | |
995 | VOP_CTRL_SET(vop, hact_st_end, val); | |
996 | VOP_CTRL_SET(vop, hpost_st_end, val); | |
997 | ||
998 | VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); | |
999 | val = vact_st << 16; | |
1000 | val |= vact_end; | |
1001 | VOP_CTRL_SET(vop, vact_st_end, val); | |
1002 | VOP_CTRL_SET(vop, vpost_st_end, val); | |
1003 | ||
2048e328 | 1004 | clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); |
ce3887ed MY |
1005 | |
1006 | VOP_CTRL_SET(vop, standby, 0); | |
2048e328 MY |
1007 | } |
1008 | ||
63ebb9fa MY |
1009 | static void vop_crtc_atomic_flush(struct drm_crtc *crtc, |
1010 | struct drm_crtc_state *old_crtc_state) | |
2048e328 MY |
1011 | { |
1012 | struct vop *vop = to_vop(crtc); | |
2048e328 | 1013 | |
63ebb9fa MY |
1014 | if (WARN_ON(!vop->is_enabled)) |
1015 | return; | |
2048e328 | 1016 | |
63ebb9fa | 1017 | spin_lock(&vop->reg_lock); |
2048e328 | 1018 | |
63ebb9fa | 1019 | vop_cfg_done(vop); |
2048e328 | 1020 | |
63ebb9fa | 1021 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
1022 | } |
1023 | ||
63ebb9fa MY |
1024 | static void vop_crtc_atomic_begin(struct drm_crtc *crtc, |
1025 | struct drm_crtc_state *old_crtc_state) | |
2048e328 | 1026 | { |
63ebb9fa | 1027 | struct vop *vop = to_vop(crtc); |
2048e328 | 1028 | |
893b6cad | 1029 | spin_lock_irq(&crtc->dev->event_lock); |
63ebb9fa MY |
1030 | if (crtc->state->event) { |
1031 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
893b6cad | 1032 | WARN_ON(vop->event); |
2048e328 | 1033 | |
63ebb9fa MY |
1034 | vop->event = crtc->state->event; |
1035 | crtc->state->event = NULL; | |
1036 | } | |
893b6cad | 1037 | spin_unlock_irq(&crtc->dev->event_lock); |
2048e328 MY |
1038 | } |
1039 | ||
63ebb9fa MY |
1040 | static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { |
1041 | .enable = vop_crtc_enable, | |
1042 | .disable = vop_crtc_disable, | |
1043 | .mode_fixup = vop_crtc_mode_fixup, | |
1044 | .atomic_flush = vop_crtc_atomic_flush, | |
1045 | .atomic_begin = vop_crtc_atomic_begin, | |
1046 | }; | |
1047 | ||
2048e328 MY |
1048 | static void vop_crtc_destroy(struct drm_crtc *crtc) |
1049 | { | |
1050 | drm_crtc_cleanup(crtc); | |
1051 | } | |
1052 | ||
dc0b408f JK |
1053 | static void vop_crtc_reset(struct drm_crtc *crtc) |
1054 | { | |
1055 | if (crtc->state) | |
1056 | __drm_atomic_helper_crtc_destroy_state(crtc->state); | |
1057 | kfree(crtc->state); | |
1058 | ||
1059 | crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); | |
1060 | if (crtc->state) | |
1061 | crtc->state->crtc = crtc; | |
1062 | } | |
1063 | ||
4e257d9e MY |
1064 | static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) |
1065 | { | |
1066 | struct rockchip_crtc_state *rockchip_state; | |
1067 | ||
1068 | rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); | |
1069 | if (!rockchip_state) | |
1070 | return NULL; | |
1071 | ||
1072 | __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); | |
1073 | return &rockchip_state->base; | |
1074 | } | |
1075 | ||
1076 | static void vop_crtc_destroy_state(struct drm_crtc *crtc, | |
1077 | struct drm_crtc_state *state) | |
1078 | { | |
1079 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); | |
1080 | ||
ec2dc6a0 | 1081 | __drm_atomic_helper_crtc_destroy_state(&s->base); |
4e257d9e MY |
1082 | kfree(s); |
1083 | } | |
1084 | ||
2048e328 | 1085 | static const struct drm_crtc_funcs vop_crtc_funcs = { |
63ebb9fa MY |
1086 | .set_config = drm_atomic_helper_set_config, |
1087 | .page_flip = drm_atomic_helper_page_flip, | |
2048e328 | 1088 | .destroy = vop_crtc_destroy, |
dc0b408f | 1089 | .reset = vop_crtc_reset, |
4e257d9e MY |
1090 | .atomic_duplicate_state = vop_crtc_duplicate_state, |
1091 | .atomic_destroy_state = vop_crtc_destroy_state, | |
2048e328 MY |
1092 | }; |
1093 | ||
63ebb9fa | 1094 | static bool vop_win_pending_is_complete(struct vop_win *vop_win) |
2048e328 | 1095 | { |
63ebb9fa | 1096 | dma_addr_t yrgb_mst; |
2048e328 | 1097 | |
4f9d39a7 | 1098 | if (!vop_win->enable) |
63ebb9fa | 1099 | return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; |
2048e328 | 1100 | |
63ebb9fa | 1101 | yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); |
2048e328 | 1102 | |
4f9d39a7 | 1103 | return yrgb_mst == vop_win->yrgb_mst; |
2048e328 MY |
1104 | } |
1105 | ||
63ebb9fa | 1106 | static void vop_handle_vblank(struct vop *vop) |
2048e328 | 1107 | { |
63ebb9fa MY |
1108 | struct drm_device *drm = vop->drm_dev; |
1109 | struct drm_crtc *crtc = &vop->crtc; | |
1110 | unsigned long flags; | |
1111 | int i; | |
2048e328 | 1112 | |
63ebb9fa MY |
1113 | for (i = 0; i < vop->data->win_size; i++) { |
1114 | if (!vop_win_pending_is_complete(&vop->win[i])) | |
1115 | return; | |
2048e328 MY |
1116 | } |
1117 | ||
893b6cad | 1118 | spin_lock_irqsave(&drm->event_lock, flags); |
63ebb9fa | 1119 | if (vop->event) { |
2048e328 | 1120 | |
63ebb9fa MY |
1121 | drm_crtc_send_vblank_event(crtc, vop->event); |
1122 | drm_crtc_vblank_put(crtc); | |
1123 | vop->event = NULL; | |
2048e328 | 1124 | |
2048e328 | 1125 | } |
893b6cad DV |
1126 | spin_unlock_irqrestore(&drm->event_lock, flags); |
1127 | ||
63ebb9fa MY |
1128 | if (!completion_done(&vop->wait_update_complete)) |
1129 | complete(&vop->wait_update_complete); | |
2048e328 MY |
1130 | } |
1131 | ||
1132 | static irqreturn_t vop_isr(int irq, void *data) | |
1133 | { | |
1134 | struct vop *vop = data; | |
b5f7b755 | 1135 | struct drm_crtc *crtc = &vop->crtc; |
dbb3d944 | 1136 | uint32_t active_irqs; |
2048e328 | 1137 | unsigned long flags; |
1067219b | 1138 | int ret = IRQ_NONE; |
2048e328 MY |
1139 | |
1140 | /* | |
dbb3d944 | 1141 | * interrupt register has interrupt status, enable and clear bits, we |
2048e328 MY |
1142 | * must hold irq_lock to avoid a race with enable/disable_vblank(). |
1143 | */ | |
1144 | spin_lock_irqsave(&vop->irq_lock, flags); | |
dbb3d944 MY |
1145 | |
1146 | active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); | |
2048e328 MY |
1147 | /* Clear all active interrupt sources */ |
1148 | if (active_irqs) | |
dbb3d944 MY |
1149 | VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); |
1150 | ||
2048e328 MY |
1151 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
1152 | ||
1153 | /* This is expected for vop iommu irqs, since the irq is shared */ | |
1154 | if (!active_irqs) | |
1155 | return IRQ_NONE; | |
1156 | ||
1067219b MY |
1157 | if (active_irqs & DSP_HOLD_VALID_INTR) { |
1158 | complete(&vop->dsp_hold_completion); | |
1159 | active_irqs &= ~DSP_HOLD_VALID_INTR; | |
1160 | ret = IRQ_HANDLED; | |
2048e328 MY |
1161 | } |
1162 | ||
1067219b | 1163 | if (active_irqs & FS_INTR) { |
b5f7b755 | 1164 | drm_crtc_handle_vblank(crtc); |
63ebb9fa | 1165 | vop_handle_vblank(vop); |
1067219b | 1166 | active_irqs &= ~FS_INTR; |
63ebb9fa | 1167 | ret = IRQ_HANDLED; |
1067219b | 1168 | } |
2048e328 | 1169 | |
1067219b MY |
1170 | /* Unhandled irqs are spurious. */ |
1171 | if (active_irqs) | |
1172 | DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); | |
1173 | ||
1174 | return ret; | |
2048e328 MY |
1175 | } |
1176 | ||
1177 | static int vop_create_crtc(struct vop *vop) | |
1178 | { | |
1179 | const struct vop_data *vop_data = vop->data; | |
1180 | struct device *dev = vop->dev; | |
1181 | struct drm_device *drm_dev = vop->drm_dev; | |
328b51c0 | 1182 | struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; |
2048e328 MY |
1183 | struct drm_crtc *crtc = &vop->crtc; |
1184 | struct device_node *port; | |
1185 | int ret; | |
1186 | int i; | |
1187 | ||
1188 | /* | |
1189 | * Create drm_plane for primary and cursor planes first, since we need | |
1190 | * to pass them to drm_crtc_init_with_planes, which sets the | |
1191 | * "possible_crtcs" to the newly initialized crtc. | |
1192 | */ | |
1193 | for (i = 0; i < vop_data->win_size; i++) { | |
1194 | struct vop_win *vop_win = &vop->win[i]; | |
1195 | const struct vop_win_data *win_data = vop_win->data; | |
1196 | ||
1197 | if (win_data->type != DRM_PLANE_TYPE_PRIMARY && | |
1198 | win_data->type != DRM_PLANE_TYPE_CURSOR) | |
1199 | continue; | |
1200 | ||
1201 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1202 | 0, &vop_plane_funcs, | |
1203 | win_data->phy->data_formats, | |
1204 | win_data->phy->nformats, | |
b0b3b795 | 1205 | win_data->type, NULL); |
2048e328 MY |
1206 | if (ret) { |
1207 | DRM_ERROR("failed to initialize plane\n"); | |
1208 | goto err_cleanup_planes; | |
1209 | } | |
1210 | ||
1211 | plane = &vop_win->base; | |
63ebb9fa | 1212 | drm_plane_helper_add(plane, &plane_helper_funcs); |
2048e328 MY |
1213 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
1214 | primary = plane; | |
1215 | else if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
1216 | cursor = plane; | |
1217 | } | |
1218 | ||
1219 | ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, | |
f9882876 | 1220 | &vop_crtc_funcs, NULL); |
2048e328 | 1221 | if (ret) |
328b51c0 | 1222 | goto err_cleanup_planes; |
2048e328 MY |
1223 | |
1224 | drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); | |
1225 | ||
1226 | /* | |
1227 | * Create drm_planes for overlay windows with possible_crtcs restricted | |
1228 | * to the newly created crtc. | |
1229 | */ | |
1230 | for (i = 0; i < vop_data->win_size; i++) { | |
1231 | struct vop_win *vop_win = &vop->win[i]; | |
1232 | const struct vop_win_data *win_data = vop_win->data; | |
1233 | unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); | |
1234 | ||
1235 | if (win_data->type != DRM_PLANE_TYPE_OVERLAY) | |
1236 | continue; | |
1237 | ||
1238 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1239 | possible_crtcs, | |
1240 | &vop_plane_funcs, | |
1241 | win_data->phy->data_formats, | |
1242 | win_data->phy->nformats, | |
b0b3b795 | 1243 | win_data->type, NULL); |
2048e328 MY |
1244 | if (ret) { |
1245 | DRM_ERROR("failed to initialize overlay plane\n"); | |
1246 | goto err_cleanup_crtc; | |
1247 | } | |
63ebb9fa | 1248 | drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); |
2048e328 MY |
1249 | } |
1250 | ||
1251 | port = of_get_child_by_name(dev->of_node, "port"); | |
1252 | if (!port) { | |
1253 | DRM_ERROR("no port node found in %s\n", | |
1254 | dev->of_node->full_name); | |
328b51c0 | 1255 | ret = -ENOENT; |
2048e328 MY |
1256 | goto err_cleanup_crtc; |
1257 | } | |
1258 | ||
1067219b | 1259 | init_completion(&vop->dsp_hold_completion); |
63ebb9fa | 1260 | init_completion(&vop->wait_update_complete); |
2048e328 | 1261 | crtc->port = port; |
b5f7b755 | 1262 | rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); |
2048e328 MY |
1263 | |
1264 | return 0; | |
1265 | ||
1266 | err_cleanup_crtc: | |
1267 | drm_crtc_cleanup(crtc); | |
1268 | err_cleanup_planes: | |
328b51c0 DA |
1269 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, |
1270 | head) | |
2048e328 MY |
1271 | drm_plane_cleanup(plane); |
1272 | return ret; | |
1273 | } | |
1274 | ||
1275 | static void vop_destroy_crtc(struct vop *vop) | |
1276 | { | |
1277 | struct drm_crtc *crtc = &vop->crtc; | |
328b51c0 DA |
1278 | struct drm_device *drm_dev = vop->drm_dev; |
1279 | struct drm_plane *plane, *tmp; | |
2048e328 | 1280 | |
b5f7b755 | 1281 | rockchip_unregister_crtc_funcs(crtc); |
2048e328 | 1282 | of_node_put(crtc->port); |
328b51c0 DA |
1283 | |
1284 | /* | |
1285 | * We need to cleanup the planes now. Why? | |
1286 | * | |
1287 | * The planes are "&vop->win[i].base". That means the memory is | |
1288 | * all part of the big "struct vop" chunk of memory. That memory | |
1289 | * was devm allocated and associated with this component. We need to | |
1290 | * free it ourselves before vop_unbind() finishes. | |
1291 | */ | |
1292 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, | |
1293 | head) | |
1294 | vop_plane_destroy(plane); | |
1295 | ||
1296 | /* | |
1297 | * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() | |
1298 | * references the CRTC. | |
1299 | */ | |
2048e328 MY |
1300 | drm_crtc_cleanup(crtc); |
1301 | } | |
1302 | ||
1303 | static int vop_initial(struct vop *vop) | |
1304 | { | |
1305 | const struct vop_data *vop_data = vop->data; | |
1306 | const struct vop_reg_data *init_table = vop_data->init_table; | |
1307 | struct reset_control *ahb_rst; | |
1308 | int i, ret; | |
1309 | ||
1310 | vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); | |
1311 | if (IS_ERR(vop->hclk)) { | |
1312 | dev_err(vop->dev, "failed to get hclk source\n"); | |
1313 | return PTR_ERR(vop->hclk); | |
1314 | } | |
1315 | vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); | |
1316 | if (IS_ERR(vop->aclk)) { | |
1317 | dev_err(vop->dev, "failed to get aclk source\n"); | |
1318 | return PTR_ERR(vop->aclk); | |
1319 | } | |
1320 | vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); | |
1321 | if (IS_ERR(vop->dclk)) { | |
1322 | dev_err(vop->dev, "failed to get dclk source\n"); | |
1323 | return PTR_ERR(vop->dclk); | |
1324 | } | |
1325 | ||
2048e328 MY |
1326 | ret = clk_prepare(vop->dclk); |
1327 | if (ret < 0) { | |
1328 | dev_err(vop->dev, "failed to prepare dclk\n"); | |
d7b53fd9 | 1329 | return ret; |
2048e328 MY |
1330 | } |
1331 | ||
d7b53fd9 SS |
1332 | /* Enable both the hclk and aclk to setup the vop */ |
1333 | ret = clk_prepare_enable(vop->hclk); | |
2048e328 | 1334 | if (ret < 0) { |
d7b53fd9 | 1335 | dev_err(vop->dev, "failed to prepare/enable hclk\n"); |
2048e328 MY |
1336 | goto err_unprepare_dclk; |
1337 | } | |
1338 | ||
d7b53fd9 | 1339 | ret = clk_prepare_enable(vop->aclk); |
2048e328 | 1340 | if (ret < 0) { |
d7b53fd9 SS |
1341 | dev_err(vop->dev, "failed to prepare/enable aclk\n"); |
1342 | goto err_disable_hclk; | |
2048e328 | 1343 | } |
d7b53fd9 | 1344 | |
2048e328 MY |
1345 | /* |
1346 | * do hclk_reset, reset all vop registers. | |
1347 | */ | |
1348 | ahb_rst = devm_reset_control_get(vop->dev, "ahb"); | |
1349 | if (IS_ERR(ahb_rst)) { | |
1350 | dev_err(vop->dev, "failed to get ahb reset\n"); | |
1351 | ret = PTR_ERR(ahb_rst); | |
d7b53fd9 | 1352 | goto err_disable_aclk; |
2048e328 MY |
1353 | } |
1354 | reset_control_assert(ahb_rst); | |
1355 | usleep_range(10, 20); | |
1356 | reset_control_deassert(ahb_rst); | |
1357 | ||
1358 | memcpy(vop->regsbak, vop->regs, vop->len); | |
1359 | ||
1360 | for (i = 0; i < vop_data->table_size; i++) | |
1361 | vop_writel(vop, init_table[i].offset, init_table[i].value); | |
1362 | ||
1363 | for (i = 0; i < vop_data->win_size; i++) { | |
1364 | const struct vop_win_data *win = &vop_data->win[i]; | |
1365 | ||
1366 | VOP_WIN_SET(vop, win, enable, 0); | |
1367 | } | |
1368 | ||
1369 | vop_cfg_done(vop); | |
1370 | ||
1371 | /* | |
1372 | * do dclk_reset, let all config take affect. | |
1373 | */ | |
1374 | vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); | |
1375 | if (IS_ERR(vop->dclk_rst)) { | |
1376 | dev_err(vop->dev, "failed to get dclk reset\n"); | |
1377 | ret = PTR_ERR(vop->dclk_rst); | |
d7b53fd9 | 1378 | goto err_disable_aclk; |
2048e328 MY |
1379 | } |
1380 | reset_control_assert(vop->dclk_rst); | |
1381 | usleep_range(10, 20); | |
1382 | reset_control_deassert(vop->dclk_rst); | |
1383 | ||
1384 | clk_disable(vop->hclk); | |
d7b53fd9 | 1385 | clk_disable(vop->aclk); |
2048e328 | 1386 | |
31e980c5 | 1387 | vop->is_enabled = false; |
2048e328 MY |
1388 | |
1389 | return 0; | |
1390 | ||
d7b53fd9 SS |
1391 | err_disable_aclk: |
1392 | clk_disable_unprepare(vop->aclk); | |
2048e328 | 1393 | err_disable_hclk: |
d7b53fd9 | 1394 | clk_disable_unprepare(vop->hclk); |
2048e328 MY |
1395 | err_unprepare_dclk: |
1396 | clk_unprepare(vop->dclk); | |
2048e328 MY |
1397 | return ret; |
1398 | } | |
1399 | ||
1400 | /* | |
1401 | * Initialize the vop->win array elements. | |
1402 | */ | |
1403 | static void vop_win_init(struct vop *vop) | |
1404 | { | |
1405 | const struct vop_data *vop_data = vop->data; | |
1406 | unsigned int i; | |
1407 | ||
1408 | for (i = 0; i < vop_data->win_size; i++) { | |
1409 | struct vop_win *vop_win = &vop->win[i]; | |
1410 | const struct vop_win_data *win_data = &vop_data->win[i]; | |
1411 | ||
1412 | vop_win->data = win_data; | |
1413 | vop_win->vop = vop; | |
2048e328 MY |
1414 | } |
1415 | } | |
1416 | ||
1417 | static int vop_bind(struct device *dev, struct device *master, void *data) | |
1418 | { | |
1419 | struct platform_device *pdev = to_platform_device(dev); | |
2048e328 MY |
1420 | const struct vop_data *vop_data; |
1421 | struct drm_device *drm_dev = data; | |
1422 | struct vop *vop; | |
1423 | struct resource *res; | |
1424 | size_t alloc_size; | |
3ea68922 | 1425 | int ret, irq; |
2048e328 | 1426 | |
a67719d1 | 1427 | vop_data = of_device_get_match_data(dev); |
2048e328 MY |
1428 | if (!vop_data) |
1429 | return -ENODEV; | |
1430 | ||
1431 | /* Allocate vop struct and its vop_win array */ | |
1432 | alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; | |
1433 | vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); | |
1434 | if (!vop) | |
1435 | return -ENOMEM; | |
1436 | ||
1437 | vop->dev = dev; | |
1438 | vop->data = vop_data; | |
1439 | vop->drm_dev = drm_dev; | |
1440 | dev_set_drvdata(dev, vop); | |
1441 | ||
1442 | vop_win_init(vop); | |
1443 | ||
1444 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1445 | vop->len = resource_size(res); | |
1446 | vop->regs = devm_ioremap_resource(dev, res); | |
1447 | if (IS_ERR(vop->regs)) | |
1448 | return PTR_ERR(vop->regs); | |
1449 | ||
1450 | vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); | |
1451 | if (!vop->regsbak) | |
1452 | return -ENOMEM; | |
1453 | ||
1454 | ret = vop_initial(vop); | |
1455 | if (ret < 0) { | |
1456 | dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); | |
1457 | return ret; | |
1458 | } | |
1459 | ||
3ea68922 HS |
1460 | irq = platform_get_irq(pdev, 0); |
1461 | if (irq < 0) { | |
2048e328 | 1462 | dev_err(dev, "cannot find irq for vop\n"); |
3ea68922 | 1463 | return irq; |
2048e328 | 1464 | } |
3ea68922 | 1465 | vop->irq = (unsigned int)irq; |
2048e328 MY |
1466 | |
1467 | spin_lock_init(&vop->reg_lock); | |
1468 | spin_lock_init(&vop->irq_lock); | |
1469 | ||
1470 | mutex_init(&vop->vsync_mutex); | |
1471 | ||
63ebb9fa MY |
1472 | ret = devm_request_irq(dev, vop->irq, vop_isr, |
1473 | IRQF_SHARED, dev_name(dev), vop); | |
2048e328 MY |
1474 | if (ret) |
1475 | return ret; | |
1476 | ||
1477 | /* IRQ is initially disabled; it gets enabled in power_on */ | |
1478 | disable_irq(vop->irq); | |
1479 | ||
1480 | ret = vop_create_crtc(vop); | |
1481 | if (ret) | |
1482 | return ret; | |
1483 | ||
1484 | pm_runtime_enable(&pdev->dev); | |
1485 | return 0; | |
1486 | } | |
1487 | ||
1488 | static void vop_unbind(struct device *dev, struct device *master, void *data) | |
1489 | { | |
1490 | struct vop *vop = dev_get_drvdata(dev); | |
1491 | ||
1492 | pm_runtime_disable(dev); | |
1493 | vop_destroy_crtc(vop); | |
1494 | } | |
1495 | ||
a67719d1 | 1496 | const struct component_ops vop_component_ops = { |
2048e328 MY |
1497 | .bind = vop_bind, |
1498 | .unbind = vop_unbind, | |
1499 | }; | |
54255e81 | 1500 | EXPORT_SYMBOL_GPL(vop_component_ops); |