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drm/rockchip: Use new vblank api drm_crtc_vblank_*
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.c
CommitLineData
2048e328
MY		 1/*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <drm/drm.h>
16#include <drm/drmP.h>
17#include <drm/drm_crtc.h>
18#include <drm/drm_crtc_helper.h>
19#include <drm/drm_plane_helper.h>
20
21#include <linux/kernel.h>
00fe6148 22#include <linux/module.h>
2048e328
MY		 23#include <linux/platform_device.h>
24#include <linux/clk.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/pm_runtime.h>
28#include <linux/component.h>
29
30#include <linux/reset.h>
31#include <linux/delay.h>
32
33#include "rockchip_drm_drv.h"
34#include "rockchip_drm_gem.h"
35#include "rockchip_drm_fb.h"
36#include "rockchip_drm_vop.h"
37
38#define VOP_REG(off, _mask, s) \
39 {.offset = off, \
40 .mask = _mask, \
41 .shift = s,}
42
43#define __REG_SET_RELAXED(x, off, mask, shift, v) \
44 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
45#define __REG_SET_NORMAL(x, off, mask, shift, v) \
46 vop_mask_write(x, off, (mask) << shift, (v) << shift)
47
48#define REG_SET(x, base, reg, v, mode) \
49 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
50
51#define VOP_WIN_SET(x, win, name, v) \
52 REG_SET(x, win->base, win->phy->name, v, RELAXED)
4c156c21
MY		 53#define VOP_SCL_SET(x, win, name, v) \
54 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
2048e328
MY		 55#define VOP_CTRL_SET(x, name, v) \
56 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
57
58#define VOP_WIN_GET(x, win, name) \
59 vop_read_reg(x, win->base, &win->phy->name)
60
61#define VOP_WIN_GET_YRGBADDR(vop, win) \
62 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
63
64#define to_vop(x) container_of(x, struct vop, crtc)
65#define to_vop_win(x) container_of(x, struct vop_win, base)
66
67struct vop_win_state {
68 struct list_head head;
69 struct drm_framebuffer *fb;
70 dma_addr_t yrgb_mst;
71 struct drm_pending_vblank_event *event;
72};
73
74struct vop_win {
75 struct drm_plane base;
76 const struct vop_win_data *data;
77 struct vop *vop;
78
79 struct list_head pending;
80 struct vop_win_state *active;
81};
82
83struct vop {
84 struct drm_crtc crtc;
85 struct device *dev;
86 struct drm_device *drm_dev;
31e980c5 87 bool is_enabled;
2048e328
MY		 88
89 int connector_type;
90 int connector_out_mode;
91
92 /* mutex vsync_ work */
93 struct mutex vsync_mutex;
94 bool vsync_work_pending;
1067219b 95 struct completion dsp_hold_completion;
2048e328
MY		 96
97 const struct vop_data *data;
98
99 uint32_t *regsbak;
100 void __iomem *regs;
101
102 /* physical map length of vop register */
103 uint32_t len;
104
105 /* one time only one process allowed to config the register */
106 spinlock_t reg_lock;
107 /* lock vop irq reg */
108 spinlock_t irq_lock;
109
110 unsigned int irq;
111
112 /* vop AHP clk */
113 struct clk *hclk;
114 /* vop dclk */
115 struct clk *dclk;
116 /* vop share memory frequency */
117 struct clk *aclk;
118
119 /* vop dclk reset */
120 struct reset_control *dclk_rst;
121
2048e328
MY		 122 struct vop_win win[];
123};
124
125enum vop_data_format {
126 VOP_FMT_ARGB8888 = 0,
127 VOP_FMT_RGB888,
128 VOP_FMT_RGB565,
129 VOP_FMT_YUV420SP = 4,
130 VOP_FMT_YUV422SP,
131 VOP_FMT_YUV444SP,
132};
133
134struct vop_reg_data {
135 uint32_t offset;
136 uint32_t value;
137};
138
139struct vop_reg {
140 uint32_t offset;
141 uint32_t shift;
142 uint32_t mask;
143};
144
145struct vop_ctrl {
146 struct vop_reg standby;
147 struct vop_reg data_blank;
148 struct vop_reg gate_en;
149 struct vop_reg mmu_en;
150 struct vop_reg rgb_en;
151 struct vop_reg edp_en;
152 struct vop_reg hdmi_en;
153 struct vop_reg mipi_en;
154 struct vop_reg out_mode;
155 struct vop_reg dither_down;
156 struct vop_reg dither_up;
157 struct vop_reg pin_pol;
158
159 struct vop_reg htotal_pw;
160 struct vop_reg hact_st_end;
161 struct vop_reg vtotal_pw;
162 struct vop_reg vact_st_end;
163 struct vop_reg hpost_st_end;
164 struct vop_reg vpost_st_end;
165};
166
4c156c21
MY		 167struct vop_scl_regs {
168 struct vop_reg cbcr_vsd_mode;
169 struct vop_reg cbcr_vsu_mode;
170 struct vop_reg cbcr_hsd_mode;
171 struct vop_reg cbcr_ver_scl_mode;
172 struct vop_reg cbcr_hor_scl_mode;
173 struct vop_reg yrgb_vsd_mode;
174 struct vop_reg yrgb_vsu_mode;
175 struct vop_reg yrgb_hsd_mode;
176 struct vop_reg yrgb_ver_scl_mode;
177 struct vop_reg yrgb_hor_scl_mode;
178 struct vop_reg line_load_mode;
179 struct vop_reg cbcr_axi_gather_num;
180 struct vop_reg yrgb_axi_gather_num;
181 struct vop_reg vsd_cbcr_gt2;
182 struct vop_reg vsd_cbcr_gt4;
183 struct vop_reg vsd_yrgb_gt2;
184 struct vop_reg vsd_yrgb_gt4;
185 struct vop_reg bic_coe_sel;
186 struct vop_reg cbcr_axi_gather_en;
187 struct vop_reg yrgb_axi_gather_en;
188
189 struct vop_reg lb_mode;
190 struct vop_reg scale_yrgb_x;
191 struct vop_reg scale_yrgb_y;
192 struct vop_reg scale_cbcr_x;
193 struct vop_reg scale_cbcr_y;
194};
195
2048e328 196struct vop_win_phy {
4c156c21 197 const struct vop_scl_regs *scl;
2048e328
MY		 198 const uint32_t *data_formats;
199 uint32_t nformats;
200
201 struct vop_reg enable;
202 struct vop_reg format;
85a359f2 203 struct vop_reg rb_swap;
2048e328
MY		 204 struct vop_reg act_info;
205 struct vop_reg dsp_info;
206 struct vop_reg dsp_st;
207 struct vop_reg yrgb_mst;
208 struct vop_reg uv_mst;
209 struct vop_reg yrgb_vir;
210 struct vop_reg uv_vir;
211
212 struct vop_reg dst_alpha_ctl;
213 struct vop_reg src_alpha_ctl;
214};
215
216struct vop_win_data {
217 uint32_t base;
218 const struct vop_win_phy *phy;
219 enum drm_plane_type type;
220};
221
222struct vop_data {
223 const struct vop_reg_data *init_table;
224 unsigned int table_size;
225 const struct vop_ctrl *ctrl;
226 const struct vop_win_data *win;
227 unsigned int win_size;
228};
229
230static const uint32_t formats_01[] = {
231 DRM_FORMAT_XRGB8888,
232 DRM_FORMAT_ARGB8888,
85a359f2
TF		 233 DRM_FORMAT_XBGR8888,
234 DRM_FORMAT_ABGR8888,
2048e328 235 DRM_FORMAT_RGB888,
85a359f2 236 DRM_FORMAT_BGR888,
2048e328 237 DRM_FORMAT_RGB565,
85a359f2 238 DRM_FORMAT_BGR565,
2048e328
MY		 239 DRM_FORMAT_NV12,
240 DRM_FORMAT_NV16,
241 DRM_FORMAT_NV24,
242};
243
244static const uint32_t formats_234[] = {
245 DRM_FORMAT_XRGB8888,
246 DRM_FORMAT_ARGB8888,
85a359f2
TF		 247 DRM_FORMAT_XBGR8888,
248 DRM_FORMAT_ABGR8888,
2048e328 249 DRM_FORMAT_RGB888,
85a359f2 250 DRM_FORMAT_BGR888,
2048e328 251 DRM_FORMAT_RGB565,
85a359f2 252 DRM_FORMAT_BGR565,
2048e328
MY		 253};
254
4c156c21
MY		 255static const struct vop_scl_regs win_full_scl = {
256 .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
257 .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
258 .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
259 .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
260 .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
261 .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
262 .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
263 .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
264 .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
265 .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
266 .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
267 .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
268 .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
269 .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
270 .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
271 .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
272 .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
273 .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
274 .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
275 .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
276 .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
277 .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
278 .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
279 .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
280 .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
281};
282
2048e328 283static const struct vop_win_phy win01_data = {
4c156c21 284 .scl = &win_full_scl,
2048e328
MY		 285 .data_formats = formats_01,
286 .nformats = ARRAY_SIZE(formats_01),
287 .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
288 .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
85a359f2 289 .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
2048e328
MY		 290 .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
291 .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
292 .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
293 .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
294 .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
295 .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
296 .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
297 .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
298 .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
299};
300
301static const struct vop_win_phy win23_data = {
302 .data_formats = formats_234,
303 .nformats = ARRAY_SIZE(formats_234),
304 .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
305 .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
85a359f2 306 .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
2048e328
MY		 307 .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
308 .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
309 .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
310 .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
311 .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
312 .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
313};
314
2048e328
MY		 315static const struct vop_ctrl ctrl_data = {
316 .standby = VOP_REG(SYS_CTRL, 0x1, 22),
317 .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
318 .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
319 .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
320 .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
321 .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
322 .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
323 .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
324 .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
325 .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
326 .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
327 .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
328 .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
329 .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
330 .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
331 .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
332 .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
333 .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
334};
335
336static const struct vop_reg_data vop_init_reg_table[] = {
337 {SYS_CTRL, 0x00c00000},
338 {DSP_CTRL0, 0x00000000},
339 {WIN0_CTRL0, 0x00000080},
340 {WIN1_CTRL0, 0x00000080},
c1998f08
MY		 341 /* TODO: Win2/3 support multiple area function, but we haven't found
342 * a suitable way to use it yet, so let's just use them as other windows
343 * with only area 0 enabled.
344 */
345 {WIN2_CTRL0, 0x00000010},
346 {WIN3_CTRL0, 0x00000010},
2048e328
MY		 347};
348
349/*
350 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
351 * special support to get alpha blending working. For now, just use overlay
d3cae7df
MY		 352 * window 3 for the drm cursor.
353 *
2048e328
MY		 354 */
355static const struct vop_win_data rk3288_vop_win_data[] = {
356 { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
d3cae7df 357 { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
2048e328 358 { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
d3cae7df 359 { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
2048e328
MY		 360};
361
362static const struct vop_data rk3288_vop = {
363 .init_table = vop_init_reg_table,
364 .table_size = ARRAY_SIZE(vop_init_reg_table),
365 .ctrl = &ctrl_data,
366 .win = rk3288_vop_win_data,
367 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
368};
369
370static const struct of_device_id vop_driver_dt_match[] = {
371 { .compatible = "rockchip,rk3288-vop",
372 .data = &rk3288_vop },
373 {},
374};
3b134ced 375MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
2048e328
MY		 376
377static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
378{
379 writel(v, vop->regs + offset);
380 vop->regsbak[offset >> 2] = v;
381}
382
383static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
384{
385 return readl(vop->regs + offset);
386}
387
388static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
389 const struct vop_reg *reg)
390{
391 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
392}
393
394static inline void vop_cfg_done(struct vop *vop)
395{
396 writel(0x01, vop->regs + REG_CFG_DONE);
397}
398
399static inline void vop_mask_write(struct vop *vop, uint32_t offset,
400 uint32_t mask, uint32_t v)
401{
402 if (mask) {
403 uint32_t cached_val = vop->regsbak[offset >> 2];
404
405 cached_val = (cached_val & ~mask) | v;
406 writel(cached_val, vop->regs + offset);
407 vop->regsbak[offset >> 2] = cached_val;
408 }
409}
410
411static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
412 uint32_t mask, uint32_t v)
413{
414 if (mask) {
415 uint32_t cached_val = vop->regsbak[offset >> 2];
416
417 cached_val = (cached_val & ~mask) | v;
418 writel_relaxed(cached_val, vop->regs + offset);
419 vop->regsbak[offset >> 2] = cached_val;
420 }
421}
422
85a359f2
TF		 423static bool has_rb_swapped(uint32_t format)
424{
425 switch (format) {
426 case DRM_FORMAT_XBGR8888:
427 case DRM_FORMAT_ABGR8888:
428 case DRM_FORMAT_BGR888:
429 case DRM_FORMAT_BGR565:
430 return true;
431 default:
432 return false;
433 }
434}
435
2048e328
MY		 436static enum vop_data_format vop_convert_format(uint32_t format)
437{
438 switch (format) {
439 case DRM_FORMAT_XRGB8888:
440 case DRM_FORMAT_ARGB8888:
85a359f2
TF		 441 case DRM_FORMAT_XBGR8888:
442 case DRM_FORMAT_ABGR8888:
2048e328
MY		 443 return VOP_FMT_ARGB8888;
444 case DRM_FORMAT_RGB888:
85a359f2 445 case DRM_FORMAT_BGR888:
2048e328
MY		 446 return VOP_FMT_RGB888;
447 case DRM_FORMAT_RGB565:
85a359f2 448 case DRM_FORMAT_BGR565:
2048e328
MY		 449 return VOP_FMT_RGB565;
450 case DRM_FORMAT_NV12:
451 return VOP_FMT_YUV420SP;
452 case DRM_FORMAT_NV16:
453 return VOP_FMT_YUV422SP;
454 case DRM_FORMAT_NV24:
455 return VOP_FMT_YUV444SP;
456 default:
457 DRM_ERROR("unsupport format[%08x]\n", format);
458 return -EINVAL;
459 }
460}
461
84c7f8ca
MY		 462static bool is_yuv_support(uint32_t format)
463{
464 switch (format) {
465 case DRM_FORMAT_NV12:
466 case DRM_FORMAT_NV16:
467 case DRM_FORMAT_NV24:
468 return true;
469 default:
470 return false;
471 }
472}
473
2048e328
MY		 474static bool is_alpha_support(uint32_t format)
475{
476 switch (format) {
477 case DRM_FORMAT_ARGB8888:
85a359f2 478 case DRM_FORMAT_ABGR8888:
2048e328
MY		 479 return true;
480 default:
481 return false;
482 }
483}
484
4c156c21
MY		 485static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
486 uint32_t dst, bool is_horizontal,
487 int vsu_mode, int *vskiplines)
488{
489 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
490
491 if (is_horizontal) {
492 if (mode == SCALE_UP)
493 val = GET_SCL_FT_BIC(src, dst);
494 else if (mode == SCALE_DOWN)
495 val = GET_SCL_FT_BILI_DN(src, dst);
496 } else {
497 if (mode == SCALE_UP) {
498 if (vsu_mode == SCALE_UP_BIL)
499 val = GET_SCL_FT_BILI_UP(src, dst);
500 else
501 val = GET_SCL_FT_BIC(src, dst);
502 } else if (mode == SCALE_DOWN) {
503 if (vskiplines) {
504 *vskiplines = scl_get_vskiplines(src, dst);
505 val = scl_get_bili_dn_vskip(src, dst,
506 *vskiplines);
507 } else {
508 val = GET_SCL_FT_BILI_DN(src, dst);
509 }
510 }
511 }
512
513 return val;
514}
515
516static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
517 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
518 uint32_t dst_h, uint32_t pixel_format)
519{
520 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
521 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
522 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
523 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
524 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
525 bool is_yuv = is_yuv_support(pixel_format);
526 uint16_t cbcr_src_w = src_w / hsub;
527 uint16_t cbcr_src_h = src_h / vsub;
528 uint16_t vsu_mode;
529 uint16_t lb_mode;
530 uint32_t val;
531 int vskiplines;
532
533 if (dst_w > 3840) {
534 DRM_ERROR("Maximum destination width (3840) exceeded\n");
535 return;
536 }
537
538 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
539 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
540
541 if (is_yuv) {
542 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
543 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
544 if (cbcr_hor_scl_mode == SCALE_DOWN)
545 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
546 else
547 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
548 } else {
549 if (yrgb_hor_scl_mode == SCALE_DOWN)
550 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
551 else
552 lb_mode = scl_vop_cal_lb_mode(src_w, false);
553 }
554
555 VOP_SCL_SET(vop, win, lb_mode, lb_mode);
556 if (lb_mode == LB_RGB_3840X2) {
557 if (yrgb_ver_scl_mode != SCALE_NONE) {
558 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
559 return;
560 }
561 if (cbcr_ver_scl_mode != SCALE_NONE) {
562 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
563 return;
564 }
565 vsu_mode = SCALE_UP_BIL;
566 } else if (lb_mode == LB_RGB_2560X4) {
567 vsu_mode = SCALE_UP_BIL;
568 } else {
569 vsu_mode = SCALE_UP_BIC;
570 }
571
572 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
573 true, 0, NULL);
574 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
575 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
576 false, vsu_mode, &vskiplines);
577 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
578
579 VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
580 VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
581
582 VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
583 VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
584 VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
585 VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
586 VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
587 if (is_yuv) {
588 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
589 dst_w, true, 0, NULL);
590 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
591 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
592 dst_h, false, vsu_mode, &vskiplines);
593 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
594
595 VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
596 VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
597 VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
598 VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
599 VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
600 VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
601 VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
602 }
603}
604
1067219b
MY		 605static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
606{
607 unsigned long flags;
608
609 if (WARN_ON(!vop->is_enabled))
610 return;
611
612 spin_lock_irqsave(&vop->irq_lock, flags);
613
614 vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
615 DSP_HOLD_VALID_INTR_EN(1));
616
617 spin_unlock_irqrestore(&vop->irq_lock, flags);
618}
619
620static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
621{
622 unsigned long flags;
623
624 if (WARN_ON(!vop->is_enabled))
625 return;
626
627 spin_lock_irqsave(&vop->irq_lock, flags);
628
629 vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
630 DSP_HOLD_VALID_INTR_EN(0));
631
632 spin_unlock_irqrestore(&vop->irq_lock, flags);
633}
634
2048e328
MY		 635static void vop_enable(struct drm_crtc *crtc)
636{
637 struct vop *vop = to_vop(crtc);
638 int ret;
639
31e980c5
MY		 640 if (vop->is_enabled)
641 return;
642
5d82d1a7
MY		 643 ret = pm_runtime_get_sync(vop->dev);
644 if (ret < 0) {
645 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
646 return;
647 }
648
2048e328
MY		 649 ret = clk_enable(vop->hclk);
650 if (ret < 0) {
651 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
652 return;
653 }
654
655 ret = clk_enable(vop->dclk);
656 if (ret < 0) {
657 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
658 goto err_disable_hclk;
659 }
660
661 ret = clk_enable(vop->aclk);
662 if (ret < 0) {
663 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
664 goto err_disable_dclk;
665 }
666
667 /*
668 * Slave iommu shares power, irq and clock with vop. It was associated
669 * automatically with this master device via common driver code.
670 * Now that we have enabled the clock we attach it to the shared drm
671 * mapping.
672 */
673 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
674 if (ret) {
675 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
676 goto err_disable_aclk;
677 }
678
77faa161 679 memcpy(vop->regs, vop->regsbak, vop->len);
52ab7891
MY		 680 /*
681 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
682 */
683 vop->is_enabled = true;
684
2048e328
MY		 685 spin_lock(&vop->reg_lock);
686
687 VOP_CTRL_SET(vop, standby, 0);
688
689 spin_unlock(&vop->reg_lock);
690
691 enable_irq(vop->irq);
692
b5f7b755 693 drm_crtc_vblank_on(crtc);
2048e328
MY		 694
695 return;
696
697err_disable_aclk:
698 clk_disable(vop->aclk);
699err_disable_dclk:
700 clk_disable(vop->dclk);
701err_disable_hclk:
702 clk_disable(vop->hclk);
703}
704
705static void vop_disable(struct drm_crtc *crtc)
706{
707 struct vop *vop = to_vop(crtc);
708
31e980c5
MY		 709 if (!vop->is_enabled)
710 return;
711
b5f7b755 712 drm_crtc_vblank_off(crtc);
2048e328 713
2048e328 714 /*
1067219b
MY		 715 * Vop standby will take effect at end of current frame,
716 * if dsp hold valid irq happen, it means standby complete.
717 *
718 * we must wait standby complete when we want to disable aclk,
719 * if not, memory bus maybe dead.
2048e328 720 */
1067219b
MY		 721 reinit_completion(&vop->dsp_hold_completion);
722 vop_dsp_hold_valid_irq_enable(vop);
723
2048e328
MY		 724 spin_lock(&vop->reg_lock);
725
726 VOP_CTRL_SET(vop, standby, 1);
727
728 spin_unlock(&vop->reg_lock);
52ab7891 729
1067219b
MY		 730 wait_for_completion(&vop->dsp_hold_completion);
731
732 vop_dsp_hold_valid_irq_disable(vop);
733
734 disable_irq(vop->irq);
735
52ab7891 736 vop->is_enabled = false;
1067219b 737
2048e328 738 /*
1067219b 739 * vop standby complete, so iommu detach is safe.
2048e328 740 */
2048e328
MY		 741 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
742
1067219b 743 clk_disable(vop->dclk);
2048e328
MY		 744 clk_disable(vop->aclk);
745 clk_disable(vop->hclk);
5d82d1a7 746 pm_runtime_put(vop->dev);
2048e328
MY		 747}
748
749/*
750 * Caller must hold vsync_mutex.
751 */
752static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win)
753{
754 struct vop_win_state *last;
755 struct vop_win_state *active = vop_win->active;
756
757 if (list_empty(&vop_win->pending))
758 return active ? active->fb : NULL;
759
760 last = list_last_entry(&vop_win->pending, struct vop_win_state, head);
761 return last ? last->fb : NULL;
762}
763
764/*
765 * Caller must hold vsync_mutex.
766 */
767static int vop_win_queue_fb(struct vop_win *vop_win,
768 struct drm_framebuffer *fb, dma_addr_t yrgb_mst,
769 struct drm_pending_vblank_event *event)
770{
771 struct vop_win_state *state;
772
773 state = kzalloc(sizeof(*state), GFP_KERNEL);
774 if (!state)
775 return -ENOMEM;
776
777 state->fb = fb;
778 state->yrgb_mst = yrgb_mst;
779 state->event = event;
780
781 list_add_tail(&state->head, &vop_win->pending);
782
783 return 0;
784}
785
786static int vop_update_plane_event(struct drm_plane *plane,
787 struct drm_crtc *crtc,
788 struct drm_framebuffer *fb, int crtc_x,
789 int crtc_y, unsigned int crtc_w,
790 unsigned int crtc_h, uint32_t src_x,
791 uint32_t src_y, uint32_t src_w,
792 uint32_t src_h,
793 struct drm_pending_vblank_event *event)
794{
795 struct vop_win *vop_win = to_vop_win(plane);
796 const struct vop_win_data *win = vop_win->data;
797 struct vop *vop = to_vop(crtc);
798 struct drm_gem_object *obj;
799 struct rockchip_gem_object *rk_obj;
84c7f8ca
MY		 800 struct drm_gem_object *uv_obj;
801 struct rockchip_gem_object *rk_uv_obj;
2048e328
MY		 802 unsigned long offset;
803 unsigned int actual_w;
804 unsigned int actual_h;
805 unsigned int dsp_stx;
806 unsigned int dsp_sty;
807 unsigned int y_vir_stride;
84c7f8ca 808 unsigned int uv_vir_stride = 0;
2048e328 809 dma_addr_t yrgb_mst;
84c7f8ca 810 dma_addr_t uv_mst = 0;
2048e328
MY		 811 enum vop_data_format format;
812 uint32_t val;
813 bool is_alpha;
85a359f2 814 bool rb_swap;
84c7f8ca 815 bool is_yuv;
2048e328
MY		 816 bool visible;
817 int ret;
818 struct drm_rect dest = {
819 .x1 = crtc_x,
820 .y1 = crtc_y,
821 .x2 = crtc_x + crtc_w,
822 .y2 = crtc_y + crtc_h,
823 };
824 struct drm_rect src = {
825 /* 16.16 fixed point */
826 .x1 = src_x,
827 .y1 = src_y,
828 .x2 = src_x + src_w,
829 .y2 = src_y + src_h,
830 };
831 const struct drm_rect clip = {
832 .x2 = crtc->mode.hdisplay,
833 .y2 = crtc->mode.vdisplay,
834 };
835 bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
4c156c21
MY		 836 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
837 DRM_PLANE_HELPER_NO_SCALING;
838 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
839 DRM_PLANE_HELPER_NO_SCALING;
2048e328
MY		 840
841 ret = drm_plane_helper_check_update(plane, crtc, fb,
842 &src, &dest, &clip,
4c156c21
MY		 843 min_scale,
844 max_scale,
2048e328
MY		 845 can_position, false, &visible);
846 if (ret)
847 return ret;
848
849 if (!visible)
850 return 0;
851
852 is_alpha = is_alpha_support(fb->pixel_format);
85a359f2 853 rb_swap = has_rb_swapped(fb->pixel_format);
84c7f8ca
MY		 854 is_yuv = is_yuv_support(fb->pixel_format);
855
2048e328
MY		 856 format = vop_convert_format(fb->pixel_format);
857 if (format < 0)
858 return format;
859
860 obj = rockchip_fb_get_gem_obj(fb, 0);
861 if (!obj) {
862 DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
863 return -EINVAL;
864 }
865
866 rk_obj = to_rockchip_obj(obj);
867
84c7f8ca
MY		 868 if (is_yuv) {
869 /*
870 * Src.x1 can be odd when do clip, but yuv plane start point
871 * need align with 2 pixel.
872 */
873 val = (src.x1 >> 16) % 2;
874 src.x1 += val << 16;
875 src.x2 += val << 16;
876 }
877
2048e328
MY		 878 actual_w = (src.x2 - src.x1) >> 16;
879 actual_h = (src.y2 - src.y1) >> 16;
2048e328 880
acf8c3e0
MY		 881 dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
882 dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
2048e328 883
84c7f8ca 884 offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
2048e328 885 offset += (src.y1 >> 16) * fb->pitches[0];
2048e328 886
84c7f8ca 887 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
f1c79abe 888 y_vir_stride = fb->pitches[0] >> 2;
2048e328 889
84c7f8ca
MY		 890 if (is_yuv) {
891 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
892 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
893 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
894
895 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
896 if (!uv_obj) {
897 DRM_ERROR("fail to get uv object from framebuffer\n");
898 return -EINVAL;
899 }
900 rk_uv_obj = to_rockchip_obj(uv_obj);
901 uv_vir_stride = fb->pitches[1] >> 2;
902
903 offset = (src.x1 >> 16) * bpp / hsub;
904 offset += (src.y1 >> 16) * fb->pitches[1] / vsub;
905
906 uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1];
907 }
908
2048e328
MY		 909 /*
910 * If this plane update changes the plane's framebuffer, (or more
911 * precisely, if this update has a different framebuffer than the last
912 * update), enqueue it so we can track when it completes.
913 *
914 * Only when we discover that this update has completed, can we
915 * unreference any previous framebuffers.
916 */
917 mutex_lock(&vop->vsync_mutex);
918 if (fb != vop_win_last_pending_fb(vop_win)) {
b5f7b755 919 ret = drm_crtc_vblank_get(crtc);
2048e328
MY		 920 if (ret) {
921 DRM_ERROR("failed to get vblank, %d\n", ret);
922 mutex_unlock(&vop->vsync_mutex);
923 return ret;
924 }
925
926 drm_framebuffer_reference(fb);
927
928 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event);
929 if (ret) {
b5f7b755 930 drm_crtc_vblank_put(crtc);
2048e328
MY		 931 mutex_unlock(&vop->vsync_mutex);
932 return ret;
933 }
934
935 vop->vsync_work_pending = true;
936 }
937 mutex_unlock(&vop->vsync_mutex);
938
939 spin_lock(&vop->reg_lock);
940
941 VOP_WIN_SET(vop, win, format, format);
942 VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
943 VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
84c7f8ca
MY		 944 if (is_yuv) {
945 VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
946 VOP_WIN_SET(vop, win, uv_mst, uv_mst);
947 }
4c156c21
MY		 948
949 if (win->phy->scl)
950 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
951 dest.x2 - dest.x1, dest.y2 - dest.y1,
952 fb->pixel_format);
953
2048e328
MY		 954 val = (actual_h - 1) << 16;
955 val |= (actual_w - 1) & 0xffff;
956 VOP_WIN_SET(vop, win, act_info, val);
4c156c21
MY		 957
958 val = (dest.y2 - dest.y1 - 1) << 16;
959 val |= (dest.x2 - dest.x1 - 1) & 0xffff;
2048e328 960 VOP_WIN_SET(vop, win, dsp_info, val);
72906ce0
DB		 961 val = dsp_sty << 16;
962 val |= dsp_stx & 0xffff;
2048e328 963 VOP_WIN_SET(vop, win, dsp_st, val);
85a359f2 964 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
2048e328
MY		 965
966 if (is_alpha) {
967 VOP_WIN_SET(vop, win, dst_alpha_ctl,
968 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
969 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
970 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
971 SRC_BLEND_M0(ALPHA_PER_PIX) |
972 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
973 SRC_FACTOR_M0(ALPHA_ONE);
974 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
975 } else {
976 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
977 }
978
979 VOP_WIN_SET(vop, win, enable, 1);
980
981 vop_cfg_done(vop);
982 spin_unlock(&vop->reg_lock);
983
984 return 0;
985}
986
987static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
988 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
989 unsigned int crtc_w, unsigned int crtc_h,
990 uint32_t src_x, uint32_t src_y, uint32_t src_w,
991 uint32_t src_h)
992{
993 return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w,
994 crtc_h, src_x, src_y, src_w, src_h,
995 NULL);
996}
997
998static int vop_update_primary_plane(struct drm_crtc *crtc,
999 struct drm_pending_vblank_event *event)
1000{
1001 unsigned int crtc_w, crtc_h;
1002
1003 crtc_w = crtc->primary->fb->width - crtc->x;
1004 crtc_h = crtc->primary->fb->height - crtc->y;
1005
1006 return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb,
1007 0, 0, crtc_w, crtc_h, crtc->x << 16,
1008 crtc->y << 16, crtc_w << 16,
1009 crtc_h << 16, event);
1010}
1011
1012static int vop_disable_plane(struct drm_plane *plane)
1013{
1014 struct vop_win *vop_win = to_vop_win(plane);
1015 const struct vop_win_data *win = vop_win->data;
1016 struct vop *vop;
1017 int ret;
1018
1019 if (!plane->crtc)
1020 return 0;
1021
1022 vop = to_vop(plane->crtc);
1023
b5f7b755 1024 ret = drm_crtc_vblank_get(plane->crtc);
2048e328
MY		 1025 if (ret) {
1026 DRM_ERROR("failed to get vblank, %d\n", ret);
1027 return ret;
1028 }
1029
1030 mutex_lock(&vop->vsync_mutex);
1031
1032 ret = vop_win_queue_fb(vop_win, NULL, 0, NULL);
1033 if (ret) {
b5f7b755 1034 drm_crtc_vblank_put(plane->crtc);
2048e328
MY		 1035 mutex_unlock(&vop->vsync_mutex);
1036 return ret;
1037 }
1038
1039 vop->vsync_work_pending = true;
1040 mutex_unlock(&vop->vsync_mutex);
1041
1042 spin_lock(&vop->reg_lock);
1043 VOP_WIN_SET(vop, win, enable, 0);
1044 vop_cfg_done(vop);
1045 spin_unlock(&vop->reg_lock);
1046
1047 return 0;
1048}
1049
1050static void vop_plane_destroy(struct drm_plane *plane)
1051{
1052 vop_disable_plane(plane);
1053 drm_plane_cleanup(plane);
1054}
1055
1056static const struct drm_plane_funcs vop_plane_funcs = {
1057 .update_plane = vop_update_plane,
1058 .disable_plane = vop_disable_plane,
1059 .destroy = vop_plane_destroy,
1060};
1061
1062int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
1063 int connector_type,
1064 int out_mode)
1065{
1066 struct vop *vop = to_vop(crtc);
1067
1068 vop->connector_type = connector_type;
1069 vop->connector_out_mode = out_mode;
1070
1071 return 0;
1072}
f66a1627 1073EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
2048e328
MY		 1074
1075static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1076{
1077 struct vop *vop = to_vop(crtc);
1078 unsigned long flags;
1079
31e980c5 1080 if (!vop->is_enabled)
2048e328
MY		 1081 return -EPERM;
1082
1083 spin_lock_irqsave(&vop->irq_lock, flags);
1084
1085 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
1086
1087 spin_unlock_irqrestore(&vop->irq_lock, flags);
1088
1089 return 0;
1090}
1091
1092static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1093{
1094 struct vop *vop = to_vop(crtc);
1095 unsigned long flags;
1096
31e980c5 1097 if (!vop->is_enabled)
2048e328 1098 return;
31e980c5 1099
2048e328
MY		 1100 spin_lock_irqsave(&vop->irq_lock, flags);
1101 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
1102 spin_unlock_irqrestore(&vop->irq_lock, flags);
1103}
1104
1105static const struct rockchip_crtc_funcs private_crtc_funcs = {
1106 .enable_vblank = vop_crtc_enable_vblank,
1107 .disable_vblank = vop_crtc_disable_vblank,
1108};
1109
1110static void vop_crtc_dpms(struct drm_crtc *crtc, int mode)
1111{
2048e328
MY		 1112 DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode);
1113
2048e328
MY		 1114 switch (mode) {
1115 case DRM_MODE_DPMS_ON:
1116 vop_enable(crtc);
1117 break;
1118 case DRM_MODE_DPMS_STANDBY:
1119 case DRM_MODE_DPMS_SUSPEND:
1120 case DRM_MODE_DPMS_OFF:
1121 vop_disable(crtc);
1122 break;
1123 default:
1124 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
1125 break;
1126 }
2048e328
MY		 1127}
1128
1129static void vop_crtc_prepare(struct drm_crtc *crtc)
1130{
1131 vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1132}
1133
1134static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1135 const struct drm_display_mode *mode,
1136 struct drm_display_mode *adjusted_mode)
1137{
1138 if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
1139 return false;
1140
1141 return true;
1142}
1143
1144static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1145 struct drm_framebuffer *old_fb)
1146{
1147 int ret;
1148
1149 crtc->x = x;
1150 crtc->y = y;
1151
1152 ret = vop_update_primary_plane(crtc, NULL);
1153 if (ret < 0) {
1154 DRM_ERROR("fail to update plane\n");
1155 return ret;
1156 }
1157
1158 return 0;
1159}
1160
1161static int vop_crtc_mode_set(struct drm_crtc *crtc,
1162 struct drm_display_mode *mode,
1163 struct drm_display_mode *adjusted_mode,
1164 int x, int y, struct drm_framebuffer *fb)
1165{
1166 struct vop *vop = to_vop(crtc);
1167 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1168 u16 hdisplay = adjusted_mode->hdisplay;
1169 u16 htotal = adjusted_mode->htotal;
1170 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1171 u16 hact_end = hact_st + hdisplay;
1172 u16 vdisplay = adjusted_mode->vdisplay;
1173 u16 vtotal = adjusted_mode->vtotal;
1174 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1175 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1176 u16 vact_end = vact_st + vdisplay;
7f53fbba 1177 int ret, ret_clk;
2048e328
MY		 1178 uint32_t val;
1179
1180 /*
1181 * disable dclk to stop frame scan, so that we can safe config mode and
1182 * enable iommu.
1183 */
1184 clk_disable(vop->dclk);
1185
1186 switch (vop->connector_type) {
1187 case DRM_MODE_CONNECTOR_LVDS:
1188 VOP_CTRL_SET(vop, rgb_en, 1);
1189 break;
1190 case DRM_MODE_CONNECTOR_eDP:
1191 VOP_CTRL_SET(vop, edp_en, 1);
1192 break;
1193 case DRM_MODE_CONNECTOR_HDMIA:
1194 VOP_CTRL_SET(vop, hdmi_en, 1);
1195 break;
1196 default:
1197 DRM_ERROR("unsupport connector_type[%d]\n",
1198 vop->connector_type);
7f53fbba
HS		 1199 ret = -EINVAL;
1200 goto out;
2048e328
MY		 1201 };
1202 VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
1203
1204 val = 0x8;
44ddb7ef
MY		 1205 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1206 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
2048e328
MY		 1207 VOP_CTRL_SET(vop, pin_pol, val);
1208
1209 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1210 val = hact_st << 16;
1211 val |= hact_end;
1212 VOP_CTRL_SET(vop, hact_st_end, val);
1213 VOP_CTRL_SET(vop, hpost_st_end, val);
1214
1215 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1216 val = vact_st << 16;
1217 val |= vact_end;
1218 VOP_CTRL_SET(vop, vact_st_end, val);
1219 VOP_CTRL_SET(vop, vpost_st_end, val);
1220
1221 ret = vop_crtc_mode_set_base(crtc, x, y, fb);
1222 if (ret)
7f53fbba 1223 goto out;
2048e328
MY		 1224
1225 /*
1226 * reset dclk, take all mode config affect, so the clk would run in
1227 * correct frame.
1228 */
1229 reset_control_assert(vop->dclk_rst);
1230 usleep_range(10, 20);
1231 reset_control_deassert(vop->dclk_rst);
1232
1233 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
7f53fbba
HS		 1234out:
1235 ret_clk = clk_enable(vop->dclk);
1236 if (ret_clk < 0) {
1237 dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk);
1238 return ret_clk;
2048e328
MY		 1239 }
1240
7f53fbba 1241 return ret;
2048e328
MY		 1242}
1243
1244static void vop_crtc_commit(struct drm_crtc *crtc)
1245{
1246}
1247
1248static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1249 .dpms = vop_crtc_dpms,
1250 .prepare = vop_crtc_prepare,
1251 .mode_fixup = vop_crtc_mode_fixup,
1252 .mode_set = vop_crtc_mode_set,
1253 .mode_set_base = vop_crtc_mode_set_base,
1254 .commit = vop_crtc_commit,
1255};
1256
1257static int vop_crtc_page_flip(struct drm_crtc *crtc,
1258 struct drm_framebuffer *fb,
1259 struct drm_pending_vblank_event *event,
1260 uint32_t page_flip_flags)
1261{
1262 struct vop *vop = to_vop(crtc);
1263 struct drm_framebuffer *old_fb = crtc->primary->fb;
1264 int ret;
1265
31e980c5
MY		 1266 /* when the page flip is requested, crtc should be on */
1267 if (!vop->is_enabled) {
1268 DRM_DEBUG("page flip request rejected because crtc is off.\n");
2048e328
MY		 1269 return 0;
1270 }
1271
1272 crtc->primary->fb = fb;
1273
1274 ret = vop_update_primary_plane(crtc, event);
1275 if (ret)
1276 crtc->primary->fb = old_fb;
1277
1278 return ret;
1279}
1280
1281static void vop_win_state_complete(struct vop_win *vop_win,
1282 struct vop_win_state *state)
1283{
1284 struct vop *vop = vop_win->vop;
1285 struct drm_crtc *crtc = &vop->crtc;
1286 struct drm_device *drm = crtc->dev;
1287 unsigned long flags;
1288
1289 if (state->event) {
1290 spin_lock_irqsave(&drm->event_lock, flags);
c9fbb7f7 1291 drm_crtc_send_vblank_event(crtc, state->event);
2048e328
MY		 1292 spin_unlock_irqrestore(&drm->event_lock, flags);
1293 }
1294
1295 list_del(&state->head);
b5f7b755 1296 drm_crtc_vblank_put(crtc);
2048e328
MY		 1297}
1298
1299static void vop_crtc_destroy(struct drm_crtc *crtc)
1300{
1301 drm_crtc_cleanup(crtc);
1302}
1303
1304static const struct drm_crtc_funcs vop_crtc_funcs = {
1305 .set_config = drm_crtc_helper_set_config,
1306 .page_flip = vop_crtc_page_flip,
1307 .destroy = vop_crtc_destroy,
1308};
1309
1310static bool vop_win_state_is_active(struct vop_win *vop_win,
1311 struct vop_win_state *state)
1312{
1313 bool active = false;
1314
1315 if (state->fb) {
1316 dma_addr_t yrgb_mst;
1317
1318 /* check yrgb_mst to tell if pending_fb is now front */
1319 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1320
1321 active = (yrgb_mst == state->yrgb_mst);
1322 } else {
1323 bool enabled;
1324
1325 /* if enable bit is clear, plane is now disabled */
1326 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable);
1327
1328 active = (enabled == 0);
1329 }
1330
1331 return active;
1332}
1333
1334static void vop_win_state_destroy(struct vop_win_state *state)
1335{
1336 struct drm_framebuffer *fb = state->fb;
1337
1338 if (fb)
1339 drm_framebuffer_unreference(fb);
1340
1341 kfree(state);
1342}
1343
1344static void vop_win_update_state(struct vop_win *vop_win)
1345{
1346 struct vop_win_state *state, *n, *new_active = NULL;
1347
1348 /* Check if any pending states are now active */
1349 list_for_each_entry(state, &vop_win->pending, head)
1350 if (vop_win_state_is_active(vop_win, state)) {
1351 new_active = state;
1352 break;
1353 }
1354
1355 if (!new_active)
1356 return;
1357
1358 /*
1359 * Destroy any 'skipped' pending states - states that were queued
1360 * before the newly active state.
1361 */
1362 list_for_each_entry_safe(state, n, &vop_win->pending, head) {
1363 if (state == new_active)
1364 break;
1365 vop_win_state_complete(vop_win, state);
1366 vop_win_state_destroy(state);
1367 }
1368
1369 vop_win_state_complete(vop_win, new_active);
1370
1371 if (vop_win->active)
1372 vop_win_state_destroy(vop_win->active);
1373 vop_win->active = new_active;
1374}
1375
1376static bool vop_win_has_pending_state(struct vop_win *vop_win)
1377{
1378 return !list_empty(&vop_win->pending);
1379}
1380
1381static irqreturn_t vop_isr_thread(int irq, void *data)
1382{
1383 struct vop *vop = data;
1384 const struct vop_data *vop_data = vop->data;
1385 unsigned int i;
1386
1387 mutex_lock(&vop->vsync_mutex);
1388
1389 if (!vop->vsync_work_pending)
1390 goto done;
1391
1392 vop->vsync_work_pending = false;
1393
1394 for (i = 0; i < vop_data->win_size; i++) {
1395 struct vop_win *vop_win = &vop->win[i];
1396
1397 vop_win_update_state(vop_win);
1398 if (vop_win_has_pending_state(vop_win))
1399 vop->vsync_work_pending = true;
1400 }
1401
1402done:
1403 mutex_unlock(&vop->vsync_mutex);
1404
1405 return IRQ_HANDLED;
1406}
1407
1408static irqreturn_t vop_isr(int irq, void *data)
1409{
1410 struct vop *vop = data;
b5f7b755 1411 struct drm_crtc *crtc = &vop->crtc;
2048e328
MY		 1412 uint32_t intr0_reg, active_irqs;
1413 unsigned long flags;
1067219b 1414 int ret = IRQ_NONE;
2048e328
MY		 1415
1416 /*
1417 * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1418 * must hold irq_lock to avoid a race with enable/disable_vblank().
1419 */
1420 spin_lock_irqsave(&vop->irq_lock, flags);
1421 intr0_reg = vop_readl(vop, INTR_CTRL0);
1422 active_irqs = intr0_reg & INTR_MASK;
1423 /* Clear all active interrupt sources */
1424 if (active_irqs)
1425 vop_writel(vop, INTR_CTRL0,
1426 intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1427 spin_unlock_irqrestore(&vop->irq_lock, flags);
1428
1429 /* This is expected for vop iommu irqs, since the irq is shared */
1430 if (!active_irqs)
1431 return IRQ_NONE;
1432
1067219b
MY		 1433 if (active_irqs & DSP_HOLD_VALID_INTR) {
1434 complete(&vop->dsp_hold_completion);
1435 active_irqs &= ~DSP_HOLD_VALID_INTR;
1436 ret = IRQ_HANDLED;
2048e328
MY		 1437 }
1438
1067219b 1439 if (active_irqs & FS_INTR) {
b5f7b755 1440 drm_crtc_handle_vblank(crtc);
1067219b
MY		 1441 active_irqs &= ~FS_INTR;
1442 ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1443 }
2048e328 1444
1067219b
MY		 1445 /* Unhandled irqs are spurious. */
1446 if (active_irqs)
1447 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1448
1449 return ret;
2048e328
MY		 1450}
1451
1452static int vop_create_crtc(struct vop *vop)
1453{
1454 const struct vop_data *vop_data = vop->data;
1455 struct device *dev = vop->dev;
1456 struct drm_device *drm_dev = vop->drm_dev;
1457 struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1458 struct drm_crtc *crtc = &vop->crtc;
1459 struct device_node *port;
1460 int ret;
1461 int i;
1462
1463 /*
1464 * Create drm_plane for primary and cursor planes first, since we need
1465 * to pass them to drm_crtc_init_with_planes, which sets the
1466 * "possible_crtcs" to the newly initialized crtc.
1467 */
1468 for (i = 0; i < vop_data->win_size; i++) {
1469 struct vop_win *vop_win = &vop->win[i];
1470 const struct vop_win_data *win_data = vop_win->data;
1471
1472 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1473 win_data->type != DRM_PLANE_TYPE_CURSOR)
1474 continue;
1475
1476 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1477 0, &vop_plane_funcs,
1478 win_data->phy->data_formats,
1479 win_data->phy->nformats,
b0b3b795 1480 win_data->type, NULL);
2048e328
MY		 1481 if (ret) {
1482 DRM_ERROR("failed to initialize plane\n");
1483 goto err_cleanup_planes;
1484 }
1485
1486 plane = &vop_win->base;
1487 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1488 primary = plane;
1489 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1490 cursor = plane;
1491 }
1492
1493 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
f9882876 1494 &vop_crtc_funcs, NULL);
2048e328
MY		 1495 if (ret)
1496 return ret;
1497
1498 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1499
1500 /*
1501 * Create drm_planes for overlay windows with possible_crtcs restricted
1502 * to the newly created crtc.
1503 */
1504 for (i = 0; i < vop_data->win_size; i++) {
1505 struct vop_win *vop_win = &vop->win[i];
1506 const struct vop_win_data *win_data = vop_win->data;
1507 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1508
1509 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1510 continue;
1511
1512 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1513 possible_crtcs,
1514 &vop_plane_funcs,
1515 win_data->phy->data_formats,
1516 win_data->phy->nformats,
b0b3b795 1517 win_data->type, NULL);
2048e328
MY		 1518 if (ret) {
1519 DRM_ERROR("failed to initialize overlay plane\n");
1520 goto err_cleanup_crtc;
1521 }
1522 }
1523
1524 port = of_get_child_by_name(dev->of_node, "port");
1525 if (!port) {
1526 DRM_ERROR("no port node found in %s\n",
1527 dev->of_node->full_name);
1528 goto err_cleanup_crtc;
1529 }
1530
1067219b 1531 init_completion(&vop->dsp_hold_completion);
2048e328 1532 crtc->port = port;
b5f7b755 1533 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2048e328
MY		 1534
1535 return 0;
1536
1537err_cleanup_crtc:
1538 drm_crtc_cleanup(crtc);
1539err_cleanup_planes:
1540 list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1541 drm_plane_cleanup(plane);
1542 return ret;
1543}
1544
1545static void vop_destroy_crtc(struct vop *vop)
1546{
1547 struct drm_crtc *crtc = &vop->crtc;
1548
b5f7b755 1549 rockchip_unregister_crtc_funcs(crtc);
2048e328
MY		 1550 of_node_put(crtc->port);
1551 drm_crtc_cleanup(crtc);
1552}
1553
1554static int vop_initial(struct vop *vop)
1555{
1556 const struct vop_data *vop_data = vop->data;
1557 const struct vop_reg_data *init_table = vop_data->init_table;
1558 struct reset_control *ahb_rst;
1559 int i, ret;
1560
1561 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1562 if (IS_ERR(vop->hclk)) {
1563 dev_err(vop->dev, "failed to get hclk source\n");
1564 return PTR_ERR(vop->hclk);
1565 }
1566 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1567 if (IS_ERR(vop->aclk)) {
1568 dev_err(vop->dev, "failed to get aclk source\n");
1569 return PTR_ERR(vop->aclk);
1570 }
1571 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1572 if (IS_ERR(vop->dclk)) {
1573 dev_err(vop->dev, "failed to get dclk source\n");
1574 return PTR_ERR(vop->dclk);
1575 }
1576
2048e328
MY		 1577 ret = clk_prepare(vop->dclk);
1578 if (ret < 0) {
1579 dev_err(vop->dev, "failed to prepare dclk\n");
d7b53fd9 1580 return ret;
2048e328
MY		 1581 }
1582
d7b53fd9
SS		 1583 /* Enable both the hclk and aclk to setup the vop */
1584 ret = clk_prepare_enable(vop->hclk);
2048e328 1585 if (ret < 0) {
d7b53fd9 1586 dev_err(vop->dev, "failed to prepare/enable hclk\n");
2048e328
MY		 1587 goto err_unprepare_dclk;
1588 }
1589
d7b53fd9 1590 ret = clk_prepare_enable(vop->aclk);
2048e328 1591 if (ret < 0) {
d7b53fd9
SS		 1592 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1593 goto err_disable_hclk;
2048e328 1594 }
d7b53fd9 1595
2048e328
MY		 1596 /*
1597 * do hclk_reset, reset all vop registers.
1598 */
1599 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1600 if (IS_ERR(ahb_rst)) {
1601 dev_err(vop->dev, "failed to get ahb reset\n");
1602 ret = PTR_ERR(ahb_rst);
d7b53fd9 1603 goto err_disable_aclk;
2048e328
MY		 1604 }
1605 reset_control_assert(ahb_rst);
1606 usleep_range(10, 20);
1607 reset_control_deassert(ahb_rst);
1608
1609 memcpy(vop->regsbak, vop->regs, vop->len);
1610
1611 for (i = 0; i < vop_data->table_size; i++)
1612 vop_writel(vop, init_table[i].offset, init_table[i].value);
1613
1614 for (i = 0; i < vop_data->win_size; i++) {
1615 const struct vop_win_data *win = &vop_data->win[i];
1616
1617 VOP_WIN_SET(vop, win, enable, 0);
1618 }
1619
1620 vop_cfg_done(vop);
1621
1622 /*
1623 * do dclk_reset, let all config take affect.
1624 */
1625 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1626 if (IS_ERR(vop->dclk_rst)) {
1627 dev_err(vop->dev, "failed to get dclk reset\n");
1628 ret = PTR_ERR(vop->dclk_rst);
d7b53fd9 1629 goto err_disable_aclk;
2048e328
MY		 1630 }
1631 reset_control_assert(vop->dclk_rst);
1632 usleep_range(10, 20);
1633 reset_control_deassert(vop->dclk_rst);
1634
1635 clk_disable(vop->hclk);
d7b53fd9 1636 clk_disable(vop->aclk);
2048e328 1637
31e980c5 1638 vop->is_enabled = false;
2048e328
MY		 1639
1640 return 0;
1641
d7b53fd9
SS		 1642err_disable_aclk:
1643 clk_disable_unprepare(vop->aclk);
2048e328 1644err_disable_hclk:
d7b53fd9 1645 clk_disable_unprepare(vop->hclk);
2048e328
MY		 1646err_unprepare_dclk:
1647 clk_unprepare(vop->dclk);
2048e328
MY		 1648 return ret;
1649}
1650
1651/*
1652 * Initialize the vop->win array elements.
1653 */
1654static void vop_win_init(struct vop *vop)
1655{
1656 const struct vop_data *vop_data = vop->data;
1657 unsigned int i;
1658
1659 for (i = 0; i < vop_data->win_size; i++) {
1660 struct vop_win *vop_win = &vop->win[i];
1661 const struct vop_win_data *win_data = &vop_data->win[i];
1662
1663 vop_win->data = win_data;
1664 vop_win->vop = vop;
1665 INIT_LIST_HEAD(&vop_win->pending);
1666 }
1667}
1668
1669static int vop_bind(struct device *dev, struct device *master, void *data)
1670{
1671 struct platform_device *pdev = to_platform_device(dev);
1672 const struct of_device_id *of_id;
1673 const struct vop_data *vop_data;
1674 struct drm_device *drm_dev = data;
1675 struct vop *vop;
1676 struct resource *res;
1677 size_t alloc_size;
3ea68922 1678 int ret, irq;
2048e328
MY		 1679
1680 of_id = of_match_device(vop_driver_dt_match, dev);
1681 vop_data = of_id->data;
1682 if (!vop_data)
1683 return -ENODEV;
1684
1685 /* Allocate vop struct and its vop_win array */
1686 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1687 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1688 if (!vop)
1689 return -ENOMEM;
1690
1691 vop->dev = dev;
1692 vop->data = vop_data;
1693 vop->drm_dev = drm_dev;
1694 dev_set_drvdata(dev, vop);
1695
1696 vop_win_init(vop);
1697
1698 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1699 vop->len = resource_size(res);
1700 vop->regs = devm_ioremap_resource(dev, res);
1701 if (IS_ERR(vop->regs))
1702 return PTR_ERR(vop->regs);
1703
1704 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1705 if (!vop->regsbak)
1706 return -ENOMEM;
1707
1708 ret = vop_initial(vop);
1709 if (ret < 0) {
1710 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1711 return ret;
1712 }
1713
3ea68922
HS		 1714 irq = platform_get_irq(pdev, 0);
1715 if (irq < 0) {
2048e328 1716 dev_err(dev, "cannot find irq for vop\n");
3ea68922 1717 return irq;
2048e328 1718 }
3ea68922 1719 vop->irq = (unsigned int)irq;
2048e328
MY		 1720
1721 spin_lock_init(&vop->reg_lock);
1722 spin_lock_init(&vop->irq_lock);
1723
1724 mutex_init(&vop->vsync_mutex);
1725
1726 ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread,
1727 IRQF_SHARED, dev_name(dev), vop);
1728 if (ret)
1729 return ret;
1730
1731 /* IRQ is initially disabled; it gets enabled in power_on */
1732 disable_irq(vop->irq);
1733
1734 ret = vop_create_crtc(vop);
1735 if (ret)
1736 return ret;
1737
1738 pm_runtime_enable(&pdev->dev);
1739 return 0;
1740}
1741
1742static void vop_unbind(struct device *dev, struct device *master, void *data)
1743{
1744 struct vop *vop = dev_get_drvdata(dev);
1745
1746 pm_runtime_disable(dev);
1747 vop_destroy_crtc(vop);
1748}
1749
1750static const struct component_ops vop_component_ops = {
1751 .bind = vop_bind,
1752 .unbind = vop_unbind,
1753};
1754
1755static int vop_probe(struct platform_device *pdev)
1756{
1757 struct device *dev = &pdev->dev;
1758
1759 if (!dev->of_node) {
1760 dev_err(dev, "can't find vop devices\n");
1761 return -ENODEV;
1762 }
1763
1764 return component_add(dev, &vop_component_ops);
1765}
1766
1767static int vop_remove(struct platform_device *pdev)
1768{
1769 component_del(&pdev->dev, &vop_component_ops);
1770
1771 return 0;
1772}
1773
1774struct platform_driver vop_platform_driver = {
1775 .probe = vop_probe,
1776 .remove = vop_remove,
1777 .driver = {
1778 .name = "rockchip-vop",
1779 .owner = THIS_MODULE,
1780 .of_match_table = of_match_ptr(vop_driver_dt_match),
1781 },
1782};
1783
1784module_platform_driver(vop_platform_driver);
1785
1786MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1787MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1788MODULE_LICENSE("GPL v2");
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