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Merge tag 'omap-for-v5.0/fixes-rc7-signed' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / sun4i / sun4i_hdmi_enc.c
CommitLineData
9c568101
MR		 1/*
2 * Copyright (C) 2016 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 */
11
12#include <drm/drmP.h>
13#include <drm/drm_atomic_helper.h>
14#include <drm/drm_crtc_helper.h>
15#include <drm/drm_edid.h>
16#include <drm/drm_encoder.h>
17#include <drm/drm_of.h>
18#include <drm/drm_panel.h>
19
20#include <linux/clk.h>
21#include <linux/component.h>
22#include <linux/iopoll.h>
939d749a 23#include <linux/of_device.h>
9c568101
MR		 24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
4b1c924b 26#include <linux/regmap.h>
939d749a 27#include <linux/reset.h>
9c568101
MR		 28
29#include "sun4i_backend.h"
30#include "sun4i_crtc.h"
31#include "sun4i_drv.h"
32#include "sun4i_hdmi.h"
9c568101 33
9c568101
MR		 34static inline struct sun4i_hdmi *
35drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
36{
37 return container_of(encoder, struct sun4i_hdmi,
38 encoder);
39}
40
41static inline struct sun4i_hdmi *
42drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
43{
44 return container_of(connector, struct sun4i_hdmi,
45 connector);
46}
47
48static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
49 struct drm_display_mode *mode)
50{
51 struct hdmi_avi_infoframe frame;
52 u8 buffer[17];
53 int i, ret;
54
0c1f528c 55 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
9c568101
MR		 56 if (ret < 0) {
57 DRM_ERROR("Failed to get infoframes from mode\n");
58 return ret;
59 }
60
61 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
62 if (ret < 0) {
63 DRM_ERROR("Failed to pack infoframes\n");
64 return ret;
65 }
66
67 for (i = 0; i < sizeof(buffer); i++)
68 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
69
70 return 0;
71}
72
73static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
74 struct drm_crtc_state *crtc_state,
75 struct drm_connector_state *conn_state)
76{
77 struct drm_display_mode *mode = &crtc_state->mode;
78
79 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
80 return -EINVAL;
81
82 return 0;
83}
84
85static void sun4i_hdmi_disable(struct drm_encoder *encoder)
86{
87 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
9c568101
MR		 88 u32 val;
89
90 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
91
92 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
93 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
94 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
5e1bc251
PL		 95
96 clk_disable_unprepare(hdmi->tmds_clk);
9c568101
MR		 97}
98
99static void sun4i_hdmi_enable(struct drm_encoder *encoder)
100{
101 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
102 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
9c568101
MR		 103 u32 val = 0;
104
105 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
106
5e1bc251
PL		 107 clk_prepare_enable(hdmi->tmds_clk);
108
9c568101
MR		 109 sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
110 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
111 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
112 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
113
114 val = SUN4I_HDMI_VID_CTRL_ENABLE;
115 if (hdmi->hdmi_monitor)
116 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
117
118 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
119}
120
121static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
122 struct drm_display_mode *mode,
123 struct drm_display_mode *adjusted_mode)
124{
125 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
9c568101
MR		 126 unsigned int x, y;
127 u32 val;
128
9c568101
MR		 129 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
130 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
131
132 /* Set input sync enable */
133 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
134 hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
135
bfddd146
CYT		 136 /*
137 * Setup output pad (?) controls
138 *
139 * This is done here instead of at probe/bind time because
140 * the controller seems to toggle some of the bits on its own.
141 *
142 * We can't just initialize the register there, we need to
143 * protect the clock bits that have already been read out and
144 * cached by the clock framework.
145 */
146 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
147 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
148 val |= hdmi->variant->pad_ctrl1_init_val;
149 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
150 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
151
9c568101
MR		 152 /* Setup timing registers */
153 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
154 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
155 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
156
157 x = mode->htotal - mode->hsync_start;
158 y = mode->vtotal - mode->vsync_start;
159 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
160 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
161
162 x = mode->hsync_start - mode->hdisplay;
163 y = mode->vsync_start - mode->vdisplay;
164 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
165 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
166
167 x = mode->hsync_end - mode->hsync_start;
168 y = mode->vsync_end - mode->vsync_start;
169 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
170 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
171
172 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK;
173 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
174 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC;
175
176 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
177 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
178
179 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
180}
181
2c08cd7c
MR		 182static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder,
183 const struct drm_display_mode *mode)
184{
185 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
186 unsigned long rate = mode->clock * 1000;
187 unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */
188 long rounded_rate;
189
190 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */
191 if (rate > 165000000)
192 return MODE_CLOCK_HIGH;
193 rounded_rate = clk_round_rate(hdmi->tmds_clk, rate);
194 if (rounded_rate > 0 &&
195 max_t(unsigned long, rounded_rate, rate) -
196 min_t(unsigned long, rounded_rate, rate) < diff)
197 return MODE_OK;
198 return MODE_NOCLOCK;
199}
200
9c568101
MR		 201static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
202 .atomic_check = sun4i_hdmi_atomic_check,
203 .disable = sun4i_hdmi_disable,
204 .enable = sun4i_hdmi_enable,
205 .mode_set = sun4i_hdmi_mode_set,
2c08cd7c 206 .mode_valid = sun4i_hdmi_mode_valid,
9c568101
MR		 207};
208
209static const struct drm_encoder_funcs sun4i_hdmi_funcs = {
210 .destroy = drm_encoder_cleanup,
211};
212
9c568101
MR		 213static int sun4i_hdmi_get_modes(struct drm_connector *connector)
214{
215 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
9c568101
MR		 216 struct edid *edid;
217 int ret;
218
f0a3dd33 219 edid = drm_get_edid(connector, hdmi->i2c);
9c568101
MR		 220 if (!edid)
221 return 0;
222
223 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
224 DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
225 hdmi->hdmi_monitor ? "an HDMI" : "a DVI");
226
c555f023 227 drm_connector_update_edid_property(connector, edid);
998140d2 228 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
9c568101
MR		 229 ret = drm_add_edid_modes(connector, edid);
230 kfree(edid);
231
9c568101
MR		 232 return ret;
233}
234
235static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
236 .get_modes = sun4i_hdmi_get_modes,
237};
238
239static enum drm_connector_status
240sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
241{
242 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
243 unsigned long reg;
244
245 if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg,
246 reg & SUN4I_HDMI_HPD_HIGH,
998140d2
HV		 247 0, 500000)) {
248 cec_phys_addr_invalidate(hdmi->cec_adap);
9c568101 249 return connector_status_disconnected;
998140d2 250 }
9c568101
MR		 251
252 return connector_status_connected;
253}
254
255static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
9c568101
MR		 256 .detect = sun4i_hdmi_connector_detect,
257 .fill_modes = drm_helper_probe_single_connector_modes,
258 .destroy = drm_connector_cleanup,
259 .reset = drm_atomic_helper_connector_reset,
260 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
261 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
262};
263
998140d2
HV		 264#ifdef CONFIG_DRM_SUN4I_HDMI_CEC
265static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
266{
267 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
268
269 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
270}
271
272static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
273{
274 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
275
276 /* Start driving the CEC pin low */
277 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
278}
279
280static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
281{
282 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
283
284 /*
285 * Stop driving the CEC pin, the pull up will take over
286 * unless another CEC device is driving the pin low.
287 */
288 writel(0, hdmi->base + SUN4I_HDMI_CEC);
289}
290
291static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
292 .read = sun4i_hdmi_cec_pin_read,
293 .low = sun4i_hdmi_cec_pin_low,
294 .high = sun4i_hdmi_cec_pin_high,
295};
296#endif
297
939d749a
CYT		 298#define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0))
299#define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0))
300
7ea4291f
CYT		 301/* Only difference from sun5i is AMP is 4 instead of 6 */
302static const struct sun4i_hdmi_variant sun4i_variant = {
303 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
304 SUN4I_HDMI_PAD_CTRL0_CKEN |
305 SUN4I_HDMI_PAD_CTRL0_PWENG |
306 SUN4I_HDMI_PAD_CTRL0_PWEND |
307 SUN4I_HDMI_PAD_CTRL0_PWENC |
308 SUN4I_HDMI_PAD_CTRL0_LDODEN |
309 SUN4I_HDMI_PAD_CTRL0_LDOCEN |
310 SUN4I_HDMI_PAD_CTRL0_BIASEN,
311 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) |
312 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
313 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
314 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
315 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
316 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
317 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
318 SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
319 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
320 SUN4I_HDMI_PLL_CTRL_CS(7) |
321 SUN4I_HDMI_PLL_CTRL_CP_S(15) |
322 SUN4I_HDMI_PLL_CTRL_S(7) |
323 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
324 SUN4I_HDMI_PLL_CTRL_SDIV2 |
325 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
326 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
327 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
328 SUN4I_HDMI_PLL_CTRL_BWS |
329 SUN4I_HDMI_PLL_CTRL_PLL_EN,
330
331 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
332 .ddc_clk_pre_divider = 2,
333 .ddc_clk_m_offset = 1,
334
335 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
336 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
337 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
338 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
339 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
340 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
341 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
342 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
343 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
344 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
345 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
346 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
347 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
348
349 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG,
350 .ddc_fifo_has_dir = true,
351};
352
939d749a
CYT		 353static const struct sun4i_hdmi_variant sun5i_variant = {
354 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
355 SUN4I_HDMI_PAD_CTRL0_CKEN |
356 SUN4I_HDMI_PAD_CTRL0_PWENG |
357 SUN4I_HDMI_PAD_CTRL0_PWEND |
358 SUN4I_HDMI_PAD_CTRL0_PWENC |
359 SUN4I_HDMI_PAD_CTRL0_LDODEN |
360 SUN4I_HDMI_PAD_CTRL0_LDOCEN |
361 SUN4I_HDMI_PAD_CTRL0_BIASEN,
362 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
363 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
364 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
365 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
366 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
367 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
368 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
369 SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
370 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
371 SUN4I_HDMI_PLL_CTRL_CS(7) |
372 SUN4I_HDMI_PLL_CTRL_CP_S(15) |
373 SUN4I_HDMI_PLL_CTRL_S(7) |
374 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
375 SUN4I_HDMI_PLL_CTRL_SDIV2 |
376 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
377 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
378 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
379 SUN4I_HDMI_PLL_CTRL_BWS |
380 SUN4I_HDMI_PLL_CTRL_PLL_EN,
381
382 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
383 .ddc_clk_pre_divider = 2,
384 .ddc_clk_m_offset = 1,
385
386 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
387 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
388 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
389 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
390 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
391 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
392 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
393 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
394 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
395 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
396 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
397 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
398 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
399
400 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG,
401 .ddc_fifo_has_dir = true,
402};
403
da184dee
CYT		 404static const struct sun4i_hdmi_variant sun6i_variant = {
405 .has_ddc_parent_clk = true,
406 .has_reset_control = true,
407 .pad_ctrl0_init_val = 0xff |
408 SUN4I_HDMI_PAD_CTRL0_TXEN |
409 SUN4I_HDMI_PAD_CTRL0_CKEN |
410 SUN4I_HDMI_PAD_CTRL0_PWENG |
411 SUN4I_HDMI_PAD_CTRL0_PWEND |
412 SUN4I_HDMI_PAD_CTRL0_PWENC |
413 SUN4I_HDMI_PAD_CTRL0_LDODEN |
414 SUN4I_HDMI_PAD_CTRL0_LDOCEN,
415 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
416 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) |
417 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
418 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
419 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
420 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
421 SUN4I_HDMI_PAD_CTRL1_PWSDT |
422 SUN4I_HDMI_PAD_CTRL1_PWSCK |
423 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
424 SUN4I_HDMI_PAD_CTRL1_AMP_OPT |
425 SUN4I_HDMI_PAD_CTRL1_UNKNOWN,
426 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
427 SUN4I_HDMI_PLL_CTRL_CS(3) |
428 SUN4I_HDMI_PLL_CTRL_CP_S(10) |
429 SUN4I_HDMI_PLL_CTRL_S(4) |
430 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
431 SUN4I_HDMI_PLL_CTRL_SDIV2 |
432 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
433 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
434 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
435 SUN4I_HDMI_PLL_CTRL_PLL_EN,
436
437 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6),
438 .ddc_clk_pre_divider = 1,
439 .ddc_clk_m_offset = 2,
440
441 .tmds_clk_div_offset = 1,
442
443 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0),
444 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27),
445 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31),
446 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31),
447 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7),
448 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8),
449 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18),
450 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
451 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
452 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25),
453 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2),
454 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6),
455 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4),
456
457 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG,
458 .ddc_fifo_thres_incl = true,
459};
460
4b1c924b
CYT		 461static const struct regmap_config sun4i_hdmi_regmap_config = {
462 .reg_bits = 32,
463 .val_bits = 32,
464 .reg_stride = 4,
465 .max_register = 0x580,
466};
467
9c568101
MR		 468static int sun4i_hdmi_bind(struct device *dev, struct device *master,
469 void *data)
470{
471 struct platform_device *pdev = to_platform_device(dev);
472 struct drm_device *drm = data;
473 struct sun4i_drv *drv = drm->dev_private;
474 struct sun4i_hdmi *hdmi;
475 struct resource *res;
476 u32 reg;
477 int ret;
478
479 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
480 if (!hdmi)
481 return -ENOMEM;
482 dev_set_drvdata(dev, hdmi);
483 hdmi->dev = dev;
484 hdmi->drv = drv;
485
939d749a
CYT		 486 hdmi->variant = of_device_get_match_data(dev);
487 if (!hdmi->variant)
488 return -EINVAL;
489
9c568101
MR		 490 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
491 hdmi->base = devm_ioremap_resource(dev, res);
492 if (IS_ERR(hdmi->base)) {
493 dev_err(dev, "Couldn't map the HDMI encoder registers\n");
494 return PTR_ERR(hdmi->base);
495 }
496
939d749a
CYT		 497 if (hdmi->variant->has_reset_control) {
498 hdmi->reset = devm_reset_control_get(dev, NULL);
499 if (IS_ERR(hdmi->reset)) {
500 dev_err(dev, "Couldn't get the HDMI reset control\n");
501 return PTR_ERR(hdmi->reset);
502 }
503
504 ret = reset_control_deassert(hdmi->reset);
505 if (ret) {
506 dev_err(dev, "Couldn't deassert HDMI reset\n");
507 return ret;
508 }
509 }
510
9c568101
MR		 511 hdmi->bus_clk = devm_clk_get(dev, "ahb");
512 if (IS_ERR(hdmi->bus_clk)) {
513 dev_err(dev, "Couldn't get the HDMI bus clock\n");
939d749a
CYT		 514 ret = PTR_ERR(hdmi->bus_clk);
515 goto err_assert_reset;
9c568101
MR		 516 }
517 clk_prepare_enable(hdmi->bus_clk);
518
519 hdmi->mod_clk = devm_clk_get(dev, "mod");
520 if (IS_ERR(hdmi->mod_clk)) {
521 dev_err(dev, "Couldn't get the HDMI mod clock\n");
544c5048
CYT		 522 ret = PTR_ERR(hdmi->mod_clk);
523 goto err_disable_bus_clk;
9c568101
MR		 524 }
525 clk_prepare_enable(hdmi->mod_clk);
526
527 hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
528 if (IS_ERR(hdmi->pll0_clk)) {
529 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
544c5048
CYT		 530 ret = PTR_ERR(hdmi->pll0_clk);
531 goto err_disable_mod_clk;
9c568101
MR		 532 }
533
534 hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
535 if (IS_ERR(hdmi->pll1_clk)) {
536 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
544c5048
CYT		 537 ret = PTR_ERR(hdmi->pll1_clk);
538 goto err_disable_mod_clk;
9c568101
MR		 539 }
540
4b1c924b
CYT		 541 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
542 &sun4i_hdmi_regmap_config);
543 if (IS_ERR(hdmi->regmap)) {
544 dev_err(dev, "Couldn't create HDMI encoder regmap\n");
8250e6ca
CJ		 545 ret = PTR_ERR(hdmi->regmap);
546 goto err_disable_mod_clk;
4b1c924b
CYT		 547 }
548
9c568101
MR		 549 ret = sun4i_tmds_create(hdmi);
550 if (ret) {
551 dev_err(dev, "Couldn't create the TMDS clock\n");
544c5048 552 goto err_disable_mod_clk;
9c568101
MR		 553 }
554
939d749a
CYT		 555 if (hdmi->variant->has_ddc_parent_clk) {
556 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
557 if (IS_ERR(hdmi->ddc_parent_clk)) {
558 dev_err(dev, "Couldn't get the HDMI DDC clock\n");
1bc659eb
CJ		 559 ret = PTR_ERR(hdmi->ddc_parent_clk);
560 goto err_disable_mod_clk;
939d749a
CYT		 561 }
562 } else {
563 hdmi->ddc_parent_clk = hdmi->tmds_clk;
564 }
565
9c568101
MR		 566 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
567
939d749a 568 writel(hdmi->variant->pad_ctrl0_init_val,
9c568101
MR		 569 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
570
9c568101
MR		 571 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
572 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
939d749a 573 reg |= hdmi->variant->pll_ctrl_init_val;
9c568101
MR		 574 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
575
f0a3dd33 576 ret = sun4i_hdmi_i2c_create(dev, hdmi);
9c568101 577 if (ret) {
f0a3dd33 578 dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
544c5048 579 goto err_disable_mod_clk;
9c568101
MR		 580 }
581
582 drm_encoder_helper_add(&hdmi->encoder,
583 &sun4i_hdmi_helper_funcs);
584 ret = drm_encoder_init(drm,
585 &hdmi->encoder,
586 &sun4i_hdmi_funcs,
587 DRM_MODE_ENCODER_TMDS,
588 NULL);
589 if (ret) {
590 dev_err(dev, "Couldn't initialise the HDMI encoder\n");
f0a3dd33 591 goto err_del_i2c_adapter;
9c568101
MR		 592 }
593
594 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
595 dev->of_node);
f0a3dd33
JL		 596 if (!hdmi->encoder.possible_crtcs) {
597 ret = -EPROBE_DEFER;
598 goto err_del_i2c_adapter;
599 }
9c568101 600
998140d2
HV		 601#ifdef CONFIG_DRM_SUN4I_HDMI_CEC
602 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
603 hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
604 CEC_CAP_PASSTHROUGH | CEC_CAP_RC);
605 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
606 if (ret < 0)
607 goto err_cleanup_connector;
608 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
609 hdmi->base + SUN4I_HDMI_CEC);
610#endif
9c568101
MR		 611
612 drm_connector_helper_add(&hdmi->connector,
613 &sun4i_hdmi_connector_helper_funcs);
614 ret = drm_connector_init(drm, &hdmi->connector,
615 &sun4i_hdmi_connector_funcs,
616 DRM_MODE_CONNECTOR_HDMIA);
617 if (ret) {
618 dev_err(dev,
619 "Couldn't initialise the HDMI connector\n");
620 goto err_cleanup_connector;
621 }
622
623 /* There is no HPD interrupt, so we need to poll the controller */
624 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
625 DRM_CONNECTOR_POLL_DISCONNECT;
626
998140d2
HV		 627 ret = cec_register_adapter(hdmi->cec_adap, dev);
628 if (ret < 0)
629 goto err_cleanup_connector;
cde4c44d 630 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
9c568101
MR		 631
632 return 0;
633
634err_cleanup_connector:
998140d2 635 cec_delete_adapter(hdmi->cec_adap);
9c568101 636 drm_encoder_cleanup(&hdmi->encoder);
f0a3dd33
JL		 637err_del_i2c_adapter:
638 i2c_del_adapter(hdmi->i2c);
544c5048
CYT		 639err_disable_mod_clk:
640 clk_disable_unprepare(hdmi->mod_clk);
641err_disable_bus_clk:
642 clk_disable_unprepare(hdmi->bus_clk);
939d749a
CYT		 643err_assert_reset:
644 reset_control_assert(hdmi->reset);
9c568101
MR		 645 return ret;
646}
647
648static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
649 void *data)
650{
651 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
652
998140d2 653 cec_unregister_adapter(hdmi->cec_adap);
9c568101
MR		 654 drm_connector_cleanup(&hdmi->connector);
655 drm_encoder_cleanup(&hdmi->encoder);
f0a3dd33 656 i2c_del_adapter(hdmi->i2c);
544c5048
CYT		 657 clk_disable_unprepare(hdmi->mod_clk);
658 clk_disable_unprepare(hdmi->bus_clk);
9c568101
MR		 659}
660
661static const struct component_ops sun4i_hdmi_ops = {
662 .bind = sun4i_hdmi_bind,
663 .unbind = sun4i_hdmi_unbind,
664};
665
666static int sun4i_hdmi_probe(struct platform_device *pdev)
667{
668 return component_add(&pdev->dev, &sun4i_hdmi_ops);
669}
670
671static int sun4i_hdmi_remove(struct platform_device *pdev)
672{
673 component_del(&pdev->dev, &sun4i_hdmi_ops);
674
675 return 0;
676}
677
678static const struct of_device_id sun4i_hdmi_of_table[] = {
7ea4291f 679 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, },
939d749a 680 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
da184dee 681 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
9c568101
MR		 682 { }
683};
684MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
685
686static struct platform_driver sun4i_hdmi_driver = {
687 .probe = sun4i_hdmi_probe,
688 .remove = sun4i_hdmi_remove,
689 .driver = {
690 .name = "sun4i-hdmi",
691 .of_match_table = sun4i_hdmi_of_table,
692 },
693};
694module_platform_driver(sun4i_hdmi_driver);
695
696MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
697MODULE_DESCRIPTION("Allwinner A10 HDMI Driver");
698MODULE_LICENSE("GPL");
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