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Merge remote-tracking branches 'asoc/topic/tas6424', 'asoc/topic/tfa9879', 'asoc...
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / sun4i / sun4i_hdmi_enc.c
CommitLineData
9c568101
MR		 1/*
2 * Copyright (C) 2016 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 */
11
12#include <drm/drmP.h>
13#include <drm/drm_atomic_helper.h>
14#include <drm/drm_crtc_helper.h>
15#include <drm/drm_edid.h>
16#include <drm/drm_encoder.h>
17#include <drm/drm_of.h>
18#include <drm/drm_panel.h>
19
20#include <linux/clk.h>
21#include <linux/component.h>
22#include <linux/iopoll.h>
939d749a 23#include <linux/of_device.h>
9c568101
MR		 24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
4b1c924b 26#include <linux/regmap.h>
939d749a 27#include <linux/reset.h>
9c568101
MR		 28
29#include "sun4i_backend.h"
30#include "sun4i_crtc.h"
31#include "sun4i_drv.h"
32#include "sun4i_hdmi.h"
9c568101 33
9c568101
MR		 34static inline struct sun4i_hdmi *
35drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
36{
37 return container_of(encoder, struct sun4i_hdmi,
38 encoder);
39}
40
41static inline struct sun4i_hdmi *
42drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
43{
44 return container_of(connector, struct sun4i_hdmi,
45 connector);
46}
47
48static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
49 struct drm_display_mode *mode)
50{
51 struct hdmi_avi_infoframe frame;
52 u8 buffer[17];
53 int i, ret;
54
0c1f528c 55 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
9c568101
MR		 56 if (ret < 0) {
57 DRM_ERROR("Failed to get infoframes from mode\n");
58 return ret;
59 }
60
61 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
62 if (ret < 0) {
63 DRM_ERROR("Failed to pack infoframes\n");
64 return ret;
65 }
66
67 for (i = 0; i < sizeof(buffer); i++)
68 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
69
70 return 0;
71}
72
73static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
74 struct drm_crtc_state *crtc_state,
75 struct drm_connector_state *conn_state)
76{
77 struct drm_display_mode *mode = &crtc_state->mode;
78
79 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
80 return -EINVAL;
81
82 return 0;
83}
84
85static void sun4i_hdmi_disable(struct drm_encoder *encoder)
86{
87 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
9c568101
MR		 88 u32 val;
89
90 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
91
92 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
93 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
94 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
9c568101
MR		 95}
96
97static void sun4i_hdmi_enable(struct drm_encoder *encoder)
98{
99 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
100 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
9c568101
MR		 101 u32 val = 0;
102
103 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
104
9c568101
MR		 105 sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
106 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
107 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
108 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
109
110 val = SUN4I_HDMI_VID_CTRL_ENABLE;
111 if (hdmi->hdmi_monitor)
112 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
113
114 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
115}
116
117static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
118 struct drm_display_mode *mode,
119 struct drm_display_mode *adjusted_mode)
120{
121 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
9c568101
MR		 122 unsigned int x, y;
123 u32 val;
124
9c568101
MR		 125 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
126 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
127
128 /* Set input sync enable */
129 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
130 hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
131
bfddd146
CYT		 132 /*
133 * Setup output pad (?) controls
134 *
135 * This is done here instead of at probe/bind time because
136 * the controller seems to toggle some of the bits on its own.
137 *
138 * We can't just initialize the register there, we need to
139 * protect the clock bits that have already been read out and
140 * cached by the clock framework.
141 */
142 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
143 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
144 val |= hdmi->variant->pad_ctrl1_init_val;
145 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
146 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
147
9c568101
MR		 148 /* Setup timing registers */
149 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
150 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
151 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
152
153 x = mode->htotal - mode->hsync_start;
154 y = mode->vtotal - mode->vsync_start;
155 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
156 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
157
158 x = mode->hsync_start - mode->hdisplay;
159 y = mode->vsync_start - mode->vdisplay;
160 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
161 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
162
163 x = mode->hsync_end - mode->hsync_start;
164 y = mode->vsync_end - mode->vsync_start;
165 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
166 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
167
168 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK;
169 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
170 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC;
171
172 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
173 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
174
175 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
176}
177
2c08cd7c
MR		 178static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder,
179 const struct drm_display_mode *mode)
180{
181 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
182 unsigned long rate = mode->clock * 1000;
183 unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */
184 long rounded_rate;
185
186 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */
187 if (rate > 165000000)
188 return MODE_CLOCK_HIGH;
189 rounded_rate = clk_round_rate(hdmi->tmds_clk, rate);
190 if (rounded_rate > 0 &&
191 max_t(unsigned long, rounded_rate, rate) -
192 min_t(unsigned long, rounded_rate, rate) < diff)
193 return MODE_OK;
194 return MODE_NOCLOCK;
195}
196
9c568101
MR		 197static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
198 .atomic_check = sun4i_hdmi_atomic_check,
199 .disable = sun4i_hdmi_disable,
200 .enable = sun4i_hdmi_enable,
201 .mode_set = sun4i_hdmi_mode_set,
2c08cd7c 202 .mode_valid = sun4i_hdmi_mode_valid,
9c568101
MR		 203};
204
205static const struct drm_encoder_funcs sun4i_hdmi_funcs = {
206 .destroy = drm_encoder_cleanup,
207};
208
9c568101
MR		 209static int sun4i_hdmi_get_modes(struct drm_connector *connector)
210{
211 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
9c568101
MR		 212 struct edid *edid;
213 int ret;
214
f0a3dd33 215 edid = drm_get_edid(connector, hdmi->i2c);
9c568101
MR		 216 if (!edid)
217 return 0;
218
219 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
220 DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
221 hdmi->hdmi_monitor ? "an HDMI" : "a DVI");
222
223 drm_mode_connector_update_edid_property(connector, edid);
998140d2 224 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
9c568101
MR		 225 ret = drm_add_edid_modes(connector, edid);
226 kfree(edid);
227
9c568101
MR		 228 return ret;
229}
230
231static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
232 .get_modes = sun4i_hdmi_get_modes,
233};
234
235static enum drm_connector_status
236sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
237{
238 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
239 unsigned long reg;
240
241 if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg,
242 reg & SUN4I_HDMI_HPD_HIGH,
998140d2
HV		 243 0, 500000)) {
244 cec_phys_addr_invalidate(hdmi->cec_adap);
9c568101 245 return connector_status_disconnected;
998140d2 246 }
9c568101
MR		 247
248 return connector_status_connected;
249}
250
251static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
9c568101
MR		 252 .detect = sun4i_hdmi_connector_detect,
253 .fill_modes = drm_helper_probe_single_connector_modes,
254 .destroy = drm_connector_cleanup,
255 .reset = drm_atomic_helper_connector_reset,
256 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
257 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
258};
259
998140d2
HV		 260#ifdef CONFIG_DRM_SUN4I_HDMI_CEC
261static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
262{
263 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
264
265 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
266}
267
268static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
269{
270 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
271
272 /* Start driving the CEC pin low */
273 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
274}
275
276static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
277{
278 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
279
280 /*
281 * Stop driving the CEC pin, the pull up will take over
282 * unless another CEC device is driving the pin low.
283 */
284 writel(0, hdmi->base + SUN4I_HDMI_CEC);
285}
286
287static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
288 .read = sun4i_hdmi_cec_pin_read,
289 .low = sun4i_hdmi_cec_pin_low,
290 .high = sun4i_hdmi_cec_pin_high,
291};
292#endif
293
939d749a
CYT		 294#define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0))
295#define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0))
296
7ea4291f
CYT		 297/* Only difference from sun5i is AMP is 4 instead of 6 */
298static const struct sun4i_hdmi_variant sun4i_variant = {
299 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
300 SUN4I_HDMI_PAD_CTRL0_CKEN |
301 SUN4I_HDMI_PAD_CTRL0_PWENG |
302 SUN4I_HDMI_PAD_CTRL0_PWEND |
303 SUN4I_HDMI_PAD_CTRL0_PWENC |
304 SUN4I_HDMI_PAD_CTRL0_LDODEN |
305 SUN4I_HDMI_PAD_CTRL0_LDOCEN |
306 SUN4I_HDMI_PAD_CTRL0_BIASEN,
307 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) |
308 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
309 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
310 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
311 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
312 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
313 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
314 SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
315 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
316 SUN4I_HDMI_PLL_CTRL_CS(7) |
317 SUN4I_HDMI_PLL_CTRL_CP_S(15) |
318 SUN4I_HDMI_PLL_CTRL_S(7) |
319 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
320 SUN4I_HDMI_PLL_CTRL_SDIV2 |
321 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
322 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
323 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
324 SUN4I_HDMI_PLL_CTRL_BWS |
325 SUN4I_HDMI_PLL_CTRL_PLL_EN,
326
327 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
328 .ddc_clk_pre_divider = 2,
329 .ddc_clk_m_offset = 1,
330
331 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
332 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
333 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
334 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
335 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
336 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
337 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
338 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
339 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
340 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
341 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
342 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
343 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
344
345 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG,
346 .ddc_fifo_has_dir = true,
347};
348
939d749a
CYT		 349static const struct sun4i_hdmi_variant sun5i_variant = {
350 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
351 SUN4I_HDMI_PAD_CTRL0_CKEN |
352 SUN4I_HDMI_PAD_CTRL0_PWENG |
353 SUN4I_HDMI_PAD_CTRL0_PWEND |
354 SUN4I_HDMI_PAD_CTRL0_PWENC |
355 SUN4I_HDMI_PAD_CTRL0_LDODEN |
356 SUN4I_HDMI_PAD_CTRL0_LDOCEN |
357 SUN4I_HDMI_PAD_CTRL0_BIASEN,
358 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
359 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
360 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
361 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
362 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
363 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
364 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
365 SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
366 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
367 SUN4I_HDMI_PLL_CTRL_CS(7) |
368 SUN4I_HDMI_PLL_CTRL_CP_S(15) |
369 SUN4I_HDMI_PLL_CTRL_S(7) |
370 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
371 SUN4I_HDMI_PLL_CTRL_SDIV2 |
372 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
373 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
374 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
375 SUN4I_HDMI_PLL_CTRL_BWS |
376 SUN4I_HDMI_PLL_CTRL_PLL_EN,
377
378 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
379 .ddc_clk_pre_divider = 2,
380 .ddc_clk_m_offset = 1,
381
382 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
383 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
384 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
385 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
386 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
387 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
388 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
389 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
390 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
391 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
392 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
393 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
394 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
395
396 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG,
397 .ddc_fifo_has_dir = true,
398};
399
da184dee
CYT		 400static const struct sun4i_hdmi_variant sun6i_variant = {
401 .has_ddc_parent_clk = true,
402 .has_reset_control = true,
403 .pad_ctrl0_init_val = 0xff |
404 SUN4I_HDMI_PAD_CTRL0_TXEN |
405 SUN4I_HDMI_PAD_CTRL0_CKEN |
406 SUN4I_HDMI_PAD_CTRL0_PWENG |
407 SUN4I_HDMI_PAD_CTRL0_PWEND |
408 SUN4I_HDMI_PAD_CTRL0_PWENC |
409 SUN4I_HDMI_PAD_CTRL0_LDODEN |
410 SUN4I_HDMI_PAD_CTRL0_LDOCEN,
411 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
412 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) |
413 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
414 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
415 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
416 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
417 SUN4I_HDMI_PAD_CTRL1_PWSDT |
418 SUN4I_HDMI_PAD_CTRL1_PWSCK |
419 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
420 SUN4I_HDMI_PAD_CTRL1_AMP_OPT |
421 SUN4I_HDMI_PAD_CTRL1_UNKNOWN,
422 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
423 SUN4I_HDMI_PLL_CTRL_CS(3) |
424 SUN4I_HDMI_PLL_CTRL_CP_S(10) |
425 SUN4I_HDMI_PLL_CTRL_S(4) |
426 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
427 SUN4I_HDMI_PLL_CTRL_SDIV2 |
428 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
429 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
430 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
431 SUN4I_HDMI_PLL_CTRL_PLL_EN,
432
433 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6),
434 .ddc_clk_pre_divider = 1,
435 .ddc_clk_m_offset = 2,
436
437 .tmds_clk_div_offset = 1,
438
439 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0),
440 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27),
441 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31),
442 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31),
443 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7),
444 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8),
445 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18),
446 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
447 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
448 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25),
449 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2),
450 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6),
451 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4),
452
453 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG,
454 .ddc_fifo_thres_incl = true,
455};
456
4b1c924b
CYT		 457static const struct regmap_config sun4i_hdmi_regmap_config = {
458 .reg_bits = 32,
459 .val_bits = 32,
460 .reg_stride = 4,
461 .max_register = 0x580,
462};
463
9c568101
MR		 464static int sun4i_hdmi_bind(struct device *dev, struct device *master,
465 void *data)
466{
467 struct platform_device *pdev = to_platform_device(dev);
468 struct drm_device *drm = data;
469 struct sun4i_drv *drv = drm->dev_private;
470 struct sun4i_hdmi *hdmi;
471 struct resource *res;
472 u32 reg;
473 int ret;
474
475 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
476 if (!hdmi)
477 return -ENOMEM;
478 dev_set_drvdata(dev, hdmi);
479 hdmi->dev = dev;
480 hdmi->drv = drv;
481
939d749a
CYT		 482 hdmi->variant = of_device_get_match_data(dev);
483 if (!hdmi->variant)
484 return -EINVAL;
485
9c568101
MR		 486 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
487 hdmi->base = devm_ioremap_resource(dev, res);
488 if (IS_ERR(hdmi->base)) {
489 dev_err(dev, "Couldn't map the HDMI encoder registers\n");
490 return PTR_ERR(hdmi->base);
491 }
492
939d749a
CYT		 493 if (hdmi->variant->has_reset_control) {
494 hdmi->reset = devm_reset_control_get(dev, NULL);
495 if (IS_ERR(hdmi->reset)) {
496 dev_err(dev, "Couldn't get the HDMI reset control\n");
497 return PTR_ERR(hdmi->reset);
498 }
499
500 ret = reset_control_deassert(hdmi->reset);
501 if (ret) {
502 dev_err(dev, "Couldn't deassert HDMI reset\n");
503 return ret;
504 }
505 }
506
9c568101
MR		 507 hdmi->bus_clk = devm_clk_get(dev, "ahb");
508 if (IS_ERR(hdmi->bus_clk)) {
509 dev_err(dev, "Couldn't get the HDMI bus clock\n");
939d749a
CYT		 510 ret = PTR_ERR(hdmi->bus_clk);
511 goto err_assert_reset;
9c568101
MR		 512 }
513 clk_prepare_enable(hdmi->bus_clk);
514
515 hdmi->mod_clk = devm_clk_get(dev, "mod");
516 if (IS_ERR(hdmi->mod_clk)) {
517 dev_err(dev, "Couldn't get the HDMI mod clock\n");
544c5048
CYT		 518 ret = PTR_ERR(hdmi->mod_clk);
519 goto err_disable_bus_clk;
9c568101
MR		 520 }
521 clk_prepare_enable(hdmi->mod_clk);
522
523 hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
524 if (IS_ERR(hdmi->pll0_clk)) {
525 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
544c5048
CYT		 526 ret = PTR_ERR(hdmi->pll0_clk);
527 goto err_disable_mod_clk;
9c568101
MR		 528 }
529
530 hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
531 if (IS_ERR(hdmi->pll1_clk)) {
532 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
544c5048
CYT		 533 ret = PTR_ERR(hdmi->pll1_clk);
534 goto err_disable_mod_clk;
9c568101
MR		 535 }
536
4b1c924b
CYT		 537 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
538 &sun4i_hdmi_regmap_config);
539 if (IS_ERR(hdmi->regmap)) {
540 dev_err(dev, "Couldn't create HDMI encoder regmap\n");
541 return PTR_ERR(hdmi->regmap);
542 }
543
9c568101
MR		 544 ret = sun4i_tmds_create(hdmi);
545 if (ret) {
546 dev_err(dev, "Couldn't create the TMDS clock\n");
544c5048 547 goto err_disable_mod_clk;
9c568101
MR		 548 }
549
939d749a
CYT		 550 if (hdmi->variant->has_ddc_parent_clk) {
551 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
552 if (IS_ERR(hdmi->ddc_parent_clk)) {
553 dev_err(dev, "Couldn't get the HDMI DDC clock\n");
554 return PTR_ERR(hdmi->ddc_parent_clk);
555 }
556 } else {
557 hdmi->ddc_parent_clk = hdmi->tmds_clk;
558 }
559
9c568101
MR		 560 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
561
939d749a 562 writel(hdmi->variant->pad_ctrl0_init_val,
9c568101
MR		 563 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
564
9c568101
MR		 565 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
566 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
939d749a 567 reg |= hdmi->variant->pll_ctrl_init_val;
9c568101
MR		 568 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
569
f0a3dd33 570 ret = sun4i_hdmi_i2c_create(dev, hdmi);
9c568101 571 if (ret) {
f0a3dd33 572 dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
544c5048 573 goto err_disable_mod_clk;
9c568101
MR		 574 }
575
576 drm_encoder_helper_add(&hdmi->encoder,
577 &sun4i_hdmi_helper_funcs);
578 ret = drm_encoder_init(drm,
579 &hdmi->encoder,
580 &sun4i_hdmi_funcs,
581 DRM_MODE_ENCODER_TMDS,
582 NULL);
583 if (ret) {
584 dev_err(dev, "Couldn't initialise the HDMI encoder\n");
f0a3dd33 585 goto err_del_i2c_adapter;
9c568101
MR		 586 }
587
588 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
589 dev->of_node);
f0a3dd33
JL		 590 if (!hdmi->encoder.possible_crtcs) {
591 ret = -EPROBE_DEFER;
592 goto err_del_i2c_adapter;
593 }
9c568101 594
998140d2
HV		 595#ifdef CONFIG_DRM_SUN4I_HDMI_CEC
596 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
597 hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
598 CEC_CAP_PASSTHROUGH | CEC_CAP_RC);
599 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
600 if (ret < 0)
601 goto err_cleanup_connector;
602 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
603 hdmi->base + SUN4I_HDMI_CEC);
604#endif
9c568101
MR		 605
606 drm_connector_helper_add(&hdmi->connector,
607 &sun4i_hdmi_connector_helper_funcs);
608 ret = drm_connector_init(drm, &hdmi->connector,
609 &sun4i_hdmi_connector_funcs,
610 DRM_MODE_CONNECTOR_HDMIA);
611 if (ret) {
612 dev_err(dev,
613 "Couldn't initialise the HDMI connector\n");
614 goto err_cleanup_connector;
615 }
616
617 /* There is no HPD interrupt, so we need to poll the controller */
618 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
619 DRM_CONNECTOR_POLL_DISCONNECT;
620
998140d2
HV		 621 ret = cec_register_adapter(hdmi->cec_adap, dev);
622 if (ret < 0)
623 goto err_cleanup_connector;
9c568101
MR		 624 drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
625
626 return 0;
627
628err_cleanup_connector:
998140d2 629 cec_delete_adapter(hdmi->cec_adap);
9c568101 630 drm_encoder_cleanup(&hdmi->encoder);
f0a3dd33
JL		 631err_del_i2c_adapter:
632 i2c_del_adapter(hdmi->i2c);
544c5048
CYT		 633err_disable_mod_clk:
634 clk_disable_unprepare(hdmi->mod_clk);
635err_disable_bus_clk:
636 clk_disable_unprepare(hdmi->bus_clk);
939d749a
CYT		 637err_assert_reset:
638 reset_control_assert(hdmi->reset);
9c568101
MR		 639 return ret;
640}
641
642static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
643 void *data)
644{
645 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
646
998140d2 647 cec_unregister_adapter(hdmi->cec_adap);
9c568101
MR		 648 drm_connector_cleanup(&hdmi->connector);
649 drm_encoder_cleanup(&hdmi->encoder);
f0a3dd33 650 i2c_del_adapter(hdmi->i2c);
544c5048
CYT		 651 clk_disable_unprepare(hdmi->mod_clk);
652 clk_disable_unprepare(hdmi->bus_clk);
9c568101
MR		 653}
654
655static const struct component_ops sun4i_hdmi_ops = {
656 .bind = sun4i_hdmi_bind,
657 .unbind = sun4i_hdmi_unbind,
658};
659
660static int sun4i_hdmi_probe(struct platform_device *pdev)
661{
662 return component_add(&pdev->dev, &sun4i_hdmi_ops);
663}
664
665static int sun4i_hdmi_remove(struct platform_device *pdev)
666{
667 component_del(&pdev->dev, &sun4i_hdmi_ops);
668
669 return 0;
670}
671
672static const struct of_device_id sun4i_hdmi_of_table[] = {
7ea4291f 673 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, },
939d749a 674 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
da184dee 675 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
9c568101
MR		 676 { }
677};
678MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
679
680static struct platform_driver sun4i_hdmi_driver = {
681 .probe = sun4i_hdmi_probe,
682 .remove = sun4i_hdmi_remove,
683 .driver = {
684 .name = "sun4i-hdmi",
685 .of_match_table = sun4i_hdmi_of_table,
686 },
687};
688module_platform_driver(sun4i_hdmi_driver);
689
690MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
691MODULE_DESCRIPTION("Allwinner A10 HDMI Driver");
692MODULE_LICENSE("GPL");
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