]>
Commit | Line | Data |
---|---|---|
9026e0d1 MR |
1 | /* |
2 | * Copyright (C) 2015 Free Electrons | |
3 | * Copyright (C) 2015 NextThing Co | |
4 | * | |
5 | * Boris Brezillon <boris.brezillon@free-electrons.com> | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #ifndef __SUN4I_TCON_H__ | |
15 | #define __SUN4I_TCON_H__ | |
16 | ||
17 | #include <drm/drm_crtc.h> | |
18 | ||
19 | #include <linux/kernel.h> | |
80a58240 | 20 | #include <linux/list.h> |
9026e0d1 MR |
21 | #include <linux/reset.h> |
22 | ||
23 | #define SUN4I_TCON_GCTL_REG 0x0 | |
24 | #define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31) | |
25 | #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0) | |
26 | #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0) | |
27 | #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0) | |
28 | ||
29 | #define SUN4I_TCON_GINT0_REG 0x4 | |
30 | #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe)) | |
31 | #define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe)) | |
32 | ||
33 | #define SUN4I_TCON_GINT1_REG 0x8 | |
34 | #define SUN4I_TCON_FRM_CTL_REG 0x10 | |
35 | ||
36 | #define SUN4I_TCON0_CTL_REG 0x40 | |
37 | #define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31) | |
38 | #define SUN4I_TCON0_CTL_CLK_DELAY_MASK GENMASK(8, 4) | |
39 | #define SUN4I_TCON0_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK) | |
27e18de7 | 40 | #define SUN4I_TCON0_CTL_SRC_SEL_MASK GENMASK(2, 0) |
9026e0d1 MR |
41 | |
42 | #define SUN4I_TCON0_DCLK_REG 0x44 | |
43 | #define SUN4I_TCON0_DCLK_GATE_BIT (31) | |
44 | #define SUN4I_TCON0_DCLK_DIV_SHIFT (0) | |
45 | #define SUN4I_TCON0_DCLK_DIV_WIDTH (7) | |
46 | ||
47 | #define SUN4I_TCON0_BASIC0_REG 0x48 | |
48 | #define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16) | |
49 | #define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff) | |
50 | ||
51 | #define SUN4I_TCON0_BASIC1_REG 0x4c | |
52 | #define SUN4I_TCON0_BASIC1_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16) | |
53 | #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff) | |
54 | ||
55 | #define SUN4I_TCON0_BASIC2_REG 0x50 | |
a88cbbd4 | 56 | #define SUN4I_TCON0_BASIC2_V_TOTAL(total) (((total) & 0x1fff) << 16) |
9026e0d1 MR |
57 | #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff) |
58 | ||
59 | #define SUN4I_TCON0_BASIC3_REG 0x54 | |
60 | #define SUN4I_TCON0_BASIC3_H_SYNC(width) ((((width) - 1) & 0x7ff) << 16) | |
61 | #define SUN4I_TCON0_BASIC3_V_SYNC(height) (((height) - 1) & 0x7ff) | |
62 | ||
63 | #define SUN4I_TCON0_HV_IF_REG 0x58 | |
64 | #define SUN4I_TCON0_CPU_IF_REG 0x60 | |
65 | #define SUN4I_TCON0_CPU_WR_REG 0x64 | |
66 | #define SUN4I_TCON0_CPU_RD0_REG 0x68 | |
67 | #define SUN4I_TCON0_CPU_RDA_REG 0x6c | |
68 | #define SUN4I_TCON0_TTL0_REG 0x70 | |
69 | #define SUN4I_TCON0_TTL1_REG 0x74 | |
70 | #define SUN4I_TCON0_TTL2_REG 0x78 | |
71 | #define SUN4I_TCON0_TTL3_REG 0x7c | |
72 | #define SUN4I_TCON0_TTL4_REG 0x80 | |
a0c1214e | 73 | |
9026e0d1 | 74 | #define SUN4I_TCON0_LVDS_IF_REG 0x84 |
a0c1214e MR |
75 | #define SUN4I_TCON0_LVDS_IF_EN BIT(31) |
76 | #define SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK BIT(26) | |
77 | #define SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS (1 << 26) | |
78 | #define SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS (0 << 26) | |
79 | #define SUN4I_TCON0_LVDS_IF_CLK_SEL_MASK BIT(20) | |
80 | #define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 (1 << 20) | |
81 | #define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK BIT(4) | |
82 | #define SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL (1 << 4) | |
83 | #define SUN4I_TCON0_LVDS_IF_CLK_POL_INV (0 << 4) | |
84 | #define SUN4I_TCON0_LVDS_IF_DATA_POL_MASK GENMASK(3, 0) | |
85 | #define SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL (0xf) | |
86 | #define SUN4I_TCON0_LVDS_IF_DATA_POL_INV (0) | |
87 | ||
9026e0d1 MR |
88 | #define SUN4I_TCON0_IO_POL_REG 0x88 |
89 | #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28) | |
90 | #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25) | |
91 | #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24) | |
92 | ||
93 | #define SUN4I_TCON0_IO_TRI_REG 0x8c | |
94 | #define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE BIT(25) | |
95 | #define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE BIT(24) | |
96 | #define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins) GENMASK(pins, 0) | |
97 | ||
98 | #define SUN4I_TCON1_CTL_REG 0x90 | |
99 | #define SUN4I_TCON1_CTL_TCON_ENABLE BIT(31) | |
100 | #define SUN4I_TCON1_CTL_INTERLACE_ENABLE BIT(20) | |
101 | #define SUN4I_TCON1_CTL_CLK_DELAY_MASK GENMASK(8, 4) | |
102 | #define SUN4I_TCON1_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK) | |
27e18de7 | 103 | #define SUN4I_TCON1_CTL_SRC_SEL_MASK GENMASK(1, 0) |
9026e0d1 MR |
104 | |
105 | #define SUN4I_TCON1_BASIC0_REG 0x94 | |
106 | #define SUN4I_TCON1_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16) | |
107 | #define SUN4I_TCON1_BASIC0_Y(height) (((height) - 1) & 0xfff) | |
108 | ||
109 | #define SUN4I_TCON1_BASIC1_REG 0x98 | |
110 | #define SUN4I_TCON1_BASIC1_X(width) ((((width) - 1) & 0xfff) << 16) | |
111 | #define SUN4I_TCON1_BASIC1_Y(height) (((height) - 1) & 0xfff) | |
112 | ||
113 | #define SUN4I_TCON1_BASIC2_REG 0x9c | |
114 | #define SUN4I_TCON1_BASIC2_X(width) ((((width) - 1) & 0xfff) << 16) | |
115 | #define SUN4I_TCON1_BASIC2_Y(height) (((height) - 1) & 0xfff) | |
116 | ||
117 | #define SUN4I_TCON1_BASIC3_REG 0xa0 | |
118 | #define SUN4I_TCON1_BASIC3_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16) | |
119 | #define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp) (((bp) - 1) & 0xfff) | |
120 | ||
121 | #define SUN4I_TCON1_BASIC4_REG 0xa4 | |
122 | #define SUN4I_TCON1_BASIC4_V_TOTAL(total) (((total) & 0x1fff) << 16) | |
123 | #define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp) (((bp) - 1) & 0xfff) | |
124 | ||
125 | #define SUN4I_TCON1_BASIC5_REG 0xa8 | |
126 | #define SUN4I_TCON1_BASIC5_H_SYNC(width) ((((width) - 1) & 0x3ff) << 16) | |
127 | #define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff) | |
128 | ||
129 | #define SUN4I_TCON1_IO_POL_REG 0xf0 | |
130 | #define SUN4I_TCON1_IO_TRI_REG 0xf4 | |
131 | #define SUN4I_TCON_CEU_CTL_REG 0x100 | |
132 | #define SUN4I_TCON_CEU_MUL_RR_REG 0x110 | |
133 | #define SUN4I_TCON_CEU_MUL_RG_REG 0x114 | |
134 | #define SUN4I_TCON_CEU_MUL_RB_REG 0x118 | |
135 | #define SUN4I_TCON_CEU_ADD_RC_REG 0x11c | |
136 | #define SUN4I_TCON_CEU_MUL_GR_REG 0x120 | |
137 | #define SUN4I_TCON_CEU_MUL_GG_REG 0x124 | |
138 | #define SUN4I_TCON_CEU_MUL_GB_REG 0x128 | |
139 | #define SUN4I_TCON_CEU_ADD_GC_REG 0x12c | |
140 | #define SUN4I_TCON_CEU_MUL_BR_REG 0x130 | |
141 | #define SUN4I_TCON_CEU_MUL_BG_REG 0x134 | |
142 | #define SUN4I_TCON_CEU_MUL_BB_REG 0x138 | |
143 | #define SUN4I_TCON_CEU_ADD_BC_REG 0x13c | |
144 | #define SUN4I_TCON_CEU_RANGE_R_REG 0x140 | |
145 | #define SUN4I_TCON_CEU_RANGE_G_REG 0x144 | |
146 | #define SUN4I_TCON_CEU_RANGE_B_REG 0x148 | |
147 | #define SUN4I_TCON_MUX_CTRL_REG 0x200 | |
a0c1214e MR |
148 | |
149 | #define SUN4I_TCON0_LVDS_ANA0_REG 0x220 | |
150 | #define SUN6I_TCON0_LVDS_ANA0_EN_MB BIT(31) | |
151 | #define SUN6I_TCON0_LVDS_ANA0_EN_LDO BIT(30) | |
152 | #define SUN6I_TCON0_LVDS_ANA0_EN_DRVC BIT(24) | |
153 | #define SUN6I_TCON0_LVDS_ANA0_EN_DRVD(x) (((x) & 0xf) << 20) | |
154 | #define SUN6I_TCON0_LVDS_ANA0_C(x) (((x) & 3) << 17) | |
155 | #define SUN6I_TCON0_LVDS_ANA0_V(x) (((x) & 3) << 8) | |
156 | #define SUN6I_TCON0_LVDS_ANA0_PD(x) (((x) & 3) << 4) | |
157 | ||
9026e0d1 MR |
158 | #define SUN4I_TCON1_FILL_CTL_REG 0x300 |
159 | #define SUN4I_TCON1_FILL_BEG0_REG 0x304 | |
160 | #define SUN4I_TCON1_FILL_END0_REG 0x308 | |
161 | #define SUN4I_TCON1_FILL_DATA0_REG 0x30c | |
162 | #define SUN4I_TCON1_FILL_BEG1_REG 0x310 | |
163 | #define SUN4I_TCON1_FILL_END1_REG 0x314 | |
164 | #define SUN4I_TCON1_FILL_DATA1_REG 0x318 | |
165 | #define SUN4I_TCON1_FILL_BEG2_REG 0x31c | |
166 | #define SUN4I_TCON1_FILL_END2_REG 0x320 | |
167 | #define SUN4I_TCON1_FILL_DATA2_REG 0x324 | |
168 | #define SUN4I_TCON1_GAMMA_TABLE_REG 0x400 | |
169 | ||
170 | #define SUN4I_TCON_MAX_CHANNELS 2 | |
171 | ||
ad537fb2 CYT |
172 | struct sun4i_tcon; |
173 | ||
91ea2f29 | 174 | struct sun4i_tcon_quirks { |
91ea2f29 | 175 | bool has_channel_1; /* a33 does not have channel 1 */ |
a0c1214e | 176 | bool has_lvds_alt; /* Does the LVDS clock have a parent other than the TCON clock? */ |
27e18de7 | 177 | bool needs_de_be_mux; /* sun6i needs mux to select backend */ |
e742a17c | 178 | bool supports_lvds; /* Does the TCON support an LVDS output? */ |
ad537fb2 CYT |
179 | |
180 | /* callback to handle tcon muxing options */ | |
abcb8766 | 181 | int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *); |
91ea2f29 CYT |
182 | }; |
183 | ||
9026e0d1 | 184 | struct sun4i_tcon { |
ae558110 | 185 | struct device *dev; |
9026e0d1 MR |
186 | struct drm_device *drm; |
187 | struct regmap *regs; | |
188 | ||
189 | /* Main bus clock */ | |
190 | struct clk *clk; | |
191 | ||
192 | /* Clocks for the TCON channels */ | |
193 | struct clk *sclk0; | |
194 | struct clk *sclk1; | |
195 | ||
a0c1214e MR |
196 | /* Possible mux for the LVDS clock */ |
197 | struct clk *lvds_pll; | |
198 | ||
9026e0d1 MR |
199 | /* Pixel clock */ |
200 | struct clk *dclk; | |
ec08d596 MR |
201 | u8 dclk_max_div; |
202 | u8 dclk_min_div; | |
9026e0d1 MR |
203 | |
204 | /* Reset control */ | |
205 | struct reset_control *lcd_rst; | |
a0c1214e | 206 | struct reset_control *lvds_rst; |
9026e0d1 | 207 | |
29e57fab | 208 | struct drm_panel *panel; |
8e924047 | 209 | |
91ea2f29 CYT |
210 | /* Platform adjustments */ |
211 | const struct sun4i_tcon_quirks *quirks; | |
46cce6da CYT |
212 | |
213 | /* Associated crtc */ | |
214 | struct sun4i_crtc *crtc; | |
80a58240 | 215 | |
d281c862 CYT |
216 | int id; |
217 | ||
80a58240 CYT |
218 | /* TCON list management */ |
219 | struct list_head list; | |
9026e0d1 MR |
220 | }; |
221 | ||
894f5a9f | 222 | struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node); |
a8444c7e MR |
223 | struct drm_panel *sun4i_tcon_find_panel(struct device_node *node); |
224 | ||
9026e0d1 | 225 | void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable); |
5b8f0910 MR |
226 | void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, |
227 | const struct drm_encoder *encoder, | |
228 | const struct drm_display_mode *mode); | |
45e88f99 MR |
229 | void sun4i_tcon_set_status(struct sun4i_tcon *crtc, |
230 | const struct drm_encoder *encoder, bool enable); | |
9026e0d1 | 231 | |
ff71c2cf CYT |
232 | extern const struct of_device_id sun4i_tcon_of_table[]; |
233 | ||
9026e0d1 | 234 | #endif /* __SUN4I_TCON_H__ */ |