]>
Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
9eb9b220 | 11 | #include <linux/debugfs.h> |
df06b759 | 12 | #include <linux/iommu.h> |
33a8eb8d | 13 | #include <linux/pm_runtime.h> |
ca48080a | 14 | #include <linux/reset.h> |
d8f4a9ed | 15 | |
9c012700 TR |
16 | #include <soc/tegra/pmc.h> |
17 | ||
de2ba664 AM |
18 | #include "dc.h" |
19 | #include "drm.h" | |
20 | #include "gem.h" | |
d8f4a9ed | 21 | |
9d44189f | 22 | #include <drm/drm_atomic.h> |
4aa3df71 | 23 | #include <drm/drm_atomic_helper.h> |
3cb9ae4f DV |
24 | #include <drm/drm_plane_helper.h> |
25 | ||
8620fc62 | 26 | struct tegra_dc_soc_info { |
42d0659b | 27 | bool supports_border_color; |
8620fc62 | 28 | bool supports_interlacing; |
e687651b | 29 | bool supports_cursor; |
c134f019 | 30 | bool supports_block_linear; |
d1f3e1e0 | 31 | unsigned int pitch_align; |
9c012700 | 32 | bool has_powergate; |
6ac1571b | 33 | bool broken_reset; |
8620fc62 TR |
34 | }; |
35 | ||
f34bc787 TR |
36 | struct tegra_plane { |
37 | struct drm_plane base; | |
38 | unsigned int index; | |
d8f4a9ed TR |
39 | }; |
40 | ||
f34bc787 TR |
41 | static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) |
42 | { | |
43 | return container_of(plane, struct tegra_plane, base); | |
44 | } | |
45 | ||
ca915b10 TR |
46 | struct tegra_dc_state { |
47 | struct drm_crtc_state base; | |
48 | ||
49 | struct clk *clk; | |
50 | unsigned long pclk; | |
51 | unsigned int div; | |
47802b09 TR |
52 | |
53 | u32 planes; | |
ca915b10 TR |
54 | }; |
55 | ||
56 | static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) | |
57 | { | |
58 | if (state) | |
59 | return container_of(state, struct tegra_dc_state, base); | |
60 | ||
61 | return NULL; | |
62 | } | |
63 | ||
8f604f8c TR |
64 | struct tegra_plane_state { |
65 | struct drm_plane_state base; | |
66 | ||
67 | struct tegra_bo_tiling tiling; | |
68 | u32 format; | |
69 | u32 swap; | |
70 | }; | |
71 | ||
72 | static inline struct tegra_plane_state * | |
73 | to_tegra_plane_state(struct drm_plane_state *state) | |
74 | { | |
75 | if (state) | |
76 | return container_of(state, struct tegra_plane_state, base); | |
77 | ||
78 | return NULL; | |
79 | } | |
80 | ||
791ddb1e TR |
81 | static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) |
82 | { | |
83 | stats->frames = 0; | |
84 | stats->vblank = 0; | |
85 | stats->underflow = 0; | |
86 | stats->overflow = 0; | |
87 | } | |
88 | ||
86df256f TR |
89 | /* |
90 | * Reads the active copy of a register. This takes the dc->lock spinlock to | |
91 | * prevent races with the VBLANK processing which also needs access to the | |
92 | * active copy of some registers. | |
93 | */ | |
94 | static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) | |
95 | { | |
96 | unsigned long flags; | |
97 | u32 value; | |
98 | ||
99 | spin_lock_irqsave(&dc->lock, flags); | |
100 | ||
101 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); | |
102 | value = tegra_dc_readl(dc, offset); | |
103 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
104 | ||
105 | spin_unlock_irqrestore(&dc->lock, flags); | |
106 | return value; | |
107 | } | |
108 | ||
d700ba7a TR |
109 | /* |
110 | * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the | |
111 | * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. | |
112 | * Latching happens mmediately if the display controller is in STOP mode or | |
113 | * on the next frame boundary otherwise. | |
114 | * | |
115 | * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The | |
116 | * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits | |
117 | * are written. When the *_ACT_REQ bits are written, the ARM copy is latched | |
118 | * into the ACTIVE copy, either immediately if the display controller is in | |
119 | * STOP mode, or at the next frame boundary otherwise. | |
120 | */ | |
62b9e063 | 121 | void tegra_dc_commit(struct tegra_dc *dc) |
205d48ed TR |
122 | { |
123 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
124 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); | |
125 | } | |
126 | ||
8f604f8c | 127 | static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap) |
10288eea TR |
128 | { |
129 | /* assume no swapping of fetched data */ | |
130 | if (swap) | |
131 | *swap = BYTE_SWAP_NOSWAP; | |
132 | ||
8f604f8c | 133 | switch (fourcc) { |
10288eea | 134 | case DRM_FORMAT_XBGR8888: |
8f604f8c TR |
135 | *format = WIN_COLOR_DEPTH_R8G8B8A8; |
136 | break; | |
10288eea TR |
137 | |
138 | case DRM_FORMAT_XRGB8888: | |
8f604f8c TR |
139 | *format = WIN_COLOR_DEPTH_B8G8R8A8; |
140 | break; | |
10288eea TR |
141 | |
142 | case DRM_FORMAT_RGB565: | |
8f604f8c TR |
143 | *format = WIN_COLOR_DEPTH_B5G6R5; |
144 | break; | |
10288eea TR |
145 | |
146 | case DRM_FORMAT_UYVY: | |
8f604f8c TR |
147 | *format = WIN_COLOR_DEPTH_YCbCr422; |
148 | break; | |
10288eea TR |
149 | |
150 | case DRM_FORMAT_YUYV: | |
151 | if (swap) | |
152 | *swap = BYTE_SWAP_SWAP2; | |
153 | ||
8f604f8c TR |
154 | *format = WIN_COLOR_DEPTH_YCbCr422; |
155 | break; | |
10288eea TR |
156 | |
157 | case DRM_FORMAT_YUV420: | |
8f604f8c TR |
158 | *format = WIN_COLOR_DEPTH_YCbCr420P; |
159 | break; | |
10288eea TR |
160 | |
161 | case DRM_FORMAT_YUV422: | |
8f604f8c TR |
162 | *format = WIN_COLOR_DEPTH_YCbCr422P; |
163 | break; | |
10288eea TR |
164 | |
165 | default: | |
8f604f8c | 166 | return -EINVAL; |
10288eea TR |
167 | } |
168 | ||
8f604f8c | 169 | return 0; |
10288eea TR |
170 | } |
171 | ||
172 | static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) | |
173 | { | |
174 | switch (format) { | |
175 | case WIN_COLOR_DEPTH_YCbCr422: | |
176 | case WIN_COLOR_DEPTH_YUV422: | |
177 | if (planar) | |
178 | *planar = false; | |
179 | ||
180 | return true; | |
181 | ||
182 | case WIN_COLOR_DEPTH_YCbCr420P: | |
183 | case WIN_COLOR_DEPTH_YUV420P: | |
184 | case WIN_COLOR_DEPTH_YCbCr422P: | |
185 | case WIN_COLOR_DEPTH_YUV422P: | |
186 | case WIN_COLOR_DEPTH_YCbCr422R: | |
187 | case WIN_COLOR_DEPTH_YUV422R: | |
188 | case WIN_COLOR_DEPTH_YCbCr422RA: | |
189 | case WIN_COLOR_DEPTH_YUV422RA: | |
190 | if (planar) | |
191 | *planar = true; | |
192 | ||
193 | return true; | |
194 | } | |
195 | ||
fb35c6b6 TR |
196 | if (planar) |
197 | *planar = false; | |
198 | ||
10288eea TR |
199 | return false; |
200 | } | |
201 | ||
202 | static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, | |
203 | unsigned int bpp) | |
204 | { | |
205 | fixed20_12 outf = dfixed_init(out); | |
206 | fixed20_12 inf = dfixed_init(in); | |
207 | u32 dda_inc; | |
208 | int max; | |
209 | ||
210 | if (v) | |
211 | max = 15; | |
212 | else { | |
213 | switch (bpp) { | |
214 | case 2: | |
215 | max = 8; | |
216 | break; | |
217 | ||
218 | default: | |
219 | WARN_ON_ONCE(1); | |
220 | /* fallthrough */ | |
221 | case 4: | |
222 | max = 4; | |
223 | break; | |
224 | } | |
225 | } | |
226 | ||
227 | outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); | |
228 | inf.full -= dfixed_const(1); | |
229 | ||
230 | dda_inc = dfixed_div(inf, outf); | |
231 | dda_inc = min_t(u32, dda_inc, dfixed_const(max)); | |
232 | ||
233 | return dda_inc; | |
234 | } | |
235 | ||
236 | static inline u32 compute_initial_dda(unsigned int in) | |
237 | { | |
238 | fixed20_12 inf = dfixed_init(in); | |
239 | return dfixed_frac(inf); | |
240 | } | |
241 | ||
4aa3df71 TR |
242 | static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, |
243 | const struct tegra_dc_window *window) | |
10288eea TR |
244 | { |
245 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; | |
93396d0f | 246 | unsigned long value, flags; |
10288eea TR |
247 | bool yuv, planar; |
248 | ||
249 | /* | |
250 | * For YUV planar modes, the number of bytes per pixel takes into | |
251 | * account only the luma component and therefore is 1. | |
252 | */ | |
253 | yuv = tegra_dc_format_is_yuv(window->format, &planar); | |
254 | if (!yuv) | |
255 | bpp = window->bits_per_pixel / 8; | |
256 | else | |
257 | bpp = planar ? 1 : 2; | |
258 | ||
93396d0f SP |
259 | spin_lock_irqsave(&dc->lock, flags); |
260 | ||
10288eea TR |
261 | value = WINDOW_A_SELECT << index; |
262 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
263 | ||
264 | tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); | |
265 | tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); | |
266 | ||
267 | value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); | |
268 | tegra_dc_writel(dc, value, DC_WIN_POSITION); | |
269 | ||
270 | value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); | |
271 | tegra_dc_writel(dc, value, DC_WIN_SIZE); | |
272 | ||
273 | h_offset = window->src.x * bpp; | |
274 | v_offset = window->src.y; | |
275 | h_size = window->src.w * bpp; | |
276 | v_size = window->src.h; | |
277 | ||
278 | value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); | |
279 | tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); | |
280 | ||
281 | /* | |
282 | * For DDA computations the number of bytes per pixel for YUV planar | |
283 | * modes needs to take into account all Y, U and V components. | |
284 | */ | |
285 | if (yuv && planar) | |
286 | bpp = 2; | |
287 | ||
288 | h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); | |
289 | v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); | |
290 | ||
291 | value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); | |
292 | tegra_dc_writel(dc, value, DC_WIN_DDA_INC); | |
293 | ||
294 | h_dda = compute_initial_dda(window->src.x); | |
295 | v_dda = compute_initial_dda(window->src.y); | |
296 | ||
297 | tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); | |
298 | tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); | |
299 | ||
300 | tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); | |
301 | tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); | |
302 | ||
303 | tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); | |
304 | ||
305 | if (yuv && planar) { | |
306 | tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); | |
307 | tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); | |
308 | value = window->stride[1] << 16 | window->stride[0]; | |
309 | tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); | |
310 | } else { | |
311 | tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); | |
312 | } | |
313 | ||
314 | if (window->bottom_up) | |
315 | v_offset += window->src.h - 1; | |
316 | ||
317 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
318 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
319 | ||
c134f019 TR |
320 | if (dc->soc->supports_block_linear) { |
321 | unsigned long height = window->tiling.value; | |
322 | ||
323 | switch (window->tiling.mode) { | |
324 | case TEGRA_BO_TILING_MODE_PITCH: | |
325 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
326 | break; | |
327 | ||
328 | case TEGRA_BO_TILING_MODE_TILED: | |
329 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
330 | break; | |
331 | ||
332 | case TEGRA_BO_TILING_MODE_BLOCK: | |
333 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
334 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
335 | break; | |
336 | } | |
337 | ||
338 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
10288eea | 339 | } else { |
c134f019 TR |
340 | switch (window->tiling.mode) { |
341 | case TEGRA_BO_TILING_MODE_PITCH: | |
342 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
343 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
344 | break; | |
10288eea | 345 | |
c134f019 TR |
346 | case TEGRA_BO_TILING_MODE_TILED: |
347 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
348 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
349 | break; | |
350 | ||
351 | case TEGRA_BO_TILING_MODE_BLOCK: | |
4aa3df71 TR |
352 | /* |
353 | * No need to handle this here because ->atomic_check | |
354 | * will already have filtered it out. | |
355 | */ | |
356 | break; | |
c134f019 TR |
357 | } |
358 | ||
359 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
360 | } | |
10288eea TR |
361 | |
362 | value = WIN_ENABLE; | |
363 | ||
364 | if (yuv) { | |
365 | /* setup default colorspace conversion coefficients */ | |
366 | tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); | |
367 | tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); | |
368 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); | |
369 | tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); | |
370 | tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); | |
371 | tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); | |
372 | tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); | |
373 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); | |
374 | ||
375 | value |= CSC_ENABLE; | |
376 | } else if (window->bits_per_pixel < 24) { | |
377 | value |= COLOR_EXPAND; | |
378 | } | |
379 | ||
380 | if (window->bottom_up) | |
381 | value |= V_DIRECTION; | |
382 | ||
383 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
384 | ||
385 | /* | |
386 | * Disable blending and assume Window A is the bottom-most window, | |
387 | * Window C is the top-most window and Window B is in the middle. | |
388 | */ | |
389 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); | |
390 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); | |
391 | ||
392 | switch (index) { | |
393 | case 0: | |
394 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); | |
395 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
396 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
397 | break; | |
398 | ||
399 | case 1: | |
400 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
401 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
402 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
403 | break; | |
404 | ||
405 | case 2: | |
406 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
407 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); | |
408 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); | |
409 | break; | |
410 | } | |
411 | ||
93396d0f | 412 | spin_unlock_irqrestore(&dc->lock, flags); |
c7679306 TR |
413 | } |
414 | ||
415 | static void tegra_plane_destroy(struct drm_plane *plane) | |
416 | { | |
417 | struct tegra_plane *p = to_tegra_plane(plane); | |
418 | ||
419 | drm_plane_cleanup(plane); | |
420 | kfree(p); | |
421 | } | |
422 | ||
423 | static const u32 tegra_primary_plane_formats[] = { | |
424 | DRM_FORMAT_XBGR8888, | |
425 | DRM_FORMAT_XRGB8888, | |
426 | DRM_FORMAT_RGB565, | |
427 | }; | |
428 | ||
4aa3df71 | 429 | static void tegra_primary_plane_destroy(struct drm_plane *plane) |
c7679306 | 430 | { |
4aa3df71 TR |
431 | tegra_plane_destroy(plane); |
432 | } | |
433 | ||
8f604f8c TR |
434 | static void tegra_plane_reset(struct drm_plane *plane) |
435 | { | |
436 | struct tegra_plane_state *state; | |
437 | ||
3b59b7ac | 438 | if (plane->state) |
2f701695 | 439 | __drm_atomic_helper_plane_destroy_state(plane->state); |
8f604f8c TR |
440 | |
441 | kfree(plane->state); | |
442 | plane->state = NULL; | |
443 | ||
444 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
445 | if (state) { | |
446 | plane->state = &state->base; | |
447 | plane->state->plane = plane; | |
448 | } | |
449 | } | |
450 | ||
451 | static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane) | |
452 | { | |
453 | struct tegra_plane_state *state = to_tegra_plane_state(plane->state); | |
454 | struct tegra_plane_state *copy; | |
455 | ||
3b59b7ac | 456 | copy = kmalloc(sizeof(*copy), GFP_KERNEL); |
8f604f8c TR |
457 | if (!copy) |
458 | return NULL; | |
459 | ||
3b59b7ac TR |
460 | __drm_atomic_helper_plane_duplicate_state(plane, ©->base); |
461 | copy->tiling = state->tiling; | |
462 | copy->format = state->format; | |
463 | copy->swap = state->swap; | |
8f604f8c TR |
464 | |
465 | return ©->base; | |
466 | } | |
467 | ||
468 | static void tegra_plane_atomic_destroy_state(struct drm_plane *plane, | |
469 | struct drm_plane_state *state) | |
470 | { | |
2f701695 | 471 | __drm_atomic_helper_plane_destroy_state(state); |
8f604f8c TR |
472 | kfree(state); |
473 | } | |
474 | ||
4aa3df71 | 475 | static const struct drm_plane_funcs tegra_primary_plane_funcs = { |
07866963 TR |
476 | .update_plane = drm_atomic_helper_update_plane, |
477 | .disable_plane = drm_atomic_helper_disable_plane, | |
4aa3df71 | 478 | .destroy = tegra_primary_plane_destroy, |
8f604f8c TR |
479 | .reset = tegra_plane_reset, |
480 | .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, | |
481 | .atomic_destroy_state = tegra_plane_atomic_destroy_state, | |
4aa3df71 TR |
482 | }; |
483 | ||
47802b09 TR |
484 | static int tegra_plane_state_add(struct tegra_plane *plane, |
485 | struct drm_plane_state *state) | |
486 | { | |
487 | struct drm_crtc_state *crtc_state; | |
488 | struct tegra_dc_state *tegra; | |
7d205857 DO |
489 | struct drm_rect clip; |
490 | int err; | |
47802b09 TR |
491 | |
492 | /* Propagate errors from allocation or locking failures. */ | |
493 | crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); | |
494 | if (IS_ERR(crtc_state)) | |
495 | return PTR_ERR(crtc_state); | |
496 | ||
7d205857 DO |
497 | clip.x1 = 0; |
498 | clip.y1 = 0; | |
499 | clip.x2 = crtc_state->mode.hdisplay; | |
500 | clip.y2 = crtc_state->mode.vdisplay; | |
501 | ||
502 | /* Check plane state for visibility and calculate clipping bounds */ | |
503 | err = drm_plane_helper_check_state(state, &clip, 0, INT_MAX, | |
504 | true, true); | |
505 | if (err < 0) | |
506 | return err; | |
507 | ||
47802b09 TR |
508 | tegra = to_dc_state(crtc_state); |
509 | ||
510 | tegra->planes |= WIN_A_ACT_REQ << plane->index; | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
4aa3df71 TR |
515 | static int tegra_plane_atomic_check(struct drm_plane *plane, |
516 | struct drm_plane_state *state) | |
517 | { | |
8f604f8c TR |
518 | struct tegra_plane_state *plane_state = to_tegra_plane_state(state); |
519 | struct tegra_bo_tiling *tiling = &plane_state->tiling; | |
47802b09 | 520 | struct tegra_plane *tegra = to_tegra_plane(plane); |
4aa3df71 | 521 | struct tegra_dc *dc = to_tegra_dc(state->crtc); |
4aa3df71 TR |
522 | int err; |
523 | ||
524 | /* no need for further checks if the plane is being disabled */ | |
525 | if (!state->crtc) | |
526 | return 0; | |
527 | ||
438b74a5 | 528 | err = tegra_dc_format(state->fb->format->format, &plane_state->format, |
8f604f8c | 529 | &plane_state->swap); |
4aa3df71 TR |
530 | if (err < 0) |
531 | return err; | |
532 | ||
8f604f8c TR |
533 | err = tegra_fb_get_tiling(state->fb, tiling); |
534 | if (err < 0) | |
535 | return err; | |
536 | ||
537 | if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && | |
4aa3df71 TR |
538 | !dc->soc->supports_block_linear) { |
539 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
540 | return -EINVAL; | |
541 | } | |
542 | ||
543 | /* | |
544 | * Tegra doesn't support different strides for U and V planes so we | |
545 | * error out if the user tries to display a framebuffer with such a | |
546 | * configuration. | |
547 | */ | |
bcb0b461 | 548 | if (state->fb->format->num_planes > 2) { |
4aa3df71 TR |
549 | if (state->fb->pitches[2] != state->fb->pitches[1]) { |
550 | DRM_ERROR("unsupported UV-plane configuration\n"); | |
551 | return -EINVAL; | |
552 | } | |
553 | } | |
554 | ||
47802b09 TR |
555 | err = tegra_plane_state_add(tegra, state); |
556 | if (err < 0) | |
557 | return err; | |
558 | ||
4aa3df71 TR |
559 | return 0; |
560 | } | |
561 | ||
80d3eef1 DO |
562 | static void tegra_dc_disable_window(struct tegra_dc *dc, int index) |
563 | { | |
564 | unsigned long flags; | |
565 | u32 value; | |
566 | ||
567 | spin_lock_irqsave(&dc->lock, flags); | |
568 | ||
569 | value = WINDOW_A_SELECT << index; | |
570 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
571 | ||
572 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
573 | value &= ~WIN_ENABLE; | |
574 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
575 | ||
576 | spin_unlock_irqrestore(&dc->lock, flags); | |
577 | } | |
578 | ||
4aa3df71 TR |
579 | static void tegra_plane_atomic_update(struct drm_plane *plane, |
580 | struct drm_plane_state *old_state) | |
581 | { | |
8f604f8c | 582 | struct tegra_plane_state *state = to_tegra_plane_state(plane->state); |
4aa3df71 TR |
583 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); |
584 | struct drm_framebuffer *fb = plane->state->fb; | |
c7679306 | 585 | struct tegra_plane *p = to_tegra_plane(plane); |
c7679306 | 586 | struct tegra_dc_window window; |
4aa3df71 | 587 | unsigned int i; |
c7679306 | 588 | |
4aa3df71 TR |
589 | /* rien ne va plus */ |
590 | if (!plane->state->crtc || !plane->state->fb) | |
591 | return; | |
592 | ||
80d3eef1 DO |
593 | if (!plane->state->visible) |
594 | return tegra_dc_disable_window(dc, p->index); | |
595 | ||
c7679306 | 596 | memset(&window, 0, sizeof(window)); |
7d205857 DO |
597 | window.src.x = plane->state->src.x1 >> 16; |
598 | window.src.y = plane->state->src.y1 >> 16; | |
599 | window.src.w = drm_rect_width(&plane->state->src) >> 16; | |
600 | window.src.h = drm_rect_height(&plane->state->src) >> 16; | |
601 | window.dst.x = plane->state->dst.x1; | |
602 | window.dst.y = plane->state->dst.y1; | |
603 | window.dst.w = drm_rect_width(&plane->state->dst); | |
604 | window.dst.h = drm_rect_height(&plane->state->dst); | |
272725c7 | 605 | window.bits_per_pixel = fb->format->cpp[0] * 8; |
c7679306 TR |
606 | window.bottom_up = tegra_fb_is_bottom_up(fb); |
607 | ||
8f604f8c TR |
608 | /* copy from state */ |
609 | window.tiling = state->tiling; | |
610 | window.format = state->format; | |
611 | window.swap = state->swap; | |
c7679306 | 612 | |
bcb0b461 | 613 | for (i = 0; i < fb->format->num_planes; i++) { |
4aa3df71 | 614 | struct tegra_bo *bo = tegra_fb_get_plane(fb, i); |
c7679306 | 615 | |
4aa3df71 | 616 | window.base[i] = bo->paddr + fb->offsets[i]; |
08ee0178 DO |
617 | |
618 | /* | |
619 | * Tegra uses a shared stride for UV planes. Framebuffers are | |
620 | * already checked for this in the tegra_plane_atomic_check() | |
621 | * function, so it's safe to ignore the V-plane pitch here. | |
622 | */ | |
623 | if (i < 2) | |
624 | window.stride[i] = fb->pitches[i]; | |
4aa3df71 | 625 | } |
10288eea | 626 | |
4aa3df71 | 627 | tegra_dc_setup_window(dc, p->index, &window); |
10288eea TR |
628 | } |
629 | ||
4aa3df71 TR |
630 | static void tegra_plane_atomic_disable(struct drm_plane *plane, |
631 | struct drm_plane_state *old_state) | |
c7679306 | 632 | { |
4aa3df71 TR |
633 | struct tegra_plane *p = to_tegra_plane(plane); |
634 | struct tegra_dc *dc; | |
4aa3df71 TR |
635 | |
636 | /* rien ne va plus */ | |
637 | if (!old_state || !old_state->crtc) | |
638 | return; | |
639 | ||
640 | dc = to_tegra_dc(old_state->crtc); | |
641 | ||
80d3eef1 | 642 | tegra_dc_disable_window(dc, p->index); |
c7679306 TR |
643 | } |
644 | ||
4aa3df71 | 645 | static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = { |
4aa3df71 TR |
646 | .atomic_check = tegra_plane_atomic_check, |
647 | .atomic_update = tegra_plane_atomic_update, | |
648 | .atomic_disable = tegra_plane_atomic_disable, | |
c7679306 TR |
649 | }; |
650 | ||
651 | static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, | |
652 | struct tegra_dc *dc) | |
653 | { | |
518e6227 TR |
654 | /* |
655 | * Ideally this would use drm_crtc_mask(), but that would require the | |
656 | * CRTC to already be in the mode_config's list of CRTCs. However, it | |
657 | * will only be added to that list in the drm_crtc_init_with_planes() | |
658 | * (in tegra_dc_init()), which in turn requires registration of these | |
659 | * planes. So we have ourselves a nice little chicken and egg problem | |
660 | * here. | |
661 | * | |
662 | * We work around this by manually creating the mask from the number | |
663 | * of CRTCs that have been registered, and should therefore always be | |
664 | * the same as drm_crtc_index() after registration. | |
665 | */ | |
666 | unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc; | |
c7679306 TR |
667 | struct tegra_plane *plane; |
668 | unsigned int num_formats; | |
669 | const u32 *formats; | |
670 | int err; | |
671 | ||
672 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
673 | if (!plane) | |
674 | return ERR_PTR(-ENOMEM); | |
675 | ||
676 | num_formats = ARRAY_SIZE(tegra_primary_plane_formats); | |
677 | formats = tegra_primary_plane_formats; | |
678 | ||
518e6227 | 679 | err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, |
c7679306 | 680 | &tegra_primary_plane_funcs, formats, |
b0b3b795 VS |
681 | num_formats, DRM_PLANE_TYPE_PRIMARY, |
682 | NULL); | |
c7679306 TR |
683 | if (err < 0) { |
684 | kfree(plane); | |
685 | return ERR_PTR(err); | |
686 | } | |
687 | ||
4aa3df71 TR |
688 | drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs); |
689 | ||
c7679306 TR |
690 | return &plane->base; |
691 | } | |
692 | ||
693 | static const u32 tegra_cursor_plane_formats[] = { | |
694 | DRM_FORMAT_RGBA8888, | |
695 | }; | |
696 | ||
4aa3df71 TR |
697 | static int tegra_cursor_atomic_check(struct drm_plane *plane, |
698 | struct drm_plane_state *state) | |
c7679306 | 699 | { |
47802b09 TR |
700 | struct tegra_plane *tegra = to_tegra_plane(plane); |
701 | int err; | |
702 | ||
4aa3df71 TR |
703 | /* no need for further checks if the plane is being disabled */ |
704 | if (!state->crtc) | |
705 | return 0; | |
c7679306 TR |
706 | |
707 | /* scaling not supported for cursor */ | |
4aa3df71 TR |
708 | if ((state->src_w >> 16 != state->crtc_w) || |
709 | (state->src_h >> 16 != state->crtc_h)) | |
c7679306 TR |
710 | return -EINVAL; |
711 | ||
712 | /* only square cursors supported */ | |
4aa3df71 TR |
713 | if (state->src_w != state->src_h) |
714 | return -EINVAL; | |
715 | ||
716 | if (state->crtc_w != 32 && state->crtc_w != 64 && | |
717 | state->crtc_w != 128 && state->crtc_w != 256) | |
c7679306 TR |
718 | return -EINVAL; |
719 | ||
47802b09 TR |
720 | err = tegra_plane_state_add(tegra, state); |
721 | if (err < 0) | |
722 | return err; | |
723 | ||
4aa3df71 TR |
724 | return 0; |
725 | } | |
726 | ||
727 | static void tegra_cursor_atomic_update(struct drm_plane *plane, | |
728 | struct drm_plane_state *old_state) | |
729 | { | |
730 | struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0); | |
731 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); | |
732 | struct drm_plane_state *state = plane->state; | |
733 | u32 value = CURSOR_CLIP_DISPLAY; | |
734 | ||
735 | /* rien ne va plus */ | |
736 | if (!plane->state->crtc || !plane->state->fb) | |
737 | return; | |
738 | ||
739 | switch (state->crtc_w) { | |
c7679306 TR |
740 | case 32: |
741 | value |= CURSOR_SIZE_32x32; | |
742 | break; | |
743 | ||
744 | case 64: | |
745 | value |= CURSOR_SIZE_64x64; | |
746 | break; | |
747 | ||
748 | case 128: | |
749 | value |= CURSOR_SIZE_128x128; | |
750 | break; | |
751 | ||
752 | case 256: | |
753 | value |= CURSOR_SIZE_256x256; | |
754 | break; | |
755 | ||
756 | default: | |
4aa3df71 TR |
757 | WARN(1, "cursor size %ux%u not supported\n", state->crtc_w, |
758 | state->crtc_h); | |
759 | return; | |
c7679306 TR |
760 | } |
761 | ||
762 | value |= (bo->paddr >> 10) & 0x3fffff; | |
763 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); | |
764 | ||
765 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
766 | value = (bo->paddr >> 32) & 0x3; | |
767 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); | |
768 | #endif | |
769 | ||
770 | /* enable cursor and set blend mode */ | |
771 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
772 | value |= CURSOR_ENABLE; | |
773 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
774 | ||
775 | value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); | |
776 | value &= ~CURSOR_DST_BLEND_MASK; | |
777 | value &= ~CURSOR_SRC_BLEND_MASK; | |
778 | value |= CURSOR_MODE_NORMAL; | |
779 | value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; | |
780 | value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; | |
781 | value |= CURSOR_ALPHA; | |
782 | tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); | |
783 | ||
784 | /* position the cursor */ | |
4aa3df71 | 785 | value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff); |
c7679306 | 786 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); |
c7679306 TR |
787 | } |
788 | ||
4aa3df71 TR |
789 | static void tegra_cursor_atomic_disable(struct drm_plane *plane, |
790 | struct drm_plane_state *old_state) | |
c7679306 | 791 | { |
4aa3df71 | 792 | struct tegra_dc *dc; |
c7679306 TR |
793 | u32 value; |
794 | ||
4aa3df71 TR |
795 | /* rien ne va plus */ |
796 | if (!old_state || !old_state->crtc) | |
797 | return; | |
798 | ||
799 | dc = to_tegra_dc(old_state->crtc); | |
c7679306 TR |
800 | |
801 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
802 | value &= ~CURSOR_ENABLE; | |
803 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
c7679306 TR |
804 | } |
805 | ||
806 | static const struct drm_plane_funcs tegra_cursor_plane_funcs = { | |
07866963 TR |
807 | .update_plane = drm_atomic_helper_update_plane, |
808 | .disable_plane = drm_atomic_helper_disable_plane, | |
c7679306 | 809 | .destroy = tegra_plane_destroy, |
8f604f8c TR |
810 | .reset = tegra_plane_reset, |
811 | .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, | |
812 | .atomic_destroy_state = tegra_plane_atomic_destroy_state, | |
4aa3df71 TR |
813 | }; |
814 | ||
815 | static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { | |
4aa3df71 TR |
816 | .atomic_check = tegra_cursor_atomic_check, |
817 | .atomic_update = tegra_cursor_atomic_update, | |
818 | .atomic_disable = tegra_cursor_atomic_disable, | |
c7679306 TR |
819 | }; |
820 | ||
821 | static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, | |
822 | struct tegra_dc *dc) | |
823 | { | |
824 | struct tegra_plane *plane; | |
825 | unsigned int num_formats; | |
826 | const u32 *formats; | |
827 | int err; | |
828 | ||
829 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
830 | if (!plane) | |
831 | return ERR_PTR(-ENOMEM); | |
832 | ||
47802b09 | 833 | /* |
a1df3b24 TR |
834 | * This index is kind of fake. The cursor isn't a regular plane, but |
835 | * its update and activation request bits in DC_CMD_STATE_CONTROL do | |
836 | * use the same programming. Setting this fake index here allows the | |
837 | * code in tegra_add_plane_state() to do the right thing without the | |
838 | * need to special-casing the cursor plane. | |
47802b09 TR |
839 | */ |
840 | plane->index = 6; | |
841 | ||
c7679306 TR |
842 | num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); |
843 | formats = tegra_cursor_plane_formats; | |
844 | ||
845 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, | |
846 | &tegra_cursor_plane_funcs, formats, | |
b0b3b795 VS |
847 | num_formats, DRM_PLANE_TYPE_CURSOR, |
848 | NULL); | |
c7679306 TR |
849 | if (err < 0) { |
850 | kfree(plane); | |
851 | return ERR_PTR(err); | |
852 | } | |
853 | ||
4aa3df71 | 854 | drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); |
f34bc787 | 855 | |
4aa3df71 | 856 | return &plane->base; |
f34bc787 TR |
857 | } |
858 | ||
c7679306 | 859 | static void tegra_overlay_plane_destroy(struct drm_plane *plane) |
f34bc787 | 860 | { |
c7679306 | 861 | tegra_plane_destroy(plane); |
f34bc787 TR |
862 | } |
863 | ||
c7679306 | 864 | static const struct drm_plane_funcs tegra_overlay_plane_funcs = { |
07866963 TR |
865 | .update_plane = drm_atomic_helper_update_plane, |
866 | .disable_plane = drm_atomic_helper_disable_plane, | |
c7679306 | 867 | .destroy = tegra_overlay_plane_destroy, |
8f604f8c TR |
868 | .reset = tegra_plane_reset, |
869 | .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, | |
870 | .atomic_destroy_state = tegra_plane_atomic_destroy_state, | |
f34bc787 TR |
871 | }; |
872 | ||
c7679306 | 873 | static const uint32_t tegra_overlay_plane_formats[] = { |
dbe4d9a7 | 874 | DRM_FORMAT_XBGR8888, |
f34bc787 | 875 | DRM_FORMAT_XRGB8888, |
dbe4d9a7 | 876 | DRM_FORMAT_RGB565, |
f34bc787 | 877 | DRM_FORMAT_UYVY, |
f925390e | 878 | DRM_FORMAT_YUYV, |
f34bc787 TR |
879 | DRM_FORMAT_YUV420, |
880 | DRM_FORMAT_YUV422, | |
881 | }; | |
882 | ||
4aa3df71 | 883 | static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = { |
4aa3df71 TR |
884 | .atomic_check = tegra_plane_atomic_check, |
885 | .atomic_update = tegra_plane_atomic_update, | |
886 | .atomic_disable = tegra_plane_atomic_disable, | |
887 | }; | |
888 | ||
c7679306 TR |
889 | static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, |
890 | struct tegra_dc *dc, | |
891 | unsigned int index) | |
f34bc787 | 892 | { |
c7679306 TR |
893 | struct tegra_plane *plane; |
894 | unsigned int num_formats; | |
895 | const u32 *formats; | |
896 | int err; | |
f34bc787 | 897 | |
c7679306 TR |
898 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
899 | if (!plane) | |
900 | return ERR_PTR(-ENOMEM); | |
f34bc787 | 901 | |
c7679306 | 902 | plane->index = index; |
f34bc787 | 903 | |
c7679306 TR |
904 | num_formats = ARRAY_SIZE(tegra_overlay_plane_formats); |
905 | formats = tegra_overlay_plane_formats; | |
f34bc787 | 906 | |
c7679306 TR |
907 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, |
908 | &tegra_overlay_plane_funcs, formats, | |
b0b3b795 VS |
909 | num_formats, DRM_PLANE_TYPE_OVERLAY, |
910 | NULL); | |
c7679306 TR |
911 | if (err < 0) { |
912 | kfree(plane); | |
913 | return ERR_PTR(err); | |
914 | } | |
915 | ||
4aa3df71 TR |
916 | drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs); |
917 | ||
c7679306 TR |
918 | return &plane->base; |
919 | } | |
920 | ||
921 | static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) | |
922 | { | |
923 | struct drm_plane *plane; | |
924 | unsigned int i; | |
925 | ||
926 | for (i = 0; i < 2; i++) { | |
927 | plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); | |
928 | if (IS_ERR(plane)) | |
929 | return PTR_ERR(plane); | |
f34bc787 TR |
930 | } |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
10437d9b | 935 | static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) |
42e9ce05 | 936 | { |
10437d9b SG |
937 | struct tegra_dc *dc = to_tegra_dc(crtc); |
938 | ||
42e9ce05 TR |
939 | if (dc->syncpt) |
940 | return host1x_syncpt_read(dc->syncpt); | |
941 | ||
942 | /* fallback to software emulated VBLANK counter */ | |
943 | return drm_crtc_vblank_count(&dc->base); | |
944 | } | |
945 | ||
10437d9b | 946 | static int tegra_dc_enable_vblank(struct drm_crtc *crtc) |
6e5ff998 | 947 | { |
10437d9b | 948 | struct tegra_dc *dc = to_tegra_dc(crtc); |
6e5ff998 TR |
949 | unsigned long value, flags; |
950 | ||
951 | spin_lock_irqsave(&dc->lock, flags); | |
952 | ||
953 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
954 | value |= VBLANK_INT; | |
955 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
956 | ||
957 | spin_unlock_irqrestore(&dc->lock, flags); | |
10437d9b SG |
958 | |
959 | return 0; | |
6e5ff998 TR |
960 | } |
961 | ||
10437d9b | 962 | static void tegra_dc_disable_vblank(struct drm_crtc *crtc) |
6e5ff998 | 963 | { |
10437d9b | 964 | struct tegra_dc *dc = to_tegra_dc(crtc); |
6e5ff998 TR |
965 | unsigned long value, flags; |
966 | ||
967 | spin_lock_irqsave(&dc->lock, flags); | |
968 | ||
969 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
970 | value &= ~VBLANK_INT; | |
971 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
972 | ||
973 | spin_unlock_irqrestore(&dc->lock, flags); | |
974 | } | |
975 | ||
3c03c46a TR |
976 | static void tegra_dc_finish_page_flip(struct tegra_dc *dc) |
977 | { | |
978 | struct drm_device *drm = dc->base.dev; | |
979 | struct drm_crtc *crtc = &dc->base; | |
3c03c46a | 980 | unsigned long flags, base; |
de2ba664 | 981 | struct tegra_bo *bo; |
3c03c46a | 982 | |
6b59cc1c TR |
983 | spin_lock_irqsave(&drm->event_lock, flags); |
984 | ||
985 | if (!dc->event) { | |
986 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a | 987 | return; |
6b59cc1c | 988 | } |
3c03c46a | 989 | |
f4510a27 | 990 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
3c03c46a | 991 | |
8643bc6d | 992 | spin_lock(&dc->lock); |
93396d0f | 993 | |
3c03c46a | 994 | /* check if new start address has been latched */ |
93396d0f | 995 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
3c03c46a TR |
996 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); |
997 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); | |
998 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
999 | ||
8643bc6d | 1000 | spin_unlock(&dc->lock); |
93396d0f | 1001 | |
f4510a27 | 1002 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { |
ed7dae58 TR |
1003 | drm_crtc_send_vblank_event(crtc, dc->event); |
1004 | drm_crtc_vblank_put(crtc); | |
3c03c46a | 1005 | dc->event = NULL; |
3c03c46a | 1006 | } |
6b59cc1c TR |
1007 | |
1008 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a TR |
1009 | } |
1010 | ||
f002abc1 TR |
1011 | static void tegra_dc_destroy(struct drm_crtc *crtc) |
1012 | { | |
1013 | drm_crtc_cleanup(crtc); | |
f002abc1 TR |
1014 | } |
1015 | ||
ca915b10 TR |
1016 | static void tegra_crtc_reset(struct drm_crtc *crtc) |
1017 | { | |
1018 | struct tegra_dc_state *state; | |
1019 | ||
3b59b7ac | 1020 | if (crtc->state) |
ec2dc6a0 | 1021 | __drm_atomic_helper_crtc_destroy_state(crtc->state); |
3b59b7ac | 1022 | |
ca915b10 TR |
1023 | kfree(crtc->state); |
1024 | crtc->state = NULL; | |
1025 | ||
1026 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
332bbe70 | 1027 | if (state) { |
ca915b10 | 1028 | crtc->state = &state->base; |
332bbe70 TR |
1029 | crtc->state->crtc = crtc; |
1030 | } | |
31930d4d TR |
1031 | |
1032 | drm_crtc_vblank_reset(crtc); | |
ca915b10 TR |
1033 | } |
1034 | ||
1035 | static struct drm_crtc_state * | |
1036 | tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) | |
1037 | { | |
1038 | struct tegra_dc_state *state = to_dc_state(crtc->state); | |
1039 | struct tegra_dc_state *copy; | |
1040 | ||
3b59b7ac | 1041 | copy = kmalloc(sizeof(*copy), GFP_KERNEL); |
ca915b10 TR |
1042 | if (!copy) |
1043 | return NULL; | |
1044 | ||
3b59b7ac TR |
1045 | __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); |
1046 | copy->clk = state->clk; | |
1047 | copy->pclk = state->pclk; | |
1048 | copy->div = state->div; | |
1049 | copy->planes = state->planes; | |
ca915b10 TR |
1050 | |
1051 | return ©->base; | |
1052 | } | |
1053 | ||
1054 | static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, | |
1055 | struct drm_crtc_state *state) | |
1056 | { | |
ec2dc6a0 | 1057 | __drm_atomic_helper_crtc_destroy_state(state); |
ca915b10 TR |
1058 | kfree(state); |
1059 | } | |
1060 | ||
d8f4a9ed | 1061 | static const struct drm_crtc_funcs tegra_crtc_funcs = { |
1503ca47 | 1062 | .page_flip = drm_atomic_helper_page_flip, |
74f48791 | 1063 | .set_config = drm_atomic_helper_set_config, |
f002abc1 | 1064 | .destroy = tegra_dc_destroy, |
ca915b10 TR |
1065 | .reset = tegra_crtc_reset, |
1066 | .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, | |
1067 | .atomic_destroy_state = tegra_crtc_atomic_destroy_state, | |
10437d9b SG |
1068 | .get_vblank_counter = tegra_dc_get_vblank_counter, |
1069 | .enable_vblank = tegra_dc_enable_vblank, | |
1070 | .disable_vblank = tegra_dc_disable_vblank, | |
d8f4a9ed TR |
1071 | }; |
1072 | ||
d8f4a9ed TR |
1073 | static int tegra_dc_set_timings(struct tegra_dc *dc, |
1074 | struct drm_display_mode *mode) | |
1075 | { | |
0444c0ff TR |
1076 | unsigned int h_ref_to_sync = 1; |
1077 | unsigned int v_ref_to_sync = 1; | |
d8f4a9ed TR |
1078 | unsigned long value; |
1079 | ||
1080 | tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); | |
1081 | ||
1082 | value = (v_ref_to_sync << 16) | h_ref_to_sync; | |
1083 | tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); | |
1084 | ||
1085 | value = ((mode->vsync_end - mode->vsync_start) << 16) | | |
1086 | ((mode->hsync_end - mode->hsync_start) << 0); | |
1087 | tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); | |
1088 | ||
d8f4a9ed TR |
1089 | value = ((mode->vtotal - mode->vsync_end) << 16) | |
1090 | ((mode->htotal - mode->hsync_end) << 0); | |
40495089 LS |
1091 | tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); |
1092 | ||
1093 | value = ((mode->vsync_start - mode->vdisplay) << 16) | | |
1094 | ((mode->hsync_start - mode->hdisplay) << 0); | |
d8f4a9ed TR |
1095 | tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); |
1096 | ||
1097 | value = (mode->vdisplay << 16) | mode->hdisplay; | |
1098 | tegra_dc_writel(dc, value, DC_DISP_ACTIVE); | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
9d910b60 TR |
1103 | /** |
1104 | * tegra_dc_state_setup_clock - check clock settings and store them in atomic | |
1105 | * state | |
1106 | * @dc: display controller | |
1107 | * @crtc_state: CRTC atomic state | |
1108 | * @clk: parent clock for display controller | |
1109 | * @pclk: pixel clock | |
1110 | * @div: shift clock divider | |
1111 | * | |
1112 | * Returns: | |
1113 | * 0 on success or a negative error-code on failure. | |
1114 | */ | |
ca915b10 TR |
1115 | int tegra_dc_state_setup_clock(struct tegra_dc *dc, |
1116 | struct drm_crtc_state *crtc_state, | |
1117 | struct clk *clk, unsigned long pclk, | |
1118 | unsigned int div) | |
1119 | { | |
1120 | struct tegra_dc_state *state = to_dc_state(crtc_state); | |
1121 | ||
d2982748 TR |
1122 | if (!clk_has_parent(dc->clk, clk)) |
1123 | return -EINVAL; | |
1124 | ||
ca915b10 TR |
1125 | state->clk = clk; |
1126 | state->pclk = pclk; | |
1127 | state->div = div; | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
76d59ed0 TR |
1132 | static void tegra_dc_commit_state(struct tegra_dc *dc, |
1133 | struct tegra_dc_state *state) | |
1134 | { | |
1135 | u32 value; | |
1136 | int err; | |
1137 | ||
1138 | err = clk_set_parent(dc->clk, state->clk); | |
1139 | if (err < 0) | |
1140 | dev_err(dc->dev, "failed to set parent clock: %d\n", err); | |
1141 | ||
1142 | /* | |
1143 | * Outputs may not want to change the parent clock rate. This is only | |
1144 | * relevant to Tegra20 where only a single display PLL is available. | |
1145 | * Since that PLL would typically be used for HDMI, an internal LVDS | |
1146 | * panel would need to be driven by some other clock such as PLL_P | |
1147 | * which is shared with other peripherals. Changing the clock rate | |
1148 | * should therefore be avoided. | |
1149 | */ | |
1150 | if (state->pclk > 0) { | |
1151 | err = clk_set_rate(state->clk, state->pclk); | |
1152 | if (err < 0) | |
1153 | dev_err(dc->dev, | |
1154 | "failed to set clock rate to %lu Hz\n", | |
1155 | state->pclk); | |
1156 | } | |
1157 | ||
1158 | DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), | |
1159 | state->div); | |
1160 | DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); | |
1161 | ||
1162 | value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; | |
1163 | tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); | |
1164 | } | |
1165 | ||
003fc848 TR |
1166 | static void tegra_dc_stop(struct tegra_dc *dc) |
1167 | { | |
1168 | u32 value; | |
1169 | ||
1170 | /* stop the display controller */ | |
1171 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); | |
1172 | value &= ~DISP_CTRL_MODE_MASK; | |
1173 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); | |
1174 | ||
1175 | tegra_dc_commit(dc); | |
1176 | } | |
1177 | ||
1178 | static bool tegra_dc_idle(struct tegra_dc *dc) | |
1179 | { | |
1180 | u32 value; | |
1181 | ||
1182 | value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); | |
1183 | ||
1184 | return (value & DISP_CTRL_MODE_MASK) == 0; | |
1185 | } | |
1186 | ||
1187 | static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) | |
1188 | { | |
1189 | timeout = jiffies + msecs_to_jiffies(timeout); | |
1190 | ||
1191 | while (time_before(jiffies, timeout)) { | |
1192 | if (tegra_dc_idle(dc)) | |
1193 | return 0; | |
1194 | ||
1195 | usleep_range(1000, 2000); | |
1196 | } | |
1197 | ||
1198 | dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); | |
1199 | return -ETIMEDOUT; | |
1200 | } | |
1201 | ||
1202 | static void tegra_crtc_disable(struct drm_crtc *crtc) | |
1203 | { | |
1204 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
1205 | u32 value; | |
1206 | ||
1207 | if (!tegra_dc_idle(dc)) { | |
1208 | tegra_dc_stop(dc); | |
1209 | ||
1210 | /* | |
1211 | * Ignore the return value, there isn't anything useful to do | |
1212 | * in case this fails. | |
1213 | */ | |
1214 | tegra_dc_wait_idle(dc, 100); | |
1215 | } | |
1216 | ||
1217 | /* | |
1218 | * This should really be part of the RGB encoder driver, but clearing | |
1219 | * these bits has the side-effect of stopping the display controller. | |
1220 | * When that happens no VBLANK interrupts will be raised. At the same | |
1221 | * time the encoder is disabled before the display controller, so the | |
1222 | * above code is always going to timeout waiting for the controller | |
1223 | * to go idle. | |
1224 | * | |
1225 | * Given the close coupling between the RGB encoder and the display | |
1226 | * controller doing it here is still kind of okay. None of the other | |
1227 | * encoder drivers require these bits to be cleared. | |
1228 | * | |
1229 | * XXX: Perhaps given that the display controller is switched off at | |
1230 | * this point anyway maybe clearing these bits isn't even useful for | |
1231 | * the RGB encoder? | |
1232 | */ | |
1233 | if (dc->rgb) { | |
1234 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); | |
1235 | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | | |
1236 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); | |
1237 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); | |
1238 | } | |
1239 | ||
1240 | tegra_dc_stats_reset(&dc->stats); | |
1241 | drm_crtc_vblank_off(crtc); | |
33a8eb8d TR |
1242 | |
1243 | pm_runtime_put_sync(dc->dev); | |
003fc848 TR |
1244 | } |
1245 | ||
0b20a0f8 LP |
1246 | static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, |
1247 | struct drm_crtc_state *old_state) | |
d8f4a9ed | 1248 | { |
4aa3df71 | 1249 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
76d59ed0 | 1250 | struct tegra_dc_state *state = to_dc_state(crtc->state); |
d8f4a9ed | 1251 | struct tegra_dc *dc = to_tegra_dc(crtc); |
dbb3f2f7 | 1252 | u32 value; |
d8f4a9ed | 1253 | |
33a8eb8d TR |
1254 | pm_runtime_get_sync(dc->dev); |
1255 | ||
1256 | /* initialize display controller */ | |
1257 | if (dc->syncpt) { | |
1258 | u32 syncpt = host1x_syncpt_id(dc->syncpt); | |
1259 | ||
1260 | value = SYNCPT_CNTRL_NO_STALL; | |
1261 | tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1262 | ||
1263 | value = SYNCPT_VSYNC_ENABLE | syncpt; | |
1264 | tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); | |
1265 | } | |
1266 | ||
1267 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1268 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1269 | tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); | |
1270 | ||
1271 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1272 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1273 | tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); | |
1274 | ||
1275 | /* initialize timer */ | |
1276 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | | |
1277 | WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); | |
1278 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1279 | ||
1280 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | | |
1281 | WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); | |
1282 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1283 | ||
1284 | value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1285 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1286 | tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); | |
1287 | ||
1288 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1289 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1290 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
1291 | ||
1292 | if (dc->soc->supports_border_color) | |
1293 | tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); | |
1294 | ||
1295 | /* apply PLL and pixel clock changes */ | |
76d59ed0 TR |
1296 | tegra_dc_commit_state(dc, state); |
1297 | ||
d8f4a9ed TR |
1298 | /* program display mode */ |
1299 | tegra_dc_set_timings(dc, mode); | |
1300 | ||
8620fc62 TR |
1301 | /* interlacing isn't supported yet, so disable it */ |
1302 | if (dc->soc->supports_interlacing) { | |
1303 | value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); | |
1304 | value &= ~INTERLACE_ENABLE; | |
1305 | tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); | |
1306 | } | |
666cb873 TR |
1307 | |
1308 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); | |
1309 | value &= ~DISP_CTRL_MODE_MASK; | |
1310 | value |= DISP_CTRL_MODE_C_DISPLAY; | |
1311 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); | |
1312 | ||
1313 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); | |
1314 | value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | | |
1315 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; | |
1316 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); | |
1317 | ||
1318 | tegra_dc_commit(dc); | |
d8f4a9ed | 1319 | |
8ff64c17 | 1320 | drm_crtc_vblank_on(crtc); |
d8f4a9ed TR |
1321 | } |
1322 | ||
4aa3df71 TR |
1323 | static int tegra_crtc_atomic_check(struct drm_crtc *crtc, |
1324 | struct drm_crtc_state *state) | |
1325 | { | |
1326 | return 0; | |
1327 | } | |
1328 | ||
613d2b27 ML |
1329 | static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, |
1330 | struct drm_crtc_state *old_crtc_state) | |
4aa3df71 | 1331 | { |
1503ca47 TR |
1332 | struct tegra_dc *dc = to_tegra_dc(crtc); |
1333 | ||
1334 | if (crtc->state->event) { | |
1335 | crtc->state->event->pipe = drm_crtc_index(crtc); | |
1336 | ||
1337 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
1338 | ||
1339 | dc->event = crtc->state->event; | |
1340 | crtc->state->event = NULL; | |
1341 | } | |
4aa3df71 TR |
1342 | } |
1343 | ||
613d2b27 ML |
1344 | static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, |
1345 | struct drm_crtc_state *old_crtc_state) | |
4aa3df71 | 1346 | { |
47802b09 TR |
1347 | struct tegra_dc_state *state = to_dc_state(crtc->state); |
1348 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
1349 | ||
1350 | tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL); | |
1351 | tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL); | |
4aa3df71 TR |
1352 | } |
1353 | ||
d8f4a9ed | 1354 | static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { |
f34bc787 | 1355 | .disable = tegra_crtc_disable, |
4aa3df71 TR |
1356 | .atomic_check = tegra_crtc_atomic_check, |
1357 | .atomic_begin = tegra_crtc_atomic_begin, | |
1358 | .atomic_flush = tegra_crtc_atomic_flush, | |
0b20a0f8 | 1359 | .atomic_enable = tegra_crtc_atomic_enable, |
d8f4a9ed TR |
1360 | }; |
1361 | ||
6e5ff998 | 1362 | static irqreturn_t tegra_dc_irq(int irq, void *data) |
d8f4a9ed TR |
1363 | { |
1364 | struct tegra_dc *dc = data; | |
1365 | unsigned long status; | |
1366 | ||
1367 | status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); | |
1368 | tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); | |
1369 | ||
1370 | if (status & FRAME_END_INT) { | |
1371 | /* | |
1372 | dev_dbg(dc->dev, "%s(): frame end\n", __func__); | |
1373 | */ | |
791ddb1e | 1374 | dc->stats.frames++; |
d8f4a9ed TR |
1375 | } |
1376 | ||
1377 | if (status & VBLANK_INT) { | |
1378 | /* | |
1379 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); | |
1380 | */ | |
ed7dae58 | 1381 | drm_crtc_handle_vblank(&dc->base); |
3c03c46a | 1382 | tegra_dc_finish_page_flip(dc); |
791ddb1e | 1383 | dc->stats.vblank++; |
d8f4a9ed TR |
1384 | } |
1385 | ||
1386 | if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { | |
1387 | /* | |
1388 | dev_dbg(dc->dev, "%s(): underflow\n", __func__); | |
1389 | */ | |
791ddb1e TR |
1390 | dc->stats.underflow++; |
1391 | } | |
1392 | ||
1393 | if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { | |
1394 | /* | |
1395 | dev_dbg(dc->dev, "%s(): overflow\n", __func__); | |
1396 | */ | |
1397 | dc->stats.overflow++; | |
d8f4a9ed TR |
1398 | } |
1399 | ||
1400 | return IRQ_HANDLED; | |
1401 | } | |
1402 | ||
1403 | static int tegra_dc_show_regs(struct seq_file *s, void *data) | |
1404 | { | |
1405 | struct drm_info_node *node = s->private; | |
1406 | struct tegra_dc *dc = node->info_ent->data; | |
003fc848 TR |
1407 | int err = 0; |
1408 | ||
99612b27 | 1409 | drm_modeset_lock(&dc->base.mutex, NULL); |
003fc848 TR |
1410 | |
1411 | if (!dc->base.state->active) { | |
1412 | err = -EBUSY; | |
1413 | goto unlock; | |
1414 | } | |
d8f4a9ed TR |
1415 | |
1416 | #define DUMP_REG(name) \ | |
03a60569 | 1417 | seq_printf(s, "%-40s %#05x %08x\n", #name, name, \ |
d8f4a9ed TR |
1418 | tegra_dc_readl(dc, name)) |
1419 | ||
1420 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); | |
1421 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1422 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); | |
1423 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); | |
1424 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); | |
1425 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); | |
1426 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); | |
1427 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); | |
1428 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); | |
1429 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); | |
1430 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); | |
1431 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); | |
1432 | DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); | |
1433 | DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); | |
1434 | DUMP_REG(DC_CMD_DISPLAY_COMMAND); | |
1435 | DUMP_REG(DC_CMD_SIGNAL_RAISE); | |
1436 | DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); | |
1437 | DUMP_REG(DC_CMD_INT_STATUS); | |
1438 | DUMP_REG(DC_CMD_INT_MASK); | |
1439 | DUMP_REG(DC_CMD_INT_ENABLE); | |
1440 | DUMP_REG(DC_CMD_INT_TYPE); | |
1441 | DUMP_REG(DC_CMD_INT_POLARITY); | |
1442 | DUMP_REG(DC_CMD_SIGNAL_RAISE1); | |
1443 | DUMP_REG(DC_CMD_SIGNAL_RAISE2); | |
1444 | DUMP_REG(DC_CMD_SIGNAL_RAISE3); | |
1445 | DUMP_REG(DC_CMD_STATE_ACCESS); | |
1446 | DUMP_REG(DC_CMD_STATE_CONTROL); | |
1447 | DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); | |
1448 | DUMP_REG(DC_CMD_REG_ACT_CONTROL); | |
1449 | DUMP_REG(DC_COM_CRC_CONTROL); | |
1450 | DUMP_REG(DC_COM_CRC_CHECKSUM); | |
1451 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); | |
1452 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); | |
1453 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); | |
1454 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); | |
1455 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); | |
1456 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); | |
1457 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); | |
1458 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); | |
1459 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); | |
1460 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); | |
1461 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); | |
1462 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); | |
1463 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); | |
1464 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); | |
1465 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); | |
1466 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); | |
1467 | DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); | |
1468 | DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); | |
1469 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); | |
1470 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); | |
1471 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); | |
1472 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); | |
1473 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); | |
1474 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); | |
1475 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); | |
1476 | DUMP_REG(DC_COM_PIN_MISC_CONTROL); | |
1477 | DUMP_REG(DC_COM_PIN_PM0_CONTROL); | |
1478 | DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); | |
1479 | DUMP_REG(DC_COM_PIN_PM1_CONTROL); | |
1480 | DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); | |
1481 | DUMP_REG(DC_COM_SPI_CONTROL); | |
1482 | DUMP_REG(DC_COM_SPI_START_BYTE); | |
1483 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); | |
1484 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); | |
1485 | DUMP_REG(DC_COM_HSPI_CS_DC); | |
1486 | DUMP_REG(DC_COM_SCRATCH_REGISTER_A); | |
1487 | DUMP_REG(DC_COM_SCRATCH_REGISTER_B); | |
1488 | DUMP_REG(DC_COM_GPIO_CTRL); | |
1489 | DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); | |
1490 | DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); | |
1491 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); | |
1492 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); | |
1493 | DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); | |
1494 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1495 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1496 | DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); | |
1497 | DUMP_REG(DC_DISP_REF_TO_SYNC); | |
1498 | DUMP_REG(DC_DISP_SYNC_WIDTH); | |
1499 | DUMP_REG(DC_DISP_BACK_PORCH); | |
1500 | DUMP_REG(DC_DISP_ACTIVE); | |
1501 | DUMP_REG(DC_DISP_FRONT_PORCH); | |
1502 | DUMP_REG(DC_DISP_H_PULSE0_CONTROL); | |
1503 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); | |
1504 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); | |
1505 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); | |
1506 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); | |
1507 | DUMP_REG(DC_DISP_H_PULSE1_CONTROL); | |
1508 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); | |
1509 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); | |
1510 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); | |
1511 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); | |
1512 | DUMP_REG(DC_DISP_H_PULSE2_CONTROL); | |
1513 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); | |
1514 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); | |
1515 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); | |
1516 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); | |
1517 | DUMP_REG(DC_DISP_V_PULSE0_CONTROL); | |
1518 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); | |
1519 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); | |
1520 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); | |
1521 | DUMP_REG(DC_DISP_V_PULSE1_CONTROL); | |
1522 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); | |
1523 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); | |
1524 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); | |
1525 | DUMP_REG(DC_DISP_V_PULSE2_CONTROL); | |
1526 | DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); | |
1527 | DUMP_REG(DC_DISP_V_PULSE3_CONTROL); | |
1528 | DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); | |
1529 | DUMP_REG(DC_DISP_M0_CONTROL); | |
1530 | DUMP_REG(DC_DISP_M1_CONTROL); | |
1531 | DUMP_REG(DC_DISP_DI_CONTROL); | |
1532 | DUMP_REG(DC_DISP_PP_CONTROL); | |
1533 | DUMP_REG(DC_DISP_PP_SELECT_A); | |
1534 | DUMP_REG(DC_DISP_PP_SELECT_B); | |
1535 | DUMP_REG(DC_DISP_PP_SELECT_C); | |
1536 | DUMP_REG(DC_DISP_PP_SELECT_D); | |
1537 | DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); | |
1538 | DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); | |
1539 | DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); | |
1540 | DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); | |
1541 | DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); | |
1542 | DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); | |
1543 | DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); | |
1544 | DUMP_REG(DC_DISP_BORDER_COLOR); | |
1545 | DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); | |
1546 | DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); | |
1547 | DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); | |
1548 | DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); | |
1549 | DUMP_REG(DC_DISP_CURSOR_FOREGROUND); | |
1550 | DUMP_REG(DC_DISP_CURSOR_BACKGROUND); | |
1551 | DUMP_REG(DC_DISP_CURSOR_START_ADDR); | |
1552 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); | |
1553 | DUMP_REG(DC_DISP_CURSOR_POSITION); | |
1554 | DUMP_REG(DC_DISP_CURSOR_POSITION_NS); | |
1555 | DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); | |
1556 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); | |
1557 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); | |
1558 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); | |
1559 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); | |
1560 | DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); | |
1561 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); | |
1562 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); | |
1563 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); | |
1564 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); | |
1565 | DUMP_REG(DC_DISP_DAC_CRT_CTRL); | |
1566 | DUMP_REG(DC_DISP_DISP_MISC_CONTROL); | |
1567 | DUMP_REG(DC_DISP_SD_CONTROL); | |
1568 | DUMP_REG(DC_DISP_SD_CSC_COEFF); | |
1569 | DUMP_REG(DC_DISP_SD_LUT(0)); | |
1570 | DUMP_REG(DC_DISP_SD_LUT(1)); | |
1571 | DUMP_REG(DC_DISP_SD_LUT(2)); | |
1572 | DUMP_REG(DC_DISP_SD_LUT(3)); | |
1573 | DUMP_REG(DC_DISP_SD_LUT(4)); | |
1574 | DUMP_REG(DC_DISP_SD_LUT(5)); | |
1575 | DUMP_REG(DC_DISP_SD_LUT(6)); | |
1576 | DUMP_REG(DC_DISP_SD_LUT(7)); | |
1577 | DUMP_REG(DC_DISP_SD_LUT(8)); | |
1578 | DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); | |
1579 | DUMP_REG(DC_DISP_DC_PIXEL_COUNT); | |
1580 | DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); | |
1581 | DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); | |
1582 | DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); | |
1583 | DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); | |
1584 | DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); | |
1585 | DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); | |
1586 | DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); | |
1587 | DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); | |
1588 | DUMP_REG(DC_DISP_SD_BL_TF(0)); | |
1589 | DUMP_REG(DC_DISP_SD_BL_TF(1)); | |
1590 | DUMP_REG(DC_DISP_SD_BL_TF(2)); | |
1591 | DUMP_REG(DC_DISP_SD_BL_TF(3)); | |
1592 | DUMP_REG(DC_DISP_SD_BL_CONTROL); | |
1593 | DUMP_REG(DC_DISP_SD_HW_K_VALUES); | |
1594 | DUMP_REG(DC_DISP_SD_MAN_K_VALUES); | |
e687651b TR |
1595 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI); |
1596 | DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL); | |
d8f4a9ed TR |
1597 | DUMP_REG(DC_WIN_WIN_OPTIONS); |
1598 | DUMP_REG(DC_WIN_BYTE_SWAP); | |
1599 | DUMP_REG(DC_WIN_BUFFER_CONTROL); | |
1600 | DUMP_REG(DC_WIN_COLOR_DEPTH); | |
1601 | DUMP_REG(DC_WIN_POSITION); | |
1602 | DUMP_REG(DC_WIN_SIZE); | |
1603 | DUMP_REG(DC_WIN_PRESCALED_SIZE); | |
1604 | DUMP_REG(DC_WIN_H_INITIAL_DDA); | |
1605 | DUMP_REG(DC_WIN_V_INITIAL_DDA); | |
1606 | DUMP_REG(DC_WIN_DDA_INC); | |
1607 | DUMP_REG(DC_WIN_LINE_STRIDE); | |
1608 | DUMP_REG(DC_WIN_BUF_STRIDE); | |
1609 | DUMP_REG(DC_WIN_UV_BUF_STRIDE); | |
1610 | DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); | |
1611 | DUMP_REG(DC_WIN_DV_CONTROL); | |
1612 | DUMP_REG(DC_WIN_BLEND_NOKEY); | |
1613 | DUMP_REG(DC_WIN_BLEND_1WIN); | |
1614 | DUMP_REG(DC_WIN_BLEND_2WIN_X); | |
1615 | DUMP_REG(DC_WIN_BLEND_2WIN_Y); | |
f34bc787 | 1616 | DUMP_REG(DC_WIN_BLEND_3WIN_XY); |
d8f4a9ed TR |
1617 | DUMP_REG(DC_WIN_HP_FETCH_CONTROL); |
1618 | DUMP_REG(DC_WINBUF_START_ADDR); | |
1619 | DUMP_REG(DC_WINBUF_START_ADDR_NS); | |
1620 | DUMP_REG(DC_WINBUF_START_ADDR_U); | |
1621 | DUMP_REG(DC_WINBUF_START_ADDR_U_NS); | |
1622 | DUMP_REG(DC_WINBUF_START_ADDR_V); | |
1623 | DUMP_REG(DC_WINBUF_START_ADDR_V_NS); | |
1624 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); | |
1625 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); | |
1626 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); | |
1627 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); | |
1628 | DUMP_REG(DC_WINBUF_UFLOW_STATUS); | |
1629 | DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); | |
1630 | DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); | |
1631 | DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); | |
1632 | ||
1633 | #undef DUMP_REG | |
1634 | ||
003fc848 | 1635 | unlock: |
99612b27 | 1636 | drm_modeset_unlock(&dc->base.mutex); |
003fc848 | 1637 | return err; |
d8f4a9ed TR |
1638 | } |
1639 | ||
6ca1f62f TR |
1640 | static int tegra_dc_show_crc(struct seq_file *s, void *data) |
1641 | { | |
1642 | struct drm_info_node *node = s->private; | |
1643 | struct tegra_dc *dc = node->info_ent->data; | |
003fc848 | 1644 | int err = 0; |
6ca1f62f TR |
1645 | u32 value; |
1646 | ||
99612b27 | 1647 | drm_modeset_lock(&dc->base.mutex, NULL); |
003fc848 TR |
1648 | |
1649 | if (!dc->base.state->active) { | |
1650 | err = -EBUSY; | |
1651 | goto unlock; | |
1652 | } | |
1653 | ||
6ca1f62f TR |
1654 | value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; |
1655 | tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); | |
1656 | tegra_dc_commit(dc); | |
1657 | ||
1658 | drm_crtc_wait_one_vblank(&dc->base); | |
1659 | drm_crtc_wait_one_vblank(&dc->base); | |
1660 | ||
1661 | value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); | |
1662 | seq_printf(s, "%08x\n", value); | |
1663 | ||
1664 | tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); | |
1665 | ||
003fc848 | 1666 | unlock: |
99612b27 | 1667 | drm_modeset_unlock(&dc->base.mutex); |
003fc848 | 1668 | return err; |
6ca1f62f TR |
1669 | } |
1670 | ||
791ddb1e TR |
1671 | static int tegra_dc_show_stats(struct seq_file *s, void *data) |
1672 | { | |
1673 | struct drm_info_node *node = s->private; | |
1674 | struct tegra_dc *dc = node->info_ent->data; | |
1675 | ||
1676 | seq_printf(s, "frames: %lu\n", dc->stats.frames); | |
1677 | seq_printf(s, "vblank: %lu\n", dc->stats.vblank); | |
1678 | seq_printf(s, "underflow: %lu\n", dc->stats.underflow); | |
1679 | seq_printf(s, "overflow: %lu\n", dc->stats.overflow); | |
1680 | ||
d8f4a9ed TR |
1681 | return 0; |
1682 | } | |
1683 | ||
1684 | static struct drm_info_list debugfs_files[] = { | |
1685 | { "regs", tegra_dc_show_regs, 0, NULL }, | |
6ca1f62f | 1686 | { "crc", tegra_dc_show_crc, 0, NULL }, |
791ddb1e | 1687 | { "stats", tegra_dc_show_stats, 0, NULL }, |
d8f4a9ed TR |
1688 | }; |
1689 | ||
1690 | static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) | |
1691 | { | |
1692 | unsigned int i; | |
1693 | char *name; | |
1694 | int err; | |
1695 | ||
1696 | name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); | |
1697 | dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); | |
1698 | kfree(name); | |
1699 | ||
1700 | if (!dc->debugfs) | |
1701 | return -ENOMEM; | |
1702 | ||
1703 | dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), | |
1704 | GFP_KERNEL); | |
1705 | if (!dc->debugfs_files) { | |
1706 | err = -ENOMEM; | |
1707 | goto remove; | |
1708 | } | |
1709 | ||
1710 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
1711 | dc->debugfs_files[i].data = dc; | |
1712 | ||
1713 | err = drm_debugfs_create_files(dc->debugfs_files, | |
1714 | ARRAY_SIZE(debugfs_files), | |
1715 | dc->debugfs, minor); | |
1716 | if (err < 0) | |
1717 | goto free; | |
1718 | ||
1719 | dc->minor = minor; | |
1720 | ||
1721 | return 0; | |
1722 | ||
1723 | free: | |
1724 | kfree(dc->debugfs_files); | |
1725 | dc->debugfs_files = NULL; | |
1726 | remove: | |
1727 | debugfs_remove(dc->debugfs); | |
1728 | dc->debugfs = NULL; | |
1729 | ||
1730 | return err; | |
1731 | } | |
1732 | ||
1733 | static int tegra_dc_debugfs_exit(struct tegra_dc *dc) | |
1734 | { | |
1735 | drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), | |
1736 | dc->minor); | |
1737 | dc->minor = NULL; | |
1738 | ||
1739 | kfree(dc->debugfs_files); | |
1740 | dc->debugfs_files = NULL; | |
1741 | ||
1742 | debugfs_remove(dc->debugfs); | |
1743 | dc->debugfs = NULL; | |
1744 | ||
1745 | return 0; | |
1746 | } | |
1747 | ||
53fa7f72 | 1748 | static int tegra_dc_init(struct host1x_client *client) |
d8f4a9ed | 1749 | { |
9910f5c4 | 1750 | struct drm_device *drm = dev_get_drvdata(client->parent); |
2bcdcbfa | 1751 | unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; |
776dc384 | 1752 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d1f3e1e0 | 1753 | struct tegra_drm *tegra = drm->dev_private; |
c7679306 TR |
1754 | struct drm_plane *primary = NULL; |
1755 | struct drm_plane *cursor = NULL; | |
d8f4a9ed TR |
1756 | int err; |
1757 | ||
2bcdcbfa TR |
1758 | dc->syncpt = host1x_syncpt_request(dc->dev, flags); |
1759 | if (!dc->syncpt) | |
1760 | dev_warn(dc->dev, "failed to allocate syncpoint\n"); | |
1761 | ||
df06b759 TR |
1762 | if (tegra->domain) { |
1763 | err = iommu_attach_device(tegra->domain, dc->dev); | |
1764 | if (err < 0) { | |
1765 | dev_err(dc->dev, "failed to attach to domain: %d\n", | |
1766 | err); | |
1767 | return err; | |
1768 | } | |
1769 | ||
1770 | dc->domain = tegra->domain; | |
1771 | } | |
1772 | ||
c7679306 TR |
1773 | primary = tegra_dc_primary_plane_create(drm, dc); |
1774 | if (IS_ERR(primary)) { | |
1775 | err = PTR_ERR(primary); | |
1776 | goto cleanup; | |
1777 | } | |
1778 | ||
1779 | if (dc->soc->supports_cursor) { | |
1780 | cursor = tegra_dc_cursor_plane_create(drm, dc); | |
1781 | if (IS_ERR(cursor)) { | |
1782 | err = PTR_ERR(cursor); | |
1783 | goto cleanup; | |
1784 | } | |
1785 | } | |
1786 | ||
1787 | err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, | |
f9882876 | 1788 | &tegra_crtc_funcs, NULL); |
c7679306 TR |
1789 | if (err < 0) |
1790 | goto cleanup; | |
1791 | ||
d8f4a9ed TR |
1792 | drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); |
1793 | ||
d1f3e1e0 TR |
1794 | /* |
1795 | * Keep track of the minimum pitch alignment across all display | |
1796 | * controllers. | |
1797 | */ | |
1798 | if (dc->soc->pitch_align > tegra->pitch_align) | |
1799 | tegra->pitch_align = dc->soc->pitch_align; | |
1800 | ||
9910f5c4 | 1801 | err = tegra_dc_rgb_init(drm, dc); |
d8f4a9ed TR |
1802 | if (err < 0 && err != -ENODEV) { |
1803 | dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); | |
c7679306 | 1804 | goto cleanup; |
d8f4a9ed TR |
1805 | } |
1806 | ||
9910f5c4 | 1807 | err = tegra_dc_add_planes(drm, dc); |
f34bc787 | 1808 | if (err < 0) |
c7679306 | 1809 | goto cleanup; |
f34bc787 | 1810 | |
d8f4a9ed | 1811 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
9910f5c4 | 1812 | err = tegra_dc_debugfs_init(dc, drm->primary); |
d8f4a9ed TR |
1813 | if (err < 0) |
1814 | dev_err(dc->dev, "debugfs setup failed: %d\n", err); | |
1815 | } | |
1816 | ||
6e5ff998 | 1817 | err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, |
d8f4a9ed TR |
1818 | dev_name(dc->dev), dc); |
1819 | if (err < 0) { | |
1820 | dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, | |
1821 | err); | |
c7679306 | 1822 | goto cleanup; |
d8f4a9ed TR |
1823 | } |
1824 | ||
1825 | return 0; | |
c7679306 TR |
1826 | |
1827 | cleanup: | |
1828 | if (cursor) | |
1829 | drm_plane_cleanup(cursor); | |
1830 | ||
1831 | if (primary) | |
1832 | drm_plane_cleanup(primary); | |
1833 | ||
1834 | if (tegra->domain) { | |
1835 | iommu_detach_device(tegra->domain, dc->dev); | |
1836 | dc->domain = NULL; | |
1837 | } | |
1838 | ||
1839 | return err; | |
d8f4a9ed TR |
1840 | } |
1841 | ||
53fa7f72 | 1842 | static int tegra_dc_exit(struct host1x_client *client) |
d8f4a9ed | 1843 | { |
776dc384 | 1844 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d8f4a9ed TR |
1845 | int err; |
1846 | ||
1847 | devm_free_irq(dc->dev, dc->irq, dc); | |
1848 | ||
1849 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1850 | err = tegra_dc_debugfs_exit(dc); | |
1851 | if (err < 0) | |
1852 | dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); | |
1853 | } | |
1854 | ||
1855 | err = tegra_dc_rgb_exit(dc); | |
1856 | if (err) { | |
1857 | dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); | |
1858 | return err; | |
1859 | } | |
1860 | ||
df06b759 TR |
1861 | if (dc->domain) { |
1862 | iommu_detach_device(dc->domain, dc->dev); | |
1863 | dc->domain = NULL; | |
1864 | } | |
1865 | ||
2bcdcbfa TR |
1866 | host1x_syncpt_free(dc->syncpt); |
1867 | ||
d8f4a9ed TR |
1868 | return 0; |
1869 | } | |
1870 | ||
1871 | static const struct host1x_client_ops dc_client_ops = { | |
53fa7f72 TR |
1872 | .init = tegra_dc_init, |
1873 | .exit = tegra_dc_exit, | |
d8f4a9ed TR |
1874 | }; |
1875 | ||
8620fc62 | 1876 | static const struct tegra_dc_soc_info tegra20_dc_soc_info = { |
42d0659b | 1877 | .supports_border_color = true, |
8620fc62 | 1878 | .supports_interlacing = false, |
e687651b | 1879 | .supports_cursor = false, |
c134f019 | 1880 | .supports_block_linear = false, |
d1f3e1e0 | 1881 | .pitch_align = 8, |
9c012700 | 1882 | .has_powergate = false, |
6ac1571b | 1883 | .broken_reset = true, |
8620fc62 TR |
1884 | }; |
1885 | ||
1886 | static const struct tegra_dc_soc_info tegra30_dc_soc_info = { | |
42d0659b | 1887 | .supports_border_color = true, |
8620fc62 | 1888 | .supports_interlacing = false, |
e687651b | 1889 | .supports_cursor = false, |
c134f019 | 1890 | .supports_block_linear = false, |
d1f3e1e0 | 1891 | .pitch_align = 8, |
9c012700 | 1892 | .has_powergate = false, |
6ac1571b | 1893 | .broken_reset = false, |
d1f3e1e0 TR |
1894 | }; |
1895 | ||
1896 | static const struct tegra_dc_soc_info tegra114_dc_soc_info = { | |
42d0659b | 1897 | .supports_border_color = true, |
d1f3e1e0 TR |
1898 | .supports_interlacing = false, |
1899 | .supports_cursor = false, | |
1900 | .supports_block_linear = false, | |
1901 | .pitch_align = 64, | |
9c012700 | 1902 | .has_powergate = true, |
6ac1571b | 1903 | .broken_reset = false, |
8620fc62 TR |
1904 | }; |
1905 | ||
1906 | static const struct tegra_dc_soc_info tegra124_dc_soc_info = { | |
42d0659b | 1907 | .supports_border_color = false, |
8620fc62 | 1908 | .supports_interlacing = true, |
e687651b | 1909 | .supports_cursor = true, |
c134f019 | 1910 | .supports_block_linear = true, |
d1f3e1e0 | 1911 | .pitch_align = 64, |
9c012700 | 1912 | .has_powergate = true, |
6ac1571b | 1913 | .broken_reset = false, |
8620fc62 TR |
1914 | }; |
1915 | ||
5b4f516f TR |
1916 | static const struct tegra_dc_soc_info tegra210_dc_soc_info = { |
1917 | .supports_border_color = false, | |
1918 | .supports_interlacing = true, | |
1919 | .supports_cursor = true, | |
1920 | .supports_block_linear = true, | |
1921 | .pitch_align = 64, | |
1922 | .has_powergate = true, | |
6ac1571b | 1923 | .broken_reset = false, |
5b4f516f TR |
1924 | }; |
1925 | ||
8620fc62 TR |
1926 | static const struct of_device_id tegra_dc_of_match[] = { |
1927 | { | |
5b4f516f TR |
1928 | .compatible = "nvidia,tegra210-dc", |
1929 | .data = &tegra210_dc_soc_info, | |
1930 | }, { | |
8620fc62 TR |
1931 | .compatible = "nvidia,tegra124-dc", |
1932 | .data = &tegra124_dc_soc_info, | |
9c012700 TR |
1933 | }, { |
1934 | .compatible = "nvidia,tegra114-dc", | |
1935 | .data = &tegra114_dc_soc_info, | |
8620fc62 TR |
1936 | }, { |
1937 | .compatible = "nvidia,tegra30-dc", | |
1938 | .data = &tegra30_dc_soc_info, | |
1939 | }, { | |
1940 | .compatible = "nvidia,tegra20-dc", | |
1941 | .data = &tegra20_dc_soc_info, | |
1942 | }, { | |
1943 | /* sentinel */ | |
1944 | } | |
1945 | }; | |
ef70728c | 1946 | MODULE_DEVICE_TABLE(of, tegra_dc_of_match); |
8620fc62 | 1947 | |
13411ddd TR |
1948 | static int tegra_dc_parse_dt(struct tegra_dc *dc) |
1949 | { | |
1950 | struct device_node *np; | |
1951 | u32 value = 0; | |
1952 | int err; | |
1953 | ||
1954 | err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); | |
1955 | if (err < 0) { | |
1956 | dev_err(dc->dev, "missing \"nvidia,head\" property\n"); | |
1957 | ||
1958 | /* | |
1959 | * If the nvidia,head property isn't present, try to find the | |
1960 | * correct head number by looking up the position of this | |
1961 | * display controller's node within the device tree. Assuming | |
1962 | * that the nodes are ordered properly in the DTS file and | |
1963 | * that the translation into a flattened device tree blob | |
1964 | * preserves that ordering this will actually yield the right | |
1965 | * head number. | |
1966 | * | |
1967 | * If those assumptions don't hold, this will still work for | |
1968 | * cases where only a single display controller is used. | |
1969 | */ | |
1970 | for_each_matching_node(np, tegra_dc_of_match) { | |
cf6b1744 JL |
1971 | if (np == dc->dev->of_node) { |
1972 | of_node_put(np); | |
13411ddd | 1973 | break; |
cf6b1744 | 1974 | } |
13411ddd TR |
1975 | |
1976 | value++; | |
1977 | } | |
1978 | } | |
1979 | ||
1980 | dc->pipe = value; | |
1981 | ||
1982 | return 0; | |
1983 | } | |
1984 | ||
d8f4a9ed TR |
1985 | static int tegra_dc_probe(struct platform_device *pdev) |
1986 | { | |
8620fc62 | 1987 | const struct of_device_id *id; |
d8f4a9ed TR |
1988 | struct resource *regs; |
1989 | struct tegra_dc *dc; | |
1990 | int err; | |
1991 | ||
1992 | dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); | |
1993 | if (!dc) | |
1994 | return -ENOMEM; | |
1995 | ||
8620fc62 TR |
1996 | id = of_match_node(tegra_dc_of_match, pdev->dev.of_node); |
1997 | if (!id) | |
1998 | return -ENODEV; | |
1999 | ||
6e5ff998 | 2000 | spin_lock_init(&dc->lock); |
d8f4a9ed TR |
2001 | INIT_LIST_HEAD(&dc->list); |
2002 | dc->dev = &pdev->dev; | |
8620fc62 | 2003 | dc->soc = id->data; |
d8f4a9ed | 2004 | |
13411ddd TR |
2005 | err = tegra_dc_parse_dt(dc); |
2006 | if (err < 0) | |
2007 | return err; | |
2008 | ||
d8f4a9ed TR |
2009 | dc->clk = devm_clk_get(&pdev->dev, NULL); |
2010 | if (IS_ERR(dc->clk)) { | |
2011 | dev_err(&pdev->dev, "failed to get clock\n"); | |
2012 | return PTR_ERR(dc->clk); | |
2013 | } | |
2014 | ||
ca48080a SW |
2015 | dc->rst = devm_reset_control_get(&pdev->dev, "dc"); |
2016 | if (IS_ERR(dc->rst)) { | |
2017 | dev_err(&pdev->dev, "failed to get reset\n"); | |
2018 | return PTR_ERR(dc->rst); | |
2019 | } | |
2020 | ||
6ac1571b DO |
2021 | if (!dc->soc->broken_reset) |
2022 | reset_control_assert(dc->rst); | |
33a8eb8d | 2023 | |
9c012700 TR |
2024 | if (dc->soc->has_powergate) { |
2025 | if (dc->pipe == 0) | |
2026 | dc->powergate = TEGRA_POWERGATE_DIS; | |
2027 | else | |
2028 | dc->powergate = TEGRA_POWERGATE_DISB; | |
2029 | ||
33a8eb8d | 2030 | tegra_powergate_power_off(dc->powergate); |
9c012700 | 2031 | } |
d8f4a9ed TR |
2032 | |
2033 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d4ed6025 TR |
2034 | dc->regs = devm_ioremap_resource(&pdev->dev, regs); |
2035 | if (IS_ERR(dc->regs)) | |
2036 | return PTR_ERR(dc->regs); | |
d8f4a9ed TR |
2037 | |
2038 | dc->irq = platform_get_irq(pdev, 0); | |
2039 | if (dc->irq < 0) { | |
2040 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
2041 | return -ENXIO; | |
2042 | } | |
2043 | ||
d8f4a9ed TR |
2044 | err = tegra_dc_rgb_probe(dc); |
2045 | if (err < 0 && err != -ENODEV) { | |
2046 | dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); | |
2047 | return err; | |
2048 | } | |
2049 | ||
33a8eb8d TR |
2050 | platform_set_drvdata(pdev, dc); |
2051 | pm_runtime_enable(&pdev->dev); | |
2052 | ||
2053 | INIT_LIST_HEAD(&dc->client.list); | |
2054 | dc->client.ops = &dc_client_ops; | |
2055 | dc->client.dev = &pdev->dev; | |
2056 | ||
776dc384 | 2057 | err = host1x_client_register(&dc->client); |
d8f4a9ed TR |
2058 | if (err < 0) { |
2059 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
2060 | err); | |
2061 | return err; | |
2062 | } | |
2063 | ||
d8f4a9ed TR |
2064 | return 0; |
2065 | } | |
2066 | ||
2067 | static int tegra_dc_remove(struct platform_device *pdev) | |
2068 | { | |
d8f4a9ed TR |
2069 | struct tegra_dc *dc = platform_get_drvdata(pdev); |
2070 | int err; | |
2071 | ||
776dc384 | 2072 | err = host1x_client_unregister(&dc->client); |
d8f4a9ed TR |
2073 | if (err < 0) { |
2074 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
2075 | err); | |
2076 | return err; | |
2077 | } | |
2078 | ||
59d29c0e TR |
2079 | err = tegra_dc_rgb_remove(dc); |
2080 | if (err < 0) { | |
2081 | dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); | |
2082 | return err; | |
2083 | } | |
2084 | ||
33a8eb8d TR |
2085 | pm_runtime_disable(&pdev->dev); |
2086 | ||
2087 | return 0; | |
2088 | } | |
2089 | ||
2090 | #ifdef CONFIG_PM | |
2091 | static int tegra_dc_suspend(struct device *dev) | |
2092 | { | |
2093 | struct tegra_dc *dc = dev_get_drvdata(dev); | |
2094 | int err; | |
2095 | ||
6ac1571b DO |
2096 | if (!dc->soc->broken_reset) { |
2097 | err = reset_control_assert(dc->rst); | |
2098 | if (err < 0) { | |
2099 | dev_err(dev, "failed to assert reset: %d\n", err); | |
2100 | return err; | |
2101 | } | |
33a8eb8d | 2102 | } |
9c012700 TR |
2103 | |
2104 | if (dc->soc->has_powergate) | |
2105 | tegra_powergate_power_off(dc->powergate); | |
2106 | ||
d8f4a9ed TR |
2107 | clk_disable_unprepare(dc->clk); |
2108 | ||
2109 | return 0; | |
2110 | } | |
2111 | ||
33a8eb8d TR |
2112 | static int tegra_dc_resume(struct device *dev) |
2113 | { | |
2114 | struct tegra_dc *dc = dev_get_drvdata(dev); | |
2115 | int err; | |
2116 | ||
2117 | if (dc->soc->has_powergate) { | |
2118 | err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, | |
2119 | dc->rst); | |
2120 | if (err < 0) { | |
2121 | dev_err(dev, "failed to power partition: %d\n", err); | |
2122 | return err; | |
2123 | } | |
2124 | } else { | |
2125 | err = clk_prepare_enable(dc->clk); | |
2126 | if (err < 0) { | |
2127 | dev_err(dev, "failed to enable clock: %d\n", err); | |
2128 | return err; | |
2129 | } | |
2130 | ||
6ac1571b DO |
2131 | if (!dc->soc->broken_reset) { |
2132 | err = reset_control_deassert(dc->rst); | |
2133 | if (err < 0) { | |
2134 | dev_err(dev, | |
2135 | "failed to deassert reset: %d\n", err); | |
2136 | return err; | |
2137 | } | |
33a8eb8d TR |
2138 | } |
2139 | } | |
2140 | ||
2141 | return 0; | |
2142 | } | |
2143 | #endif | |
2144 | ||
2145 | static const struct dev_pm_ops tegra_dc_pm_ops = { | |
2146 | SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL) | |
2147 | }; | |
2148 | ||
d8f4a9ed TR |
2149 | struct platform_driver tegra_dc_driver = { |
2150 | .driver = { | |
2151 | .name = "tegra-dc", | |
d8f4a9ed | 2152 | .of_match_table = tegra_dc_of_match, |
33a8eb8d | 2153 | .pm = &tegra_dc_pm_ops, |
d8f4a9ed TR |
2154 | }, |
2155 | .probe = tegra_dc_probe, | |
2156 | .remove = tegra_dc_remove, | |
2157 | }; |