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d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
9eb9b220 | 11 | #include <linux/debugfs.h> |
df06b759 | 12 | #include <linux/iommu.h> |
ca48080a | 13 | #include <linux/reset.h> |
d8f4a9ed | 14 | |
9c012700 TR |
15 | #include <soc/tegra/pmc.h> |
16 | ||
de2ba664 AM |
17 | #include "dc.h" |
18 | #include "drm.h" | |
19 | #include "gem.h" | |
d8f4a9ed | 20 | |
3cb9ae4f DV |
21 | #include <drm/drm_plane_helper.h> |
22 | ||
8620fc62 TR |
23 | struct tegra_dc_soc_info { |
24 | bool supports_interlacing; | |
e687651b | 25 | bool supports_cursor; |
c134f019 | 26 | bool supports_block_linear; |
d1f3e1e0 | 27 | unsigned int pitch_align; |
9c012700 | 28 | bool has_powergate; |
8620fc62 TR |
29 | }; |
30 | ||
f34bc787 TR |
31 | struct tegra_plane { |
32 | struct drm_plane base; | |
33 | unsigned int index; | |
d8f4a9ed TR |
34 | }; |
35 | ||
f34bc787 TR |
36 | static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) |
37 | { | |
38 | return container_of(plane, struct tegra_plane, base); | |
39 | } | |
40 | ||
205d48ed TR |
41 | static void tegra_dc_window_commit(struct tegra_dc *dc, unsigned int index) |
42 | { | |
43 | u32 value = WIN_A_ACT_REQ << index; | |
44 | ||
45 | tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL); | |
46 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); | |
47 | } | |
48 | ||
49 | static void tegra_dc_cursor_commit(struct tegra_dc *dc) | |
50 | { | |
51 | tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
52 | tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL); | |
53 | } | |
54 | ||
55 | static void tegra_dc_commit(struct tegra_dc *dc) | |
56 | { | |
57 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
58 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); | |
59 | } | |
60 | ||
10288eea TR |
61 | static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap) |
62 | { | |
63 | /* assume no swapping of fetched data */ | |
64 | if (swap) | |
65 | *swap = BYTE_SWAP_NOSWAP; | |
66 | ||
67 | switch (format) { | |
68 | case DRM_FORMAT_XBGR8888: | |
69 | return WIN_COLOR_DEPTH_R8G8B8A8; | |
70 | ||
71 | case DRM_FORMAT_XRGB8888: | |
72 | return WIN_COLOR_DEPTH_B8G8R8A8; | |
73 | ||
74 | case DRM_FORMAT_RGB565: | |
75 | return WIN_COLOR_DEPTH_B5G6R5; | |
76 | ||
77 | case DRM_FORMAT_UYVY: | |
78 | return WIN_COLOR_DEPTH_YCbCr422; | |
79 | ||
80 | case DRM_FORMAT_YUYV: | |
81 | if (swap) | |
82 | *swap = BYTE_SWAP_SWAP2; | |
83 | ||
84 | return WIN_COLOR_DEPTH_YCbCr422; | |
85 | ||
86 | case DRM_FORMAT_YUV420: | |
87 | return WIN_COLOR_DEPTH_YCbCr420P; | |
88 | ||
89 | case DRM_FORMAT_YUV422: | |
90 | return WIN_COLOR_DEPTH_YCbCr422P; | |
91 | ||
92 | default: | |
93 | break; | |
94 | } | |
95 | ||
96 | WARN(1, "unsupported pixel format %u, using default\n", format); | |
97 | return WIN_COLOR_DEPTH_B8G8R8A8; | |
98 | } | |
99 | ||
100 | static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) | |
101 | { | |
102 | switch (format) { | |
103 | case WIN_COLOR_DEPTH_YCbCr422: | |
104 | case WIN_COLOR_DEPTH_YUV422: | |
105 | if (planar) | |
106 | *planar = false; | |
107 | ||
108 | return true; | |
109 | ||
110 | case WIN_COLOR_DEPTH_YCbCr420P: | |
111 | case WIN_COLOR_DEPTH_YUV420P: | |
112 | case WIN_COLOR_DEPTH_YCbCr422P: | |
113 | case WIN_COLOR_DEPTH_YUV422P: | |
114 | case WIN_COLOR_DEPTH_YCbCr422R: | |
115 | case WIN_COLOR_DEPTH_YUV422R: | |
116 | case WIN_COLOR_DEPTH_YCbCr422RA: | |
117 | case WIN_COLOR_DEPTH_YUV422RA: | |
118 | if (planar) | |
119 | *planar = true; | |
120 | ||
121 | return true; | |
122 | } | |
123 | ||
124 | return false; | |
125 | } | |
126 | ||
127 | static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, | |
128 | unsigned int bpp) | |
129 | { | |
130 | fixed20_12 outf = dfixed_init(out); | |
131 | fixed20_12 inf = dfixed_init(in); | |
132 | u32 dda_inc; | |
133 | int max; | |
134 | ||
135 | if (v) | |
136 | max = 15; | |
137 | else { | |
138 | switch (bpp) { | |
139 | case 2: | |
140 | max = 8; | |
141 | break; | |
142 | ||
143 | default: | |
144 | WARN_ON_ONCE(1); | |
145 | /* fallthrough */ | |
146 | case 4: | |
147 | max = 4; | |
148 | break; | |
149 | } | |
150 | } | |
151 | ||
152 | outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); | |
153 | inf.full -= dfixed_const(1); | |
154 | ||
155 | dda_inc = dfixed_div(inf, outf); | |
156 | dda_inc = min_t(u32, dda_inc, dfixed_const(max)); | |
157 | ||
158 | return dda_inc; | |
159 | } | |
160 | ||
161 | static inline u32 compute_initial_dda(unsigned int in) | |
162 | { | |
163 | fixed20_12 inf = dfixed_init(in); | |
164 | return dfixed_frac(inf); | |
165 | } | |
166 | ||
167 | static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, | |
168 | const struct tegra_dc_window *window) | |
169 | { | |
170 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; | |
171 | unsigned long value; | |
172 | bool yuv, planar; | |
173 | ||
174 | /* | |
175 | * For YUV planar modes, the number of bytes per pixel takes into | |
176 | * account only the luma component and therefore is 1. | |
177 | */ | |
178 | yuv = tegra_dc_format_is_yuv(window->format, &planar); | |
179 | if (!yuv) | |
180 | bpp = window->bits_per_pixel / 8; | |
181 | else | |
182 | bpp = planar ? 1 : 2; | |
183 | ||
184 | value = WINDOW_A_SELECT << index; | |
185 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
186 | ||
187 | tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); | |
188 | tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); | |
189 | ||
190 | value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); | |
191 | tegra_dc_writel(dc, value, DC_WIN_POSITION); | |
192 | ||
193 | value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); | |
194 | tegra_dc_writel(dc, value, DC_WIN_SIZE); | |
195 | ||
196 | h_offset = window->src.x * bpp; | |
197 | v_offset = window->src.y; | |
198 | h_size = window->src.w * bpp; | |
199 | v_size = window->src.h; | |
200 | ||
201 | value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); | |
202 | tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); | |
203 | ||
204 | /* | |
205 | * For DDA computations the number of bytes per pixel for YUV planar | |
206 | * modes needs to take into account all Y, U and V components. | |
207 | */ | |
208 | if (yuv && planar) | |
209 | bpp = 2; | |
210 | ||
211 | h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); | |
212 | v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); | |
213 | ||
214 | value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); | |
215 | tegra_dc_writel(dc, value, DC_WIN_DDA_INC); | |
216 | ||
217 | h_dda = compute_initial_dda(window->src.x); | |
218 | v_dda = compute_initial_dda(window->src.y); | |
219 | ||
220 | tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); | |
221 | tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); | |
222 | ||
223 | tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); | |
224 | tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); | |
225 | ||
226 | tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); | |
227 | ||
228 | if (yuv && planar) { | |
229 | tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); | |
230 | tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); | |
231 | value = window->stride[1] << 16 | window->stride[0]; | |
232 | tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); | |
233 | } else { | |
234 | tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); | |
235 | } | |
236 | ||
237 | if (window->bottom_up) | |
238 | v_offset += window->src.h - 1; | |
239 | ||
240 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
241 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
242 | ||
c134f019 TR |
243 | if (dc->soc->supports_block_linear) { |
244 | unsigned long height = window->tiling.value; | |
245 | ||
246 | switch (window->tiling.mode) { | |
247 | case TEGRA_BO_TILING_MODE_PITCH: | |
248 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
249 | break; | |
250 | ||
251 | case TEGRA_BO_TILING_MODE_TILED: | |
252 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
253 | break; | |
254 | ||
255 | case TEGRA_BO_TILING_MODE_BLOCK: | |
256 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
257 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
258 | break; | |
259 | } | |
260 | ||
261 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
10288eea | 262 | } else { |
c134f019 TR |
263 | switch (window->tiling.mode) { |
264 | case TEGRA_BO_TILING_MODE_PITCH: | |
265 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
266 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
267 | break; | |
10288eea | 268 | |
c134f019 TR |
269 | case TEGRA_BO_TILING_MODE_TILED: |
270 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
271 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
272 | break; | |
273 | ||
274 | case TEGRA_BO_TILING_MODE_BLOCK: | |
275 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
276 | return -EINVAL; | |
277 | } | |
278 | ||
279 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
280 | } | |
10288eea TR |
281 | |
282 | value = WIN_ENABLE; | |
283 | ||
284 | if (yuv) { | |
285 | /* setup default colorspace conversion coefficients */ | |
286 | tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); | |
287 | tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); | |
288 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); | |
289 | tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); | |
290 | tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); | |
291 | tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); | |
292 | tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); | |
293 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); | |
294 | ||
295 | value |= CSC_ENABLE; | |
296 | } else if (window->bits_per_pixel < 24) { | |
297 | value |= COLOR_EXPAND; | |
298 | } | |
299 | ||
300 | if (window->bottom_up) | |
301 | value |= V_DIRECTION; | |
302 | ||
303 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
304 | ||
305 | /* | |
306 | * Disable blending and assume Window A is the bottom-most window, | |
307 | * Window C is the top-most window and Window B is in the middle. | |
308 | */ | |
309 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); | |
310 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); | |
311 | ||
312 | switch (index) { | |
313 | case 0: | |
314 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); | |
315 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
316 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
317 | break; | |
318 | ||
319 | case 1: | |
320 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
321 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
322 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
323 | break; | |
324 | ||
325 | case 2: | |
326 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
327 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); | |
328 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); | |
329 | break; | |
330 | } | |
331 | ||
205d48ed | 332 | tegra_dc_window_commit(dc, index); |
10288eea TR |
333 | |
334 | return 0; | |
335 | } | |
336 | ||
c7679306 TR |
337 | static int tegra_window_plane_disable(struct drm_plane *plane) |
338 | { | |
339 | struct tegra_dc *dc = to_tegra_dc(plane->crtc); | |
340 | struct tegra_plane *p = to_tegra_plane(plane); | |
341 | u32 value; | |
342 | ||
343 | if (!plane->crtc) | |
344 | return 0; | |
345 | ||
346 | value = WINDOW_A_SELECT << p->index; | |
347 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
348 | ||
349 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
350 | value &= ~WIN_ENABLE; | |
351 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
352 | ||
353 | tegra_dc_window_commit(dc, p->index); | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static void tegra_plane_destroy(struct drm_plane *plane) | |
359 | { | |
360 | struct tegra_plane *p = to_tegra_plane(plane); | |
361 | ||
362 | drm_plane_cleanup(plane); | |
363 | kfree(p); | |
364 | } | |
365 | ||
366 | static const u32 tegra_primary_plane_formats[] = { | |
367 | DRM_FORMAT_XBGR8888, | |
368 | DRM_FORMAT_XRGB8888, | |
369 | DRM_FORMAT_RGB565, | |
370 | }; | |
371 | ||
372 | static int tegra_primary_plane_update(struct drm_plane *plane, | |
373 | struct drm_crtc *crtc, | |
374 | struct drm_framebuffer *fb, int crtc_x, | |
375 | int crtc_y, unsigned int crtc_w, | |
376 | unsigned int crtc_h, uint32_t src_x, | |
377 | uint32_t src_y, uint32_t src_w, | |
378 | uint32_t src_h) | |
379 | { | |
380 | struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); | |
381 | struct tegra_plane *p = to_tegra_plane(plane); | |
382 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
383 | struct tegra_dc_window window; | |
384 | int err; | |
385 | ||
386 | memset(&window, 0, sizeof(window)); | |
387 | window.src.x = src_x >> 16; | |
388 | window.src.y = src_y >> 16; | |
389 | window.src.w = src_w >> 16; | |
390 | window.src.h = src_h >> 16; | |
391 | window.dst.x = crtc_x; | |
392 | window.dst.y = crtc_y; | |
393 | window.dst.w = crtc_w; | |
394 | window.dst.h = crtc_h; | |
395 | window.format = tegra_dc_format(fb->pixel_format, &window.swap); | |
396 | window.bits_per_pixel = fb->bits_per_pixel; | |
397 | window.bottom_up = tegra_fb_is_bottom_up(fb); | |
398 | ||
399 | err = tegra_fb_get_tiling(fb, &window.tiling); | |
400 | if (err < 0) | |
401 | return err; | |
402 | ||
403 | window.base[0] = bo->paddr + fb->offsets[0]; | |
404 | window.stride[0] = fb->pitches[0]; | |
405 | ||
406 | err = tegra_dc_setup_window(dc, p->index, &window); | |
407 | if (err < 0) | |
408 | return err; | |
10288eea TR |
409 | |
410 | return 0; | |
411 | } | |
412 | ||
c7679306 TR |
413 | static void tegra_primary_plane_destroy(struct drm_plane *plane) |
414 | { | |
415 | tegra_window_plane_disable(plane); | |
416 | tegra_plane_destroy(plane); | |
417 | } | |
418 | ||
419 | static const struct drm_plane_funcs tegra_primary_plane_funcs = { | |
420 | .update_plane = tegra_primary_plane_update, | |
421 | .disable_plane = tegra_window_plane_disable, | |
422 | .destroy = tegra_primary_plane_destroy, | |
423 | }; | |
424 | ||
425 | static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, | |
426 | struct tegra_dc *dc) | |
427 | { | |
428 | struct tegra_plane *plane; | |
429 | unsigned int num_formats; | |
430 | const u32 *formats; | |
431 | int err; | |
432 | ||
433 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
434 | if (!plane) | |
435 | return ERR_PTR(-ENOMEM); | |
436 | ||
437 | num_formats = ARRAY_SIZE(tegra_primary_plane_formats); | |
438 | formats = tegra_primary_plane_formats; | |
439 | ||
440 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, | |
441 | &tegra_primary_plane_funcs, formats, | |
442 | num_formats, DRM_PLANE_TYPE_PRIMARY); | |
443 | if (err < 0) { | |
444 | kfree(plane); | |
445 | return ERR_PTR(err); | |
446 | } | |
447 | ||
448 | return &plane->base; | |
449 | } | |
450 | ||
451 | static const u32 tegra_cursor_plane_formats[] = { | |
452 | DRM_FORMAT_RGBA8888, | |
453 | }; | |
454 | ||
455 | static int tegra_cursor_plane_update(struct drm_plane *plane, | |
456 | struct drm_crtc *crtc, | |
457 | struct drm_framebuffer *fb, int crtc_x, | |
458 | int crtc_y, unsigned int crtc_w, | |
459 | unsigned int crtc_h, uint32_t src_x, | |
460 | uint32_t src_y, uint32_t src_w, | |
461 | uint32_t src_h) | |
462 | { | |
463 | struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); | |
464 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
465 | u32 value = CURSOR_CLIP_DISPLAY; | |
466 | ||
467 | /* scaling not supported for cursor */ | |
468 | if ((src_w >> 16 != crtc_w) || (src_h >> 16 != crtc_h)) | |
469 | return -EINVAL; | |
470 | ||
471 | /* only square cursors supported */ | |
472 | if (src_w != src_h) | |
473 | return -EINVAL; | |
474 | ||
475 | switch (crtc_w) { | |
476 | case 32: | |
477 | value |= CURSOR_SIZE_32x32; | |
478 | break; | |
479 | ||
480 | case 64: | |
481 | value |= CURSOR_SIZE_64x64; | |
482 | break; | |
483 | ||
484 | case 128: | |
485 | value |= CURSOR_SIZE_128x128; | |
486 | break; | |
487 | ||
488 | case 256: | |
489 | value |= CURSOR_SIZE_256x256; | |
490 | break; | |
491 | ||
492 | default: | |
493 | return -EINVAL; | |
494 | } | |
495 | ||
496 | value |= (bo->paddr >> 10) & 0x3fffff; | |
497 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); | |
498 | ||
499 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
500 | value = (bo->paddr >> 32) & 0x3; | |
501 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); | |
502 | #endif | |
503 | ||
504 | /* enable cursor and set blend mode */ | |
505 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
506 | value |= CURSOR_ENABLE; | |
507 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
508 | ||
509 | value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); | |
510 | value &= ~CURSOR_DST_BLEND_MASK; | |
511 | value &= ~CURSOR_SRC_BLEND_MASK; | |
512 | value |= CURSOR_MODE_NORMAL; | |
513 | value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; | |
514 | value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; | |
515 | value |= CURSOR_ALPHA; | |
516 | tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); | |
517 | ||
518 | /* position the cursor */ | |
519 | value = (crtc_y & 0x3fff) << 16 | (crtc_x & 0x3fff); | |
520 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); | |
521 | ||
522 | /* apply changes */ | |
523 | tegra_dc_cursor_commit(dc); | |
524 | tegra_dc_commit(dc); | |
525 | ||
526 | return 0; | |
527 | } | |
528 | ||
529 | static int tegra_cursor_plane_disable(struct drm_plane *plane) | |
530 | { | |
531 | struct tegra_dc *dc = to_tegra_dc(plane->crtc); | |
532 | u32 value; | |
533 | ||
534 | if (!plane->crtc) | |
535 | return 0; | |
536 | ||
537 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
538 | value &= ~CURSOR_ENABLE; | |
539 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
540 | ||
541 | tegra_dc_cursor_commit(dc); | |
542 | tegra_dc_commit(dc); | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | static const struct drm_plane_funcs tegra_cursor_plane_funcs = { | |
548 | .update_plane = tegra_cursor_plane_update, | |
549 | .disable_plane = tegra_cursor_plane_disable, | |
550 | .destroy = tegra_plane_destroy, | |
551 | }; | |
552 | ||
553 | static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, | |
554 | struct tegra_dc *dc) | |
555 | { | |
556 | struct tegra_plane *plane; | |
557 | unsigned int num_formats; | |
558 | const u32 *formats; | |
559 | int err; | |
560 | ||
561 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
562 | if (!plane) | |
563 | return ERR_PTR(-ENOMEM); | |
564 | ||
565 | num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); | |
566 | formats = tegra_cursor_plane_formats; | |
567 | ||
568 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, | |
569 | &tegra_cursor_plane_funcs, formats, | |
570 | num_formats, DRM_PLANE_TYPE_CURSOR); | |
571 | if (err < 0) { | |
572 | kfree(plane); | |
573 | return ERR_PTR(err); | |
574 | } | |
575 | ||
576 | return &plane->base; | |
577 | } | |
578 | ||
579 | static int tegra_overlay_plane_update(struct drm_plane *plane, | |
580 | struct drm_crtc *crtc, | |
581 | struct drm_framebuffer *fb, int crtc_x, | |
582 | int crtc_y, unsigned int crtc_w, | |
583 | unsigned int crtc_h, uint32_t src_x, | |
584 | uint32_t src_y, uint32_t src_w, | |
585 | uint32_t src_h) | |
f34bc787 TR |
586 | { |
587 | struct tegra_plane *p = to_tegra_plane(plane); | |
588 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
589 | struct tegra_dc_window window; | |
590 | unsigned int i; | |
c134f019 | 591 | int err; |
f34bc787 TR |
592 | |
593 | memset(&window, 0, sizeof(window)); | |
594 | window.src.x = src_x >> 16; | |
595 | window.src.y = src_y >> 16; | |
596 | window.src.w = src_w >> 16; | |
597 | window.src.h = src_h >> 16; | |
598 | window.dst.x = crtc_x; | |
599 | window.dst.y = crtc_y; | |
600 | window.dst.w = crtc_w; | |
601 | window.dst.h = crtc_h; | |
f925390e | 602 | window.format = tegra_dc_format(fb->pixel_format, &window.swap); |
f34bc787 | 603 | window.bits_per_pixel = fb->bits_per_pixel; |
db7fbdfd | 604 | window.bottom_up = tegra_fb_is_bottom_up(fb); |
c134f019 TR |
605 | |
606 | err = tegra_fb_get_tiling(fb, &window.tiling); | |
607 | if (err < 0) | |
608 | return err; | |
f34bc787 TR |
609 | |
610 | for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { | |
de2ba664 | 611 | struct tegra_bo *bo = tegra_fb_get_plane(fb, i); |
f34bc787 | 612 | |
de2ba664 | 613 | window.base[i] = bo->paddr + fb->offsets[i]; |
f34bc787 TR |
614 | |
615 | /* | |
616 | * Tegra doesn't support different strides for U and V planes | |
617 | * so we display a warning if the user tries to display a | |
618 | * framebuffer with such a configuration. | |
619 | */ | |
620 | if (i >= 2) { | |
621 | if (fb->pitches[i] != window.stride[1]) | |
622 | DRM_ERROR("unsupported UV-plane configuration\n"); | |
623 | } else { | |
624 | window.stride[i] = fb->pitches[i]; | |
625 | } | |
626 | } | |
627 | ||
628 | return tegra_dc_setup_window(dc, p->index, &window); | |
629 | } | |
630 | ||
c7679306 | 631 | static void tegra_overlay_plane_destroy(struct drm_plane *plane) |
f34bc787 | 632 | { |
c7679306 TR |
633 | tegra_window_plane_disable(plane); |
634 | tegra_plane_destroy(plane); | |
f34bc787 TR |
635 | } |
636 | ||
c7679306 TR |
637 | static const struct drm_plane_funcs tegra_overlay_plane_funcs = { |
638 | .update_plane = tegra_overlay_plane_update, | |
639 | .disable_plane = tegra_window_plane_disable, | |
640 | .destroy = tegra_overlay_plane_destroy, | |
f34bc787 TR |
641 | }; |
642 | ||
c7679306 | 643 | static const uint32_t tegra_overlay_plane_formats[] = { |
dbe4d9a7 | 644 | DRM_FORMAT_XBGR8888, |
f34bc787 | 645 | DRM_FORMAT_XRGB8888, |
dbe4d9a7 | 646 | DRM_FORMAT_RGB565, |
f34bc787 | 647 | DRM_FORMAT_UYVY, |
f925390e | 648 | DRM_FORMAT_YUYV, |
f34bc787 TR |
649 | DRM_FORMAT_YUV420, |
650 | DRM_FORMAT_YUV422, | |
651 | }; | |
652 | ||
c7679306 TR |
653 | static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, |
654 | struct tegra_dc *dc, | |
655 | unsigned int index) | |
f34bc787 | 656 | { |
c7679306 TR |
657 | struct tegra_plane *plane; |
658 | unsigned int num_formats; | |
659 | const u32 *formats; | |
660 | int err; | |
f34bc787 | 661 | |
c7679306 TR |
662 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
663 | if (!plane) | |
664 | return ERR_PTR(-ENOMEM); | |
f34bc787 | 665 | |
c7679306 | 666 | plane->index = index; |
f34bc787 | 667 | |
c7679306 TR |
668 | num_formats = ARRAY_SIZE(tegra_overlay_plane_formats); |
669 | formats = tegra_overlay_plane_formats; | |
f34bc787 | 670 | |
c7679306 TR |
671 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, |
672 | &tegra_overlay_plane_funcs, formats, | |
673 | num_formats, DRM_PLANE_TYPE_OVERLAY); | |
674 | if (err < 0) { | |
675 | kfree(plane); | |
676 | return ERR_PTR(err); | |
677 | } | |
678 | ||
679 | return &plane->base; | |
680 | } | |
681 | ||
682 | static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) | |
683 | { | |
684 | struct drm_plane *plane; | |
685 | unsigned int i; | |
686 | ||
687 | for (i = 0; i < 2; i++) { | |
688 | plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); | |
689 | if (IS_ERR(plane)) | |
690 | return PTR_ERR(plane); | |
f34bc787 TR |
691 | } |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
23fb4740 TR |
696 | static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, |
697 | struct drm_framebuffer *fb) | |
698 | { | |
de2ba664 | 699 | struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); |
db7fbdfd | 700 | unsigned int h_offset = 0, v_offset = 0; |
c134f019 | 701 | struct tegra_bo_tiling tiling; |
f925390e | 702 | unsigned int format, swap; |
23fb4740 | 703 | unsigned long value; |
c134f019 TR |
704 | int err; |
705 | ||
706 | err = tegra_fb_get_tiling(fb, &tiling); | |
707 | if (err < 0) | |
708 | return err; | |
23fb4740 TR |
709 | |
710 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); | |
711 | ||
712 | value = fb->offsets[0] + y * fb->pitches[0] + | |
713 | x * fb->bits_per_pixel / 8; | |
714 | ||
de2ba664 | 715 | tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR); |
23fb4740 | 716 | tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE); |
f925390e TR |
717 | |
718 | format = tegra_dc_format(fb->pixel_format, &swap); | |
ed683aea | 719 | tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH); |
f925390e | 720 | tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP); |
23fb4740 | 721 | |
c134f019 TR |
722 | if (dc->soc->supports_block_linear) { |
723 | unsigned long height = tiling.value; | |
724 | ||
725 | switch (tiling.mode) { | |
726 | case TEGRA_BO_TILING_MODE_PITCH: | |
727 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
728 | break; | |
729 | ||
730 | case TEGRA_BO_TILING_MODE_TILED: | |
731 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
732 | break; | |
733 | ||
734 | case TEGRA_BO_TILING_MODE_BLOCK: | |
735 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
736 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
737 | break; | |
738 | } | |
739 | ||
740 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
773af77f | 741 | } else { |
c134f019 TR |
742 | switch (tiling.mode) { |
743 | case TEGRA_BO_TILING_MODE_PITCH: | |
744 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
745 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
746 | break; | |
773af77f | 747 | |
c134f019 TR |
748 | case TEGRA_BO_TILING_MODE_TILED: |
749 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
750 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
751 | break; | |
752 | ||
753 | case TEGRA_BO_TILING_MODE_BLOCK: | |
754 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
755 | return -EINVAL; | |
756 | } | |
757 | ||
758 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
759 | } | |
773af77f | 760 | |
db7fbdfd TR |
761 | /* make sure bottom-up buffers are properly displayed */ |
762 | if (tegra_fb_is_bottom_up(fb)) { | |
763 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
eba66501 | 764 | value |= V_DIRECTION; |
db7fbdfd TR |
765 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
766 | ||
767 | v_offset += fb->height - 1; | |
768 | } else { | |
769 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
eba66501 | 770 | value &= ~V_DIRECTION; |
db7fbdfd TR |
771 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
772 | } | |
773 | ||
774 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
775 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
776 | ||
23fb4740 | 777 | value = GENERAL_ACT_REQ | WIN_A_ACT_REQ; |
205d48ed | 778 | tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL); |
23fb4740 TR |
779 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
6e5ff998 TR |
784 | void tegra_dc_enable_vblank(struct tegra_dc *dc) |
785 | { | |
786 | unsigned long value, flags; | |
787 | ||
788 | spin_lock_irqsave(&dc->lock, flags); | |
789 | ||
790 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
791 | value |= VBLANK_INT; | |
792 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
793 | ||
794 | spin_unlock_irqrestore(&dc->lock, flags); | |
795 | } | |
796 | ||
797 | void tegra_dc_disable_vblank(struct tegra_dc *dc) | |
798 | { | |
799 | unsigned long value, flags; | |
800 | ||
801 | spin_lock_irqsave(&dc->lock, flags); | |
802 | ||
803 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
804 | value &= ~VBLANK_INT; | |
805 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
806 | ||
807 | spin_unlock_irqrestore(&dc->lock, flags); | |
808 | } | |
809 | ||
3c03c46a TR |
810 | static void tegra_dc_finish_page_flip(struct tegra_dc *dc) |
811 | { | |
812 | struct drm_device *drm = dc->base.dev; | |
813 | struct drm_crtc *crtc = &dc->base; | |
3c03c46a | 814 | unsigned long flags, base; |
de2ba664 | 815 | struct tegra_bo *bo; |
3c03c46a | 816 | |
6b59cc1c TR |
817 | spin_lock_irqsave(&drm->event_lock, flags); |
818 | ||
819 | if (!dc->event) { | |
820 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a | 821 | return; |
6b59cc1c | 822 | } |
3c03c46a | 823 | |
f4510a27 | 824 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
3c03c46a TR |
825 | |
826 | /* check if new start address has been latched */ | |
827 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); | |
828 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); | |
829 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
830 | ||
f4510a27 | 831 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { |
ed7dae58 TR |
832 | drm_crtc_send_vblank_event(crtc, dc->event); |
833 | drm_crtc_vblank_put(crtc); | |
3c03c46a | 834 | dc->event = NULL; |
3c03c46a | 835 | } |
6b59cc1c TR |
836 | |
837 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a TR |
838 | } |
839 | ||
840 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) | |
841 | { | |
842 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
843 | struct drm_device *drm = crtc->dev; | |
844 | unsigned long flags; | |
845 | ||
846 | spin_lock_irqsave(&drm->event_lock, flags); | |
847 | ||
848 | if (dc->event && dc->event->base.file_priv == file) { | |
849 | dc->event->base.destroy(&dc->event->base); | |
ed7dae58 | 850 | drm_crtc_vblank_put(crtc); |
3c03c46a TR |
851 | dc->event = NULL; |
852 | } | |
853 | ||
854 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
855 | } | |
856 | ||
857 | static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
a5b6f74e | 858 | struct drm_pending_vblank_event *event, uint32_t page_flip_flags) |
3c03c46a | 859 | { |
ed7dae58 | 860 | unsigned int pipe = drm_crtc_index(crtc); |
3c03c46a | 861 | struct tegra_dc *dc = to_tegra_dc(crtc); |
3c03c46a TR |
862 | |
863 | if (dc->event) | |
864 | return -EBUSY; | |
865 | ||
866 | if (event) { | |
ed7dae58 | 867 | event->pipe = pipe; |
3c03c46a | 868 | dc->event = event; |
ed7dae58 | 869 | drm_crtc_vblank_get(crtc); |
3c03c46a TR |
870 | } |
871 | ||
872 | tegra_dc_set_base(dc, 0, 0, fb); | |
f4510a27 | 873 | crtc->primary->fb = fb; |
3c03c46a TR |
874 | |
875 | return 0; | |
876 | } | |
877 | ||
f002abc1 TR |
878 | static void drm_crtc_clear(struct drm_crtc *crtc) |
879 | { | |
880 | memset(crtc, 0, sizeof(*crtc)); | |
881 | } | |
882 | ||
883 | static void tegra_dc_destroy(struct drm_crtc *crtc) | |
884 | { | |
885 | drm_crtc_cleanup(crtc); | |
886 | drm_crtc_clear(crtc); | |
887 | } | |
888 | ||
d8f4a9ed | 889 | static const struct drm_crtc_funcs tegra_crtc_funcs = { |
3c03c46a | 890 | .page_flip = tegra_dc_page_flip, |
d8f4a9ed | 891 | .set_config = drm_crtc_helper_set_config, |
f002abc1 | 892 | .destroy = tegra_dc_destroy, |
d8f4a9ed TR |
893 | }; |
894 | ||
f34bc787 | 895 | static void tegra_crtc_disable(struct drm_crtc *crtc) |
d8f4a9ed | 896 | { |
f002abc1 | 897 | struct tegra_dc *dc = to_tegra_dc(crtc); |
f34bc787 TR |
898 | struct drm_device *drm = crtc->dev; |
899 | struct drm_plane *plane; | |
900 | ||
2b4c3661 | 901 | drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) { |
f34bc787 | 902 | if (plane->crtc == crtc) { |
c7679306 | 903 | tegra_window_plane_disable(plane); |
f34bc787 TR |
904 | plane->crtc = NULL; |
905 | ||
906 | if (plane->fb) { | |
907 | drm_framebuffer_unreference(plane->fb); | |
908 | plane->fb = NULL; | |
909 | } | |
910 | } | |
911 | } | |
f002abc1 | 912 | |
8ff64c17 | 913 | drm_crtc_vblank_off(crtc); |
c7679306 | 914 | tegra_dc_commit(dc); |
d8f4a9ed TR |
915 | } |
916 | ||
917 | static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, | |
918 | const struct drm_display_mode *mode, | |
919 | struct drm_display_mode *adjusted) | |
920 | { | |
921 | return true; | |
922 | } | |
923 | ||
d8f4a9ed TR |
924 | static int tegra_dc_set_timings(struct tegra_dc *dc, |
925 | struct drm_display_mode *mode) | |
926 | { | |
0444c0ff TR |
927 | unsigned int h_ref_to_sync = 1; |
928 | unsigned int v_ref_to_sync = 1; | |
d8f4a9ed TR |
929 | unsigned long value; |
930 | ||
931 | tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); | |
932 | ||
933 | value = (v_ref_to_sync << 16) | h_ref_to_sync; | |
934 | tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); | |
935 | ||
936 | value = ((mode->vsync_end - mode->vsync_start) << 16) | | |
937 | ((mode->hsync_end - mode->hsync_start) << 0); | |
938 | tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); | |
939 | ||
d8f4a9ed TR |
940 | value = ((mode->vtotal - mode->vsync_end) << 16) | |
941 | ((mode->htotal - mode->hsync_end) << 0); | |
40495089 LS |
942 | tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); |
943 | ||
944 | value = ((mode->vsync_start - mode->vdisplay) << 16) | | |
945 | ((mode->hsync_start - mode->hdisplay) << 0); | |
d8f4a9ed TR |
946 | tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); |
947 | ||
948 | value = (mode->vdisplay << 16) | mode->hdisplay; | |
949 | tegra_dc_writel(dc, value, DC_DISP_ACTIVE); | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
954 | static int tegra_crtc_setup_clk(struct drm_crtc *crtc, | |
dbb3f2f7 | 955 | struct drm_display_mode *mode) |
d8f4a9ed | 956 | { |
91eded9b | 957 | unsigned long pclk = mode->clock * 1000; |
d8f4a9ed TR |
958 | struct tegra_dc *dc = to_tegra_dc(crtc); |
959 | struct tegra_output *output = NULL; | |
960 | struct drm_encoder *encoder; | |
dbb3f2f7 TR |
961 | unsigned int div; |
962 | u32 value; | |
d8f4a9ed TR |
963 | long err; |
964 | ||
965 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head) | |
966 | if (encoder->crtc == crtc) { | |
967 | output = encoder_to_output(encoder); | |
968 | break; | |
969 | } | |
970 | ||
971 | if (!output) | |
972 | return -ENODEV; | |
973 | ||
974 | /* | |
91eded9b TR |
975 | * This assumes that the parent clock is pll_d_out0 or pll_d2_out |
976 | * respectively, each of which divides the base pll_d by 2. | |
d8f4a9ed | 977 | */ |
91eded9b | 978 | err = tegra_output_setup_clock(output, dc->clk, pclk, &div); |
d8f4a9ed TR |
979 | if (err < 0) { |
980 | dev_err(dc->dev, "failed to setup clock: %ld\n", err); | |
981 | return err; | |
982 | } | |
983 | ||
91eded9b | 984 | DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div); |
d8f4a9ed | 985 | |
dbb3f2f7 TR |
986 | value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1; |
987 | tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); | |
d8f4a9ed TR |
988 | |
989 | return 0; | |
990 | } | |
991 | ||
992 | static int tegra_crtc_mode_set(struct drm_crtc *crtc, | |
993 | struct drm_display_mode *mode, | |
994 | struct drm_display_mode *adjusted, | |
995 | int x, int y, struct drm_framebuffer *old_fb) | |
996 | { | |
f4510a27 | 997 | struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
d8f4a9ed | 998 | struct tegra_dc *dc = to_tegra_dc(crtc); |
f34bc787 | 999 | struct tegra_dc_window window; |
dbb3f2f7 | 1000 | u32 value; |
d8f4a9ed TR |
1001 | int err; |
1002 | ||
dbb3f2f7 | 1003 | err = tegra_crtc_setup_clk(crtc, mode); |
d8f4a9ed TR |
1004 | if (err) { |
1005 | dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err); | |
1006 | return err; | |
1007 | } | |
1008 | ||
1009 | /* program display mode */ | |
1010 | tegra_dc_set_timings(dc, mode); | |
1011 | ||
8620fc62 TR |
1012 | /* interlacing isn't supported yet, so disable it */ |
1013 | if (dc->soc->supports_interlacing) { | |
1014 | value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); | |
1015 | value &= ~INTERLACE_ENABLE; | |
1016 | tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); | |
1017 | } | |
1018 | ||
d8f4a9ed | 1019 | /* setup window parameters */ |
f34bc787 TR |
1020 | memset(&window, 0, sizeof(window)); |
1021 | window.src.x = 0; | |
1022 | window.src.y = 0; | |
1023 | window.src.w = mode->hdisplay; | |
1024 | window.src.h = mode->vdisplay; | |
1025 | window.dst.x = 0; | |
1026 | window.dst.y = 0; | |
1027 | window.dst.w = mode->hdisplay; | |
1028 | window.dst.h = mode->vdisplay; | |
f925390e TR |
1029 | window.format = tegra_dc_format(crtc->primary->fb->pixel_format, |
1030 | &window.swap); | |
f4510a27 MR |
1031 | window.bits_per_pixel = crtc->primary->fb->bits_per_pixel; |
1032 | window.stride[0] = crtc->primary->fb->pitches[0]; | |
de2ba664 | 1033 | window.base[0] = bo->paddr; |
f34bc787 TR |
1034 | |
1035 | err = tegra_dc_setup_window(dc, 0, &window); | |
1036 | if (err < 0) | |
1037 | dev_err(dc->dev, "failed to enable root plane\n"); | |
d8f4a9ed | 1038 | |
d8f4a9ed TR |
1039 | return 0; |
1040 | } | |
d8f4a9ed | 1041 | |
23fb4740 TR |
1042 | static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
1043 | struct drm_framebuffer *old_fb) | |
1044 | { | |
1045 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
d8f4a9ed | 1046 | |
f4510a27 | 1047 | return tegra_dc_set_base(dc, x, y, crtc->primary->fb); |
d8f4a9ed TR |
1048 | } |
1049 | ||
1050 | static void tegra_crtc_prepare(struct drm_crtc *crtc) | |
1051 | { | |
1052 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
1053 | unsigned int syncpt; | |
1054 | unsigned long value; | |
1055 | ||
8ff64c17 TR |
1056 | drm_crtc_vblank_off(crtc); |
1057 | ||
d8f4a9ed | 1058 | /* hardware initialization */ |
ca48080a | 1059 | reset_control_deassert(dc->rst); |
d8f4a9ed TR |
1060 | usleep_range(10000, 20000); |
1061 | ||
1062 | if (dc->pipe) | |
1063 | syncpt = SYNCPT_VBLANK1; | |
1064 | else | |
1065 | syncpt = SYNCPT_VBLANK0; | |
1066 | ||
1067 | /* initialize display controller */ | |
1068 | tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1069 | tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); | |
1070 | ||
1071 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; | |
1072 | tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); | |
1073 | ||
1074 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1075 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1076 | tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); | |
1077 | ||
d8f4a9ed TR |
1078 | /* initialize timer */ |
1079 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | | |
1080 | WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); | |
1081 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1082 | ||
1083 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | | |
1084 | WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); | |
1085 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1086 | ||
d8f4a9ed TR |
1087 | value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; |
1088 | tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); | |
6e5ff998 TR |
1089 | |
1090 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; | |
1091 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
d8f4a9ed TR |
1092 | } |
1093 | ||
1094 | static void tegra_crtc_commit(struct drm_crtc *crtc) | |
1095 | { | |
1096 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
d8f4a9ed | 1097 | |
8ff64c17 | 1098 | drm_crtc_vblank_on(crtc); |
205d48ed | 1099 | tegra_dc_commit(dc); |
d8f4a9ed TR |
1100 | } |
1101 | ||
1102 | static void tegra_crtc_load_lut(struct drm_crtc *crtc) | |
1103 | { | |
1104 | } | |
1105 | ||
1106 | static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { | |
f34bc787 | 1107 | .disable = tegra_crtc_disable, |
d8f4a9ed TR |
1108 | .mode_fixup = tegra_crtc_mode_fixup, |
1109 | .mode_set = tegra_crtc_mode_set, | |
23fb4740 | 1110 | .mode_set_base = tegra_crtc_mode_set_base, |
d8f4a9ed TR |
1111 | .prepare = tegra_crtc_prepare, |
1112 | .commit = tegra_crtc_commit, | |
1113 | .load_lut = tegra_crtc_load_lut, | |
1114 | }; | |
1115 | ||
6e5ff998 | 1116 | static irqreturn_t tegra_dc_irq(int irq, void *data) |
d8f4a9ed TR |
1117 | { |
1118 | struct tegra_dc *dc = data; | |
1119 | unsigned long status; | |
1120 | ||
1121 | status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); | |
1122 | tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); | |
1123 | ||
1124 | if (status & FRAME_END_INT) { | |
1125 | /* | |
1126 | dev_dbg(dc->dev, "%s(): frame end\n", __func__); | |
1127 | */ | |
1128 | } | |
1129 | ||
1130 | if (status & VBLANK_INT) { | |
1131 | /* | |
1132 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); | |
1133 | */ | |
ed7dae58 | 1134 | drm_crtc_handle_vblank(&dc->base); |
3c03c46a | 1135 | tegra_dc_finish_page_flip(dc); |
d8f4a9ed TR |
1136 | } |
1137 | ||
1138 | if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { | |
1139 | /* | |
1140 | dev_dbg(dc->dev, "%s(): underflow\n", __func__); | |
1141 | */ | |
1142 | } | |
1143 | ||
1144 | return IRQ_HANDLED; | |
1145 | } | |
1146 | ||
1147 | static int tegra_dc_show_regs(struct seq_file *s, void *data) | |
1148 | { | |
1149 | struct drm_info_node *node = s->private; | |
1150 | struct tegra_dc *dc = node->info_ent->data; | |
1151 | ||
1152 | #define DUMP_REG(name) \ | |
03a60569 | 1153 | seq_printf(s, "%-40s %#05x %08x\n", #name, name, \ |
d8f4a9ed TR |
1154 | tegra_dc_readl(dc, name)) |
1155 | ||
1156 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); | |
1157 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1158 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); | |
1159 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); | |
1160 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); | |
1161 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); | |
1162 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); | |
1163 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); | |
1164 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); | |
1165 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); | |
1166 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); | |
1167 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); | |
1168 | DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); | |
1169 | DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); | |
1170 | DUMP_REG(DC_CMD_DISPLAY_COMMAND); | |
1171 | DUMP_REG(DC_CMD_SIGNAL_RAISE); | |
1172 | DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); | |
1173 | DUMP_REG(DC_CMD_INT_STATUS); | |
1174 | DUMP_REG(DC_CMD_INT_MASK); | |
1175 | DUMP_REG(DC_CMD_INT_ENABLE); | |
1176 | DUMP_REG(DC_CMD_INT_TYPE); | |
1177 | DUMP_REG(DC_CMD_INT_POLARITY); | |
1178 | DUMP_REG(DC_CMD_SIGNAL_RAISE1); | |
1179 | DUMP_REG(DC_CMD_SIGNAL_RAISE2); | |
1180 | DUMP_REG(DC_CMD_SIGNAL_RAISE3); | |
1181 | DUMP_REG(DC_CMD_STATE_ACCESS); | |
1182 | DUMP_REG(DC_CMD_STATE_CONTROL); | |
1183 | DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); | |
1184 | DUMP_REG(DC_CMD_REG_ACT_CONTROL); | |
1185 | DUMP_REG(DC_COM_CRC_CONTROL); | |
1186 | DUMP_REG(DC_COM_CRC_CHECKSUM); | |
1187 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); | |
1188 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); | |
1189 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); | |
1190 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); | |
1191 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); | |
1192 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); | |
1193 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); | |
1194 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); | |
1195 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); | |
1196 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); | |
1197 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); | |
1198 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); | |
1199 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); | |
1200 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); | |
1201 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); | |
1202 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); | |
1203 | DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); | |
1204 | DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); | |
1205 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); | |
1206 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); | |
1207 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); | |
1208 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); | |
1209 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); | |
1210 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); | |
1211 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); | |
1212 | DUMP_REG(DC_COM_PIN_MISC_CONTROL); | |
1213 | DUMP_REG(DC_COM_PIN_PM0_CONTROL); | |
1214 | DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); | |
1215 | DUMP_REG(DC_COM_PIN_PM1_CONTROL); | |
1216 | DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); | |
1217 | DUMP_REG(DC_COM_SPI_CONTROL); | |
1218 | DUMP_REG(DC_COM_SPI_START_BYTE); | |
1219 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); | |
1220 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); | |
1221 | DUMP_REG(DC_COM_HSPI_CS_DC); | |
1222 | DUMP_REG(DC_COM_SCRATCH_REGISTER_A); | |
1223 | DUMP_REG(DC_COM_SCRATCH_REGISTER_B); | |
1224 | DUMP_REG(DC_COM_GPIO_CTRL); | |
1225 | DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); | |
1226 | DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); | |
1227 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); | |
1228 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); | |
1229 | DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); | |
1230 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1231 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1232 | DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); | |
1233 | DUMP_REG(DC_DISP_REF_TO_SYNC); | |
1234 | DUMP_REG(DC_DISP_SYNC_WIDTH); | |
1235 | DUMP_REG(DC_DISP_BACK_PORCH); | |
1236 | DUMP_REG(DC_DISP_ACTIVE); | |
1237 | DUMP_REG(DC_DISP_FRONT_PORCH); | |
1238 | DUMP_REG(DC_DISP_H_PULSE0_CONTROL); | |
1239 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); | |
1240 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); | |
1241 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); | |
1242 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); | |
1243 | DUMP_REG(DC_DISP_H_PULSE1_CONTROL); | |
1244 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); | |
1245 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); | |
1246 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); | |
1247 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); | |
1248 | DUMP_REG(DC_DISP_H_PULSE2_CONTROL); | |
1249 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); | |
1250 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); | |
1251 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); | |
1252 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); | |
1253 | DUMP_REG(DC_DISP_V_PULSE0_CONTROL); | |
1254 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); | |
1255 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); | |
1256 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); | |
1257 | DUMP_REG(DC_DISP_V_PULSE1_CONTROL); | |
1258 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); | |
1259 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); | |
1260 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); | |
1261 | DUMP_REG(DC_DISP_V_PULSE2_CONTROL); | |
1262 | DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); | |
1263 | DUMP_REG(DC_DISP_V_PULSE3_CONTROL); | |
1264 | DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); | |
1265 | DUMP_REG(DC_DISP_M0_CONTROL); | |
1266 | DUMP_REG(DC_DISP_M1_CONTROL); | |
1267 | DUMP_REG(DC_DISP_DI_CONTROL); | |
1268 | DUMP_REG(DC_DISP_PP_CONTROL); | |
1269 | DUMP_REG(DC_DISP_PP_SELECT_A); | |
1270 | DUMP_REG(DC_DISP_PP_SELECT_B); | |
1271 | DUMP_REG(DC_DISP_PP_SELECT_C); | |
1272 | DUMP_REG(DC_DISP_PP_SELECT_D); | |
1273 | DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); | |
1274 | DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); | |
1275 | DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); | |
1276 | DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); | |
1277 | DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); | |
1278 | DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); | |
1279 | DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); | |
1280 | DUMP_REG(DC_DISP_BORDER_COLOR); | |
1281 | DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); | |
1282 | DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); | |
1283 | DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); | |
1284 | DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); | |
1285 | DUMP_REG(DC_DISP_CURSOR_FOREGROUND); | |
1286 | DUMP_REG(DC_DISP_CURSOR_BACKGROUND); | |
1287 | DUMP_REG(DC_DISP_CURSOR_START_ADDR); | |
1288 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); | |
1289 | DUMP_REG(DC_DISP_CURSOR_POSITION); | |
1290 | DUMP_REG(DC_DISP_CURSOR_POSITION_NS); | |
1291 | DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); | |
1292 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); | |
1293 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); | |
1294 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); | |
1295 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); | |
1296 | DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); | |
1297 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); | |
1298 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); | |
1299 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); | |
1300 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); | |
1301 | DUMP_REG(DC_DISP_DAC_CRT_CTRL); | |
1302 | DUMP_REG(DC_DISP_DISP_MISC_CONTROL); | |
1303 | DUMP_REG(DC_DISP_SD_CONTROL); | |
1304 | DUMP_REG(DC_DISP_SD_CSC_COEFF); | |
1305 | DUMP_REG(DC_DISP_SD_LUT(0)); | |
1306 | DUMP_REG(DC_DISP_SD_LUT(1)); | |
1307 | DUMP_REG(DC_DISP_SD_LUT(2)); | |
1308 | DUMP_REG(DC_DISP_SD_LUT(3)); | |
1309 | DUMP_REG(DC_DISP_SD_LUT(4)); | |
1310 | DUMP_REG(DC_DISP_SD_LUT(5)); | |
1311 | DUMP_REG(DC_DISP_SD_LUT(6)); | |
1312 | DUMP_REG(DC_DISP_SD_LUT(7)); | |
1313 | DUMP_REG(DC_DISP_SD_LUT(8)); | |
1314 | DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); | |
1315 | DUMP_REG(DC_DISP_DC_PIXEL_COUNT); | |
1316 | DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); | |
1317 | DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); | |
1318 | DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); | |
1319 | DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); | |
1320 | DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); | |
1321 | DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); | |
1322 | DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); | |
1323 | DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); | |
1324 | DUMP_REG(DC_DISP_SD_BL_TF(0)); | |
1325 | DUMP_REG(DC_DISP_SD_BL_TF(1)); | |
1326 | DUMP_REG(DC_DISP_SD_BL_TF(2)); | |
1327 | DUMP_REG(DC_DISP_SD_BL_TF(3)); | |
1328 | DUMP_REG(DC_DISP_SD_BL_CONTROL); | |
1329 | DUMP_REG(DC_DISP_SD_HW_K_VALUES); | |
1330 | DUMP_REG(DC_DISP_SD_MAN_K_VALUES); | |
e687651b TR |
1331 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI); |
1332 | DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL); | |
d8f4a9ed TR |
1333 | DUMP_REG(DC_WIN_WIN_OPTIONS); |
1334 | DUMP_REG(DC_WIN_BYTE_SWAP); | |
1335 | DUMP_REG(DC_WIN_BUFFER_CONTROL); | |
1336 | DUMP_REG(DC_WIN_COLOR_DEPTH); | |
1337 | DUMP_REG(DC_WIN_POSITION); | |
1338 | DUMP_REG(DC_WIN_SIZE); | |
1339 | DUMP_REG(DC_WIN_PRESCALED_SIZE); | |
1340 | DUMP_REG(DC_WIN_H_INITIAL_DDA); | |
1341 | DUMP_REG(DC_WIN_V_INITIAL_DDA); | |
1342 | DUMP_REG(DC_WIN_DDA_INC); | |
1343 | DUMP_REG(DC_WIN_LINE_STRIDE); | |
1344 | DUMP_REG(DC_WIN_BUF_STRIDE); | |
1345 | DUMP_REG(DC_WIN_UV_BUF_STRIDE); | |
1346 | DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); | |
1347 | DUMP_REG(DC_WIN_DV_CONTROL); | |
1348 | DUMP_REG(DC_WIN_BLEND_NOKEY); | |
1349 | DUMP_REG(DC_WIN_BLEND_1WIN); | |
1350 | DUMP_REG(DC_WIN_BLEND_2WIN_X); | |
1351 | DUMP_REG(DC_WIN_BLEND_2WIN_Y); | |
f34bc787 | 1352 | DUMP_REG(DC_WIN_BLEND_3WIN_XY); |
d8f4a9ed TR |
1353 | DUMP_REG(DC_WIN_HP_FETCH_CONTROL); |
1354 | DUMP_REG(DC_WINBUF_START_ADDR); | |
1355 | DUMP_REG(DC_WINBUF_START_ADDR_NS); | |
1356 | DUMP_REG(DC_WINBUF_START_ADDR_U); | |
1357 | DUMP_REG(DC_WINBUF_START_ADDR_U_NS); | |
1358 | DUMP_REG(DC_WINBUF_START_ADDR_V); | |
1359 | DUMP_REG(DC_WINBUF_START_ADDR_V_NS); | |
1360 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); | |
1361 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); | |
1362 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); | |
1363 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); | |
1364 | DUMP_REG(DC_WINBUF_UFLOW_STATUS); | |
1365 | DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); | |
1366 | DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); | |
1367 | DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); | |
1368 | ||
1369 | #undef DUMP_REG | |
1370 | ||
1371 | return 0; | |
1372 | } | |
1373 | ||
1374 | static struct drm_info_list debugfs_files[] = { | |
1375 | { "regs", tegra_dc_show_regs, 0, NULL }, | |
1376 | }; | |
1377 | ||
1378 | static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) | |
1379 | { | |
1380 | unsigned int i; | |
1381 | char *name; | |
1382 | int err; | |
1383 | ||
1384 | name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); | |
1385 | dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); | |
1386 | kfree(name); | |
1387 | ||
1388 | if (!dc->debugfs) | |
1389 | return -ENOMEM; | |
1390 | ||
1391 | dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), | |
1392 | GFP_KERNEL); | |
1393 | if (!dc->debugfs_files) { | |
1394 | err = -ENOMEM; | |
1395 | goto remove; | |
1396 | } | |
1397 | ||
1398 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
1399 | dc->debugfs_files[i].data = dc; | |
1400 | ||
1401 | err = drm_debugfs_create_files(dc->debugfs_files, | |
1402 | ARRAY_SIZE(debugfs_files), | |
1403 | dc->debugfs, minor); | |
1404 | if (err < 0) | |
1405 | goto free; | |
1406 | ||
1407 | dc->minor = minor; | |
1408 | ||
1409 | return 0; | |
1410 | ||
1411 | free: | |
1412 | kfree(dc->debugfs_files); | |
1413 | dc->debugfs_files = NULL; | |
1414 | remove: | |
1415 | debugfs_remove(dc->debugfs); | |
1416 | dc->debugfs = NULL; | |
1417 | ||
1418 | return err; | |
1419 | } | |
1420 | ||
1421 | static int tegra_dc_debugfs_exit(struct tegra_dc *dc) | |
1422 | { | |
1423 | drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), | |
1424 | dc->minor); | |
1425 | dc->minor = NULL; | |
1426 | ||
1427 | kfree(dc->debugfs_files); | |
1428 | dc->debugfs_files = NULL; | |
1429 | ||
1430 | debugfs_remove(dc->debugfs); | |
1431 | dc->debugfs = NULL; | |
1432 | ||
1433 | return 0; | |
1434 | } | |
1435 | ||
53fa7f72 | 1436 | static int tegra_dc_init(struct host1x_client *client) |
d8f4a9ed | 1437 | { |
9910f5c4 | 1438 | struct drm_device *drm = dev_get_drvdata(client->parent); |
776dc384 | 1439 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d1f3e1e0 | 1440 | struct tegra_drm *tegra = drm->dev_private; |
c7679306 TR |
1441 | struct drm_plane *primary = NULL; |
1442 | struct drm_plane *cursor = NULL; | |
d8f4a9ed TR |
1443 | int err; |
1444 | ||
df06b759 TR |
1445 | if (tegra->domain) { |
1446 | err = iommu_attach_device(tegra->domain, dc->dev); | |
1447 | if (err < 0) { | |
1448 | dev_err(dc->dev, "failed to attach to domain: %d\n", | |
1449 | err); | |
1450 | return err; | |
1451 | } | |
1452 | ||
1453 | dc->domain = tegra->domain; | |
1454 | } | |
1455 | ||
c7679306 TR |
1456 | primary = tegra_dc_primary_plane_create(drm, dc); |
1457 | if (IS_ERR(primary)) { | |
1458 | err = PTR_ERR(primary); | |
1459 | goto cleanup; | |
1460 | } | |
1461 | ||
1462 | if (dc->soc->supports_cursor) { | |
1463 | cursor = tegra_dc_cursor_plane_create(drm, dc); | |
1464 | if (IS_ERR(cursor)) { | |
1465 | err = PTR_ERR(cursor); | |
1466 | goto cleanup; | |
1467 | } | |
1468 | } | |
1469 | ||
1470 | err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, | |
1471 | &tegra_crtc_funcs); | |
1472 | if (err < 0) | |
1473 | goto cleanup; | |
1474 | ||
d8f4a9ed TR |
1475 | drm_mode_crtc_set_gamma_size(&dc->base, 256); |
1476 | drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); | |
1477 | ||
d1f3e1e0 TR |
1478 | /* |
1479 | * Keep track of the minimum pitch alignment across all display | |
1480 | * controllers. | |
1481 | */ | |
1482 | if (dc->soc->pitch_align > tegra->pitch_align) | |
1483 | tegra->pitch_align = dc->soc->pitch_align; | |
1484 | ||
9910f5c4 | 1485 | err = tegra_dc_rgb_init(drm, dc); |
d8f4a9ed TR |
1486 | if (err < 0 && err != -ENODEV) { |
1487 | dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); | |
c7679306 | 1488 | goto cleanup; |
d8f4a9ed TR |
1489 | } |
1490 | ||
9910f5c4 | 1491 | err = tegra_dc_add_planes(drm, dc); |
f34bc787 | 1492 | if (err < 0) |
c7679306 | 1493 | goto cleanup; |
f34bc787 | 1494 | |
d8f4a9ed | 1495 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
9910f5c4 | 1496 | err = tegra_dc_debugfs_init(dc, drm->primary); |
d8f4a9ed TR |
1497 | if (err < 0) |
1498 | dev_err(dc->dev, "debugfs setup failed: %d\n", err); | |
1499 | } | |
1500 | ||
6e5ff998 | 1501 | err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, |
d8f4a9ed TR |
1502 | dev_name(dc->dev), dc); |
1503 | if (err < 0) { | |
1504 | dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, | |
1505 | err); | |
c7679306 | 1506 | goto cleanup; |
d8f4a9ed TR |
1507 | } |
1508 | ||
1509 | return 0; | |
c7679306 TR |
1510 | |
1511 | cleanup: | |
1512 | if (cursor) | |
1513 | drm_plane_cleanup(cursor); | |
1514 | ||
1515 | if (primary) | |
1516 | drm_plane_cleanup(primary); | |
1517 | ||
1518 | if (tegra->domain) { | |
1519 | iommu_detach_device(tegra->domain, dc->dev); | |
1520 | dc->domain = NULL; | |
1521 | } | |
1522 | ||
1523 | return err; | |
d8f4a9ed TR |
1524 | } |
1525 | ||
53fa7f72 | 1526 | static int tegra_dc_exit(struct host1x_client *client) |
d8f4a9ed | 1527 | { |
776dc384 | 1528 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d8f4a9ed TR |
1529 | int err; |
1530 | ||
1531 | devm_free_irq(dc->dev, dc->irq, dc); | |
1532 | ||
1533 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1534 | err = tegra_dc_debugfs_exit(dc); | |
1535 | if (err < 0) | |
1536 | dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); | |
1537 | } | |
1538 | ||
1539 | err = tegra_dc_rgb_exit(dc); | |
1540 | if (err) { | |
1541 | dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); | |
1542 | return err; | |
1543 | } | |
1544 | ||
df06b759 TR |
1545 | if (dc->domain) { |
1546 | iommu_detach_device(dc->domain, dc->dev); | |
1547 | dc->domain = NULL; | |
1548 | } | |
1549 | ||
d8f4a9ed TR |
1550 | return 0; |
1551 | } | |
1552 | ||
1553 | static const struct host1x_client_ops dc_client_ops = { | |
53fa7f72 TR |
1554 | .init = tegra_dc_init, |
1555 | .exit = tegra_dc_exit, | |
d8f4a9ed TR |
1556 | }; |
1557 | ||
8620fc62 TR |
1558 | static const struct tegra_dc_soc_info tegra20_dc_soc_info = { |
1559 | .supports_interlacing = false, | |
e687651b | 1560 | .supports_cursor = false, |
c134f019 | 1561 | .supports_block_linear = false, |
d1f3e1e0 | 1562 | .pitch_align = 8, |
9c012700 | 1563 | .has_powergate = false, |
8620fc62 TR |
1564 | }; |
1565 | ||
1566 | static const struct tegra_dc_soc_info tegra30_dc_soc_info = { | |
1567 | .supports_interlacing = false, | |
e687651b | 1568 | .supports_cursor = false, |
c134f019 | 1569 | .supports_block_linear = false, |
d1f3e1e0 | 1570 | .pitch_align = 8, |
9c012700 | 1571 | .has_powergate = false, |
d1f3e1e0 TR |
1572 | }; |
1573 | ||
1574 | static const struct tegra_dc_soc_info tegra114_dc_soc_info = { | |
1575 | .supports_interlacing = false, | |
1576 | .supports_cursor = false, | |
1577 | .supports_block_linear = false, | |
1578 | .pitch_align = 64, | |
9c012700 | 1579 | .has_powergate = true, |
8620fc62 TR |
1580 | }; |
1581 | ||
1582 | static const struct tegra_dc_soc_info tegra124_dc_soc_info = { | |
1583 | .supports_interlacing = true, | |
e687651b | 1584 | .supports_cursor = true, |
c134f019 | 1585 | .supports_block_linear = true, |
d1f3e1e0 | 1586 | .pitch_align = 64, |
9c012700 | 1587 | .has_powergate = true, |
8620fc62 TR |
1588 | }; |
1589 | ||
1590 | static const struct of_device_id tegra_dc_of_match[] = { | |
1591 | { | |
1592 | .compatible = "nvidia,tegra124-dc", | |
1593 | .data = &tegra124_dc_soc_info, | |
9c012700 TR |
1594 | }, { |
1595 | .compatible = "nvidia,tegra114-dc", | |
1596 | .data = &tegra114_dc_soc_info, | |
8620fc62 TR |
1597 | }, { |
1598 | .compatible = "nvidia,tegra30-dc", | |
1599 | .data = &tegra30_dc_soc_info, | |
1600 | }, { | |
1601 | .compatible = "nvidia,tegra20-dc", | |
1602 | .data = &tegra20_dc_soc_info, | |
1603 | }, { | |
1604 | /* sentinel */ | |
1605 | } | |
1606 | }; | |
ef70728c | 1607 | MODULE_DEVICE_TABLE(of, tegra_dc_of_match); |
8620fc62 | 1608 | |
13411ddd TR |
1609 | static int tegra_dc_parse_dt(struct tegra_dc *dc) |
1610 | { | |
1611 | struct device_node *np; | |
1612 | u32 value = 0; | |
1613 | int err; | |
1614 | ||
1615 | err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); | |
1616 | if (err < 0) { | |
1617 | dev_err(dc->dev, "missing \"nvidia,head\" property\n"); | |
1618 | ||
1619 | /* | |
1620 | * If the nvidia,head property isn't present, try to find the | |
1621 | * correct head number by looking up the position of this | |
1622 | * display controller's node within the device tree. Assuming | |
1623 | * that the nodes are ordered properly in the DTS file and | |
1624 | * that the translation into a flattened device tree blob | |
1625 | * preserves that ordering this will actually yield the right | |
1626 | * head number. | |
1627 | * | |
1628 | * If those assumptions don't hold, this will still work for | |
1629 | * cases where only a single display controller is used. | |
1630 | */ | |
1631 | for_each_matching_node(np, tegra_dc_of_match) { | |
1632 | if (np == dc->dev->of_node) | |
1633 | break; | |
1634 | ||
1635 | value++; | |
1636 | } | |
1637 | } | |
1638 | ||
1639 | dc->pipe = value; | |
1640 | ||
1641 | return 0; | |
1642 | } | |
1643 | ||
d8f4a9ed TR |
1644 | static int tegra_dc_probe(struct platform_device *pdev) |
1645 | { | |
8620fc62 | 1646 | const struct of_device_id *id; |
d8f4a9ed TR |
1647 | struct resource *regs; |
1648 | struct tegra_dc *dc; | |
1649 | int err; | |
1650 | ||
1651 | dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); | |
1652 | if (!dc) | |
1653 | return -ENOMEM; | |
1654 | ||
8620fc62 TR |
1655 | id = of_match_node(tegra_dc_of_match, pdev->dev.of_node); |
1656 | if (!id) | |
1657 | return -ENODEV; | |
1658 | ||
6e5ff998 | 1659 | spin_lock_init(&dc->lock); |
d8f4a9ed TR |
1660 | INIT_LIST_HEAD(&dc->list); |
1661 | dc->dev = &pdev->dev; | |
8620fc62 | 1662 | dc->soc = id->data; |
d8f4a9ed | 1663 | |
13411ddd TR |
1664 | err = tegra_dc_parse_dt(dc); |
1665 | if (err < 0) | |
1666 | return err; | |
1667 | ||
d8f4a9ed TR |
1668 | dc->clk = devm_clk_get(&pdev->dev, NULL); |
1669 | if (IS_ERR(dc->clk)) { | |
1670 | dev_err(&pdev->dev, "failed to get clock\n"); | |
1671 | return PTR_ERR(dc->clk); | |
1672 | } | |
1673 | ||
ca48080a SW |
1674 | dc->rst = devm_reset_control_get(&pdev->dev, "dc"); |
1675 | if (IS_ERR(dc->rst)) { | |
1676 | dev_err(&pdev->dev, "failed to get reset\n"); | |
1677 | return PTR_ERR(dc->rst); | |
1678 | } | |
1679 | ||
9c012700 TR |
1680 | if (dc->soc->has_powergate) { |
1681 | if (dc->pipe == 0) | |
1682 | dc->powergate = TEGRA_POWERGATE_DIS; | |
1683 | else | |
1684 | dc->powergate = TEGRA_POWERGATE_DISB; | |
1685 | ||
1686 | err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, | |
1687 | dc->rst); | |
1688 | if (err < 0) { | |
1689 | dev_err(&pdev->dev, "failed to power partition: %d\n", | |
1690 | err); | |
1691 | return err; | |
1692 | } | |
1693 | } else { | |
1694 | err = clk_prepare_enable(dc->clk); | |
1695 | if (err < 0) { | |
1696 | dev_err(&pdev->dev, "failed to enable clock: %d\n", | |
1697 | err); | |
1698 | return err; | |
1699 | } | |
1700 | ||
1701 | err = reset_control_deassert(dc->rst); | |
1702 | if (err < 0) { | |
1703 | dev_err(&pdev->dev, "failed to deassert reset: %d\n", | |
1704 | err); | |
1705 | return err; | |
1706 | } | |
1707 | } | |
d8f4a9ed TR |
1708 | |
1709 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d4ed6025 TR |
1710 | dc->regs = devm_ioremap_resource(&pdev->dev, regs); |
1711 | if (IS_ERR(dc->regs)) | |
1712 | return PTR_ERR(dc->regs); | |
d8f4a9ed TR |
1713 | |
1714 | dc->irq = platform_get_irq(pdev, 0); | |
1715 | if (dc->irq < 0) { | |
1716 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
1717 | return -ENXIO; | |
1718 | } | |
1719 | ||
776dc384 TR |
1720 | INIT_LIST_HEAD(&dc->client.list); |
1721 | dc->client.ops = &dc_client_ops; | |
1722 | dc->client.dev = &pdev->dev; | |
d8f4a9ed TR |
1723 | |
1724 | err = tegra_dc_rgb_probe(dc); | |
1725 | if (err < 0 && err != -ENODEV) { | |
1726 | dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); | |
1727 | return err; | |
1728 | } | |
1729 | ||
776dc384 | 1730 | err = host1x_client_register(&dc->client); |
d8f4a9ed TR |
1731 | if (err < 0) { |
1732 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
1733 | err); | |
1734 | return err; | |
1735 | } | |
1736 | ||
1737 | platform_set_drvdata(pdev, dc); | |
1738 | ||
1739 | return 0; | |
1740 | } | |
1741 | ||
1742 | static int tegra_dc_remove(struct platform_device *pdev) | |
1743 | { | |
d8f4a9ed TR |
1744 | struct tegra_dc *dc = platform_get_drvdata(pdev); |
1745 | int err; | |
1746 | ||
776dc384 | 1747 | err = host1x_client_unregister(&dc->client); |
d8f4a9ed TR |
1748 | if (err < 0) { |
1749 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
1750 | err); | |
1751 | return err; | |
1752 | } | |
1753 | ||
59d29c0e TR |
1754 | err = tegra_dc_rgb_remove(dc); |
1755 | if (err < 0) { | |
1756 | dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); | |
1757 | return err; | |
1758 | } | |
1759 | ||
5482d75a | 1760 | reset_control_assert(dc->rst); |
9c012700 TR |
1761 | |
1762 | if (dc->soc->has_powergate) | |
1763 | tegra_powergate_power_off(dc->powergate); | |
1764 | ||
d8f4a9ed TR |
1765 | clk_disable_unprepare(dc->clk); |
1766 | ||
1767 | return 0; | |
1768 | } | |
1769 | ||
d8f4a9ed TR |
1770 | struct platform_driver tegra_dc_driver = { |
1771 | .driver = { | |
1772 | .name = "tegra-dc", | |
1773 | .owner = THIS_MODULE, | |
1774 | .of_match_table = tegra_dc_of_match, | |
1775 | }, | |
1776 | .probe = tegra_dc_probe, | |
1777 | .remove = tegra_dc_remove, | |
1778 | }; |