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drm/tegra: Remove redundant zeroing out of memory
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
df06b759 12#include <linux/iommu.h>
ca48080a 13#include <linux/reset.h>
d8f4a9ed 14
9c012700
TR		 15#include <soc/tegra/pmc.h>
16
de2ba664
AM		 17#include "dc.h"
18#include "drm.h"
19#include "gem.h"
d8f4a9ed 20
3cb9ae4f
DV		 21#include <drm/drm_plane_helper.h>
22
8620fc62
TR		 23struct tegra_dc_soc_info {
24 bool supports_interlacing;
e687651b 25 bool supports_cursor;
c134f019 26 bool supports_block_linear;
d1f3e1e0 27 unsigned int pitch_align;
9c012700 28 bool has_powergate;
8620fc62
TR		 29};
30
f34bc787
TR		 31struct tegra_plane {
32 struct drm_plane base;
33 unsigned int index;
d8f4a9ed
TR		 34};
35
f34bc787
TR		 36static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
37{
38 return container_of(plane, struct tegra_plane, base);
39}
40
205d48ed
TR		 41static void tegra_dc_window_commit(struct tegra_dc *dc, unsigned int index)
42{
43 u32 value = WIN_A_ACT_REQ << index;
44
45 tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
46 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
47}
48
49static void tegra_dc_cursor_commit(struct tegra_dc *dc)
50{
51 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
52 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
53}
54
55static void tegra_dc_commit(struct tegra_dc *dc)
56{
57 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
58 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
59}
60
10288eea
TR		 61static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
62{
63 /* assume no swapping of fetched data */
64 if (swap)
65 *swap = BYTE_SWAP_NOSWAP;
66
67 switch (format) {
68 case DRM_FORMAT_XBGR8888:
69 return WIN_COLOR_DEPTH_R8G8B8A8;
70
71 case DRM_FORMAT_XRGB8888:
72 return WIN_COLOR_DEPTH_B8G8R8A8;
73
74 case DRM_FORMAT_RGB565:
75 return WIN_COLOR_DEPTH_B5G6R5;
76
77 case DRM_FORMAT_UYVY:
78 return WIN_COLOR_DEPTH_YCbCr422;
79
80 case DRM_FORMAT_YUYV:
81 if (swap)
82 *swap = BYTE_SWAP_SWAP2;
83
84 return WIN_COLOR_DEPTH_YCbCr422;
85
86 case DRM_FORMAT_YUV420:
87 return WIN_COLOR_DEPTH_YCbCr420P;
88
89 case DRM_FORMAT_YUV422:
90 return WIN_COLOR_DEPTH_YCbCr422P;
91
92 default:
93 break;
94 }
95
96 WARN(1, "unsupported pixel format %u, using default\n", format);
97 return WIN_COLOR_DEPTH_B8G8R8A8;
98}
99
100static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
101{
102 switch (format) {
103 case WIN_COLOR_DEPTH_YCbCr422:
104 case WIN_COLOR_DEPTH_YUV422:
105 if (planar)
106 *planar = false;
107
108 return true;
109
110 case WIN_COLOR_DEPTH_YCbCr420P:
111 case WIN_COLOR_DEPTH_YUV420P:
112 case WIN_COLOR_DEPTH_YCbCr422P:
113 case WIN_COLOR_DEPTH_YUV422P:
114 case WIN_COLOR_DEPTH_YCbCr422R:
115 case WIN_COLOR_DEPTH_YUV422R:
116 case WIN_COLOR_DEPTH_YCbCr422RA:
117 case WIN_COLOR_DEPTH_YUV422RA:
118 if (planar)
119 *planar = true;
120
121 return true;
122 }
123
124 return false;
125}
126
127static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
128 unsigned int bpp)
129{
130 fixed20_12 outf = dfixed_init(out);
131 fixed20_12 inf = dfixed_init(in);
132 u32 dda_inc;
133 int max;
134
135 if (v)
136 max = 15;
137 else {
138 switch (bpp) {
139 case 2:
140 max = 8;
141 break;
142
143 default:
144 WARN_ON_ONCE(1);
145 /* fallthrough */
146 case 4:
147 max = 4;
148 break;
149 }
150 }
151
152 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
153 inf.full -= dfixed_const(1);
154
155 dda_inc = dfixed_div(inf, outf);
156 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
157
158 return dda_inc;
159}
160
161static inline u32 compute_initial_dda(unsigned int in)
162{
163 fixed20_12 inf = dfixed_init(in);
164 return dfixed_frac(inf);
165}
166
167static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
168 const struct tegra_dc_window *window)
169{
170 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
93396d0f 171 unsigned long value, flags;
10288eea
TR		 172 bool yuv, planar;
173
174 /*
175 * For YUV planar modes, the number of bytes per pixel takes into
176 * account only the luma component and therefore is 1.
177 */
178 yuv = tegra_dc_format_is_yuv(window->format, &planar);
179 if (!yuv)
180 bpp = window->bits_per_pixel / 8;
181 else
182 bpp = planar ? 1 : 2;
183
93396d0f
SP		 184 spin_lock_irqsave(&dc->lock, flags);
185
10288eea
TR		 186 value = WINDOW_A_SELECT << index;
187 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
188
189 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
190 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
191
192 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
193 tegra_dc_writel(dc, value, DC_WIN_POSITION);
194
195 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
196 tegra_dc_writel(dc, value, DC_WIN_SIZE);
197
198 h_offset = window->src.x * bpp;
199 v_offset = window->src.y;
200 h_size = window->src.w * bpp;
201 v_size = window->src.h;
202
203 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
204 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
205
206 /*
207 * For DDA computations the number of bytes per pixel for YUV planar
208 * modes needs to take into account all Y, U and V components.
209 */
210 if (yuv && planar)
211 bpp = 2;
212
213 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
214 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
215
216 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
217 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
218
219 h_dda = compute_initial_dda(window->src.x);
220 v_dda = compute_initial_dda(window->src.y);
221
222 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
223 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
224
225 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
226 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
227
228 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
229
230 if (yuv && planar) {
231 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
232 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
233 value = window->stride[1] << 16 | window->stride[0];
234 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
235 } else {
236 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
237 }
238
239 if (window->bottom_up)
240 v_offset += window->src.h - 1;
241
242 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
243 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
244
c134f019
TR		 245 if (dc->soc->supports_block_linear) {
246 unsigned long height = window->tiling.value;
247
248 switch (window->tiling.mode) {
249 case TEGRA_BO_TILING_MODE_PITCH:
250 value = DC_WINBUF_SURFACE_KIND_PITCH;
251 break;
252
253 case TEGRA_BO_TILING_MODE_TILED:
254 value = DC_WINBUF_SURFACE_KIND_TILED;
255 break;
256
257 case TEGRA_BO_TILING_MODE_BLOCK:
258 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
259 DC_WINBUF_SURFACE_KIND_BLOCK;
260 break;
261 }
262
263 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
10288eea 264 } else {
c134f019
TR		 265 switch (window->tiling.mode) {
266 case TEGRA_BO_TILING_MODE_PITCH:
267 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
268 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
269 break;
10288eea 270
c134f019
TR		 271 case TEGRA_BO_TILING_MODE_TILED:
272 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
273 DC_WIN_BUFFER_ADDR_MODE_TILE;
274 break;
275
276 case TEGRA_BO_TILING_MODE_BLOCK:
277 DRM_ERROR("hardware doesn't support block linear mode\n");
93396d0f 278 spin_unlock_irqrestore(&dc->lock, flags);
c134f019
TR		 279 return -EINVAL;
280 }
281
282 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
283 }
10288eea
TR		 284
285 value = WIN_ENABLE;
286
287 if (yuv) {
288 /* setup default colorspace conversion coefficients */
289 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
290 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
291 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
292 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
293 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
294 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
295 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
296 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
297
298 value |= CSC_ENABLE;
299 } else if (window->bits_per_pixel < 24) {
300 value |= COLOR_EXPAND;
301 }
302
303 if (window->bottom_up)
304 value |= V_DIRECTION;
305
306 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
307
308 /*
309 * Disable blending and assume Window A is the bottom-most window,
310 * Window C is the top-most window and Window B is in the middle.
311 */
312 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
313 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
314
315 switch (index) {
316 case 0:
317 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
318 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
319 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
320 break;
321
322 case 1:
323 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
324 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
325 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
326 break;
327
328 case 2:
329 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
330 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
331 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
332 break;
333 }
334
205d48ed 335 tegra_dc_window_commit(dc, index);
10288eea 336
93396d0f
SP		 337 spin_unlock_irqrestore(&dc->lock, flags);
338
10288eea
TR		 339 return 0;
340}
341
c7679306
TR		 342static int tegra_window_plane_disable(struct drm_plane *plane)
343{
344 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
345 struct tegra_plane *p = to_tegra_plane(plane);
93396d0f 346 unsigned long flags;
c7679306
TR		 347 u32 value;
348
349 if (!plane->crtc)
350 return 0;
351
93396d0f
SP		 352 spin_lock_irqsave(&dc->lock, flags);
353
c7679306
TR		 354 value = WINDOW_A_SELECT << p->index;
355 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
356
357 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
358 value &= ~WIN_ENABLE;
359 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
360
361 tegra_dc_window_commit(dc, p->index);
362
93396d0f
SP		 363 spin_unlock_irqrestore(&dc->lock, flags);
364
c7679306
TR		 365 return 0;
366}
367
368static void tegra_plane_destroy(struct drm_plane *plane)
369{
370 struct tegra_plane *p = to_tegra_plane(plane);
371
372 drm_plane_cleanup(plane);
373 kfree(p);
374}
375
376static const u32 tegra_primary_plane_formats[] = {
377 DRM_FORMAT_XBGR8888,
378 DRM_FORMAT_XRGB8888,
379 DRM_FORMAT_RGB565,
380};
381
382static int tegra_primary_plane_update(struct drm_plane *plane,
383 struct drm_crtc *crtc,
384 struct drm_framebuffer *fb, int crtc_x,
385 int crtc_y, unsigned int crtc_w,
386 unsigned int crtc_h, uint32_t src_x,
387 uint32_t src_y, uint32_t src_w,
388 uint32_t src_h)
389{
390 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
391 struct tegra_plane *p = to_tegra_plane(plane);
392 struct tegra_dc *dc = to_tegra_dc(crtc);
393 struct tegra_dc_window window;
394 int err;
395
396 memset(&window, 0, sizeof(window));
397 window.src.x = src_x >> 16;
398 window.src.y = src_y >> 16;
399 window.src.w = src_w >> 16;
400 window.src.h = src_h >> 16;
401 window.dst.x = crtc_x;
402 window.dst.y = crtc_y;
403 window.dst.w = crtc_w;
404 window.dst.h = crtc_h;
405 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
406 window.bits_per_pixel = fb->bits_per_pixel;
407 window.bottom_up = tegra_fb_is_bottom_up(fb);
408
409 err = tegra_fb_get_tiling(fb, &window.tiling);
410 if (err < 0)
411 return err;
412
413 window.base[0] = bo->paddr + fb->offsets[0];
414 window.stride[0] = fb->pitches[0];
415
416 err = tegra_dc_setup_window(dc, p->index, &window);
417 if (err < 0)
418 return err;
10288eea
TR		 419
420 return 0;
421}
422
c7679306
TR		 423static void tegra_primary_plane_destroy(struct drm_plane *plane)
424{
425 tegra_window_plane_disable(plane);
426 tegra_plane_destroy(plane);
427}
428
429static const struct drm_plane_funcs tegra_primary_plane_funcs = {
430 .update_plane = tegra_primary_plane_update,
431 .disable_plane = tegra_window_plane_disable,
432 .destroy = tegra_primary_plane_destroy,
433};
434
435static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
436 struct tegra_dc *dc)
437{
438 struct tegra_plane *plane;
439 unsigned int num_formats;
440 const u32 *formats;
441 int err;
442
443 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
444 if (!plane)
445 return ERR_PTR(-ENOMEM);
446
447 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
448 formats = tegra_primary_plane_formats;
449
450 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
451 &tegra_primary_plane_funcs, formats,
452 num_formats, DRM_PLANE_TYPE_PRIMARY);
453 if (err < 0) {
454 kfree(plane);
455 return ERR_PTR(err);
456 }
457
458 return &plane->base;
459}
460
461static const u32 tegra_cursor_plane_formats[] = {
462 DRM_FORMAT_RGBA8888,
463};
464
465static int tegra_cursor_plane_update(struct drm_plane *plane,
466 struct drm_crtc *crtc,
467 struct drm_framebuffer *fb, int crtc_x,
468 int crtc_y, unsigned int crtc_w,
469 unsigned int crtc_h, uint32_t src_x,
470 uint32_t src_y, uint32_t src_w,
471 uint32_t src_h)
472{
473 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
474 struct tegra_dc *dc = to_tegra_dc(crtc);
475 u32 value = CURSOR_CLIP_DISPLAY;
476
477 /* scaling not supported for cursor */
478 if ((src_w >> 16 != crtc_w) || (src_h >> 16 != crtc_h))
479 return -EINVAL;
480
481 /* only square cursors supported */
482 if (src_w != src_h)
483 return -EINVAL;
484
485 switch (crtc_w) {
486 case 32:
487 value |= CURSOR_SIZE_32x32;
488 break;
489
490 case 64:
491 value |= CURSOR_SIZE_64x64;
492 break;
493
494 case 128:
495 value |= CURSOR_SIZE_128x128;
496 break;
497
498 case 256:
499 value |= CURSOR_SIZE_256x256;
500 break;
501
502 default:
503 return -EINVAL;
504 }
505
506 value |= (bo->paddr >> 10) & 0x3fffff;
507 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
508
509#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
510 value = (bo->paddr >> 32) & 0x3;
511 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
512#endif
513
514 /* enable cursor and set blend mode */
515 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
516 value |= CURSOR_ENABLE;
517 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
518
519 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
520 value &= ~CURSOR_DST_BLEND_MASK;
521 value &= ~CURSOR_SRC_BLEND_MASK;
522 value |= CURSOR_MODE_NORMAL;
523 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
524 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
525 value |= CURSOR_ALPHA;
526 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
527
528 /* position the cursor */
529 value = (crtc_y & 0x3fff) << 16 | (crtc_x & 0x3fff);
530 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
531
532 /* apply changes */
533 tegra_dc_cursor_commit(dc);
534 tegra_dc_commit(dc);
535
536 return 0;
537}
538
539static int tegra_cursor_plane_disable(struct drm_plane *plane)
540{
541 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
542 u32 value;
543
544 if (!plane->crtc)
545 return 0;
546
547 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
548 value &= ~CURSOR_ENABLE;
549 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
550
551 tegra_dc_cursor_commit(dc);
552 tegra_dc_commit(dc);
553
554 return 0;
555}
556
557static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
558 .update_plane = tegra_cursor_plane_update,
559 .disable_plane = tegra_cursor_plane_disable,
560 .destroy = tegra_plane_destroy,
561};
562
563static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
564 struct tegra_dc *dc)
565{
566 struct tegra_plane *plane;
567 unsigned int num_formats;
568 const u32 *formats;
569 int err;
570
571 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
572 if (!plane)
573 return ERR_PTR(-ENOMEM);
574
575 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
576 formats = tegra_cursor_plane_formats;
577
578 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
579 &tegra_cursor_plane_funcs, formats,
580 num_formats, DRM_PLANE_TYPE_CURSOR);
581 if (err < 0) {
582 kfree(plane);
583 return ERR_PTR(err);
584 }
585
586 return &plane->base;
587}
588
589static int tegra_overlay_plane_update(struct drm_plane *plane,
590 struct drm_crtc *crtc,
591 struct drm_framebuffer *fb, int crtc_x,
592 int crtc_y, unsigned int crtc_w,
593 unsigned int crtc_h, uint32_t src_x,
594 uint32_t src_y, uint32_t src_w,
595 uint32_t src_h)
f34bc787
TR		 596{
597 struct tegra_plane *p = to_tegra_plane(plane);
598 struct tegra_dc *dc = to_tegra_dc(crtc);
599 struct tegra_dc_window window;
600 unsigned int i;
c134f019 601 int err;
f34bc787
TR		 602
603 memset(&window, 0, sizeof(window));
604 window.src.x = src_x >> 16;
605 window.src.y = src_y >> 16;
606 window.src.w = src_w >> 16;
607 window.src.h = src_h >> 16;
608 window.dst.x = crtc_x;
609 window.dst.y = crtc_y;
610 window.dst.w = crtc_w;
611 window.dst.h = crtc_h;
f925390e 612 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
f34bc787 613 window.bits_per_pixel = fb->bits_per_pixel;
db7fbdfd 614 window.bottom_up = tegra_fb_is_bottom_up(fb);
c134f019
TR		 615
616 err = tegra_fb_get_tiling(fb, &window.tiling);
617 if (err < 0)
618 return err;
f34bc787
TR		 619
620 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 621 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 622
de2ba664 623 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 624
625 /*
626 * Tegra doesn't support different strides for U and V planes
627 * so we display a warning if the user tries to display a
628 * framebuffer with such a configuration.
629 */
630 if (i >= 2) {
631 if (fb->pitches[i] != window.stride[1])
632 DRM_ERROR("unsupported UV-plane configuration\n");
633 } else {
634 window.stride[i] = fb->pitches[i];
635 }
636 }
637
638 return tegra_dc_setup_window(dc, p->index, &window);
639}
640
c7679306 641static void tegra_overlay_plane_destroy(struct drm_plane *plane)
f34bc787 642{
c7679306
TR		 643 tegra_window_plane_disable(plane);
644 tegra_plane_destroy(plane);
f34bc787
TR		 645}
646
c7679306
TR		 647static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
648 .update_plane = tegra_overlay_plane_update,
649 .disable_plane = tegra_window_plane_disable,
650 .destroy = tegra_overlay_plane_destroy,
f34bc787
TR		 651};
652
c7679306 653static const uint32_t tegra_overlay_plane_formats[] = {
dbe4d9a7 654 DRM_FORMAT_XBGR8888,
f34bc787 655 DRM_FORMAT_XRGB8888,
dbe4d9a7 656 DRM_FORMAT_RGB565,
f34bc787 657 DRM_FORMAT_UYVY,
f925390e 658 DRM_FORMAT_YUYV,
f34bc787
TR		 659 DRM_FORMAT_YUV420,
660 DRM_FORMAT_YUV422,
661};
662
c7679306
TR		 663static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
664 struct tegra_dc *dc,
665 unsigned int index)
f34bc787 666{
c7679306
TR		 667 struct tegra_plane *plane;
668 unsigned int num_formats;
669 const u32 *formats;
670 int err;
f34bc787 671
c7679306
TR		 672 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
673 if (!plane)
674 return ERR_PTR(-ENOMEM);
f34bc787 675
c7679306 676 plane->index = index;
f34bc787 677
c7679306
TR		 678 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
679 formats = tegra_overlay_plane_formats;
f34bc787 680
c7679306
TR		 681 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
682 &tegra_overlay_plane_funcs, formats,
683 num_formats, DRM_PLANE_TYPE_OVERLAY);
684 if (err < 0) {
685 kfree(plane);
686 return ERR_PTR(err);
687 }
688
689 return &plane->base;
690}
691
692static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
693{
694 struct drm_plane *plane;
695 unsigned int i;
696
697 for (i = 0; i < 2; i++) {
698 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
699 if (IS_ERR(plane))
700 return PTR_ERR(plane);
f34bc787
TR		 701 }
702
703 return 0;
704}
705
23fb4740
TR		 706static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
707 struct drm_framebuffer *fb)
708{
de2ba664 709 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
db7fbdfd 710 unsigned int h_offset = 0, v_offset = 0;
c134f019 711 struct tegra_bo_tiling tiling;
93396d0f 712 unsigned long value, flags;
f925390e 713 unsigned int format, swap;
c134f019
TR		 714 int err;
715
716 err = tegra_fb_get_tiling(fb, &tiling);
717 if (err < 0)
718 return err;
23fb4740 719
93396d0f
SP		 720 spin_lock_irqsave(&dc->lock, flags);
721
23fb4740
TR		 722 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
723
724 value = fb->offsets[0] + y * fb->pitches[0] +
725 x * fb->bits_per_pixel / 8;
726
de2ba664 727 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740 728 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
f925390e
TR		 729
730 format = tegra_dc_format(fb->pixel_format, &swap);
ed683aea 731 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
f925390e 732 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
23fb4740 733
c134f019
TR		 734 if (dc->soc->supports_block_linear) {
735 unsigned long height = tiling.value;
736
737 switch (tiling.mode) {
738 case TEGRA_BO_TILING_MODE_PITCH:
739 value = DC_WINBUF_SURFACE_KIND_PITCH;
740 break;
741
742 case TEGRA_BO_TILING_MODE_TILED:
743 value = DC_WINBUF_SURFACE_KIND_TILED;
744 break;
745
746 case TEGRA_BO_TILING_MODE_BLOCK:
747 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
748 DC_WINBUF_SURFACE_KIND_BLOCK;
749 break;
750 }
751
752 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
773af77f 753 } else {
c134f019
TR		 754 switch (tiling.mode) {
755 case TEGRA_BO_TILING_MODE_PITCH:
756 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
757 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
758 break;
773af77f 759
c134f019
TR		 760 case TEGRA_BO_TILING_MODE_TILED:
761 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
762 DC_WIN_BUFFER_ADDR_MODE_TILE;
763 break;
764
765 case TEGRA_BO_TILING_MODE_BLOCK:
766 DRM_ERROR("hardware doesn't support block linear mode\n");
93396d0f 767 spin_unlock_irqrestore(&dc->lock, flags);
c134f019
TR		 768 return -EINVAL;
769 }
770
771 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
772 }
773af77f 773
db7fbdfd
TR		 774 /* make sure bottom-up buffers are properly displayed */
775 if (tegra_fb_is_bottom_up(fb)) {
776 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 777 value |= V_DIRECTION;
db7fbdfd
TR		 778 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
779
780 v_offset += fb->height - 1;
781 } else {
782 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 783 value &= ~V_DIRECTION;
db7fbdfd
TR		 784 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
785 }
786
787 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
788 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
789
23fb4740 790 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
205d48ed 791 tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
23fb4740
TR		 792 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
793
93396d0f
SP		 794 spin_unlock_irqrestore(&dc->lock, flags);
795
23fb4740
TR		 796 return 0;
797}
798
6e5ff998
TR		 799void tegra_dc_enable_vblank(struct tegra_dc *dc)
800{
801 unsigned long value, flags;
802
803 spin_lock_irqsave(&dc->lock, flags);
804
805 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
806 value |= VBLANK_INT;
807 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
808
809 spin_unlock_irqrestore(&dc->lock, flags);
810}
811
812void tegra_dc_disable_vblank(struct tegra_dc *dc)
813{
814 unsigned long value, flags;
815
816 spin_lock_irqsave(&dc->lock, flags);
817
818 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
819 value &= ~VBLANK_INT;
820 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
821
822 spin_unlock_irqrestore(&dc->lock, flags);
823}
824
3c03c46a
TR		 825static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
826{
827 struct drm_device *drm = dc->base.dev;
828 struct drm_crtc *crtc = &dc->base;
3c03c46a 829 unsigned long flags, base;
de2ba664 830 struct tegra_bo *bo;
3c03c46a 831
6b59cc1c
TR		 832 spin_lock_irqsave(&drm->event_lock, flags);
833
834 if (!dc->event) {
835 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a 836 return;
6b59cc1c 837 }
3c03c46a 838
f4510a27 839 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a 840
93396d0f
SP		 841 spin_lock_irqsave(&dc->lock, flags);
842
3c03c46a 843 /* check if new start address has been latched */
93396d0f 844 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
3c03c46a
TR		 845 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
846 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
847 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
848
93396d0f
SP		 849 spin_unlock_irqrestore(&dc->lock, flags);
850
f4510a27 851 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
ed7dae58
TR		 852 drm_crtc_send_vblank_event(crtc, dc->event);
853 drm_crtc_vblank_put(crtc);
3c03c46a 854 dc->event = NULL;
3c03c46a 855 }
6b59cc1c
TR		 856
857 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a
TR		 858}
859
860void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
861{
862 struct tegra_dc *dc = to_tegra_dc(crtc);
863 struct drm_device *drm = crtc->dev;
864 unsigned long flags;
865
866 spin_lock_irqsave(&drm->event_lock, flags);
867
868 if (dc->event && dc->event->base.file_priv == file) {
869 dc->event->base.destroy(&dc->event->base);
ed7dae58 870 drm_crtc_vblank_put(crtc);
3c03c46a
TR		 871 dc->event = NULL;
872 }
873
874 spin_unlock_irqrestore(&drm->event_lock, flags);
875}
876
877static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
a5b6f74e 878 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
3c03c46a 879{
ed7dae58 880 unsigned int pipe = drm_crtc_index(crtc);
3c03c46a 881 struct tegra_dc *dc = to_tegra_dc(crtc);
3c03c46a
TR		 882
883 if (dc->event)
884 return -EBUSY;
885
886 if (event) {
ed7dae58 887 event->pipe = pipe;
3c03c46a 888 dc->event = event;
ed7dae58 889 drm_crtc_vblank_get(crtc);
3c03c46a
TR		 890 }
891
892 tegra_dc_set_base(dc, 0, 0, fb);
f4510a27 893 crtc->primary->fb = fb;
3c03c46a
TR		 894
895 return 0;
896}
897
f002abc1
TR		 898static void tegra_dc_destroy(struct drm_crtc *crtc)
899{
900 drm_crtc_cleanup(crtc);
f002abc1
TR		 901}
902
d8f4a9ed 903static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 904 .page_flip = tegra_dc_page_flip,
d8f4a9ed 905 .set_config = drm_crtc_helper_set_config,
f002abc1 906 .destroy = tegra_dc_destroy,
d8f4a9ed
TR		 907};
908
f34bc787 909static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 910{
f002abc1 911 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787
TR		 912 struct drm_device *drm = crtc->dev;
913 struct drm_plane *plane;
914
2b4c3661 915 drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
f34bc787 916 if (plane->crtc == crtc) {
c7679306 917 tegra_window_plane_disable(plane);
f34bc787
TR		 918 plane->crtc = NULL;
919
920 if (plane->fb) {
921 drm_framebuffer_unreference(plane->fb);
922 plane->fb = NULL;
923 }
924 }
925 }
f002abc1 926
8ff64c17 927 drm_crtc_vblank_off(crtc);
c7679306 928 tegra_dc_commit(dc);
d8f4a9ed
TR		 929}
930
931static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
932 const struct drm_display_mode *mode,
933 struct drm_display_mode *adjusted)
934{
935 return true;
936}
937
d8f4a9ed
TR		 938static int tegra_dc_set_timings(struct tegra_dc *dc,
939 struct drm_display_mode *mode)
940{
0444c0ff
TR		 941 unsigned int h_ref_to_sync = 1;
942 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 943 unsigned long value;
944
945 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
946
947 value = (v_ref_to_sync << 16) | h_ref_to_sync;
948 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
949
950 value = ((mode->vsync_end - mode->vsync_start) << 16) |
951 ((mode->hsync_end - mode->hsync_start) << 0);
952 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
953
d8f4a9ed
TR		 954 value = ((mode->vtotal - mode->vsync_end) << 16) |
955 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 956 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
957
958 value = ((mode->vsync_start - mode->vdisplay) << 16) |
959 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 960 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
961
962 value = (mode->vdisplay << 16) | mode->hdisplay;
963 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
964
965 return 0;
966}
967
968static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
dbb3f2f7 969 struct drm_display_mode *mode)
d8f4a9ed 970{
91eded9b 971 unsigned long pclk = mode->clock * 1000;
d8f4a9ed
TR		 972 struct tegra_dc *dc = to_tegra_dc(crtc);
973 struct tegra_output *output = NULL;
974 struct drm_encoder *encoder;
dbb3f2f7
TR		 975 unsigned int div;
976 u32 value;
d8f4a9ed
TR		 977 long err;
978
979 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
980 if (encoder->crtc == crtc) {
981 output = encoder_to_output(encoder);
982 break;
983 }
984
985 if (!output)
986 return -ENODEV;
987
988 /*
91eded9b
TR		 989 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
990 * respectively, each of which divides the base pll_d by 2.
d8f4a9ed 991 */
91eded9b 992 err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
d8f4a9ed
TR		 993 if (err < 0) {
994 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
995 return err;
996 }
997
91eded9b 998 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
d8f4a9ed 999
dbb3f2f7
TR		 1000 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
1001 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
d8f4a9ed
TR		 1002
1003 return 0;
1004}
1005
1006static int tegra_crtc_mode_set(struct drm_crtc *crtc,
1007 struct drm_display_mode *mode,
1008 struct drm_display_mode *adjusted,
1009 int x, int y, struct drm_framebuffer *old_fb)
1010{
f4510a27 1011 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
d8f4a9ed 1012 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 1013 struct tegra_dc_window window;
dbb3f2f7 1014 u32 value;
d8f4a9ed
TR		 1015 int err;
1016
dbb3f2f7 1017 err = tegra_crtc_setup_clk(crtc, mode);
d8f4a9ed
TR		 1018 if (err) {
1019 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
1020 return err;
1021 }
1022
1023 /* program display mode */
1024 tegra_dc_set_timings(dc, mode);
1025
8620fc62
TR		 1026 /* interlacing isn't supported yet, so disable it */
1027 if (dc->soc->supports_interlacing) {
1028 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1029 value &= ~INTERLACE_ENABLE;
1030 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1031 }
1032
d8f4a9ed 1033 /* setup window parameters */
f34bc787
TR		 1034 memset(&window, 0, sizeof(window));
1035 window.src.x = 0;
1036 window.src.y = 0;
1037 window.src.w = mode->hdisplay;
1038 window.src.h = mode->vdisplay;
1039 window.dst.x = 0;
1040 window.dst.y = 0;
1041 window.dst.w = mode->hdisplay;
1042 window.dst.h = mode->vdisplay;
f925390e
TR		 1043 window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
1044 &window.swap);
f4510a27
MR		 1045 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
1046 window.stride[0] = crtc->primary->fb->pitches[0];
de2ba664 1047 window.base[0] = bo->paddr;
f34bc787
TR		 1048
1049 err = tegra_dc_setup_window(dc, 0, &window);
1050 if (err < 0)
1051 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 1052
d8f4a9ed
TR		 1053 return 0;
1054}
d8f4a9ed 1055
23fb4740
TR		 1056static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1057 struct drm_framebuffer *old_fb)
1058{
1059 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 1060
f4510a27 1061 return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
d8f4a9ed
TR		 1062}
1063
1064static void tegra_crtc_prepare(struct drm_crtc *crtc)
1065{
1066 struct tegra_dc *dc = to_tegra_dc(crtc);
1067 unsigned int syncpt;
1068 unsigned long value;
1069
8ff64c17
TR		 1070 drm_crtc_vblank_off(crtc);
1071
d8f4a9ed 1072 /* hardware initialization */
ca48080a 1073 reset_control_deassert(dc->rst);
d8f4a9ed
TR		 1074 usleep_range(10000, 20000);
1075
1076 if (dc->pipe)
1077 syncpt = SYNCPT_VBLANK1;
1078 else
1079 syncpt = SYNCPT_VBLANK0;
1080
1081 /* initialize display controller */
1082 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1083 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1084
1085 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1086 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1087
1088 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1089 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1090 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1091
d8f4a9ed
TR		 1092 /* initialize timer */
1093 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1094 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1095 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1096
1097 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1098 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1099 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1100
d8f4a9ed
TR		 1101 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1102 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 1103
1104 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1105 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 1106}
1107
1108static void tegra_crtc_commit(struct drm_crtc *crtc)
1109{
1110 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 1111
8ff64c17 1112 drm_crtc_vblank_on(crtc);
205d48ed 1113 tegra_dc_commit(dc);
d8f4a9ed
TR		 1114}
1115
d8f4a9ed 1116static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 1117 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 1118 .mode_fixup = tegra_crtc_mode_fixup,
1119 .mode_set = tegra_crtc_mode_set,
23fb4740 1120 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 1121 .prepare = tegra_crtc_prepare,
1122 .commit = tegra_crtc_commit,
d8f4a9ed
TR		 1123};
1124
6e5ff998 1125static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 1126{
1127 struct tegra_dc *dc = data;
1128 unsigned long status;
1129
1130 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1131 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1132
1133 if (status & FRAME_END_INT) {
1134 /*
1135 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1136 */
1137 }
1138
1139 if (status & VBLANK_INT) {
1140 /*
1141 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1142 */
ed7dae58 1143 drm_crtc_handle_vblank(&dc->base);
3c03c46a 1144 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 1145 }
1146
1147 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1148 /*
1149 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1150 */
1151 }
1152
1153 return IRQ_HANDLED;
1154}
1155
1156static int tegra_dc_show_regs(struct seq_file *s, void *data)
1157{
1158 struct drm_info_node *node = s->private;
1159 struct tegra_dc *dc = node->info_ent->data;
1160
1161#define DUMP_REG(name) \
03a60569 1162 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
d8f4a9ed
TR		 1163 tegra_dc_readl(dc, name))
1164
1165 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1166 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1167 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1168 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1169 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1170 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1171 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1172 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1173 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1174 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1175 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1176 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1177 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1178 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1179 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1180 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1181 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1182 DUMP_REG(DC_CMD_INT_STATUS);
1183 DUMP_REG(DC_CMD_INT_MASK);
1184 DUMP_REG(DC_CMD_INT_ENABLE);
1185 DUMP_REG(DC_CMD_INT_TYPE);
1186 DUMP_REG(DC_CMD_INT_POLARITY);
1187 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1188 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1189 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1190 DUMP_REG(DC_CMD_STATE_ACCESS);
1191 DUMP_REG(DC_CMD_STATE_CONTROL);
1192 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1193 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1194 DUMP_REG(DC_COM_CRC_CONTROL);
1195 DUMP_REG(DC_COM_CRC_CHECKSUM);
1196 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1197 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1198 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1199 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1200 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1201 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1202 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1203 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1204 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1205 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1206 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1207 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1208 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1209 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1210 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1211 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1212 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1213 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1214 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1215 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1216 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1217 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1218 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1219 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1220 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1221 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1222 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1223 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1224 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1225 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1226 DUMP_REG(DC_COM_SPI_CONTROL);
1227 DUMP_REG(DC_COM_SPI_START_BYTE);
1228 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1229 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1230 DUMP_REG(DC_COM_HSPI_CS_DC);
1231 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1232 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1233 DUMP_REG(DC_COM_GPIO_CTRL);
1234 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1235 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1236 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1237 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1238 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1239 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1240 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1241 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1242 DUMP_REG(DC_DISP_REF_TO_SYNC);
1243 DUMP_REG(DC_DISP_SYNC_WIDTH);
1244 DUMP_REG(DC_DISP_BACK_PORCH);
1245 DUMP_REG(DC_DISP_ACTIVE);
1246 DUMP_REG(DC_DISP_FRONT_PORCH);
1247 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1248 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1249 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1250 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1251 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1252 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1253 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1254 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1255 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1256 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1257 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1258 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1259 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1260 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1261 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1262 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1263 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1264 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1265 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1266 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1267 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1268 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1269 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1270 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1271 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1272 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1273 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1274 DUMP_REG(DC_DISP_M0_CONTROL);
1275 DUMP_REG(DC_DISP_M1_CONTROL);
1276 DUMP_REG(DC_DISP_DI_CONTROL);
1277 DUMP_REG(DC_DISP_PP_CONTROL);
1278 DUMP_REG(DC_DISP_PP_SELECT_A);
1279 DUMP_REG(DC_DISP_PP_SELECT_B);
1280 DUMP_REG(DC_DISP_PP_SELECT_C);
1281 DUMP_REG(DC_DISP_PP_SELECT_D);
1282 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1283 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1284 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1285 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1286 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1287 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1288 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1289 DUMP_REG(DC_DISP_BORDER_COLOR);
1290 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1291 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1292 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1293 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1294 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1295 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1296 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1297 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1298 DUMP_REG(DC_DISP_CURSOR_POSITION);
1299 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1300 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1301 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1302 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1303 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1304 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1305 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1306 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1307 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1308 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1309 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1310 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1311 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1312 DUMP_REG(DC_DISP_SD_CONTROL);
1313 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1314 DUMP_REG(DC_DISP_SD_LUT(0));
1315 DUMP_REG(DC_DISP_SD_LUT(1));
1316 DUMP_REG(DC_DISP_SD_LUT(2));
1317 DUMP_REG(DC_DISP_SD_LUT(3));
1318 DUMP_REG(DC_DISP_SD_LUT(4));
1319 DUMP_REG(DC_DISP_SD_LUT(5));
1320 DUMP_REG(DC_DISP_SD_LUT(6));
1321 DUMP_REG(DC_DISP_SD_LUT(7));
1322 DUMP_REG(DC_DISP_SD_LUT(8));
1323 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1324 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1325 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1326 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1327 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1328 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1329 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1330 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1331 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1332 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1333 DUMP_REG(DC_DISP_SD_BL_TF(0));
1334 DUMP_REG(DC_DISP_SD_BL_TF(1));
1335 DUMP_REG(DC_DISP_SD_BL_TF(2));
1336 DUMP_REG(DC_DISP_SD_BL_TF(3));
1337 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1338 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1339 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
e687651b
TR		 1340 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1341 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
d8f4a9ed
TR		 1342 DUMP_REG(DC_WIN_WIN_OPTIONS);
1343 DUMP_REG(DC_WIN_BYTE_SWAP);
1344 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1345 DUMP_REG(DC_WIN_COLOR_DEPTH);
1346 DUMP_REG(DC_WIN_POSITION);
1347 DUMP_REG(DC_WIN_SIZE);
1348 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1349 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1350 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1351 DUMP_REG(DC_WIN_DDA_INC);
1352 DUMP_REG(DC_WIN_LINE_STRIDE);
1353 DUMP_REG(DC_WIN_BUF_STRIDE);
1354 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1355 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1356 DUMP_REG(DC_WIN_DV_CONTROL);
1357 DUMP_REG(DC_WIN_BLEND_NOKEY);
1358 DUMP_REG(DC_WIN_BLEND_1WIN);
1359 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1360 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1361 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1362 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1363 DUMP_REG(DC_WINBUF_START_ADDR);
1364 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1365 DUMP_REG(DC_WINBUF_START_ADDR_U);
1366 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1367 DUMP_REG(DC_WINBUF_START_ADDR_V);
1368 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1369 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1370 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1371 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1372 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1373 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1374 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1375 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1376 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1377
1378#undef DUMP_REG
1379
1380 return 0;
1381}
1382
1383static struct drm_info_list debugfs_files[] = {
1384 { "regs", tegra_dc_show_regs, 0, NULL },
1385};
1386
1387static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1388{
1389 unsigned int i;
1390 char *name;
1391 int err;
1392
1393 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1394 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1395 kfree(name);
1396
1397 if (!dc->debugfs)
1398 return -ENOMEM;
1399
1400 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1401 GFP_KERNEL);
1402 if (!dc->debugfs_files) {
1403 err = -ENOMEM;
1404 goto remove;
1405 }
1406
1407 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1408 dc->debugfs_files[i].data = dc;
1409
1410 err = drm_debugfs_create_files(dc->debugfs_files,
1411 ARRAY_SIZE(debugfs_files),
1412 dc->debugfs, minor);
1413 if (err < 0)
1414 goto free;
1415
1416 dc->minor = minor;
1417
1418 return 0;
1419
1420free:
1421 kfree(dc->debugfs_files);
1422 dc->debugfs_files = NULL;
1423remove:
1424 debugfs_remove(dc->debugfs);
1425 dc->debugfs = NULL;
1426
1427 return err;
1428}
1429
1430static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1431{
1432 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1433 dc->minor);
1434 dc->minor = NULL;
1435
1436 kfree(dc->debugfs_files);
1437 dc->debugfs_files = NULL;
1438
1439 debugfs_remove(dc->debugfs);
1440 dc->debugfs = NULL;
1441
1442 return 0;
1443}
1444
53fa7f72 1445static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1446{
9910f5c4 1447 struct drm_device *drm = dev_get_drvdata(client->parent);
776dc384 1448 struct tegra_dc *dc = host1x_client_to_dc(client);
d1f3e1e0 1449 struct tegra_drm *tegra = drm->dev_private;
c7679306
TR		 1450 struct drm_plane *primary = NULL;
1451 struct drm_plane *cursor = NULL;
d8f4a9ed
TR		 1452 int err;
1453
df06b759
TR		 1454 if (tegra->domain) {
1455 err = iommu_attach_device(tegra->domain, dc->dev);
1456 if (err < 0) {
1457 dev_err(dc->dev, "failed to attach to domain: %d\n",
1458 err);
1459 return err;
1460 }
1461
1462 dc->domain = tegra->domain;
1463 }
1464
c7679306
TR		 1465 primary = tegra_dc_primary_plane_create(drm, dc);
1466 if (IS_ERR(primary)) {
1467 err = PTR_ERR(primary);
1468 goto cleanup;
1469 }
1470
1471 if (dc->soc->supports_cursor) {
1472 cursor = tegra_dc_cursor_plane_create(drm, dc);
1473 if (IS_ERR(cursor)) {
1474 err = PTR_ERR(cursor);
1475 goto cleanup;
1476 }
1477 }
1478
1479 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1480 &tegra_crtc_funcs);
1481 if (err < 0)
1482 goto cleanup;
1483
d8f4a9ed
TR		 1484 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1485 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1486
d1f3e1e0
TR		 1487 /*
1488 * Keep track of the minimum pitch alignment across all display
1489 * controllers.
1490 */
1491 if (dc->soc->pitch_align > tegra->pitch_align)
1492 tegra->pitch_align = dc->soc->pitch_align;
1493
9910f5c4 1494 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1495 if (err < 0 && err != -ENODEV) {
1496 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
c7679306 1497 goto cleanup;
d8f4a9ed
TR		 1498 }
1499
9910f5c4 1500 err = tegra_dc_add_planes(drm, dc);
f34bc787 1501 if (err < 0)
c7679306 1502 goto cleanup;
f34bc787 1503
d8f4a9ed 1504 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1505 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1506 if (err < 0)
1507 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1508 }
1509
6e5ff998 1510 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1511 dev_name(dc->dev), dc);
1512 if (err < 0) {
1513 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1514 err);
c7679306 1515 goto cleanup;
d8f4a9ed
TR		 1516 }
1517
1518 return 0;
c7679306
TR		 1519
1520cleanup:
1521 if (cursor)
1522 drm_plane_cleanup(cursor);
1523
1524 if (primary)
1525 drm_plane_cleanup(primary);
1526
1527 if (tegra->domain) {
1528 iommu_detach_device(tegra->domain, dc->dev);
1529 dc->domain = NULL;
1530 }
1531
1532 return err;
d8f4a9ed
TR		 1533}
1534
53fa7f72 1535static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1536{
776dc384 1537 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1538 int err;
1539
1540 devm_free_irq(dc->dev, dc->irq, dc);
1541
1542 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1543 err = tegra_dc_debugfs_exit(dc);
1544 if (err < 0)
1545 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1546 }
1547
1548 err = tegra_dc_rgb_exit(dc);
1549 if (err) {
1550 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1551 return err;
1552 }
1553
df06b759
TR		 1554 if (dc->domain) {
1555 iommu_detach_device(dc->domain, dc->dev);
1556 dc->domain = NULL;
1557 }
1558
d8f4a9ed
TR		 1559 return 0;
1560}
1561
1562static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1563 .init = tegra_dc_init,
1564 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1565};
1566
8620fc62
TR		 1567static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1568 .supports_interlacing = false,
e687651b 1569 .supports_cursor = false,
c134f019 1570 .supports_block_linear = false,
d1f3e1e0 1571 .pitch_align = 8,
9c012700 1572 .has_powergate = false,
8620fc62
TR		 1573};
1574
1575static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1576 .supports_interlacing = false,
e687651b 1577 .supports_cursor = false,
c134f019 1578 .supports_block_linear = false,
d1f3e1e0 1579 .pitch_align = 8,
9c012700 1580 .has_powergate = false,
d1f3e1e0
TR		 1581};
1582
1583static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1584 .supports_interlacing = false,
1585 .supports_cursor = false,
1586 .supports_block_linear = false,
1587 .pitch_align = 64,
9c012700 1588 .has_powergate = true,
8620fc62
TR		 1589};
1590
1591static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1592 .supports_interlacing = true,
e687651b 1593 .supports_cursor = true,
c134f019 1594 .supports_block_linear = true,
d1f3e1e0 1595 .pitch_align = 64,
9c012700 1596 .has_powergate = true,
8620fc62
TR		 1597};
1598
1599static const struct of_device_id tegra_dc_of_match[] = {
1600 {
1601 .compatible = "nvidia,tegra124-dc",
1602 .data = &tegra124_dc_soc_info,
9c012700
TR		 1603 }, {
1604 .compatible = "nvidia,tegra114-dc",
1605 .data = &tegra114_dc_soc_info,
8620fc62
TR		 1606 }, {
1607 .compatible = "nvidia,tegra30-dc",
1608 .data = &tegra30_dc_soc_info,
1609 }, {
1610 .compatible = "nvidia,tegra20-dc",
1611 .data = &tegra20_dc_soc_info,
1612 }, {
1613 /* sentinel */
1614 }
1615};
ef70728c 1616MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
8620fc62 1617
13411ddd
TR		 1618static int tegra_dc_parse_dt(struct tegra_dc *dc)
1619{
1620 struct device_node *np;
1621 u32 value = 0;
1622 int err;
1623
1624 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1625 if (err < 0) {
1626 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1627
1628 /*
1629 * If the nvidia,head property isn't present, try to find the
1630 * correct head number by looking up the position of this
1631 * display controller's node within the device tree. Assuming
1632 * that the nodes are ordered properly in the DTS file and
1633 * that the translation into a flattened device tree blob
1634 * preserves that ordering this will actually yield the right
1635 * head number.
1636 *
1637 * If those assumptions don't hold, this will still work for
1638 * cases where only a single display controller is used.
1639 */
1640 for_each_matching_node(np, tegra_dc_of_match) {
1641 if (np == dc->dev->of_node)
1642 break;
1643
1644 value++;
1645 }
1646 }
1647
1648 dc->pipe = value;
1649
1650 return 0;
1651}
1652
d8f4a9ed
TR		 1653static int tegra_dc_probe(struct platform_device *pdev)
1654{
8620fc62 1655 const struct of_device_id *id;
d8f4a9ed
TR		 1656 struct resource *regs;
1657 struct tegra_dc *dc;
1658 int err;
1659
1660 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1661 if (!dc)
1662 return -ENOMEM;
1663
8620fc62
TR		 1664 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1665 if (!id)
1666 return -ENODEV;
1667
6e5ff998 1668 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1669 INIT_LIST_HEAD(&dc->list);
1670 dc->dev = &pdev->dev;
8620fc62 1671 dc->soc = id->data;
d8f4a9ed 1672
13411ddd
TR		 1673 err = tegra_dc_parse_dt(dc);
1674 if (err < 0)
1675 return err;
1676
d8f4a9ed
TR		 1677 dc->clk = devm_clk_get(&pdev->dev, NULL);
1678 if (IS_ERR(dc->clk)) {
1679 dev_err(&pdev->dev, "failed to get clock\n");
1680 return PTR_ERR(dc->clk);
1681 }
1682
ca48080a
SW		 1683 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1684 if (IS_ERR(dc->rst)) {
1685 dev_err(&pdev->dev, "failed to get reset\n");
1686 return PTR_ERR(dc->rst);
1687 }
1688
9c012700
TR		 1689 if (dc->soc->has_powergate) {
1690 if (dc->pipe == 0)
1691 dc->powergate = TEGRA_POWERGATE_DIS;
1692 else
1693 dc->powergate = TEGRA_POWERGATE_DISB;
1694
1695 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1696 dc->rst);
1697 if (err < 0) {
1698 dev_err(&pdev->dev, "failed to power partition: %d\n",
1699 err);
1700 return err;
1701 }
1702 } else {
1703 err = clk_prepare_enable(dc->clk);
1704 if (err < 0) {
1705 dev_err(&pdev->dev, "failed to enable clock: %d\n",
1706 err);
1707 return err;
1708 }
1709
1710 err = reset_control_deassert(dc->rst);
1711 if (err < 0) {
1712 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
1713 err);
1714 return err;
1715 }
1716 }
d8f4a9ed
TR		 1717
1718 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1719 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1720 if (IS_ERR(dc->regs))
1721 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1722
1723 dc->irq = platform_get_irq(pdev, 0);
1724 if (dc->irq < 0) {
1725 dev_err(&pdev->dev, "failed to get IRQ\n");
1726 return -ENXIO;
1727 }
1728
776dc384
TR		 1729 INIT_LIST_HEAD(&dc->client.list);
1730 dc->client.ops = &dc_client_ops;
1731 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 1732
1733 err = tegra_dc_rgb_probe(dc);
1734 if (err < 0 && err != -ENODEV) {
1735 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1736 return err;
1737 }
1738
776dc384 1739 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 1740 if (err < 0) {
1741 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1742 err);
1743 return err;
1744 }
1745
1746 platform_set_drvdata(pdev, dc);
1747
1748 return 0;
1749}
1750
1751static int tegra_dc_remove(struct platform_device *pdev)
1752{
d8f4a9ed
TR		 1753 struct tegra_dc *dc = platform_get_drvdata(pdev);
1754 int err;
1755
776dc384 1756 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 1757 if (err < 0) {
1758 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1759 err);
1760 return err;
1761 }
1762
59d29c0e
TR		 1763 err = tegra_dc_rgb_remove(dc);
1764 if (err < 0) {
1765 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1766 return err;
1767 }
1768
5482d75a 1769 reset_control_assert(dc->rst);
9c012700
TR		 1770
1771 if (dc->soc->has_powergate)
1772 tegra_powergate_power_off(dc->powergate);
1773
d8f4a9ed
TR		 1774 clk_disable_unprepare(dc->clk);
1775
1776 return 0;
1777}
1778
d8f4a9ed
TR		 1779struct platform_driver tegra_dc_driver = {
1780 .driver = {
1781 .name = "tegra-dc",
1782 .owner = THIS_MODULE,
1783 .of_match_table = tegra_dc_of_match,
1784 },
1785 .probe = tegra_dc_probe,
1786 .remove = tegra_dc_remove,
1787};
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