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Commit | Line | Data |
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d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
9eb9b220 | 11 | #include <linux/debugfs.h> |
df06b759 | 12 | #include <linux/iommu.h> |
ca48080a | 13 | #include <linux/reset.h> |
d8f4a9ed | 14 | |
9c012700 TR |
15 | #include <soc/tegra/pmc.h> |
16 | ||
de2ba664 AM |
17 | #include "dc.h" |
18 | #include "drm.h" | |
19 | #include "gem.h" | |
d8f4a9ed | 20 | |
9d44189f | 21 | #include <drm/drm_atomic.h> |
4aa3df71 | 22 | #include <drm/drm_atomic_helper.h> |
3cb9ae4f DV |
23 | #include <drm/drm_plane_helper.h> |
24 | ||
8620fc62 | 25 | struct tegra_dc_soc_info { |
42d0659b | 26 | bool supports_border_color; |
8620fc62 | 27 | bool supports_interlacing; |
e687651b | 28 | bool supports_cursor; |
c134f019 | 29 | bool supports_block_linear; |
d1f3e1e0 | 30 | unsigned int pitch_align; |
9c012700 | 31 | bool has_powergate; |
8620fc62 TR |
32 | }; |
33 | ||
f34bc787 TR |
34 | struct tegra_plane { |
35 | struct drm_plane base; | |
36 | unsigned int index; | |
d8f4a9ed TR |
37 | }; |
38 | ||
f34bc787 TR |
39 | static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) |
40 | { | |
41 | return container_of(plane, struct tegra_plane, base); | |
42 | } | |
43 | ||
ca915b10 TR |
44 | struct tegra_dc_state { |
45 | struct drm_crtc_state base; | |
46 | ||
47 | struct clk *clk; | |
48 | unsigned long pclk; | |
49 | unsigned int div; | |
47802b09 TR |
50 | |
51 | u32 planes; | |
ca915b10 TR |
52 | }; |
53 | ||
54 | static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) | |
55 | { | |
56 | if (state) | |
57 | return container_of(state, struct tegra_dc_state, base); | |
58 | ||
59 | return NULL; | |
60 | } | |
61 | ||
8f604f8c TR |
62 | struct tegra_plane_state { |
63 | struct drm_plane_state base; | |
64 | ||
65 | struct tegra_bo_tiling tiling; | |
66 | u32 format; | |
67 | u32 swap; | |
68 | }; | |
69 | ||
70 | static inline struct tegra_plane_state * | |
71 | to_tegra_plane_state(struct drm_plane_state *state) | |
72 | { | |
73 | if (state) | |
74 | return container_of(state, struct tegra_plane_state, base); | |
75 | ||
76 | return NULL; | |
77 | } | |
78 | ||
86df256f TR |
79 | /* |
80 | * Reads the active copy of a register. This takes the dc->lock spinlock to | |
81 | * prevent races with the VBLANK processing which also needs access to the | |
82 | * active copy of some registers. | |
83 | */ | |
84 | static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) | |
85 | { | |
86 | unsigned long flags; | |
87 | u32 value; | |
88 | ||
89 | spin_lock_irqsave(&dc->lock, flags); | |
90 | ||
91 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); | |
92 | value = tegra_dc_readl(dc, offset); | |
93 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
94 | ||
95 | spin_unlock_irqrestore(&dc->lock, flags); | |
96 | return value; | |
97 | } | |
98 | ||
d700ba7a TR |
99 | /* |
100 | * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the | |
101 | * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. | |
102 | * Latching happens mmediately if the display controller is in STOP mode or | |
103 | * on the next frame boundary otherwise. | |
104 | * | |
105 | * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The | |
106 | * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits | |
107 | * are written. When the *_ACT_REQ bits are written, the ARM copy is latched | |
108 | * into the ACTIVE copy, either immediately if the display controller is in | |
109 | * STOP mode, or at the next frame boundary otherwise. | |
110 | */ | |
62b9e063 | 111 | void tegra_dc_commit(struct tegra_dc *dc) |
205d48ed TR |
112 | { |
113 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
114 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); | |
115 | } | |
116 | ||
8f604f8c | 117 | static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap) |
10288eea TR |
118 | { |
119 | /* assume no swapping of fetched data */ | |
120 | if (swap) | |
121 | *swap = BYTE_SWAP_NOSWAP; | |
122 | ||
8f604f8c | 123 | switch (fourcc) { |
10288eea | 124 | case DRM_FORMAT_XBGR8888: |
8f604f8c TR |
125 | *format = WIN_COLOR_DEPTH_R8G8B8A8; |
126 | break; | |
10288eea TR |
127 | |
128 | case DRM_FORMAT_XRGB8888: | |
8f604f8c TR |
129 | *format = WIN_COLOR_DEPTH_B8G8R8A8; |
130 | break; | |
10288eea TR |
131 | |
132 | case DRM_FORMAT_RGB565: | |
8f604f8c TR |
133 | *format = WIN_COLOR_DEPTH_B5G6R5; |
134 | break; | |
10288eea TR |
135 | |
136 | case DRM_FORMAT_UYVY: | |
8f604f8c TR |
137 | *format = WIN_COLOR_DEPTH_YCbCr422; |
138 | break; | |
10288eea TR |
139 | |
140 | case DRM_FORMAT_YUYV: | |
141 | if (swap) | |
142 | *swap = BYTE_SWAP_SWAP2; | |
143 | ||
8f604f8c TR |
144 | *format = WIN_COLOR_DEPTH_YCbCr422; |
145 | break; | |
10288eea TR |
146 | |
147 | case DRM_FORMAT_YUV420: | |
8f604f8c TR |
148 | *format = WIN_COLOR_DEPTH_YCbCr420P; |
149 | break; | |
10288eea TR |
150 | |
151 | case DRM_FORMAT_YUV422: | |
8f604f8c TR |
152 | *format = WIN_COLOR_DEPTH_YCbCr422P; |
153 | break; | |
10288eea TR |
154 | |
155 | default: | |
8f604f8c | 156 | return -EINVAL; |
10288eea TR |
157 | } |
158 | ||
8f604f8c | 159 | return 0; |
10288eea TR |
160 | } |
161 | ||
162 | static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) | |
163 | { | |
164 | switch (format) { | |
165 | case WIN_COLOR_DEPTH_YCbCr422: | |
166 | case WIN_COLOR_DEPTH_YUV422: | |
167 | if (planar) | |
168 | *planar = false; | |
169 | ||
170 | return true; | |
171 | ||
172 | case WIN_COLOR_DEPTH_YCbCr420P: | |
173 | case WIN_COLOR_DEPTH_YUV420P: | |
174 | case WIN_COLOR_DEPTH_YCbCr422P: | |
175 | case WIN_COLOR_DEPTH_YUV422P: | |
176 | case WIN_COLOR_DEPTH_YCbCr422R: | |
177 | case WIN_COLOR_DEPTH_YUV422R: | |
178 | case WIN_COLOR_DEPTH_YCbCr422RA: | |
179 | case WIN_COLOR_DEPTH_YUV422RA: | |
180 | if (planar) | |
181 | *planar = true; | |
182 | ||
183 | return true; | |
184 | } | |
185 | ||
fb35c6b6 TR |
186 | if (planar) |
187 | *planar = false; | |
188 | ||
10288eea TR |
189 | return false; |
190 | } | |
191 | ||
192 | static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, | |
193 | unsigned int bpp) | |
194 | { | |
195 | fixed20_12 outf = dfixed_init(out); | |
196 | fixed20_12 inf = dfixed_init(in); | |
197 | u32 dda_inc; | |
198 | int max; | |
199 | ||
200 | if (v) | |
201 | max = 15; | |
202 | else { | |
203 | switch (bpp) { | |
204 | case 2: | |
205 | max = 8; | |
206 | break; | |
207 | ||
208 | default: | |
209 | WARN_ON_ONCE(1); | |
210 | /* fallthrough */ | |
211 | case 4: | |
212 | max = 4; | |
213 | break; | |
214 | } | |
215 | } | |
216 | ||
217 | outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); | |
218 | inf.full -= dfixed_const(1); | |
219 | ||
220 | dda_inc = dfixed_div(inf, outf); | |
221 | dda_inc = min_t(u32, dda_inc, dfixed_const(max)); | |
222 | ||
223 | return dda_inc; | |
224 | } | |
225 | ||
226 | static inline u32 compute_initial_dda(unsigned int in) | |
227 | { | |
228 | fixed20_12 inf = dfixed_init(in); | |
229 | return dfixed_frac(inf); | |
230 | } | |
231 | ||
4aa3df71 TR |
232 | static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, |
233 | const struct tegra_dc_window *window) | |
10288eea TR |
234 | { |
235 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; | |
93396d0f | 236 | unsigned long value, flags; |
10288eea TR |
237 | bool yuv, planar; |
238 | ||
239 | /* | |
240 | * For YUV planar modes, the number of bytes per pixel takes into | |
241 | * account only the luma component and therefore is 1. | |
242 | */ | |
243 | yuv = tegra_dc_format_is_yuv(window->format, &planar); | |
244 | if (!yuv) | |
245 | bpp = window->bits_per_pixel / 8; | |
246 | else | |
247 | bpp = planar ? 1 : 2; | |
248 | ||
93396d0f SP |
249 | spin_lock_irqsave(&dc->lock, flags); |
250 | ||
10288eea TR |
251 | value = WINDOW_A_SELECT << index; |
252 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
253 | ||
254 | tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); | |
255 | tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); | |
256 | ||
257 | value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); | |
258 | tegra_dc_writel(dc, value, DC_WIN_POSITION); | |
259 | ||
260 | value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); | |
261 | tegra_dc_writel(dc, value, DC_WIN_SIZE); | |
262 | ||
263 | h_offset = window->src.x * bpp; | |
264 | v_offset = window->src.y; | |
265 | h_size = window->src.w * bpp; | |
266 | v_size = window->src.h; | |
267 | ||
268 | value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); | |
269 | tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); | |
270 | ||
271 | /* | |
272 | * For DDA computations the number of bytes per pixel for YUV planar | |
273 | * modes needs to take into account all Y, U and V components. | |
274 | */ | |
275 | if (yuv && planar) | |
276 | bpp = 2; | |
277 | ||
278 | h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); | |
279 | v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); | |
280 | ||
281 | value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); | |
282 | tegra_dc_writel(dc, value, DC_WIN_DDA_INC); | |
283 | ||
284 | h_dda = compute_initial_dda(window->src.x); | |
285 | v_dda = compute_initial_dda(window->src.y); | |
286 | ||
287 | tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); | |
288 | tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); | |
289 | ||
290 | tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); | |
291 | tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); | |
292 | ||
293 | tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); | |
294 | ||
295 | if (yuv && planar) { | |
296 | tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); | |
297 | tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); | |
298 | value = window->stride[1] << 16 | window->stride[0]; | |
299 | tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); | |
300 | } else { | |
301 | tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); | |
302 | } | |
303 | ||
304 | if (window->bottom_up) | |
305 | v_offset += window->src.h - 1; | |
306 | ||
307 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
308 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
309 | ||
c134f019 TR |
310 | if (dc->soc->supports_block_linear) { |
311 | unsigned long height = window->tiling.value; | |
312 | ||
313 | switch (window->tiling.mode) { | |
314 | case TEGRA_BO_TILING_MODE_PITCH: | |
315 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
316 | break; | |
317 | ||
318 | case TEGRA_BO_TILING_MODE_TILED: | |
319 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
320 | break; | |
321 | ||
322 | case TEGRA_BO_TILING_MODE_BLOCK: | |
323 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
324 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
325 | break; | |
326 | } | |
327 | ||
328 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
10288eea | 329 | } else { |
c134f019 TR |
330 | switch (window->tiling.mode) { |
331 | case TEGRA_BO_TILING_MODE_PITCH: | |
332 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
333 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
334 | break; | |
10288eea | 335 | |
c134f019 TR |
336 | case TEGRA_BO_TILING_MODE_TILED: |
337 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
338 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
339 | break; | |
340 | ||
341 | case TEGRA_BO_TILING_MODE_BLOCK: | |
4aa3df71 TR |
342 | /* |
343 | * No need to handle this here because ->atomic_check | |
344 | * will already have filtered it out. | |
345 | */ | |
346 | break; | |
c134f019 TR |
347 | } |
348 | ||
349 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
350 | } | |
10288eea TR |
351 | |
352 | value = WIN_ENABLE; | |
353 | ||
354 | if (yuv) { | |
355 | /* setup default colorspace conversion coefficients */ | |
356 | tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); | |
357 | tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); | |
358 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); | |
359 | tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); | |
360 | tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); | |
361 | tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); | |
362 | tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); | |
363 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); | |
364 | ||
365 | value |= CSC_ENABLE; | |
366 | } else if (window->bits_per_pixel < 24) { | |
367 | value |= COLOR_EXPAND; | |
368 | } | |
369 | ||
370 | if (window->bottom_up) | |
371 | value |= V_DIRECTION; | |
372 | ||
373 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
374 | ||
375 | /* | |
376 | * Disable blending and assume Window A is the bottom-most window, | |
377 | * Window C is the top-most window and Window B is in the middle. | |
378 | */ | |
379 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); | |
380 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); | |
381 | ||
382 | switch (index) { | |
383 | case 0: | |
384 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); | |
385 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
386 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
387 | break; | |
388 | ||
389 | case 1: | |
390 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
391 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
392 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
393 | break; | |
394 | ||
395 | case 2: | |
396 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
397 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); | |
398 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); | |
399 | break; | |
400 | } | |
401 | ||
93396d0f | 402 | spin_unlock_irqrestore(&dc->lock, flags); |
c7679306 TR |
403 | } |
404 | ||
405 | static void tegra_plane_destroy(struct drm_plane *plane) | |
406 | { | |
407 | struct tegra_plane *p = to_tegra_plane(plane); | |
408 | ||
409 | drm_plane_cleanup(plane); | |
410 | kfree(p); | |
411 | } | |
412 | ||
413 | static const u32 tegra_primary_plane_formats[] = { | |
414 | DRM_FORMAT_XBGR8888, | |
415 | DRM_FORMAT_XRGB8888, | |
416 | DRM_FORMAT_RGB565, | |
417 | }; | |
418 | ||
4aa3df71 | 419 | static void tegra_primary_plane_destroy(struct drm_plane *plane) |
c7679306 | 420 | { |
4aa3df71 TR |
421 | tegra_plane_destroy(plane); |
422 | } | |
423 | ||
8f604f8c TR |
424 | static void tegra_plane_reset(struct drm_plane *plane) |
425 | { | |
426 | struct tegra_plane_state *state; | |
427 | ||
3b59b7ac TR |
428 | if (plane->state) |
429 | __drm_atomic_helper_plane_destroy_state(plane, plane->state); | |
8f604f8c TR |
430 | |
431 | kfree(plane->state); | |
432 | plane->state = NULL; | |
433 | ||
434 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
435 | if (state) { | |
436 | plane->state = &state->base; | |
437 | plane->state->plane = plane; | |
438 | } | |
439 | } | |
440 | ||
441 | static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane) | |
442 | { | |
443 | struct tegra_plane_state *state = to_tegra_plane_state(plane->state); | |
444 | struct tegra_plane_state *copy; | |
445 | ||
3b59b7ac | 446 | copy = kmalloc(sizeof(*copy), GFP_KERNEL); |
8f604f8c TR |
447 | if (!copy) |
448 | return NULL; | |
449 | ||
3b59b7ac TR |
450 | __drm_atomic_helper_plane_duplicate_state(plane, ©->base); |
451 | copy->tiling = state->tiling; | |
452 | copy->format = state->format; | |
453 | copy->swap = state->swap; | |
8f604f8c TR |
454 | |
455 | return ©->base; | |
456 | } | |
457 | ||
458 | static void tegra_plane_atomic_destroy_state(struct drm_plane *plane, | |
459 | struct drm_plane_state *state) | |
460 | { | |
3b59b7ac | 461 | __drm_atomic_helper_plane_destroy_state(plane, state); |
8f604f8c TR |
462 | kfree(state); |
463 | } | |
464 | ||
4aa3df71 | 465 | static const struct drm_plane_funcs tegra_primary_plane_funcs = { |
07866963 TR |
466 | .update_plane = drm_atomic_helper_update_plane, |
467 | .disable_plane = drm_atomic_helper_disable_plane, | |
4aa3df71 | 468 | .destroy = tegra_primary_plane_destroy, |
8f604f8c TR |
469 | .reset = tegra_plane_reset, |
470 | .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, | |
471 | .atomic_destroy_state = tegra_plane_atomic_destroy_state, | |
4aa3df71 TR |
472 | }; |
473 | ||
474 | static int tegra_plane_prepare_fb(struct drm_plane *plane, | |
d136dfee TU |
475 | struct drm_framebuffer *fb, |
476 | const struct drm_plane_state *new_state) | |
4aa3df71 TR |
477 | { |
478 | return 0; | |
479 | } | |
480 | ||
481 | static void tegra_plane_cleanup_fb(struct drm_plane *plane, | |
d136dfee TU |
482 | struct drm_framebuffer *fb, |
483 | const struct drm_plane_state *old_fb) | |
4aa3df71 TR |
484 | { |
485 | } | |
486 | ||
47802b09 TR |
487 | static int tegra_plane_state_add(struct tegra_plane *plane, |
488 | struct drm_plane_state *state) | |
489 | { | |
490 | struct drm_crtc_state *crtc_state; | |
491 | struct tegra_dc_state *tegra; | |
492 | ||
493 | /* Propagate errors from allocation or locking failures. */ | |
494 | crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); | |
495 | if (IS_ERR(crtc_state)) | |
496 | return PTR_ERR(crtc_state); | |
497 | ||
498 | tegra = to_dc_state(crtc_state); | |
499 | ||
500 | tegra->planes |= WIN_A_ACT_REQ << plane->index; | |
501 | ||
502 | return 0; | |
503 | } | |
504 | ||
4aa3df71 TR |
505 | static int tegra_plane_atomic_check(struct drm_plane *plane, |
506 | struct drm_plane_state *state) | |
507 | { | |
8f604f8c TR |
508 | struct tegra_plane_state *plane_state = to_tegra_plane_state(state); |
509 | struct tegra_bo_tiling *tiling = &plane_state->tiling; | |
47802b09 | 510 | struct tegra_plane *tegra = to_tegra_plane(plane); |
4aa3df71 | 511 | struct tegra_dc *dc = to_tegra_dc(state->crtc); |
4aa3df71 TR |
512 | int err; |
513 | ||
514 | /* no need for further checks if the plane is being disabled */ | |
515 | if (!state->crtc) | |
516 | return 0; | |
517 | ||
8f604f8c TR |
518 | err = tegra_dc_format(state->fb->pixel_format, &plane_state->format, |
519 | &plane_state->swap); | |
4aa3df71 TR |
520 | if (err < 0) |
521 | return err; | |
522 | ||
8f604f8c TR |
523 | err = tegra_fb_get_tiling(state->fb, tiling); |
524 | if (err < 0) | |
525 | return err; | |
526 | ||
527 | if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && | |
4aa3df71 TR |
528 | !dc->soc->supports_block_linear) { |
529 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
530 | return -EINVAL; | |
531 | } | |
532 | ||
533 | /* | |
534 | * Tegra doesn't support different strides for U and V planes so we | |
535 | * error out if the user tries to display a framebuffer with such a | |
536 | * configuration. | |
537 | */ | |
538 | if (drm_format_num_planes(state->fb->pixel_format) > 2) { | |
539 | if (state->fb->pitches[2] != state->fb->pitches[1]) { | |
540 | DRM_ERROR("unsupported UV-plane configuration\n"); | |
541 | return -EINVAL; | |
542 | } | |
543 | } | |
544 | ||
47802b09 TR |
545 | err = tegra_plane_state_add(tegra, state); |
546 | if (err < 0) | |
547 | return err; | |
548 | ||
4aa3df71 TR |
549 | return 0; |
550 | } | |
551 | ||
552 | static void tegra_plane_atomic_update(struct drm_plane *plane, | |
553 | struct drm_plane_state *old_state) | |
554 | { | |
8f604f8c | 555 | struct tegra_plane_state *state = to_tegra_plane_state(plane->state); |
4aa3df71 TR |
556 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); |
557 | struct drm_framebuffer *fb = plane->state->fb; | |
c7679306 | 558 | struct tegra_plane *p = to_tegra_plane(plane); |
c7679306 | 559 | struct tegra_dc_window window; |
4aa3df71 | 560 | unsigned int i; |
c7679306 | 561 | |
4aa3df71 TR |
562 | /* rien ne va plus */ |
563 | if (!plane->state->crtc || !plane->state->fb) | |
564 | return; | |
565 | ||
c7679306 | 566 | memset(&window, 0, sizeof(window)); |
4aa3df71 TR |
567 | window.src.x = plane->state->src_x >> 16; |
568 | window.src.y = plane->state->src_y >> 16; | |
569 | window.src.w = plane->state->src_w >> 16; | |
570 | window.src.h = plane->state->src_h >> 16; | |
571 | window.dst.x = plane->state->crtc_x; | |
572 | window.dst.y = plane->state->crtc_y; | |
573 | window.dst.w = plane->state->crtc_w; | |
574 | window.dst.h = plane->state->crtc_h; | |
c7679306 TR |
575 | window.bits_per_pixel = fb->bits_per_pixel; |
576 | window.bottom_up = tegra_fb_is_bottom_up(fb); | |
577 | ||
8f604f8c TR |
578 | /* copy from state */ |
579 | window.tiling = state->tiling; | |
580 | window.format = state->format; | |
581 | window.swap = state->swap; | |
c7679306 | 582 | |
4aa3df71 TR |
583 | for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { |
584 | struct tegra_bo *bo = tegra_fb_get_plane(fb, i); | |
c7679306 | 585 | |
4aa3df71 TR |
586 | window.base[i] = bo->paddr + fb->offsets[i]; |
587 | window.stride[i] = fb->pitches[i]; | |
588 | } | |
10288eea | 589 | |
4aa3df71 | 590 | tegra_dc_setup_window(dc, p->index, &window); |
10288eea TR |
591 | } |
592 | ||
4aa3df71 TR |
593 | static void tegra_plane_atomic_disable(struct drm_plane *plane, |
594 | struct drm_plane_state *old_state) | |
c7679306 | 595 | { |
4aa3df71 TR |
596 | struct tegra_plane *p = to_tegra_plane(plane); |
597 | struct tegra_dc *dc; | |
598 | unsigned long flags; | |
599 | u32 value; | |
600 | ||
601 | /* rien ne va plus */ | |
602 | if (!old_state || !old_state->crtc) | |
603 | return; | |
604 | ||
605 | dc = to_tegra_dc(old_state->crtc); | |
606 | ||
607 | spin_lock_irqsave(&dc->lock, flags); | |
608 | ||
609 | value = WINDOW_A_SELECT << p->index; | |
610 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
611 | ||
612 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
613 | value &= ~WIN_ENABLE; | |
614 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
615 | ||
4aa3df71 | 616 | spin_unlock_irqrestore(&dc->lock, flags); |
c7679306 TR |
617 | } |
618 | ||
4aa3df71 TR |
619 | static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = { |
620 | .prepare_fb = tegra_plane_prepare_fb, | |
621 | .cleanup_fb = tegra_plane_cleanup_fb, | |
622 | .atomic_check = tegra_plane_atomic_check, | |
623 | .atomic_update = tegra_plane_atomic_update, | |
624 | .atomic_disable = tegra_plane_atomic_disable, | |
c7679306 TR |
625 | }; |
626 | ||
627 | static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, | |
628 | struct tegra_dc *dc) | |
629 | { | |
518e6227 TR |
630 | /* |
631 | * Ideally this would use drm_crtc_mask(), but that would require the | |
632 | * CRTC to already be in the mode_config's list of CRTCs. However, it | |
633 | * will only be added to that list in the drm_crtc_init_with_planes() | |
634 | * (in tegra_dc_init()), which in turn requires registration of these | |
635 | * planes. So we have ourselves a nice little chicken and egg problem | |
636 | * here. | |
637 | * | |
638 | * We work around this by manually creating the mask from the number | |
639 | * of CRTCs that have been registered, and should therefore always be | |
640 | * the same as drm_crtc_index() after registration. | |
641 | */ | |
642 | unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc; | |
c7679306 TR |
643 | struct tegra_plane *plane; |
644 | unsigned int num_formats; | |
645 | const u32 *formats; | |
646 | int err; | |
647 | ||
648 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
649 | if (!plane) | |
650 | return ERR_PTR(-ENOMEM); | |
651 | ||
652 | num_formats = ARRAY_SIZE(tegra_primary_plane_formats); | |
653 | formats = tegra_primary_plane_formats; | |
654 | ||
518e6227 | 655 | err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, |
c7679306 TR |
656 | &tegra_primary_plane_funcs, formats, |
657 | num_formats, DRM_PLANE_TYPE_PRIMARY); | |
658 | if (err < 0) { | |
659 | kfree(plane); | |
660 | return ERR_PTR(err); | |
661 | } | |
662 | ||
4aa3df71 TR |
663 | drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs); |
664 | ||
c7679306 TR |
665 | return &plane->base; |
666 | } | |
667 | ||
668 | static const u32 tegra_cursor_plane_formats[] = { | |
669 | DRM_FORMAT_RGBA8888, | |
670 | }; | |
671 | ||
4aa3df71 TR |
672 | static int tegra_cursor_atomic_check(struct drm_plane *plane, |
673 | struct drm_plane_state *state) | |
c7679306 | 674 | { |
47802b09 TR |
675 | struct tegra_plane *tegra = to_tegra_plane(plane); |
676 | int err; | |
677 | ||
4aa3df71 TR |
678 | /* no need for further checks if the plane is being disabled */ |
679 | if (!state->crtc) | |
680 | return 0; | |
c7679306 TR |
681 | |
682 | /* scaling not supported for cursor */ | |
4aa3df71 TR |
683 | if ((state->src_w >> 16 != state->crtc_w) || |
684 | (state->src_h >> 16 != state->crtc_h)) | |
c7679306 TR |
685 | return -EINVAL; |
686 | ||
687 | /* only square cursors supported */ | |
4aa3df71 TR |
688 | if (state->src_w != state->src_h) |
689 | return -EINVAL; | |
690 | ||
691 | if (state->crtc_w != 32 && state->crtc_w != 64 && | |
692 | state->crtc_w != 128 && state->crtc_w != 256) | |
c7679306 TR |
693 | return -EINVAL; |
694 | ||
47802b09 TR |
695 | err = tegra_plane_state_add(tegra, state); |
696 | if (err < 0) | |
697 | return err; | |
698 | ||
4aa3df71 TR |
699 | return 0; |
700 | } | |
701 | ||
702 | static void tegra_cursor_atomic_update(struct drm_plane *plane, | |
703 | struct drm_plane_state *old_state) | |
704 | { | |
705 | struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0); | |
706 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); | |
707 | struct drm_plane_state *state = plane->state; | |
708 | u32 value = CURSOR_CLIP_DISPLAY; | |
709 | ||
710 | /* rien ne va plus */ | |
711 | if (!plane->state->crtc || !plane->state->fb) | |
712 | return; | |
713 | ||
714 | switch (state->crtc_w) { | |
c7679306 TR |
715 | case 32: |
716 | value |= CURSOR_SIZE_32x32; | |
717 | break; | |
718 | ||
719 | case 64: | |
720 | value |= CURSOR_SIZE_64x64; | |
721 | break; | |
722 | ||
723 | case 128: | |
724 | value |= CURSOR_SIZE_128x128; | |
725 | break; | |
726 | ||
727 | case 256: | |
728 | value |= CURSOR_SIZE_256x256; | |
729 | break; | |
730 | ||
731 | default: | |
4aa3df71 TR |
732 | WARN(1, "cursor size %ux%u not supported\n", state->crtc_w, |
733 | state->crtc_h); | |
734 | return; | |
c7679306 TR |
735 | } |
736 | ||
737 | value |= (bo->paddr >> 10) & 0x3fffff; | |
738 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); | |
739 | ||
740 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
741 | value = (bo->paddr >> 32) & 0x3; | |
742 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); | |
743 | #endif | |
744 | ||
745 | /* enable cursor and set blend mode */ | |
746 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
747 | value |= CURSOR_ENABLE; | |
748 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
749 | ||
750 | value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); | |
751 | value &= ~CURSOR_DST_BLEND_MASK; | |
752 | value &= ~CURSOR_SRC_BLEND_MASK; | |
753 | value |= CURSOR_MODE_NORMAL; | |
754 | value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; | |
755 | value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; | |
756 | value |= CURSOR_ALPHA; | |
757 | tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); | |
758 | ||
759 | /* position the cursor */ | |
4aa3df71 | 760 | value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff); |
c7679306 TR |
761 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); |
762 | ||
c7679306 TR |
763 | } |
764 | ||
4aa3df71 TR |
765 | static void tegra_cursor_atomic_disable(struct drm_plane *plane, |
766 | struct drm_plane_state *old_state) | |
c7679306 | 767 | { |
4aa3df71 | 768 | struct tegra_dc *dc; |
c7679306 TR |
769 | u32 value; |
770 | ||
4aa3df71 TR |
771 | /* rien ne va plus */ |
772 | if (!old_state || !old_state->crtc) | |
773 | return; | |
774 | ||
775 | dc = to_tegra_dc(old_state->crtc); | |
c7679306 TR |
776 | |
777 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
778 | value &= ~CURSOR_ENABLE; | |
779 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
c7679306 TR |
780 | } |
781 | ||
782 | static const struct drm_plane_funcs tegra_cursor_plane_funcs = { | |
07866963 TR |
783 | .update_plane = drm_atomic_helper_update_plane, |
784 | .disable_plane = drm_atomic_helper_disable_plane, | |
c7679306 | 785 | .destroy = tegra_plane_destroy, |
8f604f8c TR |
786 | .reset = tegra_plane_reset, |
787 | .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, | |
788 | .atomic_destroy_state = tegra_plane_atomic_destroy_state, | |
4aa3df71 TR |
789 | }; |
790 | ||
791 | static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { | |
792 | .prepare_fb = tegra_plane_prepare_fb, | |
793 | .cleanup_fb = tegra_plane_cleanup_fb, | |
794 | .atomic_check = tegra_cursor_atomic_check, | |
795 | .atomic_update = tegra_cursor_atomic_update, | |
796 | .atomic_disable = tegra_cursor_atomic_disable, | |
c7679306 TR |
797 | }; |
798 | ||
799 | static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, | |
800 | struct tegra_dc *dc) | |
801 | { | |
802 | struct tegra_plane *plane; | |
803 | unsigned int num_formats; | |
804 | const u32 *formats; | |
805 | int err; | |
806 | ||
807 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
808 | if (!plane) | |
809 | return ERR_PTR(-ENOMEM); | |
810 | ||
47802b09 TR |
811 | /* |
812 | * We'll treat the cursor as an overlay plane with index 6 here so | |
813 | * that the update and activation request bits in DC_CMD_STATE_CONTROL | |
814 | * match up. | |
815 | */ | |
816 | plane->index = 6; | |
817 | ||
c7679306 TR |
818 | num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); |
819 | formats = tegra_cursor_plane_formats; | |
820 | ||
821 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, | |
822 | &tegra_cursor_plane_funcs, formats, | |
823 | num_formats, DRM_PLANE_TYPE_CURSOR); | |
824 | if (err < 0) { | |
825 | kfree(plane); | |
826 | return ERR_PTR(err); | |
827 | } | |
828 | ||
4aa3df71 | 829 | drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); |
f34bc787 | 830 | |
4aa3df71 | 831 | return &plane->base; |
f34bc787 TR |
832 | } |
833 | ||
c7679306 | 834 | static void tegra_overlay_plane_destroy(struct drm_plane *plane) |
f34bc787 | 835 | { |
c7679306 | 836 | tegra_plane_destroy(plane); |
f34bc787 TR |
837 | } |
838 | ||
c7679306 | 839 | static const struct drm_plane_funcs tegra_overlay_plane_funcs = { |
07866963 TR |
840 | .update_plane = drm_atomic_helper_update_plane, |
841 | .disable_plane = drm_atomic_helper_disable_plane, | |
c7679306 | 842 | .destroy = tegra_overlay_plane_destroy, |
8f604f8c TR |
843 | .reset = tegra_plane_reset, |
844 | .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, | |
845 | .atomic_destroy_state = tegra_plane_atomic_destroy_state, | |
f34bc787 TR |
846 | }; |
847 | ||
c7679306 | 848 | static const uint32_t tegra_overlay_plane_formats[] = { |
dbe4d9a7 | 849 | DRM_FORMAT_XBGR8888, |
f34bc787 | 850 | DRM_FORMAT_XRGB8888, |
dbe4d9a7 | 851 | DRM_FORMAT_RGB565, |
f34bc787 | 852 | DRM_FORMAT_UYVY, |
f925390e | 853 | DRM_FORMAT_YUYV, |
f34bc787 TR |
854 | DRM_FORMAT_YUV420, |
855 | DRM_FORMAT_YUV422, | |
856 | }; | |
857 | ||
4aa3df71 TR |
858 | static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = { |
859 | .prepare_fb = tegra_plane_prepare_fb, | |
860 | .cleanup_fb = tegra_plane_cleanup_fb, | |
861 | .atomic_check = tegra_plane_atomic_check, | |
862 | .atomic_update = tegra_plane_atomic_update, | |
863 | .atomic_disable = tegra_plane_atomic_disable, | |
864 | }; | |
865 | ||
c7679306 TR |
866 | static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, |
867 | struct tegra_dc *dc, | |
868 | unsigned int index) | |
f34bc787 | 869 | { |
c7679306 TR |
870 | struct tegra_plane *plane; |
871 | unsigned int num_formats; | |
872 | const u32 *formats; | |
873 | int err; | |
f34bc787 | 874 | |
c7679306 TR |
875 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
876 | if (!plane) | |
877 | return ERR_PTR(-ENOMEM); | |
f34bc787 | 878 | |
c7679306 | 879 | plane->index = index; |
f34bc787 | 880 | |
c7679306 TR |
881 | num_formats = ARRAY_SIZE(tegra_overlay_plane_formats); |
882 | formats = tegra_overlay_plane_formats; | |
f34bc787 | 883 | |
c7679306 TR |
884 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, |
885 | &tegra_overlay_plane_funcs, formats, | |
886 | num_formats, DRM_PLANE_TYPE_OVERLAY); | |
887 | if (err < 0) { | |
888 | kfree(plane); | |
889 | return ERR_PTR(err); | |
890 | } | |
891 | ||
4aa3df71 TR |
892 | drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs); |
893 | ||
c7679306 TR |
894 | return &plane->base; |
895 | } | |
896 | ||
897 | static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) | |
898 | { | |
899 | struct drm_plane *plane; | |
900 | unsigned int i; | |
901 | ||
902 | for (i = 0; i < 2; i++) { | |
903 | plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); | |
904 | if (IS_ERR(plane)) | |
905 | return PTR_ERR(plane); | |
f34bc787 TR |
906 | } |
907 | ||
908 | return 0; | |
909 | } | |
910 | ||
42e9ce05 TR |
911 | u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc) |
912 | { | |
913 | if (dc->syncpt) | |
914 | return host1x_syncpt_read(dc->syncpt); | |
915 | ||
916 | /* fallback to software emulated VBLANK counter */ | |
917 | return drm_crtc_vblank_count(&dc->base); | |
918 | } | |
919 | ||
6e5ff998 TR |
920 | void tegra_dc_enable_vblank(struct tegra_dc *dc) |
921 | { | |
922 | unsigned long value, flags; | |
923 | ||
924 | spin_lock_irqsave(&dc->lock, flags); | |
925 | ||
926 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
927 | value |= VBLANK_INT; | |
928 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
929 | ||
930 | spin_unlock_irqrestore(&dc->lock, flags); | |
931 | } | |
932 | ||
933 | void tegra_dc_disable_vblank(struct tegra_dc *dc) | |
934 | { | |
935 | unsigned long value, flags; | |
936 | ||
937 | spin_lock_irqsave(&dc->lock, flags); | |
938 | ||
939 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
940 | value &= ~VBLANK_INT; | |
941 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
942 | ||
943 | spin_unlock_irqrestore(&dc->lock, flags); | |
944 | } | |
945 | ||
3c03c46a TR |
946 | static void tegra_dc_finish_page_flip(struct tegra_dc *dc) |
947 | { | |
948 | struct drm_device *drm = dc->base.dev; | |
949 | struct drm_crtc *crtc = &dc->base; | |
3c03c46a | 950 | unsigned long flags, base; |
de2ba664 | 951 | struct tegra_bo *bo; |
3c03c46a | 952 | |
6b59cc1c TR |
953 | spin_lock_irqsave(&drm->event_lock, flags); |
954 | ||
955 | if (!dc->event) { | |
956 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a | 957 | return; |
6b59cc1c | 958 | } |
3c03c46a | 959 | |
f4510a27 | 960 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
3c03c46a | 961 | |
8643bc6d | 962 | spin_lock(&dc->lock); |
93396d0f | 963 | |
3c03c46a | 964 | /* check if new start address has been latched */ |
93396d0f | 965 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
3c03c46a TR |
966 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); |
967 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); | |
968 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
969 | ||
8643bc6d | 970 | spin_unlock(&dc->lock); |
93396d0f | 971 | |
f4510a27 | 972 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { |
ed7dae58 TR |
973 | drm_crtc_send_vblank_event(crtc, dc->event); |
974 | drm_crtc_vblank_put(crtc); | |
3c03c46a | 975 | dc->event = NULL; |
3c03c46a | 976 | } |
6b59cc1c TR |
977 | |
978 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a TR |
979 | } |
980 | ||
981 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) | |
982 | { | |
983 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
984 | struct drm_device *drm = crtc->dev; | |
985 | unsigned long flags; | |
986 | ||
987 | spin_lock_irqsave(&drm->event_lock, flags); | |
988 | ||
989 | if (dc->event && dc->event->base.file_priv == file) { | |
990 | dc->event->base.destroy(&dc->event->base); | |
ed7dae58 | 991 | drm_crtc_vblank_put(crtc); |
3c03c46a TR |
992 | dc->event = NULL; |
993 | } | |
994 | ||
995 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
996 | } | |
997 | ||
f002abc1 TR |
998 | static void tegra_dc_destroy(struct drm_crtc *crtc) |
999 | { | |
1000 | drm_crtc_cleanup(crtc); | |
f002abc1 TR |
1001 | } |
1002 | ||
ca915b10 TR |
1003 | static void tegra_crtc_reset(struct drm_crtc *crtc) |
1004 | { | |
1005 | struct tegra_dc_state *state; | |
1006 | ||
3b59b7ac TR |
1007 | if (crtc->state) |
1008 | __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state); | |
1009 | ||
ca915b10 TR |
1010 | kfree(crtc->state); |
1011 | crtc->state = NULL; | |
1012 | ||
1013 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
332bbe70 | 1014 | if (state) { |
ca915b10 | 1015 | crtc->state = &state->base; |
332bbe70 TR |
1016 | crtc->state->crtc = crtc; |
1017 | } | |
ca915b10 TR |
1018 | } |
1019 | ||
1020 | static struct drm_crtc_state * | |
1021 | tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) | |
1022 | { | |
1023 | struct tegra_dc_state *state = to_dc_state(crtc->state); | |
1024 | struct tegra_dc_state *copy; | |
1025 | ||
3b59b7ac | 1026 | copy = kmalloc(sizeof(*copy), GFP_KERNEL); |
ca915b10 TR |
1027 | if (!copy) |
1028 | return NULL; | |
1029 | ||
3b59b7ac TR |
1030 | __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); |
1031 | copy->clk = state->clk; | |
1032 | copy->pclk = state->pclk; | |
1033 | copy->div = state->div; | |
1034 | copy->planes = state->planes; | |
ca915b10 TR |
1035 | |
1036 | return ©->base; | |
1037 | } | |
1038 | ||
1039 | static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, | |
1040 | struct drm_crtc_state *state) | |
1041 | { | |
3b59b7ac | 1042 | __drm_atomic_helper_crtc_destroy_state(crtc, state); |
ca915b10 TR |
1043 | kfree(state); |
1044 | } | |
1045 | ||
d8f4a9ed | 1046 | static const struct drm_crtc_funcs tegra_crtc_funcs = { |
1503ca47 | 1047 | .page_flip = drm_atomic_helper_page_flip, |
74f48791 | 1048 | .set_config = drm_atomic_helper_set_config, |
f002abc1 | 1049 | .destroy = tegra_dc_destroy, |
ca915b10 TR |
1050 | .reset = tegra_crtc_reset, |
1051 | .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, | |
1052 | .atomic_destroy_state = tegra_crtc_atomic_destroy_state, | |
d8f4a9ed TR |
1053 | }; |
1054 | ||
86df256f TR |
1055 | static void tegra_dc_stop(struct tegra_dc *dc) |
1056 | { | |
1057 | u32 value; | |
1058 | ||
1059 | /* stop the display controller */ | |
1060 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); | |
1061 | value &= ~DISP_CTRL_MODE_MASK; | |
1062 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); | |
1063 | ||
1064 | tegra_dc_commit(dc); | |
1065 | } | |
1066 | ||
1067 | static bool tegra_dc_idle(struct tegra_dc *dc) | |
1068 | { | |
1069 | u32 value; | |
1070 | ||
1071 | value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); | |
1072 | ||
1073 | return (value & DISP_CTRL_MODE_MASK) == 0; | |
1074 | } | |
1075 | ||
1076 | static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) | |
1077 | { | |
1078 | timeout = jiffies + msecs_to_jiffies(timeout); | |
1079 | ||
1080 | while (time_before(jiffies, timeout)) { | |
1081 | if (tegra_dc_idle(dc)) | |
1082 | return 0; | |
1083 | ||
1084 | usleep_range(1000, 2000); | |
1085 | } | |
1086 | ||
1087 | dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); | |
1088 | return -ETIMEDOUT; | |
1089 | } | |
1090 | ||
f34bc787 | 1091 | static void tegra_crtc_disable(struct drm_crtc *crtc) |
d8f4a9ed | 1092 | { |
f002abc1 | 1093 | struct tegra_dc *dc = to_tegra_dc(crtc); |
3b0e5855 | 1094 | u32 value; |
f002abc1 | 1095 | |
86df256f TR |
1096 | if (!tegra_dc_idle(dc)) { |
1097 | tegra_dc_stop(dc); | |
1098 | ||
1099 | /* | |
1100 | * Ignore the return value, there isn't anything useful to do | |
1101 | * in case this fails. | |
1102 | */ | |
1103 | tegra_dc_wait_idle(dc, 100); | |
1104 | } | |
36904adf | 1105 | |
3b0e5855 TR |
1106 | /* |
1107 | * This should really be part of the RGB encoder driver, but clearing | |
1108 | * these bits has the side-effect of stopping the display controller. | |
1109 | * When that happens no VBLANK interrupts will be raised. At the same | |
1110 | * time the encoder is disabled before the display controller, so the | |
1111 | * above code is always going to timeout waiting for the controller | |
1112 | * to go idle. | |
1113 | * | |
1114 | * Given the close coupling between the RGB encoder and the display | |
1115 | * controller doing it here is still kind of okay. None of the other | |
1116 | * encoder drivers require these bits to be cleared. | |
1117 | * | |
1118 | * XXX: Perhaps given that the display controller is switched off at | |
1119 | * this point anyway maybe clearing these bits isn't even useful for | |
1120 | * the RGB encoder? | |
1121 | */ | |
1122 | if (dc->rgb) { | |
1123 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); | |
1124 | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | | |
1125 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); | |
1126 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); | |
1127 | } | |
1128 | ||
8ff64c17 | 1129 | drm_crtc_vblank_off(crtc); |
d8f4a9ed TR |
1130 | } |
1131 | ||
1132 | static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, | |
1133 | const struct drm_display_mode *mode, | |
1134 | struct drm_display_mode *adjusted) | |
1135 | { | |
1136 | return true; | |
1137 | } | |
1138 | ||
d8f4a9ed TR |
1139 | static int tegra_dc_set_timings(struct tegra_dc *dc, |
1140 | struct drm_display_mode *mode) | |
1141 | { | |
0444c0ff TR |
1142 | unsigned int h_ref_to_sync = 1; |
1143 | unsigned int v_ref_to_sync = 1; | |
d8f4a9ed TR |
1144 | unsigned long value; |
1145 | ||
1146 | tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); | |
1147 | ||
1148 | value = (v_ref_to_sync << 16) | h_ref_to_sync; | |
1149 | tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); | |
1150 | ||
1151 | value = ((mode->vsync_end - mode->vsync_start) << 16) | | |
1152 | ((mode->hsync_end - mode->hsync_start) << 0); | |
1153 | tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); | |
1154 | ||
d8f4a9ed TR |
1155 | value = ((mode->vtotal - mode->vsync_end) << 16) | |
1156 | ((mode->htotal - mode->hsync_end) << 0); | |
40495089 LS |
1157 | tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); |
1158 | ||
1159 | value = ((mode->vsync_start - mode->vdisplay) << 16) | | |
1160 | ((mode->hsync_start - mode->hdisplay) << 0); | |
d8f4a9ed TR |
1161 | tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); |
1162 | ||
1163 | value = (mode->vdisplay << 16) | mode->hdisplay; | |
1164 | tegra_dc_writel(dc, value, DC_DISP_ACTIVE); | |
1165 | ||
1166 | return 0; | |
1167 | } | |
1168 | ||
9d910b60 TR |
1169 | /** |
1170 | * tegra_dc_state_setup_clock - check clock settings and store them in atomic | |
1171 | * state | |
1172 | * @dc: display controller | |
1173 | * @crtc_state: CRTC atomic state | |
1174 | * @clk: parent clock for display controller | |
1175 | * @pclk: pixel clock | |
1176 | * @div: shift clock divider | |
1177 | * | |
1178 | * Returns: | |
1179 | * 0 on success or a negative error-code on failure. | |
1180 | */ | |
ca915b10 TR |
1181 | int tegra_dc_state_setup_clock(struct tegra_dc *dc, |
1182 | struct drm_crtc_state *crtc_state, | |
1183 | struct clk *clk, unsigned long pclk, | |
1184 | unsigned int div) | |
1185 | { | |
1186 | struct tegra_dc_state *state = to_dc_state(crtc_state); | |
1187 | ||
d2982748 TR |
1188 | if (!clk_has_parent(dc->clk, clk)) |
1189 | return -EINVAL; | |
1190 | ||
ca915b10 TR |
1191 | state->clk = clk; |
1192 | state->pclk = pclk; | |
1193 | state->div = div; | |
1194 | ||
1195 | return 0; | |
1196 | } | |
1197 | ||
76d59ed0 TR |
1198 | static void tegra_dc_commit_state(struct tegra_dc *dc, |
1199 | struct tegra_dc_state *state) | |
1200 | { | |
1201 | u32 value; | |
1202 | int err; | |
1203 | ||
1204 | err = clk_set_parent(dc->clk, state->clk); | |
1205 | if (err < 0) | |
1206 | dev_err(dc->dev, "failed to set parent clock: %d\n", err); | |
1207 | ||
1208 | /* | |
1209 | * Outputs may not want to change the parent clock rate. This is only | |
1210 | * relevant to Tegra20 where only a single display PLL is available. | |
1211 | * Since that PLL would typically be used for HDMI, an internal LVDS | |
1212 | * panel would need to be driven by some other clock such as PLL_P | |
1213 | * which is shared with other peripherals. Changing the clock rate | |
1214 | * should therefore be avoided. | |
1215 | */ | |
1216 | if (state->pclk > 0) { | |
1217 | err = clk_set_rate(state->clk, state->pclk); | |
1218 | if (err < 0) | |
1219 | dev_err(dc->dev, | |
1220 | "failed to set clock rate to %lu Hz\n", | |
1221 | state->pclk); | |
1222 | } | |
1223 | ||
1224 | DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), | |
1225 | state->div); | |
1226 | DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); | |
1227 | ||
1228 | value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; | |
1229 | tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); | |
1230 | } | |
1231 | ||
4aa3df71 | 1232 | static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc) |
d8f4a9ed | 1233 | { |
4aa3df71 | 1234 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
76d59ed0 | 1235 | struct tegra_dc_state *state = to_dc_state(crtc->state); |
d8f4a9ed | 1236 | struct tegra_dc *dc = to_tegra_dc(crtc); |
dbb3f2f7 | 1237 | u32 value; |
d8f4a9ed | 1238 | |
76d59ed0 TR |
1239 | tegra_dc_commit_state(dc, state); |
1240 | ||
d8f4a9ed TR |
1241 | /* program display mode */ |
1242 | tegra_dc_set_timings(dc, mode); | |
1243 | ||
8620fc62 TR |
1244 | /* interlacing isn't supported yet, so disable it */ |
1245 | if (dc->soc->supports_interlacing) { | |
1246 | value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); | |
1247 | value &= ~INTERLACE_ENABLE; | |
1248 | tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); | |
1249 | } | |
666cb873 TR |
1250 | |
1251 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); | |
1252 | value &= ~DISP_CTRL_MODE_MASK; | |
1253 | value |= DISP_CTRL_MODE_C_DISPLAY; | |
1254 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); | |
1255 | ||
1256 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); | |
1257 | value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | | |
1258 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; | |
1259 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); | |
1260 | ||
1261 | tegra_dc_commit(dc); | |
d8f4a9ed TR |
1262 | } |
1263 | ||
1264 | static void tegra_crtc_prepare(struct drm_crtc *crtc) | |
1265 | { | |
8ff64c17 | 1266 | drm_crtc_vblank_off(crtc); |
d8f4a9ed TR |
1267 | } |
1268 | ||
1269 | static void tegra_crtc_commit(struct drm_crtc *crtc) | |
1270 | { | |
8ff64c17 | 1271 | drm_crtc_vblank_on(crtc); |
d8f4a9ed TR |
1272 | } |
1273 | ||
4aa3df71 TR |
1274 | static int tegra_crtc_atomic_check(struct drm_crtc *crtc, |
1275 | struct drm_crtc_state *state) | |
1276 | { | |
1277 | return 0; | |
1278 | } | |
1279 | ||
1280 | static void tegra_crtc_atomic_begin(struct drm_crtc *crtc) | |
1281 | { | |
1503ca47 TR |
1282 | struct tegra_dc *dc = to_tegra_dc(crtc); |
1283 | ||
1284 | if (crtc->state->event) { | |
1285 | crtc->state->event->pipe = drm_crtc_index(crtc); | |
1286 | ||
1287 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
1288 | ||
1289 | dc->event = crtc->state->event; | |
1290 | crtc->state->event = NULL; | |
1291 | } | |
4aa3df71 TR |
1292 | } |
1293 | ||
1294 | static void tegra_crtc_atomic_flush(struct drm_crtc *crtc) | |
1295 | { | |
47802b09 TR |
1296 | struct tegra_dc_state *state = to_dc_state(crtc->state); |
1297 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
1298 | ||
1299 | tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL); | |
1300 | tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL); | |
4aa3df71 TR |
1301 | } |
1302 | ||
d8f4a9ed | 1303 | static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { |
f34bc787 | 1304 | .disable = tegra_crtc_disable, |
d8f4a9ed | 1305 | .mode_fixup = tegra_crtc_mode_fixup, |
4aa3df71 | 1306 | .mode_set_nofb = tegra_crtc_mode_set_nofb, |
d8f4a9ed TR |
1307 | .prepare = tegra_crtc_prepare, |
1308 | .commit = tegra_crtc_commit, | |
4aa3df71 TR |
1309 | .atomic_check = tegra_crtc_atomic_check, |
1310 | .atomic_begin = tegra_crtc_atomic_begin, | |
1311 | .atomic_flush = tegra_crtc_atomic_flush, | |
d8f4a9ed TR |
1312 | }; |
1313 | ||
6e5ff998 | 1314 | static irqreturn_t tegra_dc_irq(int irq, void *data) |
d8f4a9ed TR |
1315 | { |
1316 | struct tegra_dc *dc = data; | |
1317 | unsigned long status; | |
1318 | ||
1319 | status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); | |
1320 | tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); | |
1321 | ||
1322 | if (status & FRAME_END_INT) { | |
1323 | /* | |
1324 | dev_dbg(dc->dev, "%s(): frame end\n", __func__); | |
1325 | */ | |
1326 | } | |
1327 | ||
1328 | if (status & VBLANK_INT) { | |
1329 | /* | |
1330 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); | |
1331 | */ | |
ed7dae58 | 1332 | drm_crtc_handle_vblank(&dc->base); |
3c03c46a | 1333 | tegra_dc_finish_page_flip(dc); |
d8f4a9ed TR |
1334 | } |
1335 | ||
1336 | if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { | |
1337 | /* | |
1338 | dev_dbg(dc->dev, "%s(): underflow\n", __func__); | |
1339 | */ | |
1340 | } | |
1341 | ||
1342 | return IRQ_HANDLED; | |
1343 | } | |
1344 | ||
1345 | static int tegra_dc_show_regs(struct seq_file *s, void *data) | |
1346 | { | |
1347 | struct drm_info_node *node = s->private; | |
1348 | struct tegra_dc *dc = node->info_ent->data; | |
1349 | ||
1350 | #define DUMP_REG(name) \ | |
03a60569 | 1351 | seq_printf(s, "%-40s %#05x %08x\n", #name, name, \ |
d8f4a9ed TR |
1352 | tegra_dc_readl(dc, name)) |
1353 | ||
1354 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); | |
1355 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1356 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); | |
1357 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); | |
1358 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); | |
1359 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); | |
1360 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); | |
1361 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); | |
1362 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); | |
1363 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); | |
1364 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); | |
1365 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); | |
1366 | DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); | |
1367 | DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); | |
1368 | DUMP_REG(DC_CMD_DISPLAY_COMMAND); | |
1369 | DUMP_REG(DC_CMD_SIGNAL_RAISE); | |
1370 | DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); | |
1371 | DUMP_REG(DC_CMD_INT_STATUS); | |
1372 | DUMP_REG(DC_CMD_INT_MASK); | |
1373 | DUMP_REG(DC_CMD_INT_ENABLE); | |
1374 | DUMP_REG(DC_CMD_INT_TYPE); | |
1375 | DUMP_REG(DC_CMD_INT_POLARITY); | |
1376 | DUMP_REG(DC_CMD_SIGNAL_RAISE1); | |
1377 | DUMP_REG(DC_CMD_SIGNAL_RAISE2); | |
1378 | DUMP_REG(DC_CMD_SIGNAL_RAISE3); | |
1379 | DUMP_REG(DC_CMD_STATE_ACCESS); | |
1380 | DUMP_REG(DC_CMD_STATE_CONTROL); | |
1381 | DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); | |
1382 | DUMP_REG(DC_CMD_REG_ACT_CONTROL); | |
1383 | DUMP_REG(DC_COM_CRC_CONTROL); | |
1384 | DUMP_REG(DC_COM_CRC_CHECKSUM); | |
1385 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); | |
1386 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); | |
1387 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); | |
1388 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); | |
1389 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); | |
1390 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); | |
1391 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); | |
1392 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); | |
1393 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); | |
1394 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); | |
1395 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); | |
1396 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); | |
1397 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); | |
1398 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); | |
1399 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); | |
1400 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); | |
1401 | DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); | |
1402 | DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); | |
1403 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); | |
1404 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); | |
1405 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); | |
1406 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); | |
1407 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); | |
1408 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); | |
1409 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); | |
1410 | DUMP_REG(DC_COM_PIN_MISC_CONTROL); | |
1411 | DUMP_REG(DC_COM_PIN_PM0_CONTROL); | |
1412 | DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); | |
1413 | DUMP_REG(DC_COM_PIN_PM1_CONTROL); | |
1414 | DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); | |
1415 | DUMP_REG(DC_COM_SPI_CONTROL); | |
1416 | DUMP_REG(DC_COM_SPI_START_BYTE); | |
1417 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); | |
1418 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); | |
1419 | DUMP_REG(DC_COM_HSPI_CS_DC); | |
1420 | DUMP_REG(DC_COM_SCRATCH_REGISTER_A); | |
1421 | DUMP_REG(DC_COM_SCRATCH_REGISTER_B); | |
1422 | DUMP_REG(DC_COM_GPIO_CTRL); | |
1423 | DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); | |
1424 | DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); | |
1425 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); | |
1426 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); | |
1427 | DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); | |
1428 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1429 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1430 | DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); | |
1431 | DUMP_REG(DC_DISP_REF_TO_SYNC); | |
1432 | DUMP_REG(DC_DISP_SYNC_WIDTH); | |
1433 | DUMP_REG(DC_DISP_BACK_PORCH); | |
1434 | DUMP_REG(DC_DISP_ACTIVE); | |
1435 | DUMP_REG(DC_DISP_FRONT_PORCH); | |
1436 | DUMP_REG(DC_DISP_H_PULSE0_CONTROL); | |
1437 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); | |
1438 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); | |
1439 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); | |
1440 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); | |
1441 | DUMP_REG(DC_DISP_H_PULSE1_CONTROL); | |
1442 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); | |
1443 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); | |
1444 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); | |
1445 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); | |
1446 | DUMP_REG(DC_DISP_H_PULSE2_CONTROL); | |
1447 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); | |
1448 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); | |
1449 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); | |
1450 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); | |
1451 | DUMP_REG(DC_DISP_V_PULSE0_CONTROL); | |
1452 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); | |
1453 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); | |
1454 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); | |
1455 | DUMP_REG(DC_DISP_V_PULSE1_CONTROL); | |
1456 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); | |
1457 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); | |
1458 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); | |
1459 | DUMP_REG(DC_DISP_V_PULSE2_CONTROL); | |
1460 | DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); | |
1461 | DUMP_REG(DC_DISP_V_PULSE3_CONTROL); | |
1462 | DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); | |
1463 | DUMP_REG(DC_DISP_M0_CONTROL); | |
1464 | DUMP_REG(DC_DISP_M1_CONTROL); | |
1465 | DUMP_REG(DC_DISP_DI_CONTROL); | |
1466 | DUMP_REG(DC_DISP_PP_CONTROL); | |
1467 | DUMP_REG(DC_DISP_PP_SELECT_A); | |
1468 | DUMP_REG(DC_DISP_PP_SELECT_B); | |
1469 | DUMP_REG(DC_DISP_PP_SELECT_C); | |
1470 | DUMP_REG(DC_DISP_PP_SELECT_D); | |
1471 | DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); | |
1472 | DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); | |
1473 | DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); | |
1474 | DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); | |
1475 | DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); | |
1476 | DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); | |
1477 | DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); | |
1478 | DUMP_REG(DC_DISP_BORDER_COLOR); | |
1479 | DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); | |
1480 | DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); | |
1481 | DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); | |
1482 | DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); | |
1483 | DUMP_REG(DC_DISP_CURSOR_FOREGROUND); | |
1484 | DUMP_REG(DC_DISP_CURSOR_BACKGROUND); | |
1485 | DUMP_REG(DC_DISP_CURSOR_START_ADDR); | |
1486 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); | |
1487 | DUMP_REG(DC_DISP_CURSOR_POSITION); | |
1488 | DUMP_REG(DC_DISP_CURSOR_POSITION_NS); | |
1489 | DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); | |
1490 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); | |
1491 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); | |
1492 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); | |
1493 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); | |
1494 | DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); | |
1495 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); | |
1496 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); | |
1497 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); | |
1498 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); | |
1499 | DUMP_REG(DC_DISP_DAC_CRT_CTRL); | |
1500 | DUMP_REG(DC_DISP_DISP_MISC_CONTROL); | |
1501 | DUMP_REG(DC_DISP_SD_CONTROL); | |
1502 | DUMP_REG(DC_DISP_SD_CSC_COEFF); | |
1503 | DUMP_REG(DC_DISP_SD_LUT(0)); | |
1504 | DUMP_REG(DC_DISP_SD_LUT(1)); | |
1505 | DUMP_REG(DC_DISP_SD_LUT(2)); | |
1506 | DUMP_REG(DC_DISP_SD_LUT(3)); | |
1507 | DUMP_REG(DC_DISP_SD_LUT(4)); | |
1508 | DUMP_REG(DC_DISP_SD_LUT(5)); | |
1509 | DUMP_REG(DC_DISP_SD_LUT(6)); | |
1510 | DUMP_REG(DC_DISP_SD_LUT(7)); | |
1511 | DUMP_REG(DC_DISP_SD_LUT(8)); | |
1512 | DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); | |
1513 | DUMP_REG(DC_DISP_DC_PIXEL_COUNT); | |
1514 | DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); | |
1515 | DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); | |
1516 | DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); | |
1517 | DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); | |
1518 | DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); | |
1519 | DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); | |
1520 | DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); | |
1521 | DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); | |
1522 | DUMP_REG(DC_DISP_SD_BL_TF(0)); | |
1523 | DUMP_REG(DC_DISP_SD_BL_TF(1)); | |
1524 | DUMP_REG(DC_DISP_SD_BL_TF(2)); | |
1525 | DUMP_REG(DC_DISP_SD_BL_TF(3)); | |
1526 | DUMP_REG(DC_DISP_SD_BL_CONTROL); | |
1527 | DUMP_REG(DC_DISP_SD_HW_K_VALUES); | |
1528 | DUMP_REG(DC_DISP_SD_MAN_K_VALUES); | |
e687651b TR |
1529 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI); |
1530 | DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL); | |
d8f4a9ed TR |
1531 | DUMP_REG(DC_WIN_WIN_OPTIONS); |
1532 | DUMP_REG(DC_WIN_BYTE_SWAP); | |
1533 | DUMP_REG(DC_WIN_BUFFER_CONTROL); | |
1534 | DUMP_REG(DC_WIN_COLOR_DEPTH); | |
1535 | DUMP_REG(DC_WIN_POSITION); | |
1536 | DUMP_REG(DC_WIN_SIZE); | |
1537 | DUMP_REG(DC_WIN_PRESCALED_SIZE); | |
1538 | DUMP_REG(DC_WIN_H_INITIAL_DDA); | |
1539 | DUMP_REG(DC_WIN_V_INITIAL_DDA); | |
1540 | DUMP_REG(DC_WIN_DDA_INC); | |
1541 | DUMP_REG(DC_WIN_LINE_STRIDE); | |
1542 | DUMP_REG(DC_WIN_BUF_STRIDE); | |
1543 | DUMP_REG(DC_WIN_UV_BUF_STRIDE); | |
1544 | DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); | |
1545 | DUMP_REG(DC_WIN_DV_CONTROL); | |
1546 | DUMP_REG(DC_WIN_BLEND_NOKEY); | |
1547 | DUMP_REG(DC_WIN_BLEND_1WIN); | |
1548 | DUMP_REG(DC_WIN_BLEND_2WIN_X); | |
1549 | DUMP_REG(DC_WIN_BLEND_2WIN_Y); | |
f34bc787 | 1550 | DUMP_REG(DC_WIN_BLEND_3WIN_XY); |
d8f4a9ed TR |
1551 | DUMP_REG(DC_WIN_HP_FETCH_CONTROL); |
1552 | DUMP_REG(DC_WINBUF_START_ADDR); | |
1553 | DUMP_REG(DC_WINBUF_START_ADDR_NS); | |
1554 | DUMP_REG(DC_WINBUF_START_ADDR_U); | |
1555 | DUMP_REG(DC_WINBUF_START_ADDR_U_NS); | |
1556 | DUMP_REG(DC_WINBUF_START_ADDR_V); | |
1557 | DUMP_REG(DC_WINBUF_START_ADDR_V_NS); | |
1558 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); | |
1559 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); | |
1560 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); | |
1561 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); | |
1562 | DUMP_REG(DC_WINBUF_UFLOW_STATUS); | |
1563 | DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); | |
1564 | DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); | |
1565 | DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); | |
1566 | ||
1567 | #undef DUMP_REG | |
1568 | ||
1569 | return 0; | |
1570 | } | |
1571 | ||
1572 | static struct drm_info_list debugfs_files[] = { | |
1573 | { "regs", tegra_dc_show_regs, 0, NULL }, | |
1574 | }; | |
1575 | ||
1576 | static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) | |
1577 | { | |
1578 | unsigned int i; | |
1579 | char *name; | |
1580 | int err; | |
1581 | ||
1582 | name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); | |
1583 | dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); | |
1584 | kfree(name); | |
1585 | ||
1586 | if (!dc->debugfs) | |
1587 | return -ENOMEM; | |
1588 | ||
1589 | dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), | |
1590 | GFP_KERNEL); | |
1591 | if (!dc->debugfs_files) { | |
1592 | err = -ENOMEM; | |
1593 | goto remove; | |
1594 | } | |
1595 | ||
1596 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
1597 | dc->debugfs_files[i].data = dc; | |
1598 | ||
1599 | err = drm_debugfs_create_files(dc->debugfs_files, | |
1600 | ARRAY_SIZE(debugfs_files), | |
1601 | dc->debugfs, minor); | |
1602 | if (err < 0) | |
1603 | goto free; | |
1604 | ||
1605 | dc->minor = minor; | |
1606 | ||
1607 | return 0; | |
1608 | ||
1609 | free: | |
1610 | kfree(dc->debugfs_files); | |
1611 | dc->debugfs_files = NULL; | |
1612 | remove: | |
1613 | debugfs_remove(dc->debugfs); | |
1614 | dc->debugfs = NULL; | |
1615 | ||
1616 | return err; | |
1617 | } | |
1618 | ||
1619 | static int tegra_dc_debugfs_exit(struct tegra_dc *dc) | |
1620 | { | |
1621 | drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), | |
1622 | dc->minor); | |
1623 | dc->minor = NULL; | |
1624 | ||
1625 | kfree(dc->debugfs_files); | |
1626 | dc->debugfs_files = NULL; | |
1627 | ||
1628 | debugfs_remove(dc->debugfs); | |
1629 | dc->debugfs = NULL; | |
1630 | ||
1631 | return 0; | |
1632 | } | |
1633 | ||
53fa7f72 | 1634 | static int tegra_dc_init(struct host1x_client *client) |
d8f4a9ed | 1635 | { |
9910f5c4 | 1636 | struct drm_device *drm = dev_get_drvdata(client->parent); |
776dc384 | 1637 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d1f3e1e0 | 1638 | struct tegra_drm *tegra = drm->dev_private; |
c7679306 TR |
1639 | struct drm_plane *primary = NULL; |
1640 | struct drm_plane *cursor = NULL; | |
07d05cbf | 1641 | u32 value; |
d8f4a9ed TR |
1642 | int err; |
1643 | ||
df06b759 TR |
1644 | if (tegra->domain) { |
1645 | err = iommu_attach_device(tegra->domain, dc->dev); | |
1646 | if (err < 0) { | |
1647 | dev_err(dc->dev, "failed to attach to domain: %d\n", | |
1648 | err); | |
1649 | return err; | |
1650 | } | |
1651 | ||
1652 | dc->domain = tegra->domain; | |
1653 | } | |
1654 | ||
c7679306 TR |
1655 | primary = tegra_dc_primary_plane_create(drm, dc); |
1656 | if (IS_ERR(primary)) { | |
1657 | err = PTR_ERR(primary); | |
1658 | goto cleanup; | |
1659 | } | |
1660 | ||
1661 | if (dc->soc->supports_cursor) { | |
1662 | cursor = tegra_dc_cursor_plane_create(drm, dc); | |
1663 | if (IS_ERR(cursor)) { | |
1664 | err = PTR_ERR(cursor); | |
1665 | goto cleanup; | |
1666 | } | |
1667 | } | |
1668 | ||
1669 | err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, | |
1670 | &tegra_crtc_funcs); | |
1671 | if (err < 0) | |
1672 | goto cleanup; | |
1673 | ||
d8f4a9ed TR |
1674 | drm_mode_crtc_set_gamma_size(&dc->base, 256); |
1675 | drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); | |
1676 | ||
d1f3e1e0 TR |
1677 | /* |
1678 | * Keep track of the minimum pitch alignment across all display | |
1679 | * controllers. | |
1680 | */ | |
1681 | if (dc->soc->pitch_align > tegra->pitch_align) | |
1682 | tegra->pitch_align = dc->soc->pitch_align; | |
1683 | ||
9910f5c4 | 1684 | err = tegra_dc_rgb_init(drm, dc); |
d8f4a9ed TR |
1685 | if (err < 0 && err != -ENODEV) { |
1686 | dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); | |
c7679306 | 1687 | goto cleanup; |
d8f4a9ed TR |
1688 | } |
1689 | ||
9910f5c4 | 1690 | err = tegra_dc_add_planes(drm, dc); |
f34bc787 | 1691 | if (err < 0) |
c7679306 | 1692 | goto cleanup; |
f34bc787 | 1693 | |
d8f4a9ed | 1694 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
9910f5c4 | 1695 | err = tegra_dc_debugfs_init(dc, drm->primary); |
d8f4a9ed TR |
1696 | if (err < 0) |
1697 | dev_err(dc->dev, "debugfs setup failed: %d\n", err); | |
1698 | } | |
1699 | ||
6e5ff998 | 1700 | err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, |
d8f4a9ed TR |
1701 | dev_name(dc->dev), dc); |
1702 | if (err < 0) { | |
1703 | dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, | |
1704 | err); | |
c7679306 | 1705 | goto cleanup; |
d8f4a9ed TR |
1706 | } |
1707 | ||
07d05cbf | 1708 | /* initialize display controller */ |
42e9ce05 TR |
1709 | if (dc->syncpt) { |
1710 | u32 syncpt = host1x_syncpt_id(dc->syncpt); | |
07d05cbf | 1711 | |
42e9ce05 TR |
1712 | value = SYNCPT_CNTRL_NO_STALL; |
1713 | tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1714 | ||
1715 | value = SYNCPT_VSYNC_ENABLE | syncpt; | |
1716 | tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); | |
1717 | } | |
07d05cbf TR |
1718 | |
1719 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; | |
1720 | tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); | |
1721 | ||
1722 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1723 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1724 | tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); | |
1725 | ||
1726 | /* initialize timer */ | |
1727 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | | |
1728 | WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); | |
1729 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1730 | ||
1731 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | | |
1732 | WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); | |
1733 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1734 | ||
1735 | value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; | |
1736 | tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); | |
1737 | ||
1738 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; | |
1739 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
1740 | ||
1741 | if (dc->soc->supports_border_color) | |
1742 | tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); | |
1743 | ||
d8f4a9ed | 1744 | return 0; |
c7679306 TR |
1745 | |
1746 | cleanup: | |
1747 | if (cursor) | |
1748 | drm_plane_cleanup(cursor); | |
1749 | ||
1750 | if (primary) | |
1751 | drm_plane_cleanup(primary); | |
1752 | ||
1753 | if (tegra->domain) { | |
1754 | iommu_detach_device(tegra->domain, dc->dev); | |
1755 | dc->domain = NULL; | |
1756 | } | |
1757 | ||
1758 | return err; | |
d8f4a9ed TR |
1759 | } |
1760 | ||
53fa7f72 | 1761 | static int tegra_dc_exit(struct host1x_client *client) |
d8f4a9ed | 1762 | { |
776dc384 | 1763 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d8f4a9ed TR |
1764 | int err; |
1765 | ||
1766 | devm_free_irq(dc->dev, dc->irq, dc); | |
1767 | ||
1768 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1769 | err = tegra_dc_debugfs_exit(dc); | |
1770 | if (err < 0) | |
1771 | dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); | |
1772 | } | |
1773 | ||
1774 | err = tegra_dc_rgb_exit(dc); | |
1775 | if (err) { | |
1776 | dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); | |
1777 | return err; | |
1778 | } | |
1779 | ||
df06b759 TR |
1780 | if (dc->domain) { |
1781 | iommu_detach_device(dc->domain, dc->dev); | |
1782 | dc->domain = NULL; | |
1783 | } | |
1784 | ||
d8f4a9ed TR |
1785 | return 0; |
1786 | } | |
1787 | ||
1788 | static const struct host1x_client_ops dc_client_ops = { | |
53fa7f72 TR |
1789 | .init = tegra_dc_init, |
1790 | .exit = tegra_dc_exit, | |
d8f4a9ed TR |
1791 | }; |
1792 | ||
8620fc62 | 1793 | static const struct tegra_dc_soc_info tegra20_dc_soc_info = { |
42d0659b | 1794 | .supports_border_color = true, |
8620fc62 | 1795 | .supports_interlacing = false, |
e687651b | 1796 | .supports_cursor = false, |
c134f019 | 1797 | .supports_block_linear = false, |
d1f3e1e0 | 1798 | .pitch_align = 8, |
9c012700 | 1799 | .has_powergate = false, |
8620fc62 TR |
1800 | }; |
1801 | ||
1802 | static const struct tegra_dc_soc_info tegra30_dc_soc_info = { | |
42d0659b | 1803 | .supports_border_color = true, |
8620fc62 | 1804 | .supports_interlacing = false, |
e687651b | 1805 | .supports_cursor = false, |
c134f019 | 1806 | .supports_block_linear = false, |
d1f3e1e0 | 1807 | .pitch_align = 8, |
9c012700 | 1808 | .has_powergate = false, |
d1f3e1e0 TR |
1809 | }; |
1810 | ||
1811 | static const struct tegra_dc_soc_info tegra114_dc_soc_info = { | |
42d0659b | 1812 | .supports_border_color = true, |
d1f3e1e0 TR |
1813 | .supports_interlacing = false, |
1814 | .supports_cursor = false, | |
1815 | .supports_block_linear = false, | |
1816 | .pitch_align = 64, | |
9c012700 | 1817 | .has_powergate = true, |
8620fc62 TR |
1818 | }; |
1819 | ||
1820 | static const struct tegra_dc_soc_info tegra124_dc_soc_info = { | |
42d0659b | 1821 | .supports_border_color = false, |
8620fc62 | 1822 | .supports_interlacing = true, |
e687651b | 1823 | .supports_cursor = true, |
c134f019 | 1824 | .supports_block_linear = true, |
d1f3e1e0 | 1825 | .pitch_align = 64, |
9c012700 | 1826 | .has_powergate = true, |
8620fc62 TR |
1827 | }; |
1828 | ||
1829 | static const struct of_device_id tegra_dc_of_match[] = { | |
1830 | { | |
1831 | .compatible = "nvidia,tegra124-dc", | |
1832 | .data = &tegra124_dc_soc_info, | |
9c012700 TR |
1833 | }, { |
1834 | .compatible = "nvidia,tegra114-dc", | |
1835 | .data = &tegra114_dc_soc_info, | |
8620fc62 TR |
1836 | }, { |
1837 | .compatible = "nvidia,tegra30-dc", | |
1838 | .data = &tegra30_dc_soc_info, | |
1839 | }, { | |
1840 | .compatible = "nvidia,tegra20-dc", | |
1841 | .data = &tegra20_dc_soc_info, | |
1842 | }, { | |
1843 | /* sentinel */ | |
1844 | } | |
1845 | }; | |
ef70728c | 1846 | MODULE_DEVICE_TABLE(of, tegra_dc_of_match); |
8620fc62 | 1847 | |
13411ddd TR |
1848 | static int tegra_dc_parse_dt(struct tegra_dc *dc) |
1849 | { | |
1850 | struct device_node *np; | |
1851 | u32 value = 0; | |
1852 | int err; | |
1853 | ||
1854 | err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); | |
1855 | if (err < 0) { | |
1856 | dev_err(dc->dev, "missing \"nvidia,head\" property\n"); | |
1857 | ||
1858 | /* | |
1859 | * If the nvidia,head property isn't present, try to find the | |
1860 | * correct head number by looking up the position of this | |
1861 | * display controller's node within the device tree. Assuming | |
1862 | * that the nodes are ordered properly in the DTS file and | |
1863 | * that the translation into a flattened device tree blob | |
1864 | * preserves that ordering this will actually yield the right | |
1865 | * head number. | |
1866 | * | |
1867 | * If those assumptions don't hold, this will still work for | |
1868 | * cases where only a single display controller is used. | |
1869 | */ | |
1870 | for_each_matching_node(np, tegra_dc_of_match) { | |
1871 | if (np == dc->dev->of_node) | |
1872 | break; | |
1873 | ||
1874 | value++; | |
1875 | } | |
1876 | } | |
1877 | ||
1878 | dc->pipe = value; | |
1879 | ||
1880 | return 0; | |
1881 | } | |
1882 | ||
d8f4a9ed TR |
1883 | static int tegra_dc_probe(struct platform_device *pdev) |
1884 | { | |
42e9ce05 | 1885 | unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; |
8620fc62 | 1886 | const struct of_device_id *id; |
d8f4a9ed TR |
1887 | struct resource *regs; |
1888 | struct tegra_dc *dc; | |
1889 | int err; | |
1890 | ||
1891 | dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); | |
1892 | if (!dc) | |
1893 | return -ENOMEM; | |
1894 | ||
8620fc62 TR |
1895 | id = of_match_node(tegra_dc_of_match, pdev->dev.of_node); |
1896 | if (!id) | |
1897 | return -ENODEV; | |
1898 | ||
6e5ff998 | 1899 | spin_lock_init(&dc->lock); |
d8f4a9ed TR |
1900 | INIT_LIST_HEAD(&dc->list); |
1901 | dc->dev = &pdev->dev; | |
8620fc62 | 1902 | dc->soc = id->data; |
d8f4a9ed | 1903 | |
13411ddd TR |
1904 | err = tegra_dc_parse_dt(dc); |
1905 | if (err < 0) | |
1906 | return err; | |
1907 | ||
d8f4a9ed TR |
1908 | dc->clk = devm_clk_get(&pdev->dev, NULL); |
1909 | if (IS_ERR(dc->clk)) { | |
1910 | dev_err(&pdev->dev, "failed to get clock\n"); | |
1911 | return PTR_ERR(dc->clk); | |
1912 | } | |
1913 | ||
ca48080a SW |
1914 | dc->rst = devm_reset_control_get(&pdev->dev, "dc"); |
1915 | if (IS_ERR(dc->rst)) { | |
1916 | dev_err(&pdev->dev, "failed to get reset\n"); | |
1917 | return PTR_ERR(dc->rst); | |
1918 | } | |
1919 | ||
9c012700 TR |
1920 | if (dc->soc->has_powergate) { |
1921 | if (dc->pipe == 0) | |
1922 | dc->powergate = TEGRA_POWERGATE_DIS; | |
1923 | else | |
1924 | dc->powergate = TEGRA_POWERGATE_DISB; | |
1925 | ||
1926 | err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, | |
1927 | dc->rst); | |
1928 | if (err < 0) { | |
1929 | dev_err(&pdev->dev, "failed to power partition: %d\n", | |
1930 | err); | |
1931 | return err; | |
1932 | } | |
1933 | } else { | |
1934 | err = clk_prepare_enable(dc->clk); | |
1935 | if (err < 0) { | |
1936 | dev_err(&pdev->dev, "failed to enable clock: %d\n", | |
1937 | err); | |
1938 | return err; | |
1939 | } | |
1940 | ||
1941 | err = reset_control_deassert(dc->rst); | |
1942 | if (err < 0) { | |
1943 | dev_err(&pdev->dev, "failed to deassert reset: %d\n", | |
1944 | err); | |
1945 | return err; | |
1946 | } | |
1947 | } | |
d8f4a9ed TR |
1948 | |
1949 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d4ed6025 TR |
1950 | dc->regs = devm_ioremap_resource(&pdev->dev, regs); |
1951 | if (IS_ERR(dc->regs)) | |
1952 | return PTR_ERR(dc->regs); | |
d8f4a9ed TR |
1953 | |
1954 | dc->irq = platform_get_irq(pdev, 0); | |
1955 | if (dc->irq < 0) { | |
1956 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
1957 | return -ENXIO; | |
1958 | } | |
1959 | ||
776dc384 TR |
1960 | INIT_LIST_HEAD(&dc->client.list); |
1961 | dc->client.ops = &dc_client_ops; | |
1962 | dc->client.dev = &pdev->dev; | |
d8f4a9ed TR |
1963 | |
1964 | err = tegra_dc_rgb_probe(dc); | |
1965 | if (err < 0 && err != -ENODEV) { | |
1966 | dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); | |
1967 | return err; | |
1968 | } | |
1969 | ||
776dc384 | 1970 | err = host1x_client_register(&dc->client); |
d8f4a9ed TR |
1971 | if (err < 0) { |
1972 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
1973 | err); | |
1974 | return err; | |
1975 | } | |
1976 | ||
42e9ce05 TR |
1977 | dc->syncpt = host1x_syncpt_request(&pdev->dev, flags); |
1978 | if (!dc->syncpt) | |
1979 | dev_warn(&pdev->dev, "failed to allocate syncpoint\n"); | |
1980 | ||
d8f4a9ed TR |
1981 | platform_set_drvdata(pdev, dc); |
1982 | ||
1983 | return 0; | |
1984 | } | |
1985 | ||
1986 | static int tegra_dc_remove(struct platform_device *pdev) | |
1987 | { | |
d8f4a9ed TR |
1988 | struct tegra_dc *dc = platform_get_drvdata(pdev); |
1989 | int err; | |
1990 | ||
42e9ce05 TR |
1991 | host1x_syncpt_free(dc->syncpt); |
1992 | ||
776dc384 | 1993 | err = host1x_client_unregister(&dc->client); |
d8f4a9ed TR |
1994 | if (err < 0) { |
1995 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
1996 | err); | |
1997 | return err; | |
1998 | } | |
1999 | ||
59d29c0e TR |
2000 | err = tegra_dc_rgb_remove(dc); |
2001 | if (err < 0) { | |
2002 | dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); | |
2003 | return err; | |
2004 | } | |
2005 | ||
5482d75a | 2006 | reset_control_assert(dc->rst); |
9c012700 TR |
2007 | |
2008 | if (dc->soc->has_powergate) | |
2009 | tegra_powergate_power_off(dc->powergate); | |
2010 | ||
d8f4a9ed TR |
2011 | clk_disable_unprepare(dc->clk); |
2012 | ||
2013 | return 0; | |
2014 | } | |
2015 | ||
d8f4a9ed TR |
2016 | struct platform_driver tegra_dc_driver = { |
2017 | .driver = { | |
2018 | .name = "tegra-dc", | |
2019 | .owner = THIS_MODULE, | |
2020 | .of_match_table = tegra_dc_of_match, | |
2021 | }, | |
2022 | .probe = tegra_dc_probe, | |
2023 | .remove = tegra_dc_remove, | |
2024 | }; |