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d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #ifndef TEGRA_DC_H | |
11 | #define TEGRA_DC_H 1 | |
12 | ||
2d1c18fb TR |
13 | #include <linux/host1x.h> |
14 | ||
15 | #include <drm/drm_crtc.h> | |
16 | ||
17 | #include "drm.h" | |
18 | ||
19 | struct tegra_output; | |
20 | ||
b1415ff2 TR |
21 | struct tegra_dc_state { |
22 | struct drm_crtc_state base; | |
23 | ||
24 | struct clk *clk; | |
25 | unsigned long pclk; | |
26 | unsigned int div; | |
27 | ||
28 | u32 planes; | |
29 | }; | |
30 | ||
31 | static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) | |
32 | { | |
33 | if (state) | |
34 | return container_of(state, struct tegra_dc_state, base); | |
35 | ||
36 | return NULL; | |
37 | } | |
38 | ||
2d1c18fb TR |
39 | struct tegra_dc_stats { |
40 | unsigned long frames; | |
41 | unsigned long vblank; | |
42 | unsigned long underflow; | |
43 | unsigned long overflow; | |
44 | }; | |
45 | ||
47307954 TR |
46 | struct tegra_windowgroup_soc { |
47 | unsigned int index; | |
48 | unsigned int dc; | |
49 | const unsigned int *windows; | |
50 | unsigned int num_windows; | |
51 | }; | |
52 | ||
2d1c18fb | 53 | struct tegra_dc_soc_info { |
7116e9a8 | 54 | bool supports_background_color; |
2d1c18fb TR |
55 | bool supports_interlacing; |
56 | bool supports_cursor; | |
57 | bool supports_block_linear; | |
a43d0a00 | 58 | bool has_legacy_blending; |
2d1c18fb TR |
59 | unsigned int pitch_align; |
60 | bool has_powergate; | |
f68ba691 | 61 | bool coupled_pm; |
47307954 TR |
62 | bool has_nvdisplay; |
63 | const struct tegra_windowgroup_soc *wgrps; | |
64 | unsigned int num_wgrps; | |
511c7023 TR |
65 | const u32 *primary_formats; |
66 | unsigned int num_primary_formats; | |
67 | const u32 *overlay_formats; | |
68 | unsigned int num_overlay_formats; | |
e90124cb | 69 | const u64 *modifiers; |
acc6a3a9 DO |
70 | bool has_win_a_without_filters; |
71 | bool has_win_c_without_vert_filter; | |
2d1c18fb TR |
72 | }; |
73 | ||
74 | struct tegra_dc { | |
75 | struct host1x_client client; | |
76 | struct host1x_syncpt *syncpt; | |
77 | struct device *dev; | |
2d1c18fb TR |
78 | |
79 | struct drm_crtc base; | |
80 | unsigned int powergate; | |
81 | int pipe; | |
82 | ||
83 | struct clk *clk; | |
84 | struct reset_control *rst; | |
85 | void __iomem *regs; | |
86 | int irq; | |
87 | ||
88 | struct tegra_output *rgb; | |
89 | ||
90 | struct tegra_dc_stats stats; | |
91 | struct list_head list; | |
92 | ||
93 | struct drm_info_list *debugfs_files; | |
2d1c18fb | 94 | |
2d1c18fb TR |
95 | const struct tegra_dc_soc_info *soc; |
96 | ||
6f75b16b | 97 | struct iommu_group *group; |
2d1c18fb TR |
98 | }; |
99 | ||
100 | static inline struct tegra_dc * | |
101 | host1x_client_to_dc(struct host1x_client *client) | |
102 | { | |
103 | return container_of(client, struct tegra_dc, client); | |
104 | } | |
105 | ||
106 | static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) | |
107 | { | |
108 | return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; | |
109 | } | |
110 | ||
111 | static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, | |
112 | unsigned int offset) | |
113 | { | |
114 | trace_dc_writel(dc->dev, offset, value); | |
115 | writel(value, dc->regs + (offset << 2)); | |
116 | } | |
117 | ||
118 | static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) | |
119 | { | |
120 | u32 value = readl(dc->regs + (offset << 2)); | |
121 | ||
122 | trace_dc_readl(dc->dev, offset, value); | |
123 | ||
124 | return value; | |
125 | } | |
126 | ||
127 | struct tegra_dc_window { | |
128 | struct { | |
129 | unsigned int x; | |
130 | unsigned int y; | |
131 | unsigned int w; | |
132 | unsigned int h; | |
133 | } src; | |
134 | struct { | |
135 | unsigned int x; | |
136 | unsigned int y; | |
137 | unsigned int w; | |
138 | unsigned int h; | |
139 | } dst; | |
140 | unsigned int bits_per_pixel; | |
141 | unsigned int stride[2]; | |
142 | unsigned long base[3]; | |
ab7d3f58 | 143 | unsigned int zpos; |
2d1c18fb TR |
144 | bool bottom_up; |
145 | ||
146 | struct tegra_bo_tiling tiling; | |
147 | u32 format; | |
148 | u32 swap; | |
149 | }; | |
150 | ||
151 | /* from dc.c */ | |
c57997bc | 152 | bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev); |
2d1c18fb TR |
153 | void tegra_dc_commit(struct tegra_dc *dc); |
154 | int tegra_dc_state_setup_clock(struct tegra_dc *dc, | |
155 | struct drm_crtc_state *crtc_state, | |
156 | struct clk *clk, unsigned long pclk, | |
157 | unsigned int div); | |
158 | ||
159 | /* from rgb.c */ | |
160 | int tegra_dc_rgb_probe(struct tegra_dc *dc); | |
161 | int tegra_dc_rgb_remove(struct tegra_dc *dc); | |
162 | int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); | |
163 | int tegra_dc_rgb_exit(struct tegra_dc *dc); | |
164 | ||
d8f4a9ed TR |
165 | #define DC_CMD_GENERAL_INCR_SYNCPT 0x000 |
166 | #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 | |
42e9ce05 TR |
167 | #define SYNCPT_CNTRL_NO_STALL (1 << 8) |
168 | #define SYNCPT_CNTRL_SOFT_RESET (1 << 0) | |
d8f4a9ed TR |
169 | #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 |
170 | #define DC_CMD_WIN_A_INCR_SYNCPT 0x008 | |
171 | #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 | |
172 | #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a | |
173 | #define DC_CMD_WIN_B_INCR_SYNCPT 0x010 | |
174 | #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 | |
175 | #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 | |
176 | #define DC_CMD_WIN_C_INCR_SYNCPT 0x018 | |
177 | #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019 | |
178 | #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a | |
179 | #define DC_CMD_CONT_SYNCPT_VSYNC 0x028 | |
42e9ce05 | 180 | #define SYNCPT_VSYNC_ENABLE (1 << 8) |
d8f4a9ed TR |
181 | #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 |
182 | #define DC_CMD_DISPLAY_COMMAND 0x032 | |
183 | #define DISP_CTRL_MODE_STOP (0 << 5) | |
184 | #define DISP_CTRL_MODE_C_DISPLAY (1 << 5) | |
185 | #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) | |
dec72739 | 186 | #define DISP_CTRL_MODE_MASK (3 << 5) |
d8f4a9ed TR |
187 | #define DC_CMD_SIGNAL_RAISE 0x033 |
188 | #define DC_CMD_DISPLAY_POWER_CONTROL 0x036 | |
189 | #define PW0_ENABLE (1 << 0) | |
190 | #define PW1_ENABLE (1 << 2) | |
191 | #define PW2_ENABLE (1 << 4) | |
192 | #define PW3_ENABLE (1 << 6) | |
193 | #define PW4_ENABLE (1 << 8) | |
194 | #define PM0_ENABLE (1 << 16) | |
195 | #define PM1_ENABLE (1 << 18) | |
196 | ||
197 | #define DC_CMD_INT_STATUS 0x037 | |
198 | #define DC_CMD_INT_MASK 0x038 | |
199 | #define DC_CMD_INT_ENABLE 0x039 | |
200 | #define DC_CMD_INT_TYPE 0x03a | |
201 | #define DC_CMD_INT_POLARITY 0x03b | |
47307954 TR |
202 | #define CTXSW_INT (1 << 0) |
203 | #define FRAME_END_INT (1 << 1) | |
204 | #define VBLANK_INT (1 << 2) | |
205 | #define V_PULSE3_INT (1 << 4) | |
206 | #define V_PULSE2_INT (1 << 5) | |
207 | #define REGION_CRC_INT (1 << 6) | |
208 | #define REG_TMOUT_INT (1 << 7) | |
209 | #define WIN_A_UF_INT (1 << 8) | |
210 | #define WIN_B_UF_INT (1 << 9) | |
211 | #define WIN_C_UF_INT (1 << 10) | |
212 | #define MSF_INT (1 << 12) | |
213 | #define WIN_A_OF_INT (1 << 14) | |
214 | #define WIN_B_OF_INT (1 << 15) | |
215 | #define WIN_C_OF_INT (1 << 16) | |
216 | #define HEAD_UF_INT (1 << 23) | |
217 | #define SD3_BUCKET_WALK_DONE_INT (1 << 24) | |
218 | #define DSC_OBUF_UF_INT (1 << 26) | |
219 | #define DSC_RBUF_UF_INT (1 << 27) | |
220 | #define DSC_BBUF_UF_INT (1 << 28) | |
221 | #define DSC_TO_UF_INT (1 << 29) | |
d8f4a9ed TR |
222 | |
223 | #define DC_CMD_SIGNAL_RAISE1 0x03c | |
224 | #define DC_CMD_SIGNAL_RAISE2 0x03d | |
225 | #define DC_CMD_SIGNAL_RAISE3 0x03e | |
226 | ||
227 | #define DC_CMD_STATE_ACCESS 0x040 | |
3c03c46a TR |
228 | #define READ_MUX (1 << 0) |
229 | #define WRITE_MUX (1 << 2) | |
d8f4a9ed TR |
230 | |
231 | #define DC_CMD_STATE_CONTROL 0x041 | |
232 | #define GENERAL_ACT_REQ (1 << 0) | |
233 | #define WIN_A_ACT_REQ (1 << 1) | |
234 | #define WIN_B_ACT_REQ (1 << 2) | |
235 | #define WIN_C_ACT_REQ (1 << 3) | |
e687651b | 236 | #define CURSOR_ACT_REQ (1 << 7) |
d8f4a9ed TR |
237 | #define GENERAL_UPDATE (1 << 8) |
238 | #define WIN_A_UPDATE (1 << 9) | |
239 | #define WIN_B_UPDATE (1 << 10) | |
240 | #define WIN_C_UPDATE (1 << 11) | |
e687651b | 241 | #define CURSOR_UPDATE (1 << 15) |
c4755fb9 TR |
242 | #define COMMON_ACTREQ (1 << 16) |
243 | #define COMMON_UPDATE (1 << 17) | |
d8f4a9ed TR |
244 | #define NC_HOST_TRIG (1 << 24) |
245 | ||
246 | #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 | |
247 | #define WINDOW_A_SELECT (1 << 4) | |
248 | #define WINDOW_B_SELECT (1 << 5) | |
249 | #define WINDOW_C_SELECT (1 << 6) | |
250 | ||
251 | #define DC_CMD_REG_ACT_CONTROL 0x043 | |
252 | ||
253 | #define DC_COM_CRC_CONTROL 0x300 | |
6ca1f62f TR |
254 | #define DC_COM_CRC_CONTROL_ALWAYS (1 << 3) |
255 | #define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2) | |
256 | #define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2) | |
257 | #define DC_COM_CRC_CONTROL_WAIT (1 << 1) | |
258 | #define DC_COM_CRC_CONTROL_ENABLE (1 << 0) | |
d8f4a9ed TR |
259 | #define DC_COM_CRC_CHECKSUM 0x301 |
260 | #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) | |
261 | #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) | |
262 | #define LVS_OUTPUT_POLARITY_LOW (1 << 28) | |
263 | #define LHS_OUTPUT_POLARITY_LOW (1 << 30) | |
264 | #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x)) | |
265 | #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x)) | |
266 | #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x)) | |
267 | #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x)) | |
268 | ||
269 | #define DC_COM_PIN_MISC_CONTROL 0x31b | |
270 | #define DC_COM_PIN_PM0_CONTROL 0x31c | |
271 | #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d | |
272 | #define DC_COM_PIN_PM1_CONTROL 0x31e | |
273 | #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f | |
274 | ||
275 | #define DC_COM_SPI_CONTROL 0x320 | |
276 | #define DC_COM_SPI_START_BYTE 0x321 | |
277 | #define DC_COM_HSPI_WRITE_DATA_AB 0x322 | |
278 | #define DC_COM_HSPI_WRITE_DATA_CD 0x323 | |
279 | #define DC_COM_HSPI_CS_DC 0x324 | |
280 | #define DC_COM_SCRATCH_REGISTER_A 0x325 | |
281 | #define DC_COM_SCRATCH_REGISTER_B 0x326 | |
282 | #define DC_COM_GPIO_CTRL 0x327 | |
283 | #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328 | |
284 | #define DC_COM_CRC_CHECKSUM_LATCHED 0x329 | |
285 | ||
47307954 TR |
286 | #define DC_COM_RG_UNDERFLOW 0x365 |
287 | #define UNDERFLOW_MODE_RED (1 << 8) | |
288 | #define UNDERFLOW_REPORT_ENABLE (1 << 0) | |
289 | ||
d8f4a9ed | 290 | #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 |
8fd3ffa9 TR |
291 | #define H_PULSE0_ENABLE (1 << 8) |
292 | #define H_PULSE1_ENABLE (1 << 10) | |
293 | #define H_PULSE2_ENABLE (1 << 12) | |
d8f4a9ed TR |
294 | |
295 | #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 | |
296 | ||
297 | #define DC_DISP_DISP_WIN_OPTIONS 0x402 | |
e687651b TR |
298 | #define HDMI_ENABLE (1 << 30) |
299 | #define DSI_ENABLE (1 << 29) | |
459cc2c6 | 300 | #define SOR1_TIMING_CYA (1 << 27) |
e687651b | 301 | #define CURSOR_ENABLE (1 << 16) |
d8f4a9ed | 302 | |
47443196 | 303 | #define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x)))) |
c57997bc | 304 | |
d8f4a9ed TR |
305 | #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 |
306 | #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) | |
307 | #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16) | |
308 | #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8) | |
309 | #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0) | |
310 | ||
311 | #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 | |
312 | #define CURSOR_DELAY(x) (((x) & 0x3f) << 24) | |
313 | #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16) | |
314 | #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8) | |
315 | #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0) | |
316 | ||
317 | #define DC_DISP_DISP_TIMING_OPTIONS 0x405 | |
318 | #define VSYNC_H_POSITION(x) ((x) & 0xfff) | |
319 | ||
320 | #define DC_DISP_REF_TO_SYNC 0x406 | |
321 | #define DC_DISP_SYNC_WIDTH 0x407 | |
322 | #define DC_DISP_BACK_PORCH 0x408 | |
323 | #define DC_DISP_ACTIVE 0x409 | |
324 | #define DC_DISP_FRONT_PORCH 0x40a | |
325 | #define DC_DISP_H_PULSE0_CONTROL 0x40b | |
326 | #define DC_DISP_H_PULSE0_POSITION_A 0x40c | |
327 | #define DC_DISP_H_PULSE0_POSITION_B 0x40d | |
328 | #define DC_DISP_H_PULSE0_POSITION_C 0x40e | |
329 | #define DC_DISP_H_PULSE0_POSITION_D 0x40f | |
330 | #define DC_DISP_H_PULSE1_CONTROL 0x410 | |
331 | #define DC_DISP_H_PULSE1_POSITION_A 0x411 | |
332 | #define DC_DISP_H_PULSE1_POSITION_B 0x412 | |
333 | #define DC_DISP_H_PULSE1_POSITION_C 0x413 | |
334 | #define DC_DISP_H_PULSE1_POSITION_D 0x414 | |
335 | #define DC_DISP_H_PULSE2_CONTROL 0x415 | |
336 | #define DC_DISP_H_PULSE2_POSITION_A 0x416 | |
337 | #define DC_DISP_H_PULSE2_POSITION_B 0x417 | |
338 | #define DC_DISP_H_PULSE2_POSITION_C 0x418 | |
339 | #define DC_DISP_H_PULSE2_POSITION_D 0x419 | |
340 | #define DC_DISP_V_PULSE0_CONTROL 0x41a | |
341 | #define DC_DISP_V_PULSE0_POSITION_A 0x41b | |
342 | #define DC_DISP_V_PULSE0_POSITION_B 0x41c | |
343 | #define DC_DISP_V_PULSE0_POSITION_C 0x41d | |
344 | #define DC_DISP_V_PULSE1_CONTROL 0x41e | |
345 | #define DC_DISP_V_PULSE1_POSITION_A 0x41f | |
346 | #define DC_DISP_V_PULSE1_POSITION_B 0x420 | |
347 | #define DC_DISP_V_PULSE1_POSITION_C 0x421 | |
348 | #define DC_DISP_V_PULSE2_CONTROL 0x422 | |
349 | #define DC_DISP_V_PULSE2_POSITION_A 0x423 | |
350 | #define DC_DISP_V_PULSE3_CONTROL 0x424 | |
351 | #define DC_DISP_V_PULSE3_POSITION_A 0x425 | |
352 | #define DC_DISP_M0_CONTROL 0x426 | |
353 | #define DC_DISP_M1_CONTROL 0x427 | |
354 | #define DC_DISP_DI_CONTROL 0x428 | |
355 | #define DC_DISP_PP_CONTROL 0x429 | |
356 | #define DC_DISP_PP_SELECT_A 0x42a | |
357 | #define DC_DISP_PP_SELECT_B 0x42b | |
358 | #define DC_DISP_PP_SELECT_C 0x42c | |
359 | #define DC_DISP_PP_SELECT_D 0x42d | |
360 | ||
361 | #define PULSE_MODE_NORMAL (0 << 3) | |
362 | #define PULSE_MODE_ONE_CLOCK (1 << 3) | |
363 | #define PULSE_POLARITY_HIGH (0 << 4) | |
364 | #define PULSE_POLARITY_LOW (1 << 4) | |
365 | #define PULSE_QUAL_ALWAYS (0 << 6) | |
366 | #define PULSE_QUAL_VACTIVE (2 << 6) | |
367 | #define PULSE_QUAL_VACTIVE1 (3 << 6) | |
368 | #define PULSE_LAST_START_A (0 << 8) | |
369 | #define PULSE_LAST_END_A (1 << 8) | |
370 | #define PULSE_LAST_START_B (2 << 8) | |
371 | #define PULSE_LAST_END_B (3 << 8) | |
372 | #define PULSE_LAST_START_C (4 << 8) | |
373 | #define PULSE_LAST_END_C (5 << 8) | |
374 | #define PULSE_LAST_START_D (6 << 8) | |
375 | #define PULSE_LAST_END_D (7 << 8) | |
376 | ||
377 | #define PULSE_START(x) (((x) & 0xfff) << 0) | |
378 | #define PULSE_END(x) (((x) & 0xfff) << 16) | |
379 | ||
380 | #define DC_DISP_DISP_CLOCK_CONTROL 0x42e | |
381 | #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) | |
382 | #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) | |
383 | #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) | |
384 | #define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) | |
385 | #define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) | |
386 | #define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) | |
387 | #define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) | |
388 | #define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) | |
389 | #define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) | |
390 | #define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) | |
391 | #define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) | |
392 | #define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) | |
393 | #define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) | |
394 | #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) | |
395 | ||
396 | #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f | |
397 | #define DISP_DATA_FORMAT_DF1P1C (0 << 0) | |
398 | #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) | |
399 | #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) | |
400 | #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) | |
401 | #define DISP_DATA_FORMAT_DF2S (4 << 0) | |
402 | #define DISP_DATA_FORMAT_DF3S (5 << 0) | |
403 | #define DISP_DATA_FORMAT_DFSPI (6 << 0) | |
404 | #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) | |
405 | #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) | |
406 | #define DISP_ALIGNMENT_MSB (0 << 8) | |
407 | #define DISP_ALIGNMENT_LSB (1 << 8) | |
408 | #define DISP_ORDER_RED_BLUE (0 << 9) | |
409 | #define DISP_ORDER_BLUE_RED (1 << 9) | |
410 | ||
411 | #define DC_DISP_DISP_COLOR_CONTROL 0x430 | |
47307954 TR |
412 | #define BASE_COLOR_SIZE666 ( 0 << 0) |
413 | #define BASE_COLOR_SIZE111 ( 1 << 0) | |
414 | #define BASE_COLOR_SIZE222 ( 2 << 0) | |
415 | #define BASE_COLOR_SIZE333 ( 3 << 0) | |
416 | #define BASE_COLOR_SIZE444 ( 4 << 0) | |
417 | #define BASE_COLOR_SIZE555 ( 5 << 0) | |
418 | #define BASE_COLOR_SIZE565 ( 6 << 0) | |
419 | #define BASE_COLOR_SIZE332 ( 7 << 0) | |
420 | #define BASE_COLOR_SIZE888 ( 8 << 0) | |
421 | #define BASE_COLOR_SIZE101010 (10 << 0) | |
422 | #define BASE_COLOR_SIZE121212 (12 << 0) | |
459cc2c6 | 423 | #define DITHER_CONTROL_MASK (3 << 8) |
d8f4a9ed TR |
424 | #define DITHER_CONTROL_DISABLE (0 << 8) |
425 | #define DITHER_CONTROL_ORDERED (2 << 8) | |
426 | #define DITHER_CONTROL_ERRDIFF (3 << 8) | |
459cc2c6 | 427 | #define BASE_COLOR_SIZE_MASK (0xf << 0) |
47307954 TR |
428 | #define BASE_COLOR_SIZE_666 ( 0 << 0) |
429 | #define BASE_COLOR_SIZE_111 ( 1 << 0) | |
430 | #define BASE_COLOR_SIZE_222 ( 2 << 0) | |
431 | #define BASE_COLOR_SIZE_333 ( 3 << 0) | |
432 | #define BASE_COLOR_SIZE_444 ( 4 << 0) | |
433 | #define BASE_COLOR_SIZE_555 ( 5 << 0) | |
434 | #define BASE_COLOR_SIZE_565 ( 6 << 0) | |
435 | #define BASE_COLOR_SIZE_332 ( 7 << 0) | |
436 | #define BASE_COLOR_SIZE_888 ( 8 << 0) | |
437 | #define BASE_COLOR_SIZE_101010 ( 10 << 0) | |
438 | #define BASE_COLOR_SIZE_121212 ( 12 << 0) | |
d8f4a9ed TR |
439 | |
440 | #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 | |
72d30286 TR |
441 | #define SC1_H_QUALIFIER_NONE (1 << 16) |
442 | #define SC0_H_QUALIFIER_NONE (1 << 0) | |
d8f4a9ed TR |
443 | |
444 | #define DC_DISP_DATA_ENABLE_OPTIONS 0x432 | |
445 | #define DE_SELECT_ACTIVE_BLANK (0 << 0) | |
446 | #define DE_SELECT_ACTIVE (1 << 0) | |
447 | #define DE_SELECT_ACTIVE_IS (2 << 0) | |
448 | #define DE_CONTROL_ONECLK (0 << 2) | |
449 | #define DE_CONTROL_NORMAL (1 << 2) | |
450 | #define DE_CONTROL_EARLY_EXT (2 << 2) | |
451 | #define DE_CONTROL_EARLY (3 << 2) | |
452 | #define DE_CONTROL_ACTIVE_BLANK (4 << 2) | |
453 | ||
454 | #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433 | |
455 | #define DC_DISP_LCD_SPI_OPTIONS 0x434 | |
456 | #define DC_DISP_BORDER_COLOR 0x435 | |
457 | #define DC_DISP_COLOR_KEY0_LOWER 0x436 | |
458 | #define DC_DISP_COLOR_KEY0_UPPER 0x437 | |
459 | #define DC_DISP_COLOR_KEY1_LOWER 0x438 | |
460 | #define DC_DISP_COLOR_KEY1_UPPER 0x439 | |
461 | ||
462 | #define DC_DISP_CURSOR_FOREGROUND 0x43c | |
463 | #define DC_DISP_CURSOR_BACKGROUND 0x43d | |
464 | ||
465 | #define DC_DISP_CURSOR_START_ADDR 0x43e | |
e687651b TR |
466 | #define CURSOR_CLIP_DISPLAY (0 << 28) |
467 | #define CURSOR_CLIP_WIN_A (1 << 28) | |
468 | #define CURSOR_CLIP_WIN_B (2 << 28) | |
469 | #define CURSOR_CLIP_WIN_C (3 << 28) | |
470 | #define CURSOR_SIZE_32x32 (0 << 24) | |
471 | #define CURSOR_SIZE_64x64 (1 << 24) | |
472 | #define CURSOR_SIZE_128x128 (2 << 24) | |
473 | #define CURSOR_SIZE_256x256 (3 << 24) | |
d8f4a9ed TR |
474 | #define DC_DISP_CURSOR_START_ADDR_NS 0x43f |
475 | ||
476 | #define DC_DISP_CURSOR_POSITION 0x440 | |
477 | #define DC_DISP_CURSOR_POSITION_NS 0x441 | |
478 | ||
479 | #define DC_DISP_INIT_SEQ_CONTROL 0x442 | |
480 | #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443 | |
481 | #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444 | |
482 | #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445 | |
483 | #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446 | |
484 | ||
485 | #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 | |
486 | #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481 | |
487 | #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482 | |
488 | #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483 | |
489 | #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484 | |
490 | ||
491 | #define DC_DISP_DAC_CRT_CTRL 0x4c0 | |
492 | #define DC_DISP_DISP_MISC_CONTROL 0x4c1 | |
493 | #define DC_DISP_SD_CONTROL 0x4c2 | |
494 | #define DC_DISP_SD_CSC_COEFF 0x4c3 | |
495 | #define DC_DISP_SD_LUT(x) (0x4c4 + (x)) | |
496 | #define DC_DISP_SD_FLICKER_CONTROL 0x4cd | |
497 | #define DC_DISP_DC_PIXEL_COUNT 0x4ce | |
498 | #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x)) | |
499 | #define DC_DISP_SD_BL_PARAMETERS 0x4d7 | |
500 | #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x)) | |
501 | #define DC_DISP_SD_BL_CONTROL 0x4dc | |
502 | #define DC_DISP_SD_HW_K_VALUES 0x4dd | |
503 | #define DC_DISP_SD_MAN_K_VALUES 0x4de | |
504 | ||
7116e9a8 TR |
505 | #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4 |
506 | #define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24) | |
507 | #define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16) | |
508 | #define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8) | |
509 | #define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0) | |
510 | ||
8620fc62 TR |
511 | #define DC_DISP_INTERLACE_CONTROL 0x4e5 |
512 | #define INTERLACE_STATUS (1 << 2) | |
513 | #define INTERLACE_START (1 << 1) | |
514 | #define INTERLACE_ENABLE (1 << 0) | |
515 | ||
e687651b TR |
516 | #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec |
517 | #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 | |
518 | #define CURSOR_MODE_LEGACY (0 << 24) | |
519 | #define CURSOR_MODE_NORMAL (1 << 24) | |
520 | #define CURSOR_DST_BLEND_ZERO (0 << 16) | |
521 | #define CURSOR_DST_BLEND_K1 (1 << 16) | |
522 | #define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16) | |
523 | #define CURSOR_DST_BLEND_MASK (3 << 16) | |
524 | #define CURSOR_SRC_BLEND_K1 (0 << 8) | |
525 | #define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8) | |
526 | #define CURSOR_SRC_BLEND_MASK (3 << 8) | |
527 | #define CURSOR_ALPHA 0xff | |
528 | ||
c4755fb9 TR |
529 | #define DC_WIN_CORE_ACT_CONTROL 0x50e |
530 | #define VCOUNTER (0 << 0) | |
531 | #define HCOUNTER (1 << 0) | |
532 | ||
533 | #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543 | |
534 | #define LATENCY_CTL_MODE_ENABLE (1 << 2) | |
535 | ||
536 | #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544 | |
537 | #define WATERMARK_MASK 0x1fffffff | |
538 | ||
539 | #define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560 | |
540 | #define PIPE_METER_INT(x) (((x) & 0xff) << 8) | |
541 | #define PIPE_METER_FRAC(x) (((x) & 0xff) << 0) | |
542 | ||
543 | #define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561 | |
544 | #define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0) | |
545 | ||
546 | #define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562 | |
547 | #define SLOTS(x) (((x) & 0xff) << 0) | |
548 | ||
549 | #define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563 | |
550 | #define MODE_TWO_LINES (0 << 14) | |
551 | #define MODE_FOUR_LINES (1 << 14) | |
552 | ||
553 | #define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568 | |
554 | #define THREAD_NUM_MASK (0x1f << 1) | |
555 | #define THREAD_NUM(x) (((x) & 0x1f) << 1) | |
556 | #define THREAD_GROUP_ENABLE (1 << 0) | |
557 | ||
acc6a3a9 DO |
558 | #define DC_WIN_H_FILTER_P(p) (0x601 + (p)) |
559 | #define DC_WIN_V_FILTER_P(p) (0x619 + (p)) | |
560 | ||
f34bc787 TR |
561 | #define DC_WIN_CSC_YOF 0x611 |
562 | #define DC_WIN_CSC_KYRGB 0x612 | |
563 | #define DC_WIN_CSC_KUR 0x613 | |
564 | #define DC_WIN_CSC_KVR 0x614 | |
565 | #define DC_WIN_CSC_KUG 0x615 | |
566 | #define DC_WIN_CSC_KVG 0x616 | |
567 | #define DC_WIN_CSC_KUB 0x617 | |
568 | #define DC_WIN_CSC_KVB 0x618 | |
569 | ||
d8f4a9ed | 570 | #define DC_WIN_WIN_OPTIONS 0x700 |
eba66501 TR |
571 | #define H_DIRECTION (1 << 0) |
572 | #define V_DIRECTION (1 << 2) | |
d8f4a9ed | 573 | #define COLOR_EXPAND (1 << 6) |
acc6a3a9 DO |
574 | #define H_FILTER (1 << 8) |
575 | #define V_FILTER (1 << 10) | |
f34bc787 | 576 | #define CSC_ENABLE (1 << 18) |
d8f4a9ed TR |
577 | #define WIN_ENABLE (1 << 30) |
578 | ||
579 | #define DC_WIN_BYTE_SWAP 0x701 | |
580 | #define BYTE_SWAP_NOSWAP (0 << 0) | |
581 | #define BYTE_SWAP_SWAP2 (1 << 0) | |
582 | #define BYTE_SWAP_SWAP4 (2 << 0) | |
583 | #define BYTE_SWAP_SWAP4HW (3 << 0) | |
584 | ||
585 | #define DC_WIN_BUFFER_CONTROL 0x702 | |
586 | #define BUFFER_CONTROL_HOST (0 << 0) | |
587 | #define BUFFER_CONTROL_VI (1 << 0) | |
588 | #define BUFFER_CONTROL_EPP (2 << 0) | |
589 | #define BUFFER_CONTROL_MPEGE (3 << 0) | |
590 | #define BUFFER_CONTROL_SB2D (4 << 0) | |
591 | ||
592 | #define DC_WIN_COLOR_DEPTH 0x703 | |
593 | #define WIN_COLOR_DEPTH_P1 0 | |
594 | #define WIN_COLOR_DEPTH_P2 1 | |
595 | #define WIN_COLOR_DEPTH_P4 2 | |
596 | #define WIN_COLOR_DEPTH_P8 3 | |
597 | #define WIN_COLOR_DEPTH_B4G4R4A4 4 | |
511c7023 | 598 | #define WIN_COLOR_DEPTH_B5G5R5A1 5 |
d8f4a9ed | 599 | #define WIN_COLOR_DEPTH_B5G6R5 6 |
511c7023 | 600 | #define WIN_COLOR_DEPTH_A1B5G5R5 7 |
d8f4a9ed TR |
601 | #define WIN_COLOR_DEPTH_B8G8R8A8 12 |
602 | #define WIN_COLOR_DEPTH_R8G8B8A8 13 | |
603 | #define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14 | |
604 | #define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15 | |
605 | #define WIN_COLOR_DEPTH_YCbCr422 16 | |
606 | #define WIN_COLOR_DEPTH_YUV422 17 | |
607 | #define WIN_COLOR_DEPTH_YCbCr420P 18 | |
608 | #define WIN_COLOR_DEPTH_YUV420P 19 | |
609 | #define WIN_COLOR_DEPTH_YCbCr422P 20 | |
610 | #define WIN_COLOR_DEPTH_YUV422P 21 | |
611 | #define WIN_COLOR_DEPTH_YCbCr422R 22 | |
612 | #define WIN_COLOR_DEPTH_YUV422R 23 | |
613 | #define WIN_COLOR_DEPTH_YCbCr422RA 24 | |
614 | #define WIN_COLOR_DEPTH_YUV422RA 25 | |
511c7023 TR |
615 | #define WIN_COLOR_DEPTH_R4G4B4A4 27 |
616 | #define WIN_COLOR_DEPTH_R5G5B5A 28 | |
617 | #define WIN_COLOR_DEPTH_AR5G5B5 29 | |
618 | #define WIN_COLOR_DEPTH_B5G5R5X1 30 | |
619 | #define WIN_COLOR_DEPTH_X1B5G5R5 31 | |
620 | #define WIN_COLOR_DEPTH_R5G5B5X1 32 | |
621 | #define WIN_COLOR_DEPTH_X1R5G5B5 33 | |
622 | #define WIN_COLOR_DEPTH_R5G6B5 34 | |
623 | #define WIN_COLOR_DEPTH_A8R8G8B8 35 | |
624 | #define WIN_COLOR_DEPTH_A8B8G8R8 36 | |
7772fdae TR |
625 | #define WIN_COLOR_DEPTH_B8G8R8X8 37 |
626 | #define WIN_COLOR_DEPTH_R8G8B8X8 38 | |
511c7023 TR |
627 | #define WIN_COLOR_DEPTH_X8B8G8R8 65 |
628 | #define WIN_COLOR_DEPTH_X8R8G8B8 66 | |
d8f4a9ed TR |
629 | |
630 | #define DC_WIN_POSITION 0x704 | |
47307954 TR |
631 | #define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ |
632 | #define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ | |
d8f4a9ed TR |
633 | |
634 | #define DC_WIN_SIZE 0x705 | |
47307954 TR |
635 | #define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ |
636 | #define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ | |
d8f4a9ed TR |
637 | |
638 | #define DC_WIN_PRESCALED_SIZE 0x706 | |
639 | #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) | |
47307954 | 640 | #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ |
d8f4a9ed TR |
641 | |
642 | #define DC_WIN_H_INITIAL_DDA 0x707 | |
643 | #define DC_WIN_V_INITIAL_DDA 0x708 | |
644 | #define DC_WIN_DDA_INC 0x709 | |
645 | #define H_DDA_INC(x) (((x) & 0xffff) << 0) | |
646 | #define V_DDA_INC(x) (((x) & 0xffff) << 16) | |
647 | ||
648 | #define DC_WIN_LINE_STRIDE 0x70a | |
649 | #define DC_WIN_BUF_STRIDE 0x70b | |
650 | #define DC_WIN_UV_BUF_STRIDE 0x70c | |
651 | #define DC_WIN_BUFFER_ADDR_MODE 0x70d | |
773af77f TR |
652 | #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0) |
653 | #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0) | |
654 | #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16) | |
655 | #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16) | |
47307954 | 656 | |
d8f4a9ed TR |
657 | #define DC_WIN_DV_CONTROL 0x70e |
658 | ||
659 | #define DC_WIN_BLEND_NOKEY 0x70f | |
ebae8d07 TR |
660 | #define BLEND_WEIGHT1(x) (((x) & 0xff) << 16) |
661 | #define BLEND_WEIGHT0(x) (((x) & 0xff) << 8) | |
662 | ||
d8f4a9ed | 663 | #define DC_WIN_BLEND_1WIN 0x710 |
ebae8d07 TR |
664 | #define BLEND_CONTROL_FIX (0 << 2) |
665 | #define BLEND_CONTROL_ALPHA (1 << 2) | |
666 | #define BLEND_COLOR_KEY_NONE (0 << 0) | |
667 | #define BLEND_COLOR_KEY_0 (1 << 0) | |
668 | #define BLEND_COLOR_KEY_1 (2 << 0) | |
669 | #define BLEND_COLOR_KEY_BOTH (3 << 0) | |
670 | ||
d8f4a9ed | 671 | #define DC_WIN_BLEND_2WIN_X 0x711 |
ebae8d07 TR |
672 | #define BLEND_CONTROL_DEPENDENT (2 << 2) |
673 | ||
d8f4a9ed | 674 | #define DC_WIN_BLEND_2WIN_Y 0x712 |
f34bc787 | 675 | #define DC_WIN_BLEND_3WIN_XY 0x713 |
d8f4a9ed TR |
676 | |
677 | #define DC_WIN_HP_FETCH_CONTROL 0x714 | |
678 | ||
679 | #define DC_WINBUF_START_ADDR 0x800 | |
680 | #define DC_WINBUF_START_ADDR_NS 0x801 | |
681 | #define DC_WINBUF_START_ADDR_U 0x802 | |
682 | #define DC_WINBUF_START_ADDR_U_NS 0x803 | |
683 | #define DC_WINBUF_START_ADDR_V 0x804 | |
684 | #define DC_WINBUF_START_ADDR_V_NS 0x805 | |
685 | ||
686 | #define DC_WINBUF_ADDR_H_OFFSET 0x806 | |
687 | #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807 | |
688 | #define DC_WINBUF_ADDR_V_OFFSET 0x808 | |
689 | #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 | |
690 | ||
691 | #define DC_WINBUF_UFLOW_STATUS 0x80a | |
c134f019 TR |
692 | #define DC_WINBUF_SURFACE_KIND 0x80b |
693 | #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0) | |
694 | #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0) | |
695 | #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0) | |
696 | #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) | |
d8f4a9ed | 697 | |
31b02cae TR |
698 | #define DC_WINBUF_START_ADDR_HI 0x80d |
699 | ||
c4755fb9 TR |
700 | #define DC_WINBUF_CDE_CONTROL 0x82f |
701 | #define ENABLE_SURFACE (1 << 0) | |
702 | ||
d8f4a9ed TR |
703 | #define DC_WINBUF_AD_UFLOW_STATUS 0xbca |
704 | #define DC_WINBUF_BD_UFLOW_STATUS 0xdca | |
705 | #define DC_WINBUF_CD_UFLOW_STATUS 0xfca | |
706 | ||
c4755fb9 | 707 | /* Tegra186 and later */ |
47307954 TR |
708 | #define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x)) |
709 | #define PROTOCOL_MASK (0xf << 8) | |
710 | #define PROTOCOL_SINGLE_TMDS_A (0x1 << 8) | |
711 | ||
c4755fb9 TR |
712 | #define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702 |
713 | #define OWNER_MASK (0xf << 0) | |
714 | #define OWNER(x) (((x) & 0xf) << 0) | |
715 | ||
716 | #define DC_WIN_CROPPED_SIZE 0x706 | |
717 | ||
718 | #define DC_WIN_PLANAR_STORAGE 0x709 | |
719 | #define PITCH(x) (((x) >> 6) & 0x1fff) | |
720 | ||
721 | #define DC_WIN_SET_PARAMS 0x70d | |
722 | #define CLAMP_BEFORE_BLEND (1 << 15) | |
723 | #define DEGAMMA_NONE (0 << 13) | |
724 | #define DEGAMMA_SRGB (1 << 13) | |
725 | #define DEGAMMA_YUV8_10 (2 << 13) | |
726 | #define DEGAMMA_YUV12 (3 << 13) | |
727 | #define INPUT_RANGE_BYPASS (0 << 10) | |
728 | #define INPUT_RANGE_LIMITED (1 << 10) | |
729 | #define INPUT_RANGE_FULL (2 << 10) | |
730 | #define COLOR_SPACE_RGB (0 << 8) | |
731 | #define COLOR_SPACE_YUV_601 (1 << 8) | |
732 | #define COLOR_SPACE_YUV_709 (2 << 8) | |
733 | #define COLOR_SPACE_YUV_2020 (3 << 8) | |
734 | ||
735 | #define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e | |
736 | #define HORIZONTAL_TAPS_2 (1 << 3) | |
737 | #define HORIZONTAL_TAPS_5 (4 << 3) | |
738 | #define VERTICAL_TAPS_2 (1 << 0) | |
739 | #define VERTICAL_TAPS_5 (4 << 0) | |
740 | ||
741 | #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711 | |
742 | #define INPUT_SCALER_USE422 (1 << 2) | |
743 | #define INPUT_SCALER_VBYPASS (1 << 1) | |
744 | #define INPUT_SCALER_HBYPASS (1 << 0) | |
745 | ||
746 | #define DC_WIN_BLEND_LAYER_CONTROL 0x716 | |
747 | #define COLOR_KEY_NONE (0 << 25) | |
748 | #define COLOR_KEY_SRC (1 << 25) | |
749 | #define COLOR_KEY_DST (2 << 25) | |
750 | #define BLEND_BYPASS (1 << 24) | |
751 | #define K2(x) (((x) & 0xff) << 16) | |
752 | #define K1(x) (((x) & 0xff) << 8) | |
753 | #define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0) | |
754 | ||
755 | #define DC_WIN_BLEND_MATCH_SELECT 0x717 | |
756 | #define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12) | |
757 | #define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12) | |
758 | #define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12) | |
759 | #define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12) | |
760 | #define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8) | |
761 | #define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8) | |
762 | #define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8) | |
763 | #define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8) | |
764 | #define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4) | |
765 | #define BLEND_FACTOR_DST_COLOR_ONE (1 << 4) | |
766 | #define BLEND_FACTOR_DST_COLOR_K1 (2 << 4) | |
767 | #define BLEND_FACTOR_DST_COLOR_K2 (3 << 4) | |
768 | #define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4) | |
769 | #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4) | |
770 | #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4) | |
771 | #define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4) | |
772 | #define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0) | |
773 | #define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0) | |
774 | #define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0) | |
775 | #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0) | |
776 | #define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0) | |
777 | #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0) | |
778 | ||
779 | #define DC_WIN_BLEND_NOMATCH_SELECT 0x718 | |
780 | ||
781 | #define DC_WIN_PRECOMP_WGRP_PARAMS 0x724 | |
782 | #define SWAP_UV (1 << 0) | |
783 | ||
784 | #define DC_WIN_WINDOW_SET_CONTROL 0x730 | |
785 | #define CONTROL_CSC_ENABLE (1 << 5) | |
786 | ||
787 | #define DC_WINBUF_CROPPED_POINT 0x806 | |
788 | #define OFFSET_Y(x) (((x) & 0xffff) << 16) | |
789 | #define OFFSET_X(x) (((x) & 0xffff) << 0) | |
790 | ||
d8f4a9ed | 791 | #endif /* TEGRA_DC_H */ |