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d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #ifndef TEGRA_DC_H | |
11 | #define TEGRA_DC_H 1 | |
12 | ||
2d1c18fb TR |
13 | #include <linux/host1x.h> |
14 | ||
15 | #include <drm/drm_crtc.h> | |
16 | ||
17 | #include "drm.h" | |
18 | ||
19 | struct tegra_output; | |
20 | ||
21 | struct tegra_dc_stats { | |
22 | unsigned long frames; | |
23 | unsigned long vblank; | |
24 | unsigned long underflow; | |
25 | unsigned long overflow; | |
26 | }; | |
27 | ||
28 | struct tegra_dc_soc_info { | |
7116e9a8 | 29 | bool supports_background_color; |
2d1c18fb TR |
30 | bool supports_interlacing; |
31 | bool supports_cursor; | |
32 | bool supports_block_linear; | |
33 | unsigned int pitch_align; | |
34 | bool has_powergate; | |
35 | bool broken_reset; | |
36 | }; | |
37 | ||
38 | struct tegra_dc { | |
39 | struct host1x_client client; | |
40 | struct host1x_syncpt *syncpt; | |
41 | struct device *dev; | |
42 | spinlock_t lock; | |
43 | ||
44 | struct drm_crtc base; | |
45 | unsigned int powergate; | |
46 | int pipe; | |
47 | ||
48 | struct clk *clk; | |
49 | struct reset_control *rst; | |
50 | void __iomem *regs; | |
51 | int irq; | |
52 | ||
53 | struct tegra_output *rgb; | |
54 | ||
55 | struct tegra_dc_stats stats; | |
56 | struct list_head list; | |
57 | ||
58 | struct drm_info_list *debugfs_files; | |
2d1c18fb | 59 | |
2d1c18fb TR |
60 | const struct tegra_dc_soc_info *soc; |
61 | ||
62 | struct iommu_domain *domain; | |
63 | }; | |
64 | ||
65 | static inline struct tegra_dc * | |
66 | host1x_client_to_dc(struct host1x_client *client) | |
67 | { | |
68 | return container_of(client, struct tegra_dc, client); | |
69 | } | |
70 | ||
71 | static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) | |
72 | { | |
73 | return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; | |
74 | } | |
75 | ||
76 | static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, | |
77 | unsigned int offset) | |
78 | { | |
79 | trace_dc_writel(dc->dev, offset, value); | |
80 | writel(value, dc->regs + (offset << 2)); | |
81 | } | |
82 | ||
83 | static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) | |
84 | { | |
85 | u32 value = readl(dc->regs + (offset << 2)); | |
86 | ||
87 | trace_dc_readl(dc->dev, offset, value); | |
88 | ||
89 | return value; | |
90 | } | |
91 | ||
92 | struct tegra_dc_window { | |
93 | struct { | |
94 | unsigned int x; | |
95 | unsigned int y; | |
96 | unsigned int w; | |
97 | unsigned int h; | |
98 | } src; | |
99 | struct { | |
100 | unsigned int x; | |
101 | unsigned int y; | |
102 | unsigned int w; | |
103 | unsigned int h; | |
104 | } dst; | |
105 | unsigned int bits_per_pixel; | |
106 | unsigned int stride[2]; | |
107 | unsigned long base[3]; | |
108 | bool bottom_up; | |
109 | ||
110 | struct tegra_bo_tiling tiling; | |
111 | u32 format; | |
112 | u32 swap; | |
113 | }; | |
114 | ||
115 | /* from dc.c */ | |
116 | void tegra_dc_commit(struct tegra_dc *dc); | |
117 | int tegra_dc_state_setup_clock(struct tegra_dc *dc, | |
118 | struct drm_crtc_state *crtc_state, | |
119 | struct clk *clk, unsigned long pclk, | |
120 | unsigned int div); | |
121 | ||
122 | /* from rgb.c */ | |
123 | int tegra_dc_rgb_probe(struct tegra_dc *dc); | |
124 | int tegra_dc_rgb_remove(struct tegra_dc *dc); | |
125 | int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); | |
126 | int tegra_dc_rgb_exit(struct tegra_dc *dc); | |
127 | ||
d8f4a9ed TR |
128 | #define DC_CMD_GENERAL_INCR_SYNCPT 0x000 |
129 | #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 | |
42e9ce05 TR |
130 | #define SYNCPT_CNTRL_NO_STALL (1 << 8) |
131 | #define SYNCPT_CNTRL_SOFT_RESET (1 << 0) | |
d8f4a9ed TR |
132 | #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 |
133 | #define DC_CMD_WIN_A_INCR_SYNCPT 0x008 | |
134 | #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 | |
135 | #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a | |
136 | #define DC_CMD_WIN_B_INCR_SYNCPT 0x010 | |
137 | #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 | |
138 | #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 | |
139 | #define DC_CMD_WIN_C_INCR_SYNCPT 0x018 | |
140 | #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019 | |
141 | #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a | |
142 | #define DC_CMD_CONT_SYNCPT_VSYNC 0x028 | |
42e9ce05 | 143 | #define SYNCPT_VSYNC_ENABLE (1 << 8) |
d8f4a9ed TR |
144 | #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 |
145 | #define DC_CMD_DISPLAY_COMMAND 0x032 | |
146 | #define DISP_CTRL_MODE_STOP (0 << 5) | |
147 | #define DISP_CTRL_MODE_C_DISPLAY (1 << 5) | |
148 | #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) | |
dec72739 | 149 | #define DISP_CTRL_MODE_MASK (3 << 5) |
d8f4a9ed TR |
150 | #define DC_CMD_SIGNAL_RAISE 0x033 |
151 | #define DC_CMD_DISPLAY_POWER_CONTROL 0x036 | |
152 | #define PW0_ENABLE (1 << 0) | |
153 | #define PW1_ENABLE (1 << 2) | |
154 | #define PW2_ENABLE (1 << 4) | |
155 | #define PW3_ENABLE (1 << 6) | |
156 | #define PW4_ENABLE (1 << 8) | |
157 | #define PM0_ENABLE (1 << 16) | |
158 | #define PM1_ENABLE (1 << 18) | |
159 | ||
160 | #define DC_CMD_INT_STATUS 0x037 | |
161 | #define DC_CMD_INT_MASK 0x038 | |
162 | #define DC_CMD_INT_ENABLE 0x039 | |
163 | #define DC_CMD_INT_TYPE 0x03a | |
164 | #define DC_CMD_INT_POLARITY 0x03b | |
165 | #define CTXSW_INT (1 << 0) | |
166 | #define FRAME_END_INT (1 << 1) | |
167 | #define VBLANK_INT (1 << 2) | |
168 | #define WIN_A_UF_INT (1 << 8) | |
169 | #define WIN_B_UF_INT (1 << 9) | |
170 | #define WIN_C_UF_INT (1 << 10) | |
171 | #define WIN_A_OF_INT (1 << 14) | |
172 | #define WIN_B_OF_INT (1 << 15) | |
173 | #define WIN_C_OF_INT (1 << 16) | |
174 | ||
175 | #define DC_CMD_SIGNAL_RAISE1 0x03c | |
176 | #define DC_CMD_SIGNAL_RAISE2 0x03d | |
177 | #define DC_CMD_SIGNAL_RAISE3 0x03e | |
178 | ||
179 | #define DC_CMD_STATE_ACCESS 0x040 | |
3c03c46a TR |
180 | #define READ_MUX (1 << 0) |
181 | #define WRITE_MUX (1 << 2) | |
d8f4a9ed TR |
182 | |
183 | #define DC_CMD_STATE_CONTROL 0x041 | |
184 | #define GENERAL_ACT_REQ (1 << 0) | |
185 | #define WIN_A_ACT_REQ (1 << 1) | |
186 | #define WIN_B_ACT_REQ (1 << 2) | |
187 | #define WIN_C_ACT_REQ (1 << 3) | |
e687651b | 188 | #define CURSOR_ACT_REQ (1 << 7) |
d8f4a9ed TR |
189 | #define GENERAL_UPDATE (1 << 8) |
190 | #define WIN_A_UPDATE (1 << 9) | |
191 | #define WIN_B_UPDATE (1 << 10) | |
192 | #define WIN_C_UPDATE (1 << 11) | |
e687651b | 193 | #define CURSOR_UPDATE (1 << 15) |
d8f4a9ed TR |
194 | #define NC_HOST_TRIG (1 << 24) |
195 | ||
196 | #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 | |
197 | #define WINDOW_A_SELECT (1 << 4) | |
198 | #define WINDOW_B_SELECT (1 << 5) | |
199 | #define WINDOW_C_SELECT (1 << 6) | |
200 | ||
201 | #define DC_CMD_REG_ACT_CONTROL 0x043 | |
202 | ||
203 | #define DC_COM_CRC_CONTROL 0x300 | |
6ca1f62f TR |
204 | #define DC_COM_CRC_CONTROL_ALWAYS (1 << 3) |
205 | #define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2) | |
206 | #define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2) | |
207 | #define DC_COM_CRC_CONTROL_WAIT (1 << 1) | |
208 | #define DC_COM_CRC_CONTROL_ENABLE (1 << 0) | |
d8f4a9ed TR |
209 | #define DC_COM_CRC_CHECKSUM 0x301 |
210 | #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) | |
211 | #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) | |
212 | #define LVS_OUTPUT_POLARITY_LOW (1 << 28) | |
213 | #define LHS_OUTPUT_POLARITY_LOW (1 << 30) | |
214 | #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x)) | |
215 | #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x)) | |
216 | #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x)) | |
217 | #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x)) | |
218 | ||
219 | #define DC_COM_PIN_MISC_CONTROL 0x31b | |
220 | #define DC_COM_PIN_PM0_CONTROL 0x31c | |
221 | #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d | |
222 | #define DC_COM_PIN_PM1_CONTROL 0x31e | |
223 | #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f | |
224 | ||
225 | #define DC_COM_SPI_CONTROL 0x320 | |
226 | #define DC_COM_SPI_START_BYTE 0x321 | |
227 | #define DC_COM_HSPI_WRITE_DATA_AB 0x322 | |
228 | #define DC_COM_HSPI_WRITE_DATA_CD 0x323 | |
229 | #define DC_COM_HSPI_CS_DC 0x324 | |
230 | #define DC_COM_SCRATCH_REGISTER_A 0x325 | |
231 | #define DC_COM_SCRATCH_REGISTER_B 0x326 | |
232 | #define DC_COM_GPIO_CTRL 0x327 | |
233 | #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328 | |
234 | #define DC_COM_CRC_CHECKSUM_LATCHED 0x329 | |
235 | ||
236 | #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 | |
8fd3ffa9 TR |
237 | #define H_PULSE0_ENABLE (1 << 8) |
238 | #define H_PULSE1_ENABLE (1 << 10) | |
239 | #define H_PULSE2_ENABLE (1 << 12) | |
d8f4a9ed TR |
240 | |
241 | #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 | |
242 | ||
243 | #define DC_DISP_DISP_WIN_OPTIONS 0x402 | |
e687651b TR |
244 | #define HDMI_ENABLE (1 << 30) |
245 | #define DSI_ENABLE (1 << 29) | |
459cc2c6 TR |
246 | #define SOR1_TIMING_CYA (1 << 27) |
247 | #define SOR1_ENABLE (1 << 26) | |
e687651b TR |
248 | #define SOR_ENABLE (1 << 25) |
249 | #define CURSOR_ENABLE (1 << 16) | |
d8f4a9ed TR |
250 | |
251 | #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 | |
252 | #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) | |
253 | #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16) | |
254 | #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8) | |
255 | #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0) | |
256 | ||
257 | #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 | |
258 | #define CURSOR_DELAY(x) (((x) & 0x3f) << 24) | |
259 | #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16) | |
260 | #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8) | |
261 | #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0) | |
262 | ||
263 | #define DC_DISP_DISP_TIMING_OPTIONS 0x405 | |
264 | #define VSYNC_H_POSITION(x) ((x) & 0xfff) | |
265 | ||
266 | #define DC_DISP_REF_TO_SYNC 0x406 | |
267 | #define DC_DISP_SYNC_WIDTH 0x407 | |
268 | #define DC_DISP_BACK_PORCH 0x408 | |
269 | #define DC_DISP_ACTIVE 0x409 | |
270 | #define DC_DISP_FRONT_PORCH 0x40a | |
271 | #define DC_DISP_H_PULSE0_CONTROL 0x40b | |
272 | #define DC_DISP_H_PULSE0_POSITION_A 0x40c | |
273 | #define DC_DISP_H_PULSE0_POSITION_B 0x40d | |
274 | #define DC_DISP_H_PULSE0_POSITION_C 0x40e | |
275 | #define DC_DISP_H_PULSE0_POSITION_D 0x40f | |
276 | #define DC_DISP_H_PULSE1_CONTROL 0x410 | |
277 | #define DC_DISP_H_PULSE1_POSITION_A 0x411 | |
278 | #define DC_DISP_H_PULSE1_POSITION_B 0x412 | |
279 | #define DC_DISP_H_PULSE1_POSITION_C 0x413 | |
280 | #define DC_DISP_H_PULSE1_POSITION_D 0x414 | |
281 | #define DC_DISP_H_PULSE2_CONTROL 0x415 | |
282 | #define DC_DISP_H_PULSE2_POSITION_A 0x416 | |
283 | #define DC_DISP_H_PULSE2_POSITION_B 0x417 | |
284 | #define DC_DISP_H_PULSE2_POSITION_C 0x418 | |
285 | #define DC_DISP_H_PULSE2_POSITION_D 0x419 | |
286 | #define DC_DISP_V_PULSE0_CONTROL 0x41a | |
287 | #define DC_DISP_V_PULSE0_POSITION_A 0x41b | |
288 | #define DC_DISP_V_PULSE0_POSITION_B 0x41c | |
289 | #define DC_DISP_V_PULSE0_POSITION_C 0x41d | |
290 | #define DC_DISP_V_PULSE1_CONTROL 0x41e | |
291 | #define DC_DISP_V_PULSE1_POSITION_A 0x41f | |
292 | #define DC_DISP_V_PULSE1_POSITION_B 0x420 | |
293 | #define DC_DISP_V_PULSE1_POSITION_C 0x421 | |
294 | #define DC_DISP_V_PULSE2_CONTROL 0x422 | |
295 | #define DC_DISP_V_PULSE2_POSITION_A 0x423 | |
296 | #define DC_DISP_V_PULSE3_CONTROL 0x424 | |
297 | #define DC_DISP_V_PULSE3_POSITION_A 0x425 | |
298 | #define DC_DISP_M0_CONTROL 0x426 | |
299 | #define DC_DISP_M1_CONTROL 0x427 | |
300 | #define DC_DISP_DI_CONTROL 0x428 | |
301 | #define DC_DISP_PP_CONTROL 0x429 | |
302 | #define DC_DISP_PP_SELECT_A 0x42a | |
303 | #define DC_DISP_PP_SELECT_B 0x42b | |
304 | #define DC_DISP_PP_SELECT_C 0x42c | |
305 | #define DC_DISP_PP_SELECT_D 0x42d | |
306 | ||
307 | #define PULSE_MODE_NORMAL (0 << 3) | |
308 | #define PULSE_MODE_ONE_CLOCK (1 << 3) | |
309 | #define PULSE_POLARITY_HIGH (0 << 4) | |
310 | #define PULSE_POLARITY_LOW (1 << 4) | |
311 | #define PULSE_QUAL_ALWAYS (0 << 6) | |
312 | #define PULSE_QUAL_VACTIVE (2 << 6) | |
313 | #define PULSE_QUAL_VACTIVE1 (3 << 6) | |
314 | #define PULSE_LAST_START_A (0 << 8) | |
315 | #define PULSE_LAST_END_A (1 << 8) | |
316 | #define PULSE_LAST_START_B (2 << 8) | |
317 | #define PULSE_LAST_END_B (3 << 8) | |
318 | #define PULSE_LAST_START_C (4 << 8) | |
319 | #define PULSE_LAST_END_C (5 << 8) | |
320 | #define PULSE_LAST_START_D (6 << 8) | |
321 | #define PULSE_LAST_END_D (7 << 8) | |
322 | ||
323 | #define PULSE_START(x) (((x) & 0xfff) << 0) | |
324 | #define PULSE_END(x) (((x) & 0xfff) << 16) | |
325 | ||
326 | #define DC_DISP_DISP_CLOCK_CONTROL 0x42e | |
327 | #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) | |
328 | #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) | |
329 | #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) | |
330 | #define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) | |
331 | #define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) | |
332 | #define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) | |
333 | #define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) | |
334 | #define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) | |
335 | #define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) | |
336 | #define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) | |
337 | #define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) | |
338 | #define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) | |
339 | #define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) | |
340 | #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) | |
341 | ||
342 | #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f | |
343 | #define DISP_DATA_FORMAT_DF1P1C (0 << 0) | |
344 | #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) | |
345 | #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) | |
346 | #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) | |
347 | #define DISP_DATA_FORMAT_DF2S (4 << 0) | |
348 | #define DISP_DATA_FORMAT_DF3S (5 << 0) | |
349 | #define DISP_DATA_FORMAT_DFSPI (6 << 0) | |
350 | #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) | |
351 | #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) | |
352 | #define DISP_ALIGNMENT_MSB (0 << 8) | |
353 | #define DISP_ALIGNMENT_LSB (1 << 8) | |
354 | #define DISP_ORDER_RED_BLUE (0 << 9) | |
355 | #define DISP_ORDER_BLUE_RED (1 << 9) | |
356 | ||
357 | #define DC_DISP_DISP_COLOR_CONTROL 0x430 | |
358 | #define BASE_COLOR_SIZE666 (0 << 0) | |
359 | #define BASE_COLOR_SIZE111 (1 << 0) | |
360 | #define BASE_COLOR_SIZE222 (2 << 0) | |
361 | #define BASE_COLOR_SIZE333 (3 << 0) | |
362 | #define BASE_COLOR_SIZE444 (4 << 0) | |
363 | #define BASE_COLOR_SIZE555 (5 << 0) | |
364 | #define BASE_COLOR_SIZE565 (6 << 0) | |
365 | #define BASE_COLOR_SIZE332 (7 << 0) | |
366 | #define BASE_COLOR_SIZE888 (8 << 0) | |
459cc2c6 | 367 | #define DITHER_CONTROL_MASK (3 << 8) |
d8f4a9ed TR |
368 | #define DITHER_CONTROL_DISABLE (0 << 8) |
369 | #define DITHER_CONTROL_ORDERED (2 << 8) | |
370 | #define DITHER_CONTROL_ERRDIFF (3 << 8) | |
459cc2c6 | 371 | #define BASE_COLOR_SIZE_MASK (0xf << 0) |
472a6d1f TR |
372 | #define BASE_COLOR_SIZE_666 (0 << 0) |
373 | #define BASE_COLOR_SIZE_111 (1 << 0) | |
374 | #define BASE_COLOR_SIZE_222 (2 << 0) | |
375 | #define BASE_COLOR_SIZE_333 (3 << 0) | |
376 | #define BASE_COLOR_SIZE_444 (4 << 0) | |
377 | #define BASE_COLOR_SIZE_555 (5 << 0) | |
378 | #define BASE_COLOR_SIZE_565 (6 << 0) | |
379 | #define BASE_COLOR_SIZE_332 (7 << 0) | |
380 | #define BASE_COLOR_SIZE_888 (8 << 0) | |
d8f4a9ed TR |
381 | |
382 | #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 | |
72d30286 TR |
383 | #define SC1_H_QUALIFIER_NONE (1 << 16) |
384 | #define SC0_H_QUALIFIER_NONE (1 << 0) | |
d8f4a9ed TR |
385 | |
386 | #define DC_DISP_DATA_ENABLE_OPTIONS 0x432 | |
387 | #define DE_SELECT_ACTIVE_BLANK (0 << 0) | |
388 | #define DE_SELECT_ACTIVE (1 << 0) | |
389 | #define DE_SELECT_ACTIVE_IS (2 << 0) | |
390 | #define DE_CONTROL_ONECLK (0 << 2) | |
391 | #define DE_CONTROL_NORMAL (1 << 2) | |
392 | #define DE_CONTROL_EARLY_EXT (2 << 2) | |
393 | #define DE_CONTROL_EARLY (3 << 2) | |
394 | #define DE_CONTROL_ACTIVE_BLANK (4 << 2) | |
395 | ||
396 | #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433 | |
397 | #define DC_DISP_LCD_SPI_OPTIONS 0x434 | |
398 | #define DC_DISP_BORDER_COLOR 0x435 | |
399 | #define DC_DISP_COLOR_KEY0_LOWER 0x436 | |
400 | #define DC_DISP_COLOR_KEY0_UPPER 0x437 | |
401 | #define DC_DISP_COLOR_KEY1_LOWER 0x438 | |
402 | #define DC_DISP_COLOR_KEY1_UPPER 0x439 | |
403 | ||
404 | #define DC_DISP_CURSOR_FOREGROUND 0x43c | |
405 | #define DC_DISP_CURSOR_BACKGROUND 0x43d | |
406 | ||
407 | #define DC_DISP_CURSOR_START_ADDR 0x43e | |
e687651b TR |
408 | #define CURSOR_CLIP_DISPLAY (0 << 28) |
409 | #define CURSOR_CLIP_WIN_A (1 << 28) | |
410 | #define CURSOR_CLIP_WIN_B (2 << 28) | |
411 | #define CURSOR_CLIP_WIN_C (3 << 28) | |
412 | #define CURSOR_SIZE_32x32 (0 << 24) | |
413 | #define CURSOR_SIZE_64x64 (1 << 24) | |
414 | #define CURSOR_SIZE_128x128 (2 << 24) | |
415 | #define CURSOR_SIZE_256x256 (3 << 24) | |
d8f4a9ed TR |
416 | #define DC_DISP_CURSOR_START_ADDR_NS 0x43f |
417 | ||
418 | #define DC_DISP_CURSOR_POSITION 0x440 | |
419 | #define DC_DISP_CURSOR_POSITION_NS 0x441 | |
420 | ||
421 | #define DC_DISP_INIT_SEQ_CONTROL 0x442 | |
422 | #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443 | |
423 | #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444 | |
424 | #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445 | |
425 | #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446 | |
426 | ||
427 | #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 | |
428 | #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481 | |
429 | #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482 | |
430 | #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483 | |
431 | #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484 | |
432 | ||
433 | #define DC_DISP_DAC_CRT_CTRL 0x4c0 | |
434 | #define DC_DISP_DISP_MISC_CONTROL 0x4c1 | |
435 | #define DC_DISP_SD_CONTROL 0x4c2 | |
436 | #define DC_DISP_SD_CSC_COEFF 0x4c3 | |
437 | #define DC_DISP_SD_LUT(x) (0x4c4 + (x)) | |
438 | #define DC_DISP_SD_FLICKER_CONTROL 0x4cd | |
439 | #define DC_DISP_DC_PIXEL_COUNT 0x4ce | |
440 | #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x)) | |
441 | #define DC_DISP_SD_BL_PARAMETERS 0x4d7 | |
442 | #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x)) | |
443 | #define DC_DISP_SD_BL_CONTROL 0x4dc | |
444 | #define DC_DISP_SD_HW_K_VALUES 0x4dd | |
445 | #define DC_DISP_SD_MAN_K_VALUES 0x4de | |
446 | ||
7116e9a8 TR |
447 | #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4 |
448 | #define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24) | |
449 | #define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16) | |
450 | #define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8) | |
451 | #define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0) | |
452 | ||
8620fc62 TR |
453 | #define DC_DISP_INTERLACE_CONTROL 0x4e5 |
454 | #define INTERLACE_STATUS (1 << 2) | |
455 | #define INTERLACE_START (1 << 1) | |
456 | #define INTERLACE_ENABLE (1 << 0) | |
457 | ||
e687651b TR |
458 | #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec |
459 | #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 | |
460 | #define CURSOR_MODE_LEGACY (0 << 24) | |
461 | #define CURSOR_MODE_NORMAL (1 << 24) | |
462 | #define CURSOR_DST_BLEND_ZERO (0 << 16) | |
463 | #define CURSOR_DST_BLEND_K1 (1 << 16) | |
464 | #define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16) | |
465 | #define CURSOR_DST_BLEND_MASK (3 << 16) | |
466 | #define CURSOR_SRC_BLEND_K1 (0 << 8) | |
467 | #define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8) | |
468 | #define CURSOR_SRC_BLEND_MASK (3 << 8) | |
469 | #define CURSOR_ALPHA 0xff | |
470 | ||
f34bc787 TR |
471 | #define DC_WIN_CSC_YOF 0x611 |
472 | #define DC_WIN_CSC_KYRGB 0x612 | |
473 | #define DC_WIN_CSC_KUR 0x613 | |
474 | #define DC_WIN_CSC_KVR 0x614 | |
475 | #define DC_WIN_CSC_KUG 0x615 | |
476 | #define DC_WIN_CSC_KVG 0x616 | |
477 | #define DC_WIN_CSC_KUB 0x617 | |
478 | #define DC_WIN_CSC_KVB 0x618 | |
479 | ||
d8f4a9ed | 480 | #define DC_WIN_WIN_OPTIONS 0x700 |
eba66501 TR |
481 | #define H_DIRECTION (1 << 0) |
482 | #define V_DIRECTION (1 << 2) | |
d8f4a9ed | 483 | #define COLOR_EXPAND (1 << 6) |
f34bc787 | 484 | #define CSC_ENABLE (1 << 18) |
d8f4a9ed TR |
485 | #define WIN_ENABLE (1 << 30) |
486 | ||
487 | #define DC_WIN_BYTE_SWAP 0x701 | |
488 | #define BYTE_SWAP_NOSWAP (0 << 0) | |
489 | #define BYTE_SWAP_SWAP2 (1 << 0) | |
490 | #define BYTE_SWAP_SWAP4 (2 << 0) | |
491 | #define BYTE_SWAP_SWAP4HW (3 << 0) | |
492 | ||
493 | #define DC_WIN_BUFFER_CONTROL 0x702 | |
494 | #define BUFFER_CONTROL_HOST (0 << 0) | |
495 | #define BUFFER_CONTROL_VI (1 << 0) | |
496 | #define BUFFER_CONTROL_EPP (2 << 0) | |
497 | #define BUFFER_CONTROL_MPEGE (3 << 0) | |
498 | #define BUFFER_CONTROL_SB2D (4 << 0) | |
499 | ||
500 | #define DC_WIN_COLOR_DEPTH 0x703 | |
501 | #define WIN_COLOR_DEPTH_P1 0 | |
502 | #define WIN_COLOR_DEPTH_P2 1 | |
503 | #define WIN_COLOR_DEPTH_P4 2 | |
504 | #define WIN_COLOR_DEPTH_P8 3 | |
505 | #define WIN_COLOR_DEPTH_B4G4R4A4 4 | |
506 | #define WIN_COLOR_DEPTH_B5G5R5A 5 | |
507 | #define WIN_COLOR_DEPTH_B5G6R5 6 | |
508 | #define WIN_COLOR_DEPTH_AB5G5R5 7 | |
509 | #define WIN_COLOR_DEPTH_B8G8R8A8 12 | |
510 | #define WIN_COLOR_DEPTH_R8G8B8A8 13 | |
511 | #define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14 | |
512 | #define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15 | |
513 | #define WIN_COLOR_DEPTH_YCbCr422 16 | |
514 | #define WIN_COLOR_DEPTH_YUV422 17 | |
515 | #define WIN_COLOR_DEPTH_YCbCr420P 18 | |
516 | #define WIN_COLOR_DEPTH_YUV420P 19 | |
517 | #define WIN_COLOR_DEPTH_YCbCr422P 20 | |
518 | #define WIN_COLOR_DEPTH_YUV422P 21 | |
519 | #define WIN_COLOR_DEPTH_YCbCr422R 22 | |
520 | #define WIN_COLOR_DEPTH_YUV422R 23 | |
521 | #define WIN_COLOR_DEPTH_YCbCr422RA 24 | |
522 | #define WIN_COLOR_DEPTH_YUV422RA 25 | |
523 | ||
524 | #define DC_WIN_POSITION 0x704 | |
525 | #define H_POSITION(x) (((x) & 0x1fff) << 0) | |
526 | #define V_POSITION(x) (((x) & 0x1fff) << 16) | |
527 | ||
528 | #define DC_WIN_SIZE 0x705 | |
529 | #define H_SIZE(x) (((x) & 0x1fff) << 0) | |
530 | #define V_SIZE(x) (((x) & 0x1fff) << 16) | |
531 | ||
532 | #define DC_WIN_PRESCALED_SIZE 0x706 | |
533 | #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) | |
534 | #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) | |
535 | ||
536 | #define DC_WIN_H_INITIAL_DDA 0x707 | |
537 | #define DC_WIN_V_INITIAL_DDA 0x708 | |
538 | #define DC_WIN_DDA_INC 0x709 | |
539 | #define H_DDA_INC(x) (((x) & 0xffff) << 0) | |
540 | #define V_DDA_INC(x) (((x) & 0xffff) << 16) | |
541 | ||
542 | #define DC_WIN_LINE_STRIDE 0x70a | |
543 | #define DC_WIN_BUF_STRIDE 0x70b | |
544 | #define DC_WIN_UV_BUF_STRIDE 0x70c | |
545 | #define DC_WIN_BUFFER_ADDR_MODE 0x70d | |
773af77f TR |
546 | #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0) |
547 | #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0) | |
548 | #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16) | |
549 | #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16) | |
d8f4a9ed TR |
550 | #define DC_WIN_DV_CONTROL 0x70e |
551 | ||
552 | #define DC_WIN_BLEND_NOKEY 0x70f | |
553 | #define DC_WIN_BLEND_1WIN 0x710 | |
554 | #define DC_WIN_BLEND_2WIN_X 0x711 | |
555 | #define DC_WIN_BLEND_2WIN_Y 0x712 | |
f34bc787 | 556 | #define DC_WIN_BLEND_3WIN_XY 0x713 |
d8f4a9ed TR |
557 | |
558 | #define DC_WIN_HP_FETCH_CONTROL 0x714 | |
559 | ||
560 | #define DC_WINBUF_START_ADDR 0x800 | |
561 | #define DC_WINBUF_START_ADDR_NS 0x801 | |
562 | #define DC_WINBUF_START_ADDR_U 0x802 | |
563 | #define DC_WINBUF_START_ADDR_U_NS 0x803 | |
564 | #define DC_WINBUF_START_ADDR_V 0x804 | |
565 | #define DC_WINBUF_START_ADDR_V_NS 0x805 | |
566 | ||
567 | #define DC_WINBUF_ADDR_H_OFFSET 0x806 | |
568 | #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807 | |
569 | #define DC_WINBUF_ADDR_V_OFFSET 0x808 | |
570 | #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 | |
571 | ||
572 | #define DC_WINBUF_UFLOW_STATUS 0x80a | |
c134f019 TR |
573 | #define DC_WINBUF_SURFACE_KIND 0x80b |
574 | #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0) | |
575 | #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0) | |
576 | #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0) | |
577 | #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) | |
d8f4a9ed | 578 | |
31b02cae TR |
579 | #define DC_WINBUF_START_ADDR_HI 0x80d |
580 | ||
d8f4a9ed TR |
581 | #define DC_WINBUF_AD_UFLOW_STATUS 0xbca |
582 | #define DC_WINBUF_BD_UFLOW_STATUS 0xdca | |
583 | #define DC_WINBUF_CD_UFLOW_STATUS 0xfca | |
584 | ||
d8f4a9ed | 585 | #endif /* TEGRA_DC_H */ |