[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / tegra / dc.h

/*
 * Copyright (C) 2012 Avionic Design GmbH
 * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef TEGRA_DC_H
#define TEGRA_DC_H 1

#include <linux/host1x.h>

#include <drm/drm_crtc.h>

#include "drm.h"

struct tegra_output;

struct tegra_dc_stats {
	unsigned long frames;
	unsigned long vblank;
	unsigned long underflow;
	unsigned long overflow;
};

struct tegra_dc_soc_info {
	bool supports_background_color;
	bool supports_interlacing;
	bool supports_cursor;
	bool supports_block_linear;
	unsigned int pitch_align;
	bool has_powergate;
	bool broken_reset;
};

struct tegra_dc {
	struct host1x_client client;
	struct host1x_syncpt *syncpt;
	struct device *dev;
	spinlock_t lock;

	struct drm_crtc base;
	unsigned int powergate;
	int pipe;

	struct clk *clk;
	struct reset_control *rst;
	void __iomem *regs;
	int irq;

	struct tegra_output *rgb;

	struct tegra_dc_stats stats;
	struct list_head list;

	struct drm_info_list *debugfs_files;

	/* page-flip handling */
	struct drm_pending_vblank_event *event;

	const struct tegra_dc_soc_info *soc;

	struct iommu_domain *domain;
};

static inline struct tegra_dc *
host1x_client_to_dc(struct host1x_client *client)
{
	return container_of(client, struct tegra_dc, client);
}

static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
{
	return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
}

static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
				   unsigned int offset)
{
	trace_dc_writel(dc->dev, offset, value);
	writel(value, dc->regs + (offset << 2));
}

static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset)
{
	u32 value = readl(dc->regs + (offset << 2));

	trace_dc_readl(dc->dev, offset, value);

	return value;
}

struct tegra_dc_window {
	struct {
		unsigned int x;
		unsigned int y;
		unsigned int w;
		unsigned int h;
	} src;
	struct {
		unsigned int x;
		unsigned int y;
		unsigned int w;
		unsigned int h;
	} dst;
	unsigned int bits_per_pixel;
	unsigned int stride[2];
	unsigned long base[3];
	bool bottom_up;

	struct tegra_bo_tiling tiling;
	u32 format;
	u32 swap;
};

/* from dc.c */
void tegra_dc_commit(struct tegra_dc *dc);
int tegra_dc_state_setup_clock(struct tegra_dc *dc,
			       struct drm_crtc_state *crtc_state,
			       struct clk *clk, unsigned long pclk,
			       unsigned int div);

/* from rgb.c */
int tegra_dc_rgb_probe(struct tegra_dc *dc);
int tegra_dc_rgb_remove(struct tegra_dc *dc);
int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
int tegra_dc_rgb_exit(struct tegra_dc *dc);

#define DC_CMD_GENERAL_INCR_SYNCPT		0x000
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL	0x001
#define  SYNCPT_CNTRL_NO_STALL   (1 << 8)
#define  SYNCPT_CNTRL_SOFT_RESET (1 << 0)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR	0x002
#define DC_CMD_WIN_A_INCR_SYNCPT		0x008
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL		0x009
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR		0x00a
#define DC_CMD_WIN_B_INCR_SYNCPT		0x010
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL		0x011
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR		0x012
#define DC_CMD_WIN_C_INCR_SYNCPT		0x018
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL		0x019
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR		0x01a
#define DC_CMD_CONT_SYNCPT_VSYNC		0x028
#define  SYNCPT_VSYNC_ENABLE (1 << 8)
#define DC_CMD_DISPLAY_COMMAND_OPTION0		0x031
#define DC_CMD_DISPLAY_COMMAND			0x032
#define DISP_CTRL_MODE_STOP (0 << 5)
#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
#define DISP_CTRL_MODE_MASK (3 << 5)
#define DC_CMD_SIGNAL_RAISE			0x033
#define DC_CMD_DISPLAY_POWER_CONTROL		0x036
#define PW0_ENABLE (1 <<  0)
#define PW1_ENABLE (1 <<  2)
#define PW2_ENABLE (1 <<  4)
#define PW3_ENABLE (1 <<  6)
#define PW4_ENABLE (1 <<  8)
#define PM0_ENABLE (1 << 16)
#define PM1_ENABLE (1 << 18)

#define DC_CMD_INT_STATUS			0x037
#define DC_CMD_INT_MASK				0x038
#define DC_CMD_INT_ENABLE			0x039
#define DC_CMD_INT_TYPE				0x03a
#define DC_CMD_INT_POLARITY			0x03b
#define CTXSW_INT     (1 << 0)
#define FRAME_END_INT (1 << 1)
#define VBLANK_INT    (1 << 2)
#define WIN_A_UF_INT  (1 << 8)
#define WIN_B_UF_INT  (1 << 9)
#define WIN_C_UF_INT  (1 << 10)
#define WIN_A_OF_INT  (1 << 14)
#define WIN_B_OF_INT  (1 << 15)
#define WIN_C_OF_INT  (1 << 16)

#define DC_CMD_SIGNAL_RAISE1			0x03c
#define DC_CMD_SIGNAL_RAISE2			0x03d
#define DC_CMD_SIGNAL_RAISE3			0x03e

#define DC_CMD_STATE_ACCESS			0x040
#define READ_MUX  (1 << 0)
#define WRITE_MUX (1 << 2)

#define DC_CMD_STATE_CONTROL			0x041
#define GENERAL_ACT_REQ (1 <<  0)
#define WIN_A_ACT_REQ   (1 <<  1)
#define WIN_B_ACT_REQ   (1 <<  2)
#define WIN_C_ACT_REQ   (1 <<  3)
#define CURSOR_ACT_REQ  (1 <<  7)
#define GENERAL_UPDATE  (1 <<  8)
#define WIN_A_UPDATE    (1 <<  9)
#define WIN_B_UPDATE    (1 << 10)
#define WIN_C_UPDATE    (1 << 11)
#define CURSOR_UPDATE   (1 << 15)
#define NC_HOST_TRIG    (1 << 24)

#define DC_CMD_DISPLAY_WINDOW_HEADER		0x042
#define WINDOW_A_SELECT (1 << 4)
#define WINDOW_B_SELECT (1 << 5)
#define WINDOW_C_SELECT (1 << 6)

#define DC_CMD_REG_ACT_CONTROL			0x043

#define DC_COM_CRC_CONTROL			0x300
#define  DC_COM_CRC_CONTROL_ALWAYS (1 << 3)
#define  DC_COM_CRC_CONTROL_FULL_FRAME  (0 << 2)
#define  DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2)
#define  DC_COM_CRC_CONTROL_WAIT (1 << 1)
#define  DC_COM_CRC_CONTROL_ENABLE (1 << 0)
#define DC_COM_CRC_CHECKSUM			0x301
#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
#define LVS_OUTPUT_POLARITY_LOW (1 << 28)
#define LHS_OUTPUT_POLARITY_LOW (1 << 30)
#define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
#define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
#define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
#define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))

#define DC_COM_PIN_MISC_CONTROL			0x31b
#define DC_COM_PIN_PM0_CONTROL			0x31c
#define DC_COM_PIN_PM0_DUTY_CYCLE		0x31d
#define DC_COM_PIN_PM1_CONTROL			0x31e
#define DC_COM_PIN_PM1_DUTY_CYCLE		0x31f

#define DC_COM_SPI_CONTROL			0x320
#define DC_COM_SPI_START_BYTE			0x321
#define DC_COM_HSPI_WRITE_DATA_AB		0x322
#define DC_COM_HSPI_WRITE_DATA_CD		0x323
#define DC_COM_HSPI_CS_DC			0x324
#define DC_COM_SCRATCH_REGISTER_A		0x325
#define DC_COM_SCRATCH_REGISTER_B		0x326
#define DC_COM_GPIO_CTRL			0x327
#define DC_COM_GPIO_DEBOUNCE_COUNTER		0x328
#define DC_COM_CRC_CHECKSUM_LATCHED		0x329

#define DC_DISP_DISP_SIGNAL_OPTIONS0		0x400
#define H_PULSE0_ENABLE (1 <<  8)
#define H_PULSE1_ENABLE (1 << 10)
#define H_PULSE2_ENABLE (1 << 12)

#define DC_DISP_DISP_SIGNAL_OPTIONS1		0x401

#define DC_DISP_DISP_WIN_OPTIONS		0x402
#define HDMI_ENABLE	(1 << 30)
#define DSI_ENABLE	(1 << 29)
#define SOR1_TIMING_CYA	(1 << 27)
#define SOR1_ENABLE	(1 << 26)
#define SOR_ENABLE	(1 << 25)
#define CURSOR_ENABLE	(1 << 16)

#define DC_DISP_DISP_MEM_HIGH_PRIORITY		0x403
#define CURSOR_THRESHOLD(x)   (((x) & 0x03) << 24)
#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
#define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) <<  8)
#define WINDOW_C_THRESHOLD(x) (((x) & 0xff) <<  0)

#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER	0x404
#define CURSOR_DELAY(x)   (((x) & 0x3f) << 24)
#define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
#define WINDOW_B_DELAY(x) (((x) & 0x3f) <<  8)
#define WINDOW_C_DELAY(x) (((x) & 0x3f) <<  0)

#define DC_DISP_DISP_TIMING_OPTIONS		0x405
#define VSYNC_H_POSITION(x) ((x) & 0xfff)

#define DC_DISP_REF_TO_SYNC			0x406
#define DC_DISP_SYNC_WIDTH			0x407
#define DC_DISP_BACK_PORCH			0x408
#define DC_DISP_ACTIVE				0x409
#define DC_DISP_FRONT_PORCH			0x40a
#define DC_DISP_H_PULSE0_CONTROL		0x40b
#define DC_DISP_H_PULSE0_POSITION_A		0x40c
#define DC_DISP_H_PULSE0_POSITION_B		0x40d
#define DC_DISP_H_PULSE0_POSITION_C		0x40e
#define DC_DISP_H_PULSE0_POSITION_D		0x40f
#define DC_DISP_H_PULSE1_CONTROL		0x410
#define DC_DISP_H_PULSE1_POSITION_A		0x411
#define DC_DISP_H_PULSE1_POSITION_B		0x412
#define DC_DISP_H_PULSE1_POSITION_C		0x413
#define DC_DISP_H_PULSE1_POSITION_D		0x414
#define DC_DISP_H_PULSE2_CONTROL		0x415
#define DC_DISP_H_PULSE2_POSITION_A		0x416
#define DC_DISP_H_PULSE2_POSITION_B		0x417
#define DC_DISP_H_PULSE2_POSITION_C		0x418
#define DC_DISP_H_PULSE2_POSITION_D		0x419
#define DC_DISP_V_PULSE0_CONTROL		0x41a
#define DC_DISP_V_PULSE0_POSITION_A		0x41b
#define DC_DISP_V_PULSE0_POSITION_B		0x41c
#define DC_DISP_V_PULSE0_POSITION_C		0x41d
#define DC_DISP_V_PULSE1_CONTROL		0x41e
#define DC_DISP_V_PULSE1_POSITION_A		0x41f
#define DC_DISP_V_PULSE1_POSITION_B		0x420
#define DC_DISP_V_PULSE1_POSITION_C		0x421
#define DC_DISP_V_PULSE2_CONTROL		0x422
#define DC_DISP_V_PULSE2_POSITION_A		0x423
#define DC_DISP_V_PULSE3_CONTROL		0x424
#define DC_DISP_V_PULSE3_POSITION_A		0x425
#define DC_DISP_M0_CONTROL			0x426
#define DC_DISP_M1_CONTROL			0x427
#define DC_DISP_DI_CONTROL			0x428
#define DC_DISP_PP_CONTROL			0x429
#define DC_DISP_PP_SELECT_A			0x42a
#define DC_DISP_PP_SELECT_B			0x42b
#define DC_DISP_PP_SELECT_C			0x42c
#define DC_DISP_PP_SELECT_D			0x42d

#define PULSE_MODE_NORMAL    (0 << 3)
#define PULSE_MODE_ONE_CLOCK (1 << 3)
#define PULSE_POLARITY_HIGH  (0 << 4)
#define PULSE_POLARITY_LOW   (1 << 4)
#define PULSE_QUAL_ALWAYS    (0 << 6)
#define PULSE_QUAL_VACTIVE   (2 << 6)
#define PULSE_QUAL_VACTIVE1  (3 << 6)
#define PULSE_LAST_START_A   (0 << 8)
#define PULSE_LAST_END_A     (1 << 8)
#define PULSE_LAST_START_B   (2 << 8)
#define PULSE_LAST_END_B     (3 << 8)
#define PULSE_LAST_START_C   (4 << 8)
#define PULSE_LAST_END_C     (5 << 8)
#define PULSE_LAST_START_D   (6 << 8)
#define PULSE_LAST_END_D     (7 << 8)

#define PULSE_START(x) (((x) & 0xfff) <<  0)
#define PULSE_END(x)   (((x) & 0xfff) << 16)

#define DC_DISP_DISP_CLOCK_CONTROL		0x42e
#define PIXEL_CLK_DIVIDER_PCD1  (0 << 8)
#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
#define PIXEL_CLK_DIVIDER_PCD2  (2 << 8)
#define PIXEL_CLK_DIVIDER_PCD3  (3 << 8)
#define PIXEL_CLK_DIVIDER_PCD4  (4 << 8)
#define PIXEL_CLK_DIVIDER_PCD6  (5 << 8)
#define PIXEL_CLK_DIVIDER_PCD8  (6 << 8)
#define PIXEL_CLK_DIVIDER_PCD9  (7 << 8)
#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
#define SHIFT_CLK_DIVIDER(x)    ((x) & 0xff)

#define DC_DISP_DISP_INTERFACE_CONTROL		0x42f
#define DISP_DATA_FORMAT_DF1P1C    (0 << 0)
#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
#define DISP_DATA_FORMAT_DF2S      (4 << 0)
#define DISP_DATA_FORMAT_DF3S      (5 << 0)
#define DISP_DATA_FORMAT_DFSPI     (6 << 0)
#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
#define DISP_ALIGNMENT_MSB         (0 << 8)
#define DISP_ALIGNMENT_LSB         (1 << 8)
#define DISP_ORDER_RED_BLUE        (0 << 9)
#define DISP_ORDER_BLUE_RED        (1 << 9)

#define DC_DISP_DISP_COLOR_CONTROL		0x430
#define BASE_COLOR_SIZE666     (0 << 0)
#define BASE_COLOR_SIZE111     (1 << 0)
#define BASE_COLOR_SIZE222     (2 << 0)
#define BASE_COLOR_SIZE333     (3 << 0)
#define BASE_COLOR_SIZE444     (4 << 0)
#define BASE_COLOR_SIZE555     (5 << 0)
#define BASE_COLOR_SIZE565     (6 << 0)
#define BASE_COLOR_SIZE332     (7 << 0)
#define BASE_COLOR_SIZE888     (8 << 0)
#define DITHER_CONTROL_MASK    (3 << 8)
#define DITHER_CONTROL_DISABLE (0 << 8)
#define DITHER_CONTROL_ORDERED (2 << 8)
#define DITHER_CONTROL_ERRDIFF (3 << 8)
#define BASE_COLOR_SIZE_MASK   (0xf << 0)
#define BASE_COLOR_SIZE_666    (0 << 0)
#define BASE_COLOR_SIZE_111    (1 << 0)
#define BASE_COLOR_SIZE_222    (2 << 0)
#define BASE_COLOR_SIZE_333    (3 << 0)
#define BASE_COLOR_SIZE_444    (4 << 0)
#define BASE_COLOR_SIZE_555    (5 << 0)
#define BASE_COLOR_SIZE_565    (6 << 0)
#define BASE_COLOR_SIZE_332    (7 << 0)
#define BASE_COLOR_SIZE_888    (8 << 0)

#define DC_DISP_SHIFT_CLOCK_OPTIONS		0x431
#define  SC1_H_QUALIFIER_NONE	(1 << 16)
#define  SC0_H_QUALIFIER_NONE	(1 <<  0)

#define DC_DISP_DATA_ENABLE_OPTIONS		0x432
#define DE_SELECT_ACTIVE_BLANK  (0 << 0)
#define DE_SELECT_ACTIVE        (1 << 0)
#define DE_SELECT_ACTIVE_IS     (2 << 0)
#define DE_CONTROL_ONECLK       (0 << 2)
#define DE_CONTROL_NORMAL       (1 << 2)
#define DE_CONTROL_EARLY_EXT    (2 << 2)
#define DE_CONTROL_EARLY        (3 << 2)
#define DE_CONTROL_ACTIVE_BLANK (4 << 2)

#define DC_DISP_SERIAL_INTERFACE_OPTIONS	0x433
#define DC_DISP_LCD_SPI_OPTIONS			0x434
#define DC_DISP_BORDER_COLOR			0x435
#define DC_DISP_COLOR_KEY0_LOWER		0x436
#define DC_DISP_COLOR_KEY0_UPPER		0x437
#define DC_DISP_COLOR_KEY1_LOWER		0x438
#define DC_DISP_COLOR_KEY1_UPPER		0x439

#define DC_DISP_CURSOR_FOREGROUND		0x43c
#define DC_DISP_CURSOR_BACKGROUND		0x43d

#define DC_DISP_CURSOR_START_ADDR		0x43e
#define CURSOR_CLIP_DISPLAY	(0 << 28)
#define CURSOR_CLIP_WIN_A	(1 << 28)
#define CURSOR_CLIP_WIN_B	(2 << 28)
#define CURSOR_CLIP_WIN_C	(3 << 28)
#define CURSOR_SIZE_32x32	(0 << 24)
#define CURSOR_SIZE_64x64	(1 << 24)
#define CURSOR_SIZE_128x128	(2 << 24)
#define CURSOR_SIZE_256x256	(3 << 24)
#define DC_DISP_CURSOR_START_ADDR_NS		0x43f

#define DC_DISP_CURSOR_POSITION			0x440
#define DC_DISP_CURSOR_POSITION_NS		0x441

#define DC_DISP_INIT_SEQ_CONTROL		0x442
#define DC_DISP_SPI_INIT_SEQ_DATA_A		0x443
#define DC_DISP_SPI_INIT_SEQ_DATA_B		0x444
#define DC_DISP_SPI_INIT_SEQ_DATA_C		0x445
#define DC_DISP_SPI_INIT_SEQ_DATA_D		0x446

#define DC_DISP_DC_MCCIF_FIFOCTRL		0x480
#define DC_DISP_MCCIF_DISPLAY0A_HYST		0x481
#define DC_DISP_MCCIF_DISPLAY0B_HYST		0x482
#define DC_DISP_MCCIF_DISPLAY1A_HYST		0x483
#define DC_DISP_MCCIF_DISPLAY1B_HYST		0x484

#define DC_DISP_DAC_CRT_CTRL			0x4c0
#define DC_DISP_DISP_MISC_CONTROL		0x4c1
#define DC_DISP_SD_CONTROL			0x4c2
#define DC_DISP_SD_CSC_COEFF			0x4c3
#define DC_DISP_SD_LUT(x)			(0x4c4 + (x))
#define DC_DISP_SD_FLICKER_CONTROL		0x4cd
#define DC_DISP_DC_PIXEL_COUNT			0x4ce
#define DC_DISP_SD_HISTOGRAM(x)			(0x4cf + (x))
#define DC_DISP_SD_BL_PARAMETERS		0x4d7
#define DC_DISP_SD_BL_TF(x)			(0x4d8 + (x))
#define DC_DISP_SD_BL_CONTROL			0x4dc
#define DC_DISP_SD_HW_K_VALUES			0x4dd
#define DC_DISP_SD_MAN_K_VALUES			0x4de

#define DC_DISP_BLEND_BACKGROUND_COLOR		0x4e4
#define  BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24)
#define  BACKGROUND_COLOR_BLUE(x)  (((x) & 0xff) << 16)
#define  BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8)
#define  BACKGROUND_COLOR_RED(x)   (((x) & 0xff) << 0)

#define DC_DISP_INTERLACE_CONTROL		0x4e5
#define  INTERLACE_STATUS (1 << 2)
#define  INTERLACE_START  (1 << 1)
#define  INTERLACE_ENABLE (1 << 0)

#define DC_DISP_CURSOR_START_ADDR_HI		0x4ec
#define DC_DISP_BLEND_CURSOR_CONTROL		0x4f1
#define CURSOR_MODE_LEGACY			(0 << 24)
#define CURSOR_MODE_NORMAL			(1 << 24)
#define CURSOR_DST_BLEND_ZERO			(0 << 16)
#define CURSOR_DST_BLEND_K1			(1 << 16)
#define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC	(2 << 16)
#define CURSOR_DST_BLEND_MASK			(3 << 16)
#define CURSOR_SRC_BLEND_K1			(0 << 8)
#define CURSOR_SRC_BLEND_K1_TIMES_SRC		(1 << 8)
#define CURSOR_SRC_BLEND_MASK			(3 << 8)
#define CURSOR_ALPHA				0xff

#define DC_WIN_CSC_YOF				0x611
#define DC_WIN_CSC_KYRGB			0x612
#define DC_WIN_CSC_KUR				0x613
#define DC_WIN_CSC_KVR				0x614
#define DC_WIN_CSC_KUG				0x615
#define DC_WIN_CSC_KVG				0x616
#define DC_WIN_CSC_KUB				0x617
#define DC_WIN_CSC_KVB				0x618

#define DC_WIN_WIN_OPTIONS			0x700
#define H_DIRECTION  (1 <<  0)
#define V_DIRECTION  (1 <<  2)
#define COLOR_EXPAND (1 <<  6)
#define CSC_ENABLE   (1 << 18)
#define WIN_ENABLE   (1 << 30)

#define DC_WIN_BYTE_SWAP			0x701
#define BYTE_SWAP_NOSWAP  (0 << 0)
#define BYTE_SWAP_SWAP2   (1 << 0)
#define BYTE_SWAP_SWAP4   (2 << 0)
#define BYTE_SWAP_SWAP4HW (3 << 0)

#define DC_WIN_BUFFER_CONTROL			0x702
#define BUFFER_CONTROL_HOST  (0 << 0)
#define BUFFER_CONTROL_VI    (1 << 0)
#define BUFFER_CONTROL_EPP   (2 << 0)
#define BUFFER_CONTROL_MPEGE (3 << 0)
#define BUFFER_CONTROL_SB2D  (4 << 0)

#define DC_WIN_COLOR_DEPTH			0x703
#define WIN_COLOR_DEPTH_P1              0
#define WIN_COLOR_DEPTH_P2              1
#define WIN_COLOR_DEPTH_P4              2
#define WIN_COLOR_DEPTH_P8              3
#define WIN_COLOR_DEPTH_B4G4R4A4        4
#define WIN_COLOR_DEPTH_B5G5R5A         5
#define WIN_COLOR_DEPTH_B5G6R5          6
#define WIN_COLOR_DEPTH_AB5G5R5         7
#define WIN_COLOR_DEPTH_B8G8R8A8       12
#define WIN_COLOR_DEPTH_R8G8B8A8       13
#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
#define WIN_COLOR_DEPTH_YCbCr422       16
#define WIN_COLOR_DEPTH_YUV422         17
#define WIN_COLOR_DEPTH_YCbCr420P      18
#define WIN_COLOR_DEPTH_YUV420P        19
#define WIN_COLOR_DEPTH_YCbCr422P      20
#define WIN_COLOR_DEPTH_YUV422P        21
#define WIN_COLOR_DEPTH_YCbCr422R      22
#define WIN_COLOR_DEPTH_YUV422R        23
#define WIN_COLOR_DEPTH_YCbCr422RA     24
#define WIN_COLOR_DEPTH_YUV422RA       25

#define DC_WIN_POSITION				0x704
#define H_POSITION(x) (((x) & 0x1fff) <<  0)
#define V_POSITION(x) (((x) & 0x1fff) << 16)

#define DC_WIN_SIZE				0x705
#define H_SIZE(x) (((x) & 0x1fff) <<  0)
#define V_SIZE(x) (((x) & 0x1fff) << 16)

#define DC_WIN_PRESCALED_SIZE			0x706
#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) <<  0)
#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)

#define DC_WIN_H_INITIAL_DDA			0x707
#define DC_WIN_V_INITIAL_DDA			0x708
#define DC_WIN_DDA_INC				0x709
#define H_DDA_INC(x) (((x) & 0xffff) <<  0)
#define V_DDA_INC(x) (((x) & 0xffff) << 16)

#define DC_WIN_LINE_STRIDE			0x70a
#define DC_WIN_BUF_STRIDE			0x70b
#define DC_WIN_UV_BUF_STRIDE			0x70c
#define DC_WIN_BUFFER_ADDR_MODE			0x70d
#define DC_WIN_BUFFER_ADDR_MODE_LINEAR		(0 <<  0)
#define DC_WIN_BUFFER_ADDR_MODE_TILE		(1 <<  0)
#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV	(0 << 16)
#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV		(1 << 16)
#define DC_WIN_DV_CONTROL			0x70e

#define DC_WIN_BLEND_NOKEY			0x70f
#define DC_WIN_BLEND_1WIN			0x710
#define DC_WIN_BLEND_2WIN_X			0x711
#define DC_WIN_BLEND_2WIN_Y			0x712
#define DC_WIN_BLEND_3WIN_XY			0x713

#define DC_WIN_HP_FETCH_CONTROL			0x714

#define DC_WINBUF_START_ADDR			0x800
#define DC_WINBUF_START_ADDR_NS			0x801
#define DC_WINBUF_START_ADDR_U			0x802
#define DC_WINBUF_START_ADDR_U_NS		0x803
#define DC_WINBUF_START_ADDR_V			0x804
#define DC_WINBUF_START_ADDR_V_NS		0x805

#define DC_WINBUF_ADDR_H_OFFSET			0x806
#define DC_WINBUF_ADDR_H_OFFSET_NS		0x807
#define DC_WINBUF_ADDR_V_OFFSET			0x808
#define DC_WINBUF_ADDR_V_OFFSET_NS		0x809

#define DC_WINBUF_UFLOW_STATUS			0x80a
#define DC_WINBUF_SURFACE_KIND			0x80b
#define DC_WINBUF_SURFACE_KIND_PITCH	(0 << 0)
#define DC_WINBUF_SURFACE_KIND_TILED	(1 << 0)
#define DC_WINBUF_SURFACE_KIND_BLOCK	(2 << 0)
#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)

#define DC_WINBUF_AD_UFLOW_STATUS		0xbca
#define DC_WINBUF_BD_UFLOW_STATUS		0xdca
#define DC_WINBUF_CD_UFLOW_STATUS		0xfca

#endif /* TEGRA_DC_H */
Commit	Line	Data
d8f4a9ed TR	1	/*
	2	* Copyright (C) 2012 Avionic Design GmbH
	3	* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*/
	9
	10	#ifndef TEGRA_DC_H
	11	#define TEGRA_DC_H 1
	12
2d1c18fb TR	13	#include <linux/host1x.h>
	14
	15	#include <drm/drm_crtc.h>
	16
	17	#include "drm.h"
	18
	19	struct tegra_output;
	20
	21	struct tegra_dc_stats {
	22	unsigned long frames;
	23	unsigned long vblank;
	24	unsigned long underflow;
	25	unsigned long overflow;
	26	};
	27
	28	struct tegra_dc_soc_info {
7116e9a8	29	bool supports_background_color;
2d1c18fb TR	30	bool supports_interlacing;
	31	bool supports_cursor;
	32	bool supports_block_linear;
	33	unsigned int pitch_align;
	34	bool has_powergate;
	35	bool broken_reset;
	36	};
	37
	38	struct tegra_dc {
	39	struct host1x_client client;
	40	struct host1x_syncpt *syncpt;
	41	struct device *dev;
	42	spinlock_t lock;
	43
	44	struct drm_crtc base;
	45	unsigned int powergate;
	46	int pipe;
	47
	48	struct clk *clk;
	49	struct reset_control *rst;
	50	void __iomem *regs;
	51	int irq;
	52
	53	struct tegra_output *rgb;
	54
	55	struct tegra_dc_stats stats;
	56	struct list_head list;
	57
	58	struct drm_info_list *debugfs_files;
2d1c18fb TR	59
	60	/* page-flip handling */
	61	struct drm_pending_vblank_event *event;
	62
	63	const struct tegra_dc_soc_info *soc;
	64
	65	struct iommu_domain *domain;
	66	};
	67
	68	static inline struct tegra_dc *
	69	host1x_client_to_dc(struct host1x_client *client)
	70	{
	71	return container_of(client, struct tegra_dc, client);
	72	}
	73
	74	static inline struct tegra_dc to_tegra_dc(struct drm_crtc crtc)
	75	{
	76	return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
	77	}
	78
	79	static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
	80	unsigned int offset)
	81	{
	82	trace_dc_writel(dc->dev, offset, value);
	83	writel(value, dc->regs + (offset << 2));
	84	}
	85
	86	static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset)
	87	{
	88	u32 value = readl(dc->regs + (offset << 2));
	89
	90	trace_dc_readl(dc->dev, offset, value);
	91
	92	return value;
	93	}
	94
	95	struct tegra_dc_window {
	96	struct {
	97	unsigned int x;
	98	unsigned int y;
	99	unsigned int w;
	100	unsigned int h;
	101	} src;
	102	struct {
	103	unsigned int x;
	104	unsigned int y;
	105	unsigned int w;
	106	unsigned int h;
	107	} dst;
	108	unsigned int bits_per_pixel;
	109	unsigned int stride[2];
	110	unsigned long base[3];
	111	bool bottom_up;
	112
	113	struct tegra_bo_tiling tiling;
	114	u32 format;
	115	u32 swap;
	116	};
	117
	118	/* from dc.c */
	119	void tegra_dc_commit(struct tegra_dc *dc);
	120	int tegra_dc_state_setup_clock(struct tegra_dc *dc,
	121	struct drm_crtc_state *crtc_state,
	122	struct clk *clk, unsigned long pclk,
123	unsigned int div);
124
125	/* from rgb.c */
126	int tegra_dc_rgb_probe(struct tegra_dc *dc);
127	int tegra_dc_rgb_remove(struct tegra_dc *dc);
128	int tegra_dc_rgb_init(struct drm_device drm, struct tegra_dc dc);
129	int tegra_dc_rgb_exit(struct tegra_dc *dc);
130
d8f4a9ed TR	131	#define DC_CMD_GENERAL_INCR_SYNCPT 0x000
d8f4a9ed TR	132	#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
42e9ce05 TR	133	#define SYNCPT_CNTRL_NO_STALL (1 << 8)
42e9ce05 TR	134	#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
d8f4a9ed TR	135	#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
	136	#define DC_CMD_WIN_A_INCR_SYNCPT 0x008
	137	#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
	138	#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
	139	#define DC_CMD_WIN_B_INCR_SYNCPT 0x010
	140	#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
	141	#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
	142	#define DC_CMD_WIN_C_INCR_SYNCPT 0x018
	143	#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
	144	#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
	145	#define DC_CMD_CONT_SYNCPT_VSYNC 0x028
42e9ce05	146	#define SYNCPT_VSYNC_ENABLE (1 << 8)
d8f4a9ed TR	147	#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
	148	#define DC_CMD_DISPLAY_COMMAND 0x032
	149	#define DISP_CTRL_MODE_STOP (0 << 5)
	150	#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
	151	#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
dec72739	152	#define DISP_CTRL_MODE_MASK (3 << 5)
d8f4a9ed TR	153	#define DC_CMD_SIGNAL_RAISE 0x033
	154	#define DC_CMD_DISPLAY_POWER_CONTROL 0x036
	155	#define PW0_ENABLE (1 << 0)
	156	#define PW1_ENABLE (1 << 2)
	157	#define PW2_ENABLE (1 << 4)
	158	#define PW3_ENABLE (1 << 6)
	159	#define PW4_ENABLE (1 << 8)
	160	#define PM0_ENABLE (1 << 16)
	161	#define PM1_ENABLE (1 << 18)
	162
	163	#define DC_CMD_INT_STATUS 0x037
	164	#define DC_CMD_INT_MASK 0x038
	165	#define DC_CMD_INT_ENABLE 0x039
	166	#define DC_CMD_INT_TYPE 0x03a
	167	#define DC_CMD_INT_POLARITY 0x03b
	168	#define CTXSW_INT (1 << 0)
	169	#define FRAME_END_INT (1 << 1)
	170	#define VBLANK_INT (1 << 2)
	171	#define WIN_A_UF_INT (1 << 8)
	172	#define WIN_B_UF_INT (1 << 9)
	173	#define WIN_C_UF_INT (1 << 10)
	174	#define WIN_A_OF_INT (1 << 14)
	175	#define WIN_B_OF_INT (1 << 15)
	176	#define WIN_C_OF_INT (1 << 16)
	177
	178	#define DC_CMD_SIGNAL_RAISE1 0x03c
	179	#define DC_CMD_SIGNAL_RAISE2 0x03d
	180	#define DC_CMD_SIGNAL_RAISE3 0x03e
	181
	182	#define DC_CMD_STATE_ACCESS 0x040
3c03c46a TR	183	#define READ_MUX (1 << 0)
3c03c46a TR	184	#define WRITE_MUX (1 << 2)
d8f4a9ed TR	185
	186	#define DC_CMD_STATE_CONTROL 0x041
	187	#define GENERAL_ACT_REQ (1 << 0)
	188	#define WIN_A_ACT_REQ (1 << 1)
	189	#define WIN_B_ACT_REQ (1 << 2)
	190	#define WIN_C_ACT_REQ (1 << 3)
e687651b	191	#define CURSOR_ACT_REQ (1 << 7)
d8f4a9ed TR	192	#define GENERAL_UPDATE (1 << 8)
	193	#define WIN_A_UPDATE (1 << 9)
	194	#define WIN_B_UPDATE (1 << 10)
	195	#define WIN_C_UPDATE (1 << 11)
e687651b	196	#define CURSOR_UPDATE (1 << 15)
d8f4a9ed TR	197	#define NC_HOST_TRIG (1 << 24)
	198
	199	#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
	200	#define WINDOW_A_SELECT (1 << 4)
	201	#define WINDOW_B_SELECT (1 << 5)
	202	#define WINDOW_C_SELECT (1 << 6)
	203
	204	#define DC_CMD_REG_ACT_CONTROL 0x043
	205
	206	#define DC_COM_CRC_CONTROL 0x300
6ca1f62f TR	207	#define DC_COM_CRC_CONTROL_ALWAYS (1 << 3)
	208	#define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2)
	209	#define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2)
	210	#define DC_COM_CRC_CONTROL_WAIT (1 << 1)
	211	#define DC_COM_CRC_CONTROL_ENABLE (1 << 0)
d8f4a9ed TR	212	#define DC_COM_CRC_CHECKSUM 0x301
	213	#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
	214	#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
	215	#define LVS_OUTPUT_POLARITY_LOW (1 << 28)
	216	#define LHS_OUTPUT_POLARITY_LOW (1 << 30)
	217	#define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
	218	#define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
	219	#define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
	220	#define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
	221
	222	#define DC_COM_PIN_MISC_CONTROL 0x31b
	223	#define DC_COM_PIN_PM0_CONTROL 0x31c
	224	#define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
	225	#define DC_COM_PIN_PM1_CONTROL 0x31e
	226	#define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
	227
	228	#define DC_COM_SPI_CONTROL 0x320
	229	#define DC_COM_SPI_START_BYTE 0x321
	230	#define DC_COM_HSPI_WRITE_DATA_AB 0x322
	231	#define DC_COM_HSPI_WRITE_DATA_CD 0x323
	232	#define DC_COM_HSPI_CS_DC 0x324
	233	#define DC_COM_SCRATCH_REGISTER_A 0x325
	234	#define DC_COM_SCRATCH_REGISTER_B 0x326
	235	#define DC_COM_GPIO_CTRL 0x327
	236	#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
	237	#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
	238
	239	#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
8fd3ffa9 TR	240	#define H_PULSE0_ENABLE (1 << 8)
	241	#define H_PULSE1_ENABLE (1 << 10)
	242	#define H_PULSE2_ENABLE (1 << 12)
d8f4a9ed TR	243
	244	#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
	245
	246	#define DC_DISP_DISP_WIN_OPTIONS 0x402
e687651b TR	247	#define HDMI_ENABLE (1 << 30)
e687651b TR	248	#define DSI_ENABLE (1 << 29)
459cc2c6 TR	249	#define SOR1_TIMING_CYA (1 << 27)
459cc2c6 TR	250	#define SOR1_ENABLE (1 << 26)
e687651b TR	251	#define SOR_ENABLE (1 << 25)
e687651b TR	252	#define CURSOR_ENABLE (1 << 16)
d8f4a9ed TR	253
	254	#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
	255	#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
	256	#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
	257	#define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
	258	#define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
	259
	260	#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
	261	#define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
	262	#define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
	263	#define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
	264	#define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
	265
	266	#define DC_DISP_DISP_TIMING_OPTIONS 0x405
	267	#define VSYNC_H_POSITION(x) ((x) & 0xfff)
	268
	269	#define DC_DISP_REF_TO_SYNC 0x406
	270	#define DC_DISP_SYNC_WIDTH 0x407
	271	#define DC_DISP_BACK_PORCH 0x408
	272	#define DC_DISP_ACTIVE 0x409
	273	#define DC_DISP_FRONT_PORCH 0x40a
	274	#define DC_DISP_H_PULSE0_CONTROL 0x40b
	275	#define DC_DISP_H_PULSE0_POSITION_A 0x40c
	276	#define DC_DISP_H_PULSE0_POSITION_B 0x40d
	277	#define DC_DISP_H_PULSE0_POSITION_C 0x40e
	278	#define DC_DISP_H_PULSE0_POSITION_D 0x40f
	279	#define DC_DISP_H_PULSE1_CONTROL 0x410
	280	#define DC_DISP_H_PULSE1_POSITION_A 0x411
	281	#define DC_DISP_H_PULSE1_POSITION_B 0x412
	282	#define DC_DISP_H_PULSE1_POSITION_C 0x413
	283	#define DC_DISP_H_PULSE1_POSITION_D 0x414
	284	#define DC_DISP_H_PULSE2_CONTROL 0x415
	285	#define DC_DISP_H_PULSE2_POSITION_A 0x416
	286	#define DC_DISP_H_PULSE2_POSITION_B 0x417
	287	#define DC_DISP_H_PULSE2_POSITION_C 0x418
	288	#define DC_DISP_H_PULSE2_POSITION_D 0x419
	289	#define DC_DISP_V_PULSE0_CONTROL 0x41a
	290	#define DC_DISP_V_PULSE0_POSITION_A 0x41b
	291	#define DC_DISP_V_PULSE0_POSITION_B 0x41c
	292	#define DC_DISP_V_PULSE0_POSITION_C 0x41d
	293	#define DC_DISP_V_PULSE1_CONTROL 0x41e
	294	#define DC_DISP_V_PULSE1_POSITION_A 0x41f
	295	#define DC_DISP_V_PULSE1_POSITION_B 0x420
	296	#define DC_DISP_V_PULSE1_POSITION_C 0x421
	297	#define DC_DISP_V_PULSE2_CONTROL 0x422
	298	#define DC_DISP_V_PULSE2_POSITION_A 0x423
	299	#define DC_DISP_V_PULSE3_CONTROL 0x424
	300	#define DC_DISP_V_PULSE3_POSITION_A 0x425
	301	#define DC_DISP_M0_CONTROL 0x426
	302	#define DC_DISP_M1_CONTROL 0x427
	303	#define DC_DISP_DI_CONTROL 0x428
	304	#define DC_DISP_PP_CONTROL 0x429
	305	#define DC_DISP_PP_SELECT_A 0x42a
	306	#define DC_DISP_PP_SELECT_B 0x42b
	307	#define DC_DISP_PP_SELECT_C 0x42c
	308	#define DC_DISP_PP_SELECT_D 0x42d
	309
	310	#define PULSE_MODE_NORMAL (0 << 3)
	311	#define PULSE_MODE_ONE_CLOCK (1 << 3)
	312	#define PULSE_POLARITY_HIGH (0 << 4)
	313	#define PULSE_POLARITY_LOW (1 << 4)
	314	#define PULSE_QUAL_ALWAYS (0 << 6)
	315	#define PULSE_QUAL_VACTIVE (2 << 6)
	316	#define PULSE_QUAL_VACTIVE1 (3 << 6)
317	#define PULSE_LAST_START_A (0 << 8)
318	#define PULSE_LAST_END_A (1 << 8)
319	#define PULSE_LAST_START_B (2 << 8)
320	#define PULSE_LAST_END_B (3 << 8)
321	#define PULSE_LAST_START_C (4 << 8)
322	#define PULSE_LAST_END_C (5 << 8)
323	#define PULSE_LAST_START_D (6 << 8)
324	#define PULSE_LAST_END_D (7 << 8)
325
326	#define PULSE_START(x) (((x) & 0xfff) << 0)
327	#define PULSE_END(x) (((x) & 0xfff) << 16)
328
329	#define DC_DISP_DISP_CLOCK_CONTROL 0x42e
330	#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
331	#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
332	#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
333	#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
334	#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
335	#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
336	#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
337	#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
338	#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
339	#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
340	#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
341	#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
342	#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
343	#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
344
345	#define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
346	#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
347	#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
348	#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
349	#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
350	#define DISP_DATA_FORMAT_DF2S (4 << 0)
351	#define DISP_DATA_FORMAT_DF3S (5 << 0)
352	#define DISP_DATA_FORMAT_DFSPI (6 << 0)
353	#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
354	#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
355	#define DISP_ALIGNMENT_MSB (0 << 8)
356	#define DISP_ALIGNMENT_LSB (1 << 8)
357	#define DISP_ORDER_RED_BLUE (0 << 9)
358	#define DISP_ORDER_BLUE_RED (1 << 9)
359
360	#define DC_DISP_DISP_COLOR_CONTROL 0x430
361	#define BASE_COLOR_SIZE666 (0 << 0)
362	#define BASE_COLOR_SIZE111 (1 << 0)
363	#define BASE_COLOR_SIZE222 (2 << 0)
364	#define BASE_COLOR_SIZE333 (3 << 0)
365	#define BASE_COLOR_SIZE444 (4 << 0)
366	#define BASE_COLOR_SIZE555 (5 << 0)
367	#define BASE_COLOR_SIZE565 (6 << 0)
368	#define BASE_COLOR_SIZE332 (7 << 0)
369	#define BASE_COLOR_SIZE888 (8 << 0)
459cc2c6	370	#define DITHER_CONTROL_MASK (3 << 8)
d8f4a9ed TR	371	#define DITHER_CONTROL_DISABLE (0 << 8)
	372	#define DITHER_CONTROL_ORDERED (2 << 8)
	373	#define DITHER_CONTROL_ERRDIFF (3 << 8)
459cc2c6	374	#define BASE_COLOR_SIZE_MASK (0xf << 0)
472a6d1f TR	375	#define BASE_COLOR_SIZE_666 (0 << 0)
	376	#define BASE_COLOR_SIZE_111 (1 << 0)
	377	#define BASE_COLOR_SIZE_222 (2 << 0)
	378	#define BASE_COLOR_SIZE_333 (3 << 0)
	379	#define BASE_COLOR_SIZE_444 (4 << 0)
	380	#define BASE_COLOR_SIZE_555 (5 << 0)
	381	#define BASE_COLOR_SIZE_565 (6 << 0)
	382	#define BASE_COLOR_SIZE_332 (7 << 0)
	383	#define BASE_COLOR_SIZE_888 (8 << 0)
d8f4a9ed TR	384
d8f4a9ed TR	385	#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
72d30286 TR	386	#define SC1_H_QUALIFIER_NONE (1 << 16)
72d30286 TR	387	#define SC0_H_QUALIFIER_NONE (1 << 0)
d8f4a9ed TR	388
	389	#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
	390	#define DE_SELECT_ACTIVE_BLANK (0 << 0)
	391	#define DE_SELECT_ACTIVE (1 << 0)
	392	#define DE_SELECT_ACTIVE_IS (2 << 0)
	393	#define DE_CONTROL_ONECLK (0 << 2)
	394	#define DE_CONTROL_NORMAL (1 << 2)
	395	#define DE_CONTROL_EARLY_EXT (2 << 2)
	396	#define DE_CONTROL_EARLY (3 << 2)
	397	#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
	398
	399	#define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
	400	#define DC_DISP_LCD_SPI_OPTIONS 0x434
	401	#define DC_DISP_BORDER_COLOR 0x435
	402	#define DC_DISP_COLOR_KEY0_LOWER 0x436
	403	#define DC_DISP_COLOR_KEY0_UPPER 0x437
	404	#define DC_DISP_COLOR_KEY1_LOWER 0x438
	405	#define DC_DISP_COLOR_KEY1_UPPER 0x439
	406
	407	#define DC_DISP_CURSOR_FOREGROUND 0x43c
	408	#define DC_DISP_CURSOR_BACKGROUND 0x43d
	409
	410	#define DC_DISP_CURSOR_START_ADDR 0x43e
e687651b TR	411	#define CURSOR_CLIP_DISPLAY (0 << 28)
	412	#define CURSOR_CLIP_WIN_A (1 << 28)
	413	#define CURSOR_CLIP_WIN_B (2 << 28)
	414	#define CURSOR_CLIP_WIN_C (3 << 28)
	415	#define CURSOR_SIZE_32x32 (0 << 24)
	416	#define CURSOR_SIZE_64x64 (1 << 24)
	417	#define CURSOR_SIZE_128x128 (2 << 24)
	418	#define CURSOR_SIZE_256x256 (3 << 24)
d8f4a9ed TR	419	#define DC_DISP_CURSOR_START_ADDR_NS 0x43f
	420
	421	#define DC_DISP_CURSOR_POSITION 0x440
	422	#define DC_DISP_CURSOR_POSITION_NS 0x441
	423
	424	#define DC_DISP_INIT_SEQ_CONTROL 0x442
	425	#define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
	426	#define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
	427	#define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
	428	#define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
	429
	430	#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
	431	#define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
	432	#define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
	433	#define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
	434	#define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
	435
	436	#define DC_DISP_DAC_CRT_CTRL 0x4c0
	437	#define DC_DISP_DISP_MISC_CONTROL 0x4c1
	438	#define DC_DISP_SD_CONTROL 0x4c2
	439	#define DC_DISP_SD_CSC_COEFF 0x4c3
	440	#define DC_DISP_SD_LUT(x) (0x4c4 + (x))
	441	#define DC_DISP_SD_FLICKER_CONTROL 0x4cd
	442	#define DC_DISP_DC_PIXEL_COUNT 0x4ce
	443	#define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
	444	#define DC_DISP_SD_BL_PARAMETERS 0x4d7
	445	#define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
	446	#define DC_DISP_SD_BL_CONTROL 0x4dc
	447	#define DC_DISP_SD_HW_K_VALUES 0x4dd
	448	#define DC_DISP_SD_MAN_K_VALUES 0x4de
	449
7116e9a8 TR	450	#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4
	451	#define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24)
	452	#define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16)
	453	#define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8)
	454	#define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0)
	455
8620fc62 TR	456	#define DC_DISP_INTERLACE_CONTROL 0x4e5
	457	#define INTERLACE_STATUS (1 << 2)
	458	#define INTERLACE_START (1 << 1)
	459	#define INTERLACE_ENABLE (1 << 0)
	460
e687651b TR	461	#define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
	462	#define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
	463	#define CURSOR_MODE_LEGACY (0 << 24)
	464	#define CURSOR_MODE_NORMAL (1 << 24)
	465	#define CURSOR_DST_BLEND_ZERO (0 << 16)
	466	#define CURSOR_DST_BLEND_K1 (1 << 16)
	467	#define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16)
	468	#define CURSOR_DST_BLEND_MASK (3 << 16)
	469	#define CURSOR_SRC_BLEND_K1 (0 << 8)
	470	#define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8)
	471	#define CURSOR_SRC_BLEND_MASK (3 << 8)
	472	#define CURSOR_ALPHA 0xff
	473
f34bc787 TR	474	#define DC_WIN_CSC_YOF 0x611
	475	#define DC_WIN_CSC_KYRGB 0x612
	476	#define DC_WIN_CSC_KUR 0x613
	477	#define DC_WIN_CSC_KVR 0x614
	478	#define DC_WIN_CSC_KUG 0x615
	479	#define DC_WIN_CSC_KVG 0x616
	480	#define DC_WIN_CSC_KUB 0x617
	481	#define DC_WIN_CSC_KVB 0x618
	482
d8f4a9ed	483	#define DC_WIN_WIN_OPTIONS 0x700
eba66501 TR	484	#define H_DIRECTION (1 << 0)
eba66501 TR	485	#define V_DIRECTION (1 << 2)
d8f4a9ed	486	#define COLOR_EXPAND (1 << 6)
f34bc787	487	#define CSC_ENABLE (1 << 18)
d8f4a9ed TR	488	#define WIN_ENABLE (1 << 30)
	489
	490	#define DC_WIN_BYTE_SWAP 0x701
	491	#define BYTE_SWAP_NOSWAP (0 << 0)
	492	#define BYTE_SWAP_SWAP2 (1 << 0)
	493	#define BYTE_SWAP_SWAP4 (2 << 0)
	494	#define BYTE_SWAP_SWAP4HW (3 << 0)
	495
	496	#define DC_WIN_BUFFER_CONTROL 0x702
	497	#define BUFFER_CONTROL_HOST (0 << 0)
	498	#define BUFFER_CONTROL_VI (1 << 0)
	499	#define BUFFER_CONTROL_EPP (2 << 0)
	500	#define BUFFER_CONTROL_MPEGE (3 << 0)
	501	#define BUFFER_CONTROL_SB2D (4 << 0)
	502
	503	#define DC_WIN_COLOR_DEPTH 0x703
	504	#define WIN_COLOR_DEPTH_P1 0
	505	#define WIN_COLOR_DEPTH_P2 1
	506	#define WIN_COLOR_DEPTH_P4 2
	507	#define WIN_COLOR_DEPTH_P8 3
	508	#define WIN_COLOR_DEPTH_B4G4R4A4 4
	509	#define WIN_COLOR_DEPTH_B5G5R5A 5
	510	#define WIN_COLOR_DEPTH_B5G6R5 6
	511	#define WIN_COLOR_DEPTH_AB5G5R5 7
	512	#define WIN_COLOR_DEPTH_B8G8R8A8 12
	513	#define WIN_COLOR_DEPTH_R8G8B8A8 13
	514	#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
	515	#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
	516	#define WIN_COLOR_DEPTH_YCbCr422 16
	517	#define WIN_COLOR_DEPTH_YUV422 17
	518	#define WIN_COLOR_DEPTH_YCbCr420P 18
	519	#define WIN_COLOR_DEPTH_YUV420P 19
	520	#define WIN_COLOR_DEPTH_YCbCr422P 20
	521	#define WIN_COLOR_DEPTH_YUV422P 21
	522	#define WIN_COLOR_DEPTH_YCbCr422R 22
	523	#define WIN_COLOR_DEPTH_YUV422R 23
	524	#define WIN_COLOR_DEPTH_YCbCr422RA 24
	525	#define WIN_COLOR_DEPTH_YUV422RA 25
	526
	527	#define DC_WIN_POSITION 0x704
	528	#define H_POSITION(x) (((x) & 0x1fff) << 0)
	529	#define V_POSITION(x) (((x) & 0x1fff) << 16)
	530
	531	#define DC_WIN_SIZE 0x705
	532	#define H_SIZE(x) (((x) & 0x1fff) << 0)
	533	#define V_SIZE(x) (((x) & 0x1fff) << 16)
	534
	535	#define DC_WIN_PRESCALED_SIZE 0x706
	536	#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
	537	#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
	538
	539	#define DC_WIN_H_INITIAL_DDA 0x707
	540	#define DC_WIN_V_INITIAL_DDA 0x708
	541	#define DC_WIN_DDA_INC 0x709
	542	#define H_DDA_INC(x) (((x) & 0xffff) << 0)
	543	#define V_DDA_INC(x) (((x) & 0xffff) << 16)
	544
	545	#define DC_WIN_LINE_STRIDE 0x70a
	546	#define DC_WIN_BUF_STRIDE 0x70b
	547	#define DC_WIN_UV_BUF_STRIDE 0x70c
	548	#define DC_WIN_BUFFER_ADDR_MODE 0x70d
773af77f TR	549	#define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
	550	#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
	551	#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
	552	#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
d8f4a9ed TR	553	#define DC_WIN_DV_CONTROL 0x70e
	554
	555	#define DC_WIN_BLEND_NOKEY 0x70f
	556	#define DC_WIN_BLEND_1WIN 0x710
	557	#define DC_WIN_BLEND_2WIN_X 0x711
	558	#define DC_WIN_BLEND_2WIN_Y 0x712
f34bc787	559	#define DC_WIN_BLEND_3WIN_XY 0x713
d8f4a9ed TR	560
	561	#define DC_WIN_HP_FETCH_CONTROL 0x714
	562
	563	#define DC_WINBUF_START_ADDR 0x800
	564	#define DC_WINBUF_START_ADDR_NS 0x801
	565	#define DC_WINBUF_START_ADDR_U 0x802
	566	#define DC_WINBUF_START_ADDR_U_NS 0x803
	567	#define DC_WINBUF_START_ADDR_V 0x804
	568	#define DC_WINBUF_START_ADDR_V_NS 0x805
	569
	570	#define DC_WINBUF_ADDR_H_OFFSET 0x806
	571	#define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
	572	#define DC_WINBUF_ADDR_V_OFFSET 0x808
	573	#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
	574
	575	#define DC_WINBUF_UFLOW_STATUS 0x80a
c134f019 TR	576	#define DC_WINBUF_SURFACE_KIND 0x80b
	577	#define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
	578	#define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
	579	#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
	580	#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
d8f4a9ed TR	581
	582	#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
	583	#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
	584	#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
	585
d8f4a9ed	586	#endif /* TEGRA_DC_H */