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Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
ad926015 | 3 | * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. |
d8f4a9ed TR |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
ad926015 | 10 | #include <linux/bitops.h> |
776dc384 | 11 | #include <linux/host1x.h> |
bdd2f9cd | 12 | #include <linux/idr.h> |
df06b759 | 13 | #include <linux/iommu.h> |
776dc384 | 14 | |
1503ca47 | 15 | #include <drm/drm_atomic.h> |
07866963 TR |
16 | #include <drm/drm_atomic_helper.h> |
17 | ||
d8f4a9ed | 18 | #include "drm.h" |
de2ba664 | 19 | #include "gem.h" |
d8f4a9ed TR |
20 | |
21 | #define DRIVER_NAME "tegra" | |
22 | #define DRIVER_DESC "NVIDIA Tegra graphics" | |
23 | #define DRIVER_DATE "20120330" | |
24 | #define DRIVER_MAJOR 0 | |
25 | #define DRIVER_MINOR 0 | |
26 | #define DRIVER_PATCHLEVEL 0 | |
27 | ||
ad926015 MP |
28 | #define CARVEOUT_SZ SZ_64M |
29 | ||
08943e6c | 30 | struct tegra_drm_file { |
bdd2f9cd TR |
31 | struct idr contexts; |
32 | struct mutex lock; | |
08943e6c TR |
33 | }; |
34 | ||
1503ca47 TR |
35 | static void tegra_atomic_schedule(struct tegra_drm *tegra, |
36 | struct drm_atomic_state *state) | |
37 | { | |
38 | tegra->commit.state = state; | |
39 | schedule_work(&tegra->commit.work); | |
40 | } | |
41 | ||
42 | static void tegra_atomic_complete(struct tegra_drm *tegra, | |
43 | struct drm_atomic_state *state) | |
44 | { | |
45 | struct drm_device *drm = tegra->drm; | |
46 | ||
47 | /* | |
48 | * Everything below can be run asynchronously without the need to grab | |
49 | * any modeset locks at all under one condition: It must be guaranteed | |
50 | * that the asynchronous work has either been cancelled (if the driver | |
51 | * supports it, which at least requires that the framebuffers get | |
52 | * cleaned up with drm_atomic_helper_cleanup_planes()) or completed | |
53 | * before the new state gets committed on the software side with | |
54 | * drm_atomic_helper_swap_state(). | |
55 | * | |
56 | * This scheme allows new atomic state updates to be prepared and | |
57 | * checked in parallel to the asynchronous completion of the previous | |
58 | * update. Which is important since compositors need to figure out the | |
59 | * composition of the next frame right after having submitted the | |
60 | * current layout. | |
61 | */ | |
62 | ||
1af434a9 | 63 | drm_atomic_helper_commit_modeset_disables(drm, state); |
1af434a9 | 64 | drm_atomic_helper_commit_modeset_enables(drm, state); |
2b58e98d LY |
65 | drm_atomic_helper_commit_planes(drm, state, |
66 | DRM_PLANE_COMMIT_ACTIVE_ONLY); | |
1503ca47 TR |
67 | |
68 | drm_atomic_helper_wait_for_vblanks(drm, state); | |
69 | ||
70 | drm_atomic_helper_cleanup_planes(drm, state); | |
0853695c | 71 | drm_atomic_state_put(state); |
1503ca47 TR |
72 | } |
73 | ||
74 | static void tegra_atomic_work(struct work_struct *work) | |
75 | { | |
76 | struct tegra_drm *tegra = container_of(work, struct tegra_drm, | |
77 | commit.work); | |
78 | ||
79 | tegra_atomic_complete(tegra, tegra->commit.state); | |
80 | } | |
81 | ||
82 | static int tegra_atomic_commit(struct drm_device *drm, | |
2dacdd70 | 83 | struct drm_atomic_state *state, bool nonblock) |
1503ca47 TR |
84 | { |
85 | struct tegra_drm *tegra = drm->dev_private; | |
86 | int err; | |
87 | ||
88 | err = drm_atomic_helper_prepare_planes(drm, state); | |
89 | if (err) | |
90 | return err; | |
91 | ||
2dacdd70 | 92 | /* serialize outstanding nonblocking commits */ |
1503ca47 TR |
93 | mutex_lock(&tegra->commit.lock); |
94 | flush_work(&tegra->commit.work); | |
95 | ||
96 | /* | |
97 | * This is the point of no return - everything below never fails except | |
98 | * when the hw goes bonghits. Which means we can commit the new state on | |
99 | * the software side now. | |
100 | */ | |
101 | ||
5e84c269 | 102 | drm_atomic_helper_swap_state(state, true); |
1503ca47 | 103 | |
0853695c | 104 | drm_atomic_state_get(state); |
2dacdd70 | 105 | if (nonblock) |
1503ca47 TR |
106 | tegra_atomic_schedule(tegra, state); |
107 | else | |
108 | tegra_atomic_complete(tegra, state); | |
109 | ||
110 | mutex_unlock(&tegra->commit.lock); | |
111 | return 0; | |
112 | } | |
113 | ||
f9914214 TR |
114 | static const struct drm_mode_config_funcs tegra_drm_mode_funcs = { |
115 | .fb_create = tegra_fb_create, | |
b110ef37 | 116 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
f9914214 TR |
117 | .output_poll_changed = tegra_fb_output_poll_changed, |
118 | #endif | |
07866963 | 119 | .atomic_check = drm_atomic_helper_check, |
1503ca47 | 120 | .atomic_commit = tegra_atomic_commit, |
f9914214 TR |
121 | }; |
122 | ||
776dc384 | 123 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
692e6d7b | 124 | { |
776dc384 | 125 | struct host1x_device *device = to_host1x_device(drm->dev); |
386a2a71 | 126 | struct tegra_drm *tegra; |
692e6d7b TB |
127 | int err; |
128 | ||
776dc384 | 129 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
386a2a71 | 130 | if (!tegra) |
692e6d7b TB |
131 | return -ENOMEM; |
132 | ||
df06b759 | 133 | if (iommu_present(&platform_bus_type)) { |
ad926015 | 134 | u64 carveout_start, carveout_end, gem_start, gem_end; |
4553f733 | 135 | struct iommu_domain_geometry *geometry; |
ad926015 | 136 | unsigned long order; |
4553f733 | 137 | |
df06b759 | 138 | tegra->domain = iommu_domain_alloc(&platform_bus_type); |
bf19b885 DC |
139 | if (!tegra->domain) { |
140 | err = -ENOMEM; | |
df06b759 TR |
141 | goto free; |
142 | } | |
143 | ||
4553f733 | 144 | geometry = &tegra->domain->geometry; |
ad926015 MP |
145 | gem_start = geometry->aperture_start; |
146 | gem_end = geometry->aperture_end - CARVEOUT_SZ; | |
147 | carveout_start = gem_end + 1; | |
148 | carveout_end = geometry->aperture_end; | |
149 | ||
150 | order = __ffs(tegra->domain->pgsize_bitmap); | |
151 | init_iova_domain(&tegra->carveout.domain, 1UL << order, | |
152 | carveout_start >> order, | |
153 | carveout_end >> order); | |
4553f733 | 154 | |
ad926015 MP |
155 | tegra->carveout.shift = iova_shift(&tegra->carveout.domain); |
156 | tegra->carveout.limit = carveout_end >> tegra->carveout.shift; | |
157 | ||
158 | drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1); | |
347ad49d | 159 | mutex_init(&tegra->mm_lock); |
ad926015 MP |
160 | |
161 | DRM_DEBUG("IOMMU apertures:\n"); | |
162 | DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end); | |
163 | DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start, | |
164 | carveout_end); | |
df06b759 TR |
165 | } |
166 | ||
386a2a71 TR |
167 | mutex_init(&tegra->clients_lock); |
168 | INIT_LIST_HEAD(&tegra->clients); | |
1503ca47 TR |
169 | |
170 | mutex_init(&tegra->commit.lock); | |
171 | INIT_WORK(&tegra->commit.work, tegra_atomic_work); | |
172 | ||
386a2a71 TR |
173 | drm->dev_private = tegra; |
174 | tegra->drm = drm; | |
d8f4a9ed TR |
175 | |
176 | drm_mode_config_init(drm); | |
177 | ||
f9914214 TR |
178 | drm->mode_config.min_width = 0; |
179 | drm->mode_config.min_height = 0; | |
180 | ||
181 | drm->mode_config.max_width = 4096; | |
182 | drm->mode_config.max_height = 4096; | |
183 | ||
5e91144d AC |
184 | drm->mode_config.allow_fb_modifiers = true; |
185 | ||
f9914214 TR |
186 | drm->mode_config.funcs = &tegra_drm_mode_funcs; |
187 | ||
e2215321 TR |
188 | err = tegra_drm_fb_prepare(drm); |
189 | if (err < 0) | |
1d1e6fe9 | 190 | goto config; |
e2215321 TR |
191 | |
192 | drm_kms_helper_poll_init(drm); | |
193 | ||
776dc384 | 194 | err = host1x_device_init(device); |
d8f4a9ed | 195 | if (err < 0) |
1d1e6fe9 | 196 | goto fbdev; |
d8f4a9ed | 197 | |
603f0cc9 TR |
198 | /* |
199 | * We don't use the drm_irq_install() helpers provided by the DRM | |
200 | * core, so we need to set this manually in order to allow the | |
201 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. | |
202 | */ | |
4423843c | 203 | drm->irq_enabled = true; |
603f0cc9 | 204 | |
42e9ce05 | 205 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
42e9ce05 TR |
206 | drm->max_vblank_count = 0xffffffff; |
207 | ||
6e5ff998 TR |
208 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
209 | if (err < 0) | |
1d1e6fe9 | 210 | goto device; |
6e5ff998 | 211 | |
31930d4d TR |
212 | drm_mode_config_reset(drm); |
213 | ||
d8f4a9ed TR |
214 | err = tegra_drm_fb_init(drm); |
215 | if (err < 0) | |
1d1e6fe9 | 216 | goto vblank; |
d8f4a9ed | 217 | |
d8f4a9ed | 218 | return 0; |
1d1e6fe9 TR |
219 | |
220 | vblank: | |
221 | drm_vblank_cleanup(drm); | |
222 | device: | |
223 | host1x_device_exit(device); | |
224 | fbdev: | |
225 | drm_kms_helper_poll_fini(drm); | |
226 | tegra_drm_fb_free(drm); | |
227 | config: | |
228 | drm_mode_config_cleanup(drm); | |
df06b759 TR |
229 | |
230 | if (tegra->domain) { | |
231 | iommu_domain_free(tegra->domain); | |
232 | drm_mm_takedown(&tegra->mm); | |
347ad49d | 233 | mutex_destroy(&tegra->mm_lock); |
ad926015 | 234 | put_iova_domain(&tegra->carveout.domain); |
df06b759 TR |
235 | } |
236 | free: | |
1d1e6fe9 TR |
237 | kfree(tegra); |
238 | return err; | |
d8f4a9ed TR |
239 | } |
240 | ||
11b3c20b | 241 | static void tegra_drm_unload(struct drm_device *drm) |
d8f4a9ed | 242 | { |
776dc384 | 243 | struct host1x_device *device = to_host1x_device(drm->dev); |
df06b759 | 244 | struct tegra_drm *tegra = drm->dev_private; |
776dc384 TR |
245 | int err; |
246 | ||
d8f4a9ed TR |
247 | drm_kms_helper_poll_fini(drm); |
248 | tegra_drm_fb_exit(drm); | |
f002abc1 | 249 | drm_mode_config_cleanup(drm); |
4aa3df71 | 250 | drm_vblank_cleanup(drm); |
d8f4a9ed | 251 | |
776dc384 TR |
252 | err = host1x_device_exit(device); |
253 | if (err < 0) | |
11b3c20b | 254 | return; |
776dc384 | 255 | |
df06b759 TR |
256 | if (tegra->domain) { |
257 | iommu_domain_free(tegra->domain); | |
258 | drm_mm_takedown(&tegra->mm); | |
347ad49d | 259 | mutex_destroy(&tegra->mm_lock); |
ad926015 | 260 | put_iova_domain(&tegra->carveout.domain); |
df06b759 TR |
261 | } |
262 | ||
1053f4dd | 263 | kfree(tegra); |
d8f4a9ed TR |
264 | } |
265 | ||
266 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) | |
267 | { | |
08943e6c | 268 | struct tegra_drm_file *fpriv; |
d43f81cb TB |
269 | |
270 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
271 | if (!fpriv) | |
272 | return -ENOMEM; | |
273 | ||
bdd2f9cd TR |
274 | idr_init(&fpriv->contexts); |
275 | mutex_init(&fpriv->lock); | |
d43f81cb TB |
276 | filp->driver_priv = fpriv; |
277 | ||
d8f4a9ed TR |
278 | return 0; |
279 | } | |
280 | ||
c88c3630 | 281 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
d43f81cb TB |
282 | { |
283 | context->client->ops->close_channel(context); | |
284 | kfree(context); | |
285 | } | |
286 | ||
d8f4a9ed TR |
287 | static void tegra_drm_lastclose(struct drm_device *drm) |
288 | { | |
b110ef37 | 289 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
386a2a71 | 290 | struct tegra_drm *tegra = drm->dev_private; |
d8f4a9ed | 291 | |
386a2a71 | 292 | tegra_fbdev_restore_mode(tegra->fbdev); |
60c2f709 | 293 | #endif |
d8f4a9ed TR |
294 | } |
295 | ||
c40f0f1a | 296 | static struct host1x_bo * |
a8ad0bd8 | 297 | host1x_bo_lookup(struct drm_file *file, u32 handle) |
c40f0f1a TR |
298 | { |
299 | struct drm_gem_object *gem; | |
300 | struct tegra_bo *bo; | |
301 | ||
a8ad0bd8 | 302 | gem = drm_gem_object_lookup(file, handle); |
c40f0f1a TR |
303 | if (!gem) |
304 | return NULL; | |
305 | ||
a07cdfe5 | 306 | drm_gem_object_unreference_unlocked(gem); |
c40f0f1a TR |
307 | |
308 | bo = to_tegra_bo(gem); | |
309 | return &bo->base; | |
310 | } | |
311 | ||
961e3bea TR |
312 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
313 | struct drm_tegra_reloc __user *src, | |
314 | struct drm_device *drm, | |
315 | struct drm_file *file) | |
316 | { | |
317 | u32 cmdbuf, target; | |
318 | int err; | |
319 | ||
320 | err = get_user(cmdbuf, &src->cmdbuf.handle); | |
321 | if (err < 0) | |
322 | return err; | |
323 | ||
324 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); | |
325 | if (err < 0) | |
326 | return err; | |
327 | ||
328 | err = get_user(target, &src->target.handle); | |
329 | if (err < 0) | |
330 | return err; | |
331 | ||
31f40f86 | 332 | err = get_user(dest->target.offset, &src->target.offset); |
961e3bea TR |
333 | if (err < 0) |
334 | return err; | |
335 | ||
336 | err = get_user(dest->shift, &src->shift); | |
337 | if (err < 0) | |
338 | return err; | |
339 | ||
a8ad0bd8 | 340 | dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf); |
961e3bea TR |
341 | if (!dest->cmdbuf.bo) |
342 | return -ENOENT; | |
343 | ||
a8ad0bd8 | 344 | dest->target.bo = host1x_bo_lookup(file, target); |
961e3bea TR |
345 | if (!dest->target.bo) |
346 | return -ENOENT; | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
c40f0f1a TR |
351 | int tegra_drm_submit(struct tegra_drm_context *context, |
352 | struct drm_tegra_submit *args, struct drm_device *drm, | |
353 | struct drm_file *file) | |
354 | { | |
355 | unsigned int num_cmdbufs = args->num_cmdbufs; | |
356 | unsigned int num_relocs = args->num_relocs; | |
357 | unsigned int num_waitchks = args->num_waitchks; | |
358 | struct drm_tegra_cmdbuf __user *cmdbufs = | |
a7ed68fc | 359 | (void __user *)(uintptr_t)args->cmdbufs; |
c40f0f1a | 360 | struct drm_tegra_reloc __user *relocs = |
a7ed68fc | 361 | (void __user *)(uintptr_t)args->relocs; |
c40f0f1a | 362 | struct drm_tegra_waitchk __user *waitchks = |
a7ed68fc | 363 | (void __user *)(uintptr_t)args->waitchks; |
c40f0f1a TR |
364 | struct drm_tegra_syncpt syncpt; |
365 | struct host1x_job *job; | |
366 | int err; | |
367 | ||
368 | /* We don't yet support other than one syncpt_incr struct per submit */ | |
369 | if (args->num_syncpts != 1) | |
370 | return -EINVAL; | |
371 | ||
372 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, | |
373 | args->num_relocs, args->num_waitchks); | |
374 | if (!job) | |
375 | return -ENOMEM; | |
376 | ||
377 | job->num_relocs = args->num_relocs; | |
378 | job->num_waitchk = args->num_waitchks; | |
379 | job->client = (u32)args->context; | |
380 | job->class = context->client->base.class; | |
381 | job->serialize = true; | |
382 | ||
383 | while (num_cmdbufs) { | |
384 | struct drm_tegra_cmdbuf cmdbuf; | |
385 | struct host1x_bo *bo; | |
386 | ||
9a991600 DC |
387 | if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) { |
388 | err = -EFAULT; | |
c40f0f1a | 389 | goto fail; |
9a991600 | 390 | } |
c40f0f1a | 391 | |
a8ad0bd8 | 392 | bo = host1x_bo_lookup(file, cmdbuf.handle); |
c40f0f1a TR |
393 | if (!bo) { |
394 | err = -ENOENT; | |
395 | goto fail; | |
396 | } | |
397 | ||
398 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); | |
399 | num_cmdbufs--; | |
400 | cmdbufs++; | |
401 | } | |
402 | ||
961e3bea | 403 | /* copy and resolve relocations from submit */ |
c40f0f1a | 404 | while (num_relocs--) { |
961e3bea TR |
405 | err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs], |
406 | &relocs[num_relocs], drm, | |
407 | file); | |
408 | if (err < 0) | |
c40f0f1a | 409 | goto fail; |
c40f0f1a TR |
410 | } |
411 | ||
9a991600 DC |
412 | if (copy_from_user(job->waitchk, waitchks, |
413 | sizeof(*waitchks) * num_waitchks)) { | |
414 | err = -EFAULT; | |
c40f0f1a | 415 | goto fail; |
9a991600 | 416 | } |
c40f0f1a | 417 | |
9a991600 DC |
418 | if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts, |
419 | sizeof(syncpt))) { | |
420 | err = -EFAULT; | |
c40f0f1a | 421 | goto fail; |
9a991600 | 422 | } |
c40f0f1a TR |
423 | |
424 | job->is_addr_reg = context->client->ops->is_addr_reg; | |
425 | job->syncpt_incrs = syncpt.incrs; | |
426 | job->syncpt_id = syncpt.id; | |
427 | job->timeout = 10000; | |
428 | ||
429 | if (args->timeout && args->timeout < 10000) | |
430 | job->timeout = args->timeout; | |
431 | ||
432 | err = host1x_job_pin(job, context->client->base.dev); | |
433 | if (err) | |
434 | goto fail; | |
435 | ||
436 | err = host1x_job_submit(job); | |
437 | if (err) | |
438 | goto fail_submit; | |
439 | ||
440 | args->fence = job->syncpt_end; | |
441 | ||
442 | host1x_job_put(job); | |
443 | return 0; | |
444 | ||
445 | fail_submit: | |
446 | host1x_job_unpin(job); | |
447 | fail: | |
448 | host1x_job_put(job); | |
449 | return err; | |
450 | } | |
451 | ||
452 | ||
d43f81cb | 453 | #ifdef CONFIG_DRM_TEGRA_STAGING |
d43f81cb TB |
454 | static int tegra_gem_create(struct drm_device *drm, void *data, |
455 | struct drm_file *file) | |
456 | { | |
457 | struct drm_tegra_gem_create *args = data; | |
458 | struct tegra_bo *bo; | |
459 | ||
773af77f | 460 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
d43f81cb TB |
461 | &args->handle); |
462 | if (IS_ERR(bo)) | |
463 | return PTR_ERR(bo); | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
468 | static int tegra_gem_mmap(struct drm_device *drm, void *data, | |
469 | struct drm_file *file) | |
470 | { | |
471 | struct drm_tegra_gem_mmap *args = data; | |
472 | struct drm_gem_object *gem; | |
473 | struct tegra_bo *bo; | |
474 | ||
a8ad0bd8 | 475 | gem = drm_gem_object_lookup(file, args->handle); |
d43f81cb TB |
476 | if (!gem) |
477 | return -EINVAL; | |
478 | ||
479 | bo = to_tegra_bo(gem); | |
480 | ||
2bc7b0ca | 481 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
d43f81cb | 482 | |
11533304 | 483 | drm_gem_object_unreference_unlocked(gem); |
d43f81cb TB |
484 | |
485 | return 0; | |
486 | } | |
487 | ||
488 | static int tegra_syncpt_read(struct drm_device *drm, void *data, | |
489 | struct drm_file *file) | |
490 | { | |
776dc384 | 491 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 492 | struct drm_tegra_syncpt_read *args = data; |
776dc384 | 493 | struct host1x_syncpt *sp; |
d43f81cb | 494 | |
776dc384 | 495 | sp = host1x_syncpt_get(host, args->id); |
d43f81cb TB |
496 | if (!sp) |
497 | return -EINVAL; | |
498 | ||
499 | args->value = host1x_syncpt_read_min(sp); | |
500 | return 0; | |
501 | } | |
502 | ||
503 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, | |
504 | struct drm_file *file) | |
505 | { | |
776dc384 | 506 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 507 | struct drm_tegra_syncpt_incr *args = data; |
776dc384 | 508 | struct host1x_syncpt *sp; |
d43f81cb | 509 | |
776dc384 | 510 | sp = host1x_syncpt_get(host1x, args->id); |
d43f81cb TB |
511 | if (!sp) |
512 | return -EINVAL; | |
513 | ||
ebae30b1 | 514 | return host1x_syncpt_incr(sp); |
d43f81cb TB |
515 | } |
516 | ||
517 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, | |
518 | struct drm_file *file) | |
519 | { | |
776dc384 | 520 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 521 | struct drm_tegra_syncpt_wait *args = data; |
776dc384 | 522 | struct host1x_syncpt *sp; |
d43f81cb | 523 | |
776dc384 | 524 | sp = host1x_syncpt_get(host1x, args->id); |
d43f81cb TB |
525 | if (!sp) |
526 | return -EINVAL; | |
527 | ||
528 | return host1x_syncpt_wait(sp, args->thresh, args->timeout, | |
529 | &args->value); | |
530 | } | |
531 | ||
bdd2f9cd TR |
532 | static int tegra_client_open(struct tegra_drm_file *fpriv, |
533 | struct tegra_drm_client *client, | |
534 | struct tegra_drm_context *context) | |
535 | { | |
536 | int err; | |
537 | ||
538 | err = client->ops->open_channel(client, context); | |
539 | if (err < 0) | |
540 | return err; | |
541 | ||
542 | err = idr_alloc(&fpriv->contexts, context, 0, 0, GFP_KERNEL); | |
543 | if (err < 0) { | |
544 | client->ops->close_channel(context); | |
545 | return err; | |
546 | } | |
547 | ||
548 | context->client = client; | |
549 | context->id = err; | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
d43f81cb TB |
554 | static int tegra_open_channel(struct drm_device *drm, void *data, |
555 | struct drm_file *file) | |
556 | { | |
08943e6c | 557 | struct tegra_drm_file *fpriv = file->driver_priv; |
386a2a71 | 558 | struct tegra_drm *tegra = drm->dev_private; |
d43f81cb | 559 | struct drm_tegra_open_channel *args = data; |
c88c3630 | 560 | struct tegra_drm_context *context; |
53fa7f72 | 561 | struct tegra_drm_client *client; |
d43f81cb TB |
562 | int err = -ENODEV; |
563 | ||
564 | context = kzalloc(sizeof(*context), GFP_KERNEL); | |
565 | if (!context) | |
566 | return -ENOMEM; | |
567 | ||
bdd2f9cd TR |
568 | mutex_lock(&fpriv->lock); |
569 | ||
776dc384 | 570 | list_for_each_entry(client, &tegra->clients, list) |
53fa7f72 | 571 | if (client->base.class == args->client) { |
bdd2f9cd TR |
572 | err = tegra_client_open(fpriv, client, context); |
573 | if (err < 0) | |
d43f81cb TB |
574 | break; |
575 | ||
bdd2f9cd TR |
576 | args->context = context->id; |
577 | break; | |
d43f81cb TB |
578 | } |
579 | ||
bdd2f9cd TR |
580 | if (err < 0) |
581 | kfree(context); | |
582 | ||
583 | mutex_unlock(&fpriv->lock); | |
d43f81cb TB |
584 | return err; |
585 | } | |
586 | ||
587 | static int tegra_close_channel(struct drm_device *drm, void *data, | |
588 | struct drm_file *file) | |
589 | { | |
08943e6c | 590 | struct tegra_drm_file *fpriv = file->driver_priv; |
776dc384 | 591 | struct drm_tegra_close_channel *args = data; |
c88c3630 | 592 | struct tegra_drm_context *context; |
bdd2f9cd | 593 | int err = 0; |
c88c3630 | 594 | |
bdd2f9cd | 595 | mutex_lock(&fpriv->lock); |
d43f81cb | 596 | |
1066a895 | 597 | context = idr_find(&fpriv->contexts, args->context); |
bdd2f9cd TR |
598 | if (!context) { |
599 | err = -EINVAL; | |
600 | goto unlock; | |
601 | } | |
d43f81cb | 602 | |
bdd2f9cd | 603 | idr_remove(&fpriv->contexts, context->id); |
c88c3630 | 604 | tegra_drm_context_free(context); |
d43f81cb | 605 | |
bdd2f9cd TR |
606 | unlock: |
607 | mutex_unlock(&fpriv->lock); | |
608 | return err; | |
d43f81cb TB |
609 | } |
610 | ||
611 | static int tegra_get_syncpt(struct drm_device *drm, void *data, | |
612 | struct drm_file *file) | |
613 | { | |
08943e6c | 614 | struct tegra_drm_file *fpriv = file->driver_priv; |
d43f81cb | 615 | struct drm_tegra_get_syncpt *args = data; |
c88c3630 | 616 | struct tegra_drm_context *context; |
d43f81cb | 617 | struct host1x_syncpt *syncpt; |
bdd2f9cd | 618 | int err = 0; |
d43f81cb | 619 | |
bdd2f9cd | 620 | mutex_lock(&fpriv->lock); |
c88c3630 | 621 | |
1066a895 | 622 | context = idr_find(&fpriv->contexts, args->context); |
bdd2f9cd TR |
623 | if (!context) { |
624 | err = -ENODEV; | |
625 | goto unlock; | |
626 | } | |
d43f81cb | 627 | |
bdd2f9cd TR |
628 | if (args->index >= context->client->base.num_syncpts) { |
629 | err = -EINVAL; | |
630 | goto unlock; | |
631 | } | |
d43f81cb | 632 | |
53fa7f72 | 633 | syncpt = context->client->base.syncpts[args->index]; |
d43f81cb TB |
634 | args->id = host1x_syncpt_id(syncpt); |
635 | ||
bdd2f9cd TR |
636 | unlock: |
637 | mutex_unlock(&fpriv->lock); | |
638 | return err; | |
d43f81cb TB |
639 | } |
640 | ||
641 | static int tegra_submit(struct drm_device *drm, void *data, | |
642 | struct drm_file *file) | |
643 | { | |
08943e6c | 644 | struct tegra_drm_file *fpriv = file->driver_priv; |
d43f81cb | 645 | struct drm_tegra_submit *args = data; |
c88c3630 | 646 | struct tegra_drm_context *context; |
bdd2f9cd | 647 | int err; |
c88c3630 | 648 | |
bdd2f9cd | 649 | mutex_lock(&fpriv->lock); |
d43f81cb | 650 | |
1066a895 | 651 | context = idr_find(&fpriv->contexts, args->context); |
bdd2f9cd TR |
652 | if (!context) { |
653 | err = -ENODEV; | |
654 | goto unlock; | |
655 | } | |
d43f81cb | 656 | |
bdd2f9cd | 657 | err = context->client->ops->submit(context, args, drm, file); |
d43f81cb | 658 | |
bdd2f9cd TR |
659 | unlock: |
660 | mutex_unlock(&fpriv->lock); | |
661 | return err; | |
d43f81cb | 662 | } |
c54a169b AM |
663 | |
664 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, | |
665 | struct drm_file *file) | |
666 | { | |
667 | struct tegra_drm_file *fpriv = file->driver_priv; | |
668 | struct drm_tegra_get_syncpt_base *args = data; | |
669 | struct tegra_drm_context *context; | |
670 | struct host1x_syncpt_base *base; | |
671 | struct host1x_syncpt *syncpt; | |
bdd2f9cd | 672 | int err = 0; |
c54a169b | 673 | |
bdd2f9cd | 674 | mutex_lock(&fpriv->lock); |
c54a169b | 675 | |
1066a895 | 676 | context = idr_find(&fpriv->contexts, args->context); |
bdd2f9cd TR |
677 | if (!context) { |
678 | err = -ENODEV; | |
679 | goto unlock; | |
680 | } | |
c54a169b | 681 | |
bdd2f9cd TR |
682 | if (args->syncpt >= context->client->base.num_syncpts) { |
683 | err = -EINVAL; | |
684 | goto unlock; | |
685 | } | |
c54a169b AM |
686 | |
687 | syncpt = context->client->base.syncpts[args->syncpt]; | |
688 | ||
689 | base = host1x_syncpt_get_base(syncpt); | |
bdd2f9cd TR |
690 | if (!base) { |
691 | err = -ENXIO; | |
692 | goto unlock; | |
693 | } | |
c54a169b AM |
694 | |
695 | args->id = host1x_syncpt_base_id(base); | |
696 | ||
bdd2f9cd TR |
697 | unlock: |
698 | mutex_unlock(&fpriv->lock); | |
699 | return err; | |
c54a169b | 700 | } |
7678d71f TR |
701 | |
702 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, | |
703 | struct drm_file *file) | |
704 | { | |
705 | struct drm_tegra_gem_set_tiling *args = data; | |
706 | enum tegra_bo_tiling_mode mode; | |
707 | struct drm_gem_object *gem; | |
708 | unsigned long value = 0; | |
709 | struct tegra_bo *bo; | |
710 | ||
711 | switch (args->mode) { | |
712 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: | |
713 | mode = TEGRA_BO_TILING_MODE_PITCH; | |
714 | ||
715 | if (args->value != 0) | |
716 | return -EINVAL; | |
717 | ||
718 | break; | |
719 | ||
720 | case DRM_TEGRA_GEM_TILING_MODE_TILED: | |
721 | mode = TEGRA_BO_TILING_MODE_TILED; | |
722 | ||
723 | if (args->value != 0) | |
724 | return -EINVAL; | |
725 | ||
726 | break; | |
727 | ||
728 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: | |
729 | mode = TEGRA_BO_TILING_MODE_BLOCK; | |
730 | ||
731 | if (args->value > 5) | |
732 | return -EINVAL; | |
733 | ||
734 | value = args->value; | |
735 | break; | |
736 | ||
737 | default: | |
738 | return -EINVAL; | |
739 | } | |
740 | ||
a8ad0bd8 | 741 | gem = drm_gem_object_lookup(file, args->handle); |
7678d71f TR |
742 | if (!gem) |
743 | return -ENOENT; | |
744 | ||
745 | bo = to_tegra_bo(gem); | |
746 | ||
747 | bo->tiling.mode = mode; | |
748 | bo->tiling.value = value; | |
749 | ||
11533304 | 750 | drm_gem_object_unreference_unlocked(gem); |
7678d71f TR |
751 | |
752 | return 0; | |
753 | } | |
754 | ||
755 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, | |
756 | struct drm_file *file) | |
757 | { | |
758 | struct drm_tegra_gem_get_tiling *args = data; | |
759 | struct drm_gem_object *gem; | |
760 | struct tegra_bo *bo; | |
761 | int err = 0; | |
762 | ||
a8ad0bd8 | 763 | gem = drm_gem_object_lookup(file, args->handle); |
7678d71f TR |
764 | if (!gem) |
765 | return -ENOENT; | |
766 | ||
767 | bo = to_tegra_bo(gem); | |
768 | ||
769 | switch (bo->tiling.mode) { | |
770 | case TEGRA_BO_TILING_MODE_PITCH: | |
771 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; | |
772 | args->value = 0; | |
773 | break; | |
774 | ||
775 | case TEGRA_BO_TILING_MODE_TILED: | |
776 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; | |
777 | args->value = 0; | |
778 | break; | |
779 | ||
780 | case TEGRA_BO_TILING_MODE_BLOCK: | |
781 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; | |
782 | args->value = bo->tiling.value; | |
783 | break; | |
784 | ||
785 | default: | |
786 | err = -EINVAL; | |
787 | break; | |
788 | } | |
789 | ||
11533304 | 790 | drm_gem_object_unreference_unlocked(gem); |
7678d71f TR |
791 | |
792 | return err; | |
793 | } | |
7b129087 TR |
794 | |
795 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, | |
796 | struct drm_file *file) | |
797 | { | |
798 | struct drm_tegra_gem_set_flags *args = data; | |
799 | struct drm_gem_object *gem; | |
800 | struct tegra_bo *bo; | |
801 | ||
802 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) | |
803 | return -EINVAL; | |
804 | ||
a8ad0bd8 | 805 | gem = drm_gem_object_lookup(file, args->handle); |
7b129087 TR |
806 | if (!gem) |
807 | return -ENOENT; | |
808 | ||
809 | bo = to_tegra_bo(gem); | |
810 | bo->flags = 0; | |
811 | ||
812 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) | |
813 | bo->flags |= TEGRA_BO_BOTTOM_UP; | |
814 | ||
11533304 | 815 | drm_gem_object_unreference_unlocked(gem); |
7b129087 TR |
816 | |
817 | return 0; | |
818 | } | |
819 | ||
820 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, | |
821 | struct drm_file *file) | |
822 | { | |
823 | struct drm_tegra_gem_get_flags *args = data; | |
824 | struct drm_gem_object *gem; | |
825 | struct tegra_bo *bo; | |
826 | ||
a8ad0bd8 | 827 | gem = drm_gem_object_lookup(file, args->handle); |
7b129087 TR |
828 | if (!gem) |
829 | return -ENOENT; | |
830 | ||
831 | bo = to_tegra_bo(gem); | |
832 | args->flags = 0; | |
833 | ||
834 | if (bo->flags & TEGRA_BO_BOTTOM_UP) | |
835 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; | |
836 | ||
11533304 | 837 | drm_gem_object_unreference_unlocked(gem); |
7b129087 TR |
838 | |
839 | return 0; | |
840 | } | |
d43f81cb TB |
841 | #endif |
842 | ||
baa70943 | 843 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
d43f81cb | 844 | #ifdef CONFIG_DRM_TEGRA_STAGING |
f8c47144 DV |
845 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0), |
846 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0), | |
847 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0), | |
848 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0), | |
849 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0), | |
850 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0), | |
851 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0), | |
852 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0), | |
853 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0), | |
854 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0), | |
855 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0), | |
856 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0), | |
857 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0), | |
858 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0), | |
d43f81cb | 859 | #endif |
d8f4a9ed TR |
860 | }; |
861 | ||
862 | static const struct file_operations tegra_drm_fops = { | |
863 | .owner = THIS_MODULE, | |
864 | .open = drm_open, | |
865 | .release = drm_release, | |
866 | .unlocked_ioctl = drm_ioctl, | |
de2ba664 | 867 | .mmap = tegra_drm_mmap, |
d8f4a9ed | 868 | .poll = drm_poll, |
d8f4a9ed | 869 | .read = drm_read, |
d8f4a9ed | 870 | .compat_ioctl = drm_compat_ioctl, |
d8f4a9ed TR |
871 | .llseek = noop_llseek, |
872 | }; | |
873 | ||
bdd2f9cd TR |
874 | static int tegra_drm_context_cleanup(int id, void *p, void *data) |
875 | { | |
876 | struct tegra_drm_context *context = p; | |
877 | ||
878 | tegra_drm_context_free(context); | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
3c03c46a TR |
883 | static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file) |
884 | { | |
08943e6c | 885 | struct tegra_drm_file *fpriv = file->driver_priv; |
3c03c46a | 886 | |
bdd2f9cd TR |
887 | mutex_lock(&fpriv->lock); |
888 | idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL); | |
889 | mutex_unlock(&fpriv->lock); | |
d43f81cb | 890 | |
bdd2f9cd TR |
891 | idr_destroy(&fpriv->contexts); |
892 | mutex_destroy(&fpriv->lock); | |
d43f81cb | 893 | kfree(fpriv); |
3c03c46a TR |
894 | } |
895 | ||
e450fcc6 TR |
896 | #ifdef CONFIG_DEBUG_FS |
897 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) | |
898 | { | |
899 | struct drm_info_node *node = (struct drm_info_node *)s->private; | |
900 | struct drm_device *drm = node->minor->dev; | |
901 | struct drm_framebuffer *fb; | |
902 | ||
903 | mutex_lock(&drm->mode_config.fb_lock); | |
904 | ||
905 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { | |
906 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", | |
b00c600e VS |
907 | fb->base.id, fb->width, fb->height, |
908 | fb->format->depth, | |
272725c7 | 909 | fb->format->cpp[0] * 8, |
747a598f | 910 | drm_framebuffer_read_refcount(fb)); |
e450fcc6 TR |
911 | } |
912 | ||
913 | mutex_unlock(&drm->mode_config.fb_lock); | |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
28c23373 TR |
918 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
919 | { | |
920 | struct drm_info_node *node = (struct drm_info_node *)s->private; | |
921 | struct drm_device *drm = node->minor->dev; | |
922 | struct tegra_drm *tegra = drm->dev_private; | |
b5c3714f | 923 | struct drm_printer p = drm_seq_file_printer(s); |
28c23373 | 924 | |
347ad49d | 925 | mutex_lock(&tegra->mm_lock); |
b5c3714f | 926 | drm_mm_print(&tegra->mm, &p); |
347ad49d | 927 | mutex_unlock(&tegra->mm_lock); |
b5c3714f DV |
928 | |
929 | return 0; | |
28c23373 TR |
930 | } |
931 | ||
e450fcc6 TR |
932 | static struct drm_info_list tegra_debugfs_list[] = { |
933 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, | |
28c23373 | 934 | { "iova", tegra_debugfs_iova, 0 }, |
e450fcc6 TR |
935 | }; |
936 | ||
937 | static int tegra_debugfs_init(struct drm_minor *minor) | |
938 | { | |
939 | return drm_debugfs_create_files(tegra_debugfs_list, | |
940 | ARRAY_SIZE(tegra_debugfs_list), | |
941 | minor->debugfs_root, minor); | |
942 | } | |
e450fcc6 TR |
943 | #endif |
944 | ||
9b57f5f2 | 945 | static struct drm_driver tegra_drm_driver = { |
ad906599 TR |
946 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | |
947 | DRIVER_ATOMIC, | |
d8f4a9ed TR |
948 | .load = tegra_drm_load, |
949 | .unload = tegra_drm_unload, | |
950 | .open = tegra_drm_open, | |
3c03c46a | 951 | .preclose = tegra_drm_preclose, |
d8f4a9ed TR |
952 | .lastclose = tegra_drm_lastclose, |
953 | ||
e450fcc6 TR |
954 | #if defined(CONFIG_DEBUG_FS) |
955 | .debugfs_init = tegra_debugfs_init, | |
e450fcc6 TR |
956 | #endif |
957 | ||
1ddbdbd6 | 958 | .gem_free_object_unlocked = tegra_bo_free_object, |
de2ba664 | 959 | .gem_vm_ops = &tegra_bo_vm_ops, |
3800391d TR |
960 | |
961 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
962 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
963 | .gem_prime_export = tegra_gem_prime_export, | |
964 | .gem_prime_import = tegra_gem_prime_import, | |
965 | ||
de2ba664 AM |
966 | .dumb_create = tegra_bo_dumb_create, |
967 | .dumb_map_offset = tegra_bo_dumb_map_offset, | |
43387b37 | 968 | .dumb_destroy = drm_gem_dumb_destroy, |
d8f4a9ed TR |
969 | |
970 | .ioctls = tegra_drm_ioctls, | |
971 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), | |
972 | .fops = &tegra_drm_fops, | |
973 | ||
974 | .name = DRIVER_NAME, | |
975 | .desc = DRIVER_DESC, | |
976 | .date = DRIVER_DATE, | |
977 | .major = DRIVER_MAJOR, | |
978 | .minor = DRIVER_MINOR, | |
979 | .patchlevel = DRIVER_PATCHLEVEL, | |
980 | }; | |
776dc384 TR |
981 | |
982 | int tegra_drm_register_client(struct tegra_drm *tegra, | |
983 | struct tegra_drm_client *client) | |
984 | { | |
985 | mutex_lock(&tegra->clients_lock); | |
986 | list_add_tail(&client->list, &tegra->clients); | |
987 | mutex_unlock(&tegra->clients_lock); | |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
992 | int tegra_drm_unregister_client(struct tegra_drm *tegra, | |
993 | struct tegra_drm_client *client) | |
994 | { | |
995 | mutex_lock(&tegra->clients_lock); | |
996 | list_del_init(&client->list); | |
997 | mutex_unlock(&tegra->clients_lock); | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
ad926015 MP |
1002 | void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, |
1003 | dma_addr_t *dma) | |
1004 | { | |
1005 | struct iova *alloc; | |
1006 | void *virt; | |
1007 | gfp_t gfp; | |
1008 | int err; | |
1009 | ||
1010 | if (tegra->domain) | |
1011 | size = iova_align(&tegra->carveout.domain, size); | |
1012 | else | |
1013 | size = PAGE_ALIGN(size); | |
1014 | ||
1015 | gfp = GFP_KERNEL | __GFP_ZERO; | |
1016 | if (!tegra->domain) { | |
1017 | /* | |
1018 | * Many units only support 32-bit addresses, even on 64-bit | |
1019 | * SoCs. If there is no IOMMU to translate into a 32-bit IO | |
1020 | * virtual address space, force allocations to be in the | |
1021 | * lower 32-bit range. | |
1022 | */ | |
1023 | gfp |= GFP_DMA; | |
1024 | } | |
1025 | ||
1026 | virt = (void *)__get_free_pages(gfp, get_order(size)); | |
1027 | if (!virt) | |
1028 | return ERR_PTR(-ENOMEM); | |
1029 | ||
1030 | if (!tegra->domain) { | |
1031 | /* | |
1032 | * If IOMMU is disabled, devices address physical memory | |
1033 | * directly. | |
1034 | */ | |
1035 | *dma = virt_to_phys(virt); | |
1036 | return virt; | |
1037 | } | |
1038 | ||
1039 | alloc = alloc_iova(&tegra->carveout.domain, | |
1040 | size >> tegra->carveout.shift, | |
1041 | tegra->carveout.limit, true); | |
1042 | if (!alloc) { | |
1043 | err = -EBUSY; | |
1044 | goto free_pages; | |
1045 | } | |
1046 | ||
1047 | *dma = iova_dma_addr(&tegra->carveout.domain, alloc); | |
1048 | err = iommu_map(tegra->domain, *dma, virt_to_phys(virt), | |
1049 | size, IOMMU_READ | IOMMU_WRITE); | |
1050 | if (err < 0) | |
1051 | goto free_iova; | |
1052 | ||
1053 | return virt; | |
1054 | ||
1055 | free_iova: | |
1056 | __free_iova(&tegra->carveout.domain, alloc); | |
1057 | free_pages: | |
1058 | free_pages((unsigned long)virt, get_order(size)); | |
1059 | ||
1060 | return ERR_PTR(err); | |
1061 | } | |
1062 | ||
1063 | void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, | |
1064 | dma_addr_t dma) | |
1065 | { | |
1066 | if (tegra->domain) | |
1067 | size = iova_align(&tegra->carveout.domain, size); | |
1068 | else | |
1069 | size = PAGE_ALIGN(size); | |
1070 | ||
1071 | if (tegra->domain) { | |
1072 | iommu_unmap(tegra->domain, dma, size); | |
1073 | free_iova(&tegra->carveout.domain, | |
1074 | iova_pfn(&tegra->carveout.domain, dma)); | |
1075 | } | |
1076 | ||
1077 | free_pages((unsigned long)virt, get_order(size)); | |
1078 | } | |
1079 | ||
9910f5c4 | 1080 | static int host1x_drm_probe(struct host1x_device *dev) |
776dc384 | 1081 | { |
9910f5c4 TR |
1082 | struct drm_driver *driver = &tegra_drm_driver; |
1083 | struct drm_device *drm; | |
1084 | int err; | |
1085 | ||
1086 | drm = drm_dev_alloc(driver, &dev->dev); | |
0f288605 TG |
1087 | if (IS_ERR(drm)) |
1088 | return PTR_ERR(drm); | |
9910f5c4 | 1089 | |
9910f5c4 TR |
1090 | dev_set_drvdata(&dev->dev, drm); |
1091 | ||
1092 | err = drm_dev_register(drm, 0); | |
1093 | if (err < 0) | |
1094 | goto unref; | |
1095 | ||
9910f5c4 TR |
1096 | return 0; |
1097 | ||
1098 | unref: | |
1099 | drm_dev_unref(drm); | |
1100 | return err; | |
776dc384 TR |
1101 | } |
1102 | ||
9910f5c4 | 1103 | static int host1x_drm_remove(struct host1x_device *dev) |
776dc384 | 1104 | { |
9910f5c4 TR |
1105 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
1106 | ||
1107 | drm_dev_unregister(drm); | |
1108 | drm_dev_unref(drm); | |
776dc384 TR |
1109 | |
1110 | return 0; | |
1111 | } | |
1112 | ||
359ae687 TR |
1113 | #ifdef CONFIG_PM_SLEEP |
1114 | static int host1x_drm_suspend(struct device *dev) | |
1115 | { | |
1116 | struct drm_device *drm = dev_get_drvdata(dev); | |
986c58d1 | 1117 | struct tegra_drm *tegra = drm->dev_private; |
359ae687 TR |
1118 | |
1119 | drm_kms_helper_poll_disable(drm); | |
986c58d1 TR |
1120 | tegra_drm_fb_suspend(drm); |
1121 | ||
1122 | tegra->state = drm_atomic_helper_suspend(drm); | |
1123 | if (IS_ERR(tegra->state)) { | |
1124 | tegra_drm_fb_resume(drm); | |
1125 | drm_kms_helper_poll_enable(drm); | |
1126 | return PTR_ERR(tegra->state); | |
1127 | } | |
359ae687 TR |
1128 | |
1129 | return 0; | |
1130 | } | |
1131 | ||
1132 | static int host1x_drm_resume(struct device *dev) | |
1133 | { | |
1134 | struct drm_device *drm = dev_get_drvdata(dev); | |
986c58d1 | 1135 | struct tegra_drm *tegra = drm->dev_private; |
359ae687 | 1136 | |
986c58d1 TR |
1137 | drm_atomic_helper_resume(drm, tegra->state); |
1138 | tegra_drm_fb_resume(drm); | |
359ae687 TR |
1139 | drm_kms_helper_poll_enable(drm); |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | #endif | |
1144 | ||
a13f1dc4 TR |
1145 | static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, |
1146 | host1x_drm_resume); | |
359ae687 | 1147 | |
776dc384 TR |
1148 | static const struct of_device_id host1x_drm_subdevs[] = { |
1149 | { .compatible = "nvidia,tegra20-dc", }, | |
1150 | { .compatible = "nvidia,tegra20-hdmi", }, | |
1151 | { .compatible = "nvidia,tegra20-gr2d", }, | |
5f60ed0d | 1152 | { .compatible = "nvidia,tegra20-gr3d", }, |
776dc384 TR |
1153 | { .compatible = "nvidia,tegra30-dc", }, |
1154 | { .compatible = "nvidia,tegra30-hdmi", }, | |
1155 | { .compatible = "nvidia,tegra30-gr2d", }, | |
5f60ed0d | 1156 | { .compatible = "nvidia,tegra30-gr3d", }, |
dec72739 | 1157 | { .compatible = "nvidia,tegra114-dsi", }, |
7d1d28ac | 1158 | { .compatible = "nvidia,tegra114-hdmi", }, |
5f60ed0d | 1159 | { .compatible = "nvidia,tegra114-gr3d", }, |
8620fc62 | 1160 | { .compatible = "nvidia,tegra124-dc", }, |
6b6b6042 | 1161 | { .compatible = "nvidia,tegra124-sor", }, |
fb7be70e | 1162 | { .compatible = "nvidia,tegra124-hdmi", }, |
7d338587 | 1163 | { .compatible = "nvidia,tegra124-dsi", }, |
0ae797a8 | 1164 | { .compatible = "nvidia,tegra124-vic", }, |
c06c7930 | 1165 | { .compatible = "nvidia,tegra132-dsi", }, |
5b4f516f | 1166 | { .compatible = "nvidia,tegra210-dc", }, |
ddfb406b | 1167 | { .compatible = "nvidia,tegra210-dsi", }, |
3309ac83 | 1168 | { .compatible = "nvidia,tegra210-sor", }, |
459cc2c6 | 1169 | { .compatible = "nvidia,tegra210-sor1", }, |
0ae797a8 | 1170 | { .compatible = "nvidia,tegra210-vic", }, |
776dc384 TR |
1171 | { /* sentinel */ } |
1172 | }; | |
1173 | ||
1174 | static struct host1x_driver host1x_drm_driver = { | |
f4c5cf88 TR |
1175 | .driver = { |
1176 | .name = "drm", | |
359ae687 | 1177 | .pm = &host1x_drm_pm_ops, |
f4c5cf88 | 1178 | }, |
776dc384 TR |
1179 | .probe = host1x_drm_probe, |
1180 | .remove = host1x_drm_remove, | |
1181 | .subdevs = host1x_drm_subdevs, | |
1182 | }; | |
1183 | ||
473112e4 TR |
1184 | static struct platform_driver * const drivers[] = { |
1185 | &tegra_dc_driver, | |
1186 | &tegra_hdmi_driver, | |
1187 | &tegra_dsi_driver, | |
1188 | &tegra_dpaux_driver, | |
1189 | &tegra_sor_driver, | |
1190 | &tegra_gr2d_driver, | |
1191 | &tegra_gr3d_driver, | |
0ae797a8 | 1192 | &tegra_vic_driver, |
473112e4 TR |
1193 | }; |
1194 | ||
776dc384 TR |
1195 | static int __init host1x_drm_init(void) |
1196 | { | |
1197 | int err; | |
1198 | ||
1199 | err = host1x_driver_register(&host1x_drm_driver); | |
1200 | if (err < 0) | |
1201 | return err; | |
1202 | ||
473112e4 | 1203 | err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
776dc384 TR |
1204 | if (err < 0) |
1205 | goto unregister_host1x; | |
1206 | ||
776dc384 TR |
1207 | return 0; |
1208 | ||
776dc384 TR |
1209 | unregister_host1x: |
1210 | host1x_driver_unregister(&host1x_drm_driver); | |
1211 | return err; | |
1212 | } | |
1213 | module_init(host1x_drm_init); | |
1214 | ||
1215 | static void __exit host1x_drm_exit(void) | |
1216 | { | |
473112e4 | 1217 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
776dc384 TR |
1218 | host1x_driver_unregister(&host1x_drm_driver); |
1219 | } | |
1220 | module_exit(host1x_drm_exit); | |
1221 | ||
1222 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); | |
1223 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); | |
1224 | MODULE_LICENSE("GPL v2"); |