]>
Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
d43f81cb | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
d8f4a9ed TR |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
776dc384 | 10 | #include <linux/host1x.h> |
df06b759 | 11 | #include <linux/iommu.h> |
776dc384 | 12 | |
1503ca47 | 13 | #include <drm/drm_atomic.h> |
07866963 TR |
14 | #include <drm/drm_atomic_helper.h> |
15 | ||
d8f4a9ed | 16 | #include "drm.h" |
de2ba664 | 17 | #include "gem.h" |
d8f4a9ed TR |
18 | |
19 | #define DRIVER_NAME "tegra" | |
20 | #define DRIVER_DESC "NVIDIA Tegra graphics" | |
21 | #define DRIVER_DATE "20120330" | |
22 | #define DRIVER_MAJOR 0 | |
23 | #define DRIVER_MINOR 0 | |
24 | #define DRIVER_PATCHLEVEL 0 | |
25 | ||
08943e6c TR |
26 | struct tegra_drm_file { |
27 | struct list_head contexts; | |
28 | }; | |
29 | ||
1503ca47 TR |
30 | static void tegra_atomic_schedule(struct tegra_drm *tegra, |
31 | struct drm_atomic_state *state) | |
32 | { | |
33 | tegra->commit.state = state; | |
34 | schedule_work(&tegra->commit.work); | |
35 | } | |
36 | ||
37 | static void tegra_atomic_complete(struct tegra_drm *tegra, | |
38 | struct drm_atomic_state *state) | |
39 | { | |
40 | struct drm_device *drm = tegra->drm; | |
41 | ||
42 | /* | |
43 | * Everything below can be run asynchronously without the need to grab | |
44 | * any modeset locks at all under one condition: It must be guaranteed | |
45 | * that the asynchronous work has either been cancelled (if the driver | |
46 | * supports it, which at least requires that the framebuffers get | |
47 | * cleaned up with drm_atomic_helper_cleanup_planes()) or completed | |
48 | * before the new state gets committed on the software side with | |
49 | * drm_atomic_helper_swap_state(). | |
50 | * | |
51 | * This scheme allows new atomic state updates to be prepared and | |
52 | * checked in parallel to the asynchronous completion of the previous | |
53 | * update. Which is important since compositors need to figure out the | |
54 | * composition of the next frame right after having submitted the | |
55 | * current layout. | |
56 | */ | |
57 | ||
1af434a9 | 58 | drm_atomic_helper_commit_modeset_disables(drm, state); |
1af434a9 | 59 | drm_atomic_helper_commit_modeset_enables(drm, state); |
2b58e98d LY |
60 | drm_atomic_helper_commit_planes(drm, state, |
61 | DRM_PLANE_COMMIT_ACTIVE_ONLY); | |
1503ca47 TR |
62 | |
63 | drm_atomic_helper_wait_for_vblanks(drm, state); | |
64 | ||
65 | drm_atomic_helper_cleanup_planes(drm, state); | |
0853695c | 66 | drm_atomic_state_put(state); |
1503ca47 TR |
67 | } |
68 | ||
69 | static void tegra_atomic_work(struct work_struct *work) | |
70 | { | |
71 | struct tegra_drm *tegra = container_of(work, struct tegra_drm, | |
72 | commit.work); | |
73 | ||
74 | tegra_atomic_complete(tegra, tegra->commit.state); | |
75 | } | |
76 | ||
77 | static int tegra_atomic_commit(struct drm_device *drm, | |
2dacdd70 | 78 | struct drm_atomic_state *state, bool nonblock) |
1503ca47 TR |
79 | { |
80 | struct tegra_drm *tegra = drm->dev_private; | |
81 | int err; | |
82 | ||
83 | err = drm_atomic_helper_prepare_planes(drm, state); | |
84 | if (err) | |
85 | return err; | |
86 | ||
2dacdd70 | 87 | /* serialize outstanding nonblocking commits */ |
1503ca47 TR |
88 | mutex_lock(&tegra->commit.lock); |
89 | flush_work(&tegra->commit.work); | |
90 | ||
91 | /* | |
92 | * This is the point of no return - everything below never fails except | |
93 | * when the hw goes bonghits. Which means we can commit the new state on | |
94 | * the software side now. | |
95 | */ | |
96 | ||
5e84c269 | 97 | drm_atomic_helper_swap_state(state, true); |
1503ca47 | 98 | |
0853695c | 99 | drm_atomic_state_get(state); |
2dacdd70 | 100 | if (nonblock) |
1503ca47 TR |
101 | tegra_atomic_schedule(tegra, state); |
102 | else | |
103 | tegra_atomic_complete(tegra, state); | |
104 | ||
105 | mutex_unlock(&tegra->commit.lock); | |
106 | return 0; | |
107 | } | |
108 | ||
f9914214 TR |
109 | static const struct drm_mode_config_funcs tegra_drm_mode_funcs = { |
110 | .fb_create = tegra_fb_create, | |
b110ef37 | 111 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
f9914214 TR |
112 | .output_poll_changed = tegra_fb_output_poll_changed, |
113 | #endif | |
07866963 | 114 | .atomic_check = drm_atomic_helper_check, |
1503ca47 | 115 | .atomic_commit = tegra_atomic_commit, |
f9914214 TR |
116 | }; |
117 | ||
776dc384 | 118 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
692e6d7b | 119 | { |
776dc384 | 120 | struct host1x_device *device = to_host1x_device(drm->dev); |
386a2a71 | 121 | struct tegra_drm *tegra; |
692e6d7b TB |
122 | int err; |
123 | ||
776dc384 | 124 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
386a2a71 | 125 | if (!tegra) |
692e6d7b TB |
126 | return -ENOMEM; |
127 | ||
df06b759 | 128 | if (iommu_present(&platform_bus_type)) { |
4553f733 TR |
129 | struct iommu_domain_geometry *geometry; |
130 | u64 start, end; | |
131 | ||
df06b759 | 132 | tegra->domain = iommu_domain_alloc(&platform_bus_type); |
bf19b885 DC |
133 | if (!tegra->domain) { |
134 | err = -ENOMEM; | |
df06b759 TR |
135 | goto free; |
136 | } | |
137 | ||
4553f733 TR |
138 | geometry = &tegra->domain->geometry; |
139 | start = geometry->aperture_start; | |
140 | end = geometry->aperture_end; | |
141 | ||
d2d8c358 TR |
142 | DRM_DEBUG_DRIVER("IOMMU aperture initialized (%#llx-%#llx)\n", |
143 | start, end); | |
4553f733 | 144 | drm_mm_init(&tegra->mm, start, end - start + 1); |
df06b759 TR |
145 | } |
146 | ||
386a2a71 TR |
147 | mutex_init(&tegra->clients_lock); |
148 | INIT_LIST_HEAD(&tegra->clients); | |
1503ca47 TR |
149 | |
150 | mutex_init(&tegra->commit.lock); | |
151 | INIT_WORK(&tegra->commit.work, tegra_atomic_work); | |
152 | ||
386a2a71 TR |
153 | drm->dev_private = tegra; |
154 | tegra->drm = drm; | |
d8f4a9ed TR |
155 | |
156 | drm_mode_config_init(drm); | |
157 | ||
f9914214 TR |
158 | drm->mode_config.min_width = 0; |
159 | drm->mode_config.min_height = 0; | |
160 | ||
161 | drm->mode_config.max_width = 4096; | |
162 | drm->mode_config.max_height = 4096; | |
163 | ||
164 | drm->mode_config.funcs = &tegra_drm_mode_funcs; | |
165 | ||
e2215321 TR |
166 | err = tegra_drm_fb_prepare(drm); |
167 | if (err < 0) | |
1d1e6fe9 | 168 | goto config; |
e2215321 TR |
169 | |
170 | drm_kms_helper_poll_init(drm); | |
171 | ||
776dc384 | 172 | err = host1x_device_init(device); |
d8f4a9ed | 173 | if (err < 0) |
1d1e6fe9 | 174 | goto fbdev; |
d8f4a9ed | 175 | |
603f0cc9 TR |
176 | /* |
177 | * We don't use the drm_irq_install() helpers provided by the DRM | |
178 | * core, so we need to set this manually in order to allow the | |
179 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. | |
180 | */ | |
4423843c | 181 | drm->irq_enabled = true; |
603f0cc9 | 182 | |
42e9ce05 | 183 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
42e9ce05 TR |
184 | drm->max_vblank_count = 0xffffffff; |
185 | ||
6e5ff998 TR |
186 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
187 | if (err < 0) | |
1d1e6fe9 | 188 | goto device; |
6e5ff998 | 189 | |
31930d4d TR |
190 | drm_mode_config_reset(drm); |
191 | ||
d8f4a9ed TR |
192 | err = tegra_drm_fb_init(drm); |
193 | if (err < 0) | |
1d1e6fe9 | 194 | goto vblank; |
d8f4a9ed | 195 | |
d8f4a9ed | 196 | return 0; |
1d1e6fe9 TR |
197 | |
198 | vblank: | |
199 | drm_vblank_cleanup(drm); | |
200 | device: | |
201 | host1x_device_exit(device); | |
202 | fbdev: | |
203 | drm_kms_helper_poll_fini(drm); | |
204 | tegra_drm_fb_free(drm); | |
205 | config: | |
206 | drm_mode_config_cleanup(drm); | |
df06b759 TR |
207 | |
208 | if (tegra->domain) { | |
209 | iommu_domain_free(tegra->domain); | |
210 | drm_mm_takedown(&tegra->mm); | |
211 | } | |
212 | free: | |
1d1e6fe9 TR |
213 | kfree(tegra); |
214 | return err; | |
d8f4a9ed TR |
215 | } |
216 | ||
217 | static int tegra_drm_unload(struct drm_device *drm) | |
218 | { | |
776dc384 | 219 | struct host1x_device *device = to_host1x_device(drm->dev); |
df06b759 | 220 | struct tegra_drm *tegra = drm->dev_private; |
776dc384 TR |
221 | int err; |
222 | ||
d8f4a9ed TR |
223 | drm_kms_helper_poll_fini(drm); |
224 | tegra_drm_fb_exit(drm); | |
f002abc1 | 225 | drm_mode_config_cleanup(drm); |
4aa3df71 | 226 | drm_vblank_cleanup(drm); |
d8f4a9ed | 227 | |
776dc384 TR |
228 | err = host1x_device_exit(device); |
229 | if (err < 0) | |
230 | return err; | |
231 | ||
df06b759 TR |
232 | if (tegra->domain) { |
233 | iommu_domain_free(tegra->domain); | |
234 | drm_mm_takedown(&tegra->mm); | |
235 | } | |
236 | ||
1053f4dd TR |
237 | kfree(tegra); |
238 | ||
d8f4a9ed TR |
239 | return 0; |
240 | } | |
241 | ||
242 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) | |
243 | { | |
08943e6c | 244 | struct tegra_drm_file *fpriv; |
d43f81cb TB |
245 | |
246 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
247 | if (!fpriv) | |
248 | return -ENOMEM; | |
249 | ||
250 | INIT_LIST_HEAD(&fpriv->contexts); | |
251 | filp->driver_priv = fpriv; | |
252 | ||
d8f4a9ed TR |
253 | return 0; |
254 | } | |
255 | ||
c88c3630 | 256 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
d43f81cb TB |
257 | { |
258 | context->client->ops->close_channel(context); | |
259 | kfree(context); | |
260 | } | |
261 | ||
d8f4a9ed TR |
262 | static void tegra_drm_lastclose(struct drm_device *drm) |
263 | { | |
b110ef37 | 264 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
386a2a71 | 265 | struct tegra_drm *tegra = drm->dev_private; |
d8f4a9ed | 266 | |
386a2a71 | 267 | tegra_fbdev_restore_mode(tegra->fbdev); |
60c2f709 | 268 | #endif |
d8f4a9ed TR |
269 | } |
270 | ||
c40f0f1a | 271 | static struct host1x_bo * |
a8ad0bd8 | 272 | host1x_bo_lookup(struct drm_file *file, u32 handle) |
c40f0f1a TR |
273 | { |
274 | struct drm_gem_object *gem; | |
275 | struct tegra_bo *bo; | |
276 | ||
a8ad0bd8 | 277 | gem = drm_gem_object_lookup(file, handle); |
c40f0f1a TR |
278 | if (!gem) |
279 | return NULL; | |
280 | ||
a07cdfe5 | 281 | drm_gem_object_unreference_unlocked(gem); |
c40f0f1a TR |
282 | |
283 | bo = to_tegra_bo(gem); | |
284 | return &bo->base; | |
285 | } | |
286 | ||
961e3bea TR |
287 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
288 | struct drm_tegra_reloc __user *src, | |
289 | struct drm_device *drm, | |
290 | struct drm_file *file) | |
291 | { | |
292 | u32 cmdbuf, target; | |
293 | int err; | |
294 | ||
295 | err = get_user(cmdbuf, &src->cmdbuf.handle); | |
296 | if (err < 0) | |
297 | return err; | |
298 | ||
299 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); | |
300 | if (err < 0) | |
301 | return err; | |
302 | ||
303 | err = get_user(target, &src->target.handle); | |
304 | if (err < 0) | |
305 | return err; | |
306 | ||
31f40f86 | 307 | err = get_user(dest->target.offset, &src->target.offset); |
961e3bea TR |
308 | if (err < 0) |
309 | return err; | |
310 | ||
311 | err = get_user(dest->shift, &src->shift); | |
312 | if (err < 0) | |
313 | return err; | |
314 | ||
a8ad0bd8 | 315 | dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf); |
961e3bea TR |
316 | if (!dest->cmdbuf.bo) |
317 | return -ENOENT; | |
318 | ||
a8ad0bd8 | 319 | dest->target.bo = host1x_bo_lookup(file, target); |
961e3bea TR |
320 | if (!dest->target.bo) |
321 | return -ENOENT; | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
c40f0f1a TR |
326 | int tegra_drm_submit(struct tegra_drm_context *context, |
327 | struct drm_tegra_submit *args, struct drm_device *drm, | |
328 | struct drm_file *file) | |
329 | { | |
330 | unsigned int num_cmdbufs = args->num_cmdbufs; | |
331 | unsigned int num_relocs = args->num_relocs; | |
332 | unsigned int num_waitchks = args->num_waitchks; | |
333 | struct drm_tegra_cmdbuf __user *cmdbufs = | |
a7ed68fc | 334 | (void __user *)(uintptr_t)args->cmdbufs; |
c40f0f1a | 335 | struct drm_tegra_reloc __user *relocs = |
a7ed68fc | 336 | (void __user *)(uintptr_t)args->relocs; |
c40f0f1a | 337 | struct drm_tegra_waitchk __user *waitchks = |
a7ed68fc | 338 | (void __user *)(uintptr_t)args->waitchks; |
c40f0f1a TR |
339 | struct drm_tegra_syncpt syncpt; |
340 | struct host1x_job *job; | |
341 | int err; | |
342 | ||
343 | /* We don't yet support other than one syncpt_incr struct per submit */ | |
344 | if (args->num_syncpts != 1) | |
345 | return -EINVAL; | |
346 | ||
347 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, | |
348 | args->num_relocs, args->num_waitchks); | |
349 | if (!job) | |
350 | return -ENOMEM; | |
351 | ||
352 | job->num_relocs = args->num_relocs; | |
353 | job->num_waitchk = args->num_waitchks; | |
354 | job->client = (u32)args->context; | |
355 | job->class = context->client->base.class; | |
356 | job->serialize = true; | |
357 | ||
358 | while (num_cmdbufs) { | |
359 | struct drm_tegra_cmdbuf cmdbuf; | |
360 | struct host1x_bo *bo; | |
361 | ||
9a991600 DC |
362 | if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) { |
363 | err = -EFAULT; | |
c40f0f1a | 364 | goto fail; |
9a991600 | 365 | } |
c40f0f1a | 366 | |
a8ad0bd8 | 367 | bo = host1x_bo_lookup(file, cmdbuf.handle); |
c40f0f1a TR |
368 | if (!bo) { |
369 | err = -ENOENT; | |
370 | goto fail; | |
371 | } | |
372 | ||
373 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); | |
374 | num_cmdbufs--; | |
375 | cmdbufs++; | |
376 | } | |
377 | ||
961e3bea | 378 | /* copy and resolve relocations from submit */ |
c40f0f1a | 379 | while (num_relocs--) { |
961e3bea TR |
380 | err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs], |
381 | &relocs[num_relocs], drm, | |
382 | file); | |
383 | if (err < 0) | |
c40f0f1a | 384 | goto fail; |
c40f0f1a TR |
385 | } |
386 | ||
9a991600 DC |
387 | if (copy_from_user(job->waitchk, waitchks, |
388 | sizeof(*waitchks) * num_waitchks)) { | |
389 | err = -EFAULT; | |
c40f0f1a | 390 | goto fail; |
9a991600 | 391 | } |
c40f0f1a | 392 | |
9a991600 DC |
393 | if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts, |
394 | sizeof(syncpt))) { | |
395 | err = -EFAULT; | |
c40f0f1a | 396 | goto fail; |
9a991600 | 397 | } |
c40f0f1a TR |
398 | |
399 | job->is_addr_reg = context->client->ops->is_addr_reg; | |
400 | job->syncpt_incrs = syncpt.incrs; | |
401 | job->syncpt_id = syncpt.id; | |
402 | job->timeout = 10000; | |
403 | ||
404 | if (args->timeout && args->timeout < 10000) | |
405 | job->timeout = args->timeout; | |
406 | ||
407 | err = host1x_job_pin(job, context->client->base.dev); | |
408 | if (err) | |
409 | goto fail; | |
410 | ||
411 | err = host1x_job_submit(job); | |
412 | if (err) | |
413 | goto fail_submit; | |
414 | ||
415 | args->fence = job->syncpt_end; | |
416 | ||
417 | host1x_job_put(job); | |
418 | return 0; | |
419 | ||
420 | fail_submit: | |
421 | host1x_job_unpin(job); | |
422 | fail: | |
423 | host1x_job_put(job); | |
424 | return err; | |
425 | } | |
426 | ||
427 | ||
d43f81cb | 428 | #ifdef CONFIG_DRM_TEGRA_STAGING |
c88c3630 TR |
429 | static struct tegra_drm_context *tegra_drm_get_context(__u64 context) |
430 | { | |
431 | return (struct tegra_drm_context *)(uintptr_t)context; | |
432 | } | |
433 | ||
08943e6c | 434 | static bool tegra_drm_file_owns_context(struct tegra_drm_file *file, |
c88c3630 | 435 | struct tegra_drm_context *context) |
d43f81cb | 436 | { |
c88c3630 | 437 | struct tegra_drm_context *ctx; |
d43f81cb TB |
438 | |
439 | list_for_each_entry(ctx, &file->contexts, list) | |
440 | if (ctx == context) | |
441 | return true; | |
442 | ||
443 | return false; | |
444 | } | |
445 | ||
446 | static int tegra_gem_create(struct drm_device *drm, void *data, | |
447 | struct drm_file *file) | |
448 | { | |
449 | struct drm_tegra_gem_create *args = data; | |
450 | struct tegra_bo *bo; | |
451 | ||
773af77f | 452 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
d43f81cb TB |
453 | &args->handle); |
454 | if (IS_ERR(bo)) | |
455 | return PTR_ERR(bo); | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static int tegra_gem_mmap(struct drm_device *drm, void *data, | |
461 | struct drm_file *file) | |
462 | { | |
463 | struct drm_tegra_gem_mmap *args = data; | |
464 | struct drm_gem_object *gem; | |
465 | struct tegra_bo *bo; | |
466 | ||
a8ad0bd8 | 467 | gem = drm_gem_object_lookup(file, args->handle); |
d43f81cb TB |
468 | if (!gem) |
469 | return -EINVAL; | |
470 | ||
471 | bo = to_tegra_bo(gem); | |
472 | ||
2bc7b0ca | 473 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
d43f81cb | 474 | |
11533304 | 475 | drm_gem_object_unreference_unlocked(gem); |
d43f81cb TB |
476 | |
477 | return 0; | |
478 | } | |
479 | ||
480 | static int tegra_syncpt_read(struct drm_device *drm, void *data, | |
481 | struct drm_file *file) | |
482 | { | |
776dc384 | 483 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 484 | struct drm_tegra_syncpt_read *args = data; |
776dc384 | 485 | struct host1x_syncpt *sp; |
d43f81cb | 486 | |
776dc384 | 487 | sp = host1x_syncpt_get(host, args->id); |
d43f81cb TB |
488 | if (!sp) |
489 | return -EINVAL; | |
490 | ||
491 | args->value = host1x_syncpt_read_min(sp); | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, | |
496 | struct drm_file *file) | |
497 | { | |
776dc384 | 498 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 499 | struct drm_tegra_syncpt_incr *args = data; |
776dc384 | 500 | struct host1x_syncpt *sp; |
d43f81cb | 501 | |
776dc384 | 502 | sp = host1x_syncpt_get(host1x, args->id); |
d43f81cb TB |
503 | if (!sp) |
504 | return -EINVAL; | |
505 | ||
ebae30b1 | 506 | return host1x_syncpt_incr(sp); |
d43f81cb TB |
507 | } |
508 | ||
509 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, | |
510 | struct drm_file *file) | |
511 | { | |
776dc384 | 512 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 513 | struct drm_tegra_syncpt_wait *args = data; |
776dc384 | 514 | struct host1x_syncpt *sp; |
d43f81cb | 515 | |
776dc384 | 516 | sp = host1x_syncpt_get(host1x, args->id); |
d43f81cb TB |
517 | if (!sp) |
518 | return -EINVAL; | |
519 | ||
520 | return host1x_syncpt_wait(sp, args->thresh, args->timeout, | |
521 | &args->value); | |
522 | } | |
523 | ||
524 | static int tegra_open_channel(struct drm_device *drm, void *data, | |
525 | struct drm_file *file) | |
526 | { | |
08943e6c | 527 | struct tegra_drm_file *fpriv = file->driver_priv; |
386a2a71 | 528 | struct tegra_drm *tegra = drm->dev_private; |
d43f81cb | 529 | struct drm_tegra_open_channel *args = data; |
c88c3630 | 530 | struct tegra_drm_context *context; |
53fa7f72 | 531 | struct tegra_drm_client *client; |
d43f81cb TB |
532 | int err = -ENODEV; |
533 | ||
534 | context = kzalloc(sizeof(*context), GFP_KERNEL); | |
535 | if (!context) | |
536 | return -ENOMEM; | |
537 | ||
776dc384 | 538 | list_for_each_entry(client, &tegra->clients, list) |
53fa7f72 | 539 | if (client->base.class == args->client) { |
d43f81cb TB |
540 | err = client->ops->open_channel(client, context); |
541 | if (err) | |
542 | break; | |
543 | ||
d43f81cb TB |
544 | list_add(&context->list, &fpriv->contexts); |
545 | args->context = (uintptr_t)context; | |
53fa7f72 | 546 | context->client = client; |
d43f81cb TB |
547 | return 0; |
548 | } | |
549 | ||
550 | kfree(context); | |
551 | return err; | |
552 | } | |
553 | ||
554 | static int tegra_close_channel(struct drm_device *drm, void *data, | |
555 | struct drm_file *file) | |
556 | { | |
08943e6c | 557 | struct tegra_drm_file *fpriv = file->driver_priv; |
776dc384 | 558 | struct drm_tegra_close_channel *args = data; |
c88c3630 TR |
559 | struct tegra_drm_context *context; |
560 | ||
561 | context = tegra_drm_get_context(args->context); | |
d43f81cb | 562 | |
08943e6c | 563 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
564 | return -EINVAL; |
565 | ||
566 | list_del(&context->list); | |
c88c3630 | 567 | tegra_drm_context_free(context); |
d43f81cb TB |
568 | |
569 | return 0; | |
570 | } | |
571 | ||
572 | static int tegra_get_syncpt(struct drm_device *drm, void *data, | |
573 | struct drm_file *file) | |
574 | { | |
08943e6c | 575 | struct tegra_drm_file *fpriv = file->driver_priv; |
d43f81cb | 576 | struct drm_tegra_get_syncpt *args = data; |
c88c3630 | 577 | struct tegra_drm_context *context; |
d43f81cb TB |
578 | struct host1x_syncpt *syncpt; |
579 | ||
c88c3630 TR |
580 | context = tegra_drm_get_context(args->context); |
581 | ||
08943e6c | 582 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
583 | return -ENODEV; |
584 | ||
53fa7f72 | 585 | if (args->index >= context->client->base.num_syncpts) |
d43f81cb TB |
586 | return -EINVAL; |
587 | ||
53fa7f72 | 588 | syncpt = context->client->base.syncpts[args->index]; |
d43f81cb TB |
589 | args->id = host1x_syncpt_id(syncpt); |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
594 | static int tegra_submit(struct drm_device *drm, void *data, | |
595 | struct drm_file *file) | |
596 | { | |
08943e6c | 597 | struct tegra_drm_file *fpriv = file->driver_priv; |
d43f81cb | 598 | struct drm_tegra_submit *args = data; |
c88c3630 TR |
599 | struct tegra_drm_context *context; |
600 | ||
601 | context = tegra_drm_get_context(args->context); | |
d43f81cb | 602 | |
08943e6c | 603 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
604 | return -ENODEV; |
605 | ||
606 | return context->client->ops->submit(context, args, drm, file); | |
607 | } | |
c54a169b AM |
608 | |
609 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, | |
610 | struct drm_file *file) | |
611 | { | |
612 | struct tegra_drm_file *fpriv = file->driver_priv; | |
613 | struct drm_tegra_get_syncpt_base *args = data; | |
614 | struct tegra_drm_context *context; | |
615 | struct host1x_syncpt_base *base; | |
616 | struct host1x_syncpt *syncpt; | |
617 | ||
618 | context = tegra_drm_get_context(args->context); | |
619 | ||
620 | if (!tegra_drm_file_owns_context(fpriv, context)) | |
621 | return -ENODEV; | |
622 | ||
623 | if (args->syncpt >= context->client->base.num_syncpts) | |
624 | return -EINVAL; | |
625 | ||
626 | syncpt = context->client->base.syncpts[args->syncpt]; | |
627 | ||
628 | base = host1x_syncpt_get_base(syncpt); | |
629 | if (!base) | |
630 | return -ENXIO; | |
631 | ||
632 | args->id = host1x_syncpt_base_id(base); | |
633 | ||
634 | return 0; | |
635 | } | |
7678d71f TR |
636 | |
637 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, | |
638 | struct drm_file *file) | |
639 | { | |
640 | struct drm_tegra_gem_set_tiling *args = data; | |
641 | enum tegra_bo_tiling_mode mode; | |
642 | struct drm_gem_object *gem; | |
643 | unsigned long value = 0; | |
644 | struct tegra_bo *bo; | |
645 | ||
646 | switch (args->mode) { | |
647 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: | |
648 | mode = TEGRA_BO_TILING_MODE_PITCH; | |
649 | ||
650 | if (args->value != 0) | |
651 | return -EINVAL; | |
652 | ||
653 | break; | |
654 | ||
655 | case DRM_TEGRA_GEM_TILING_MODE_TILED: | |
656 | mode = TEGRA_BO_TILING_MODE_TILED; | |
657 | ||
658 | if (args->value != 0) | |
659 | return -EINVAL; | |
660 | ||
661 | break; | |
662 | ||
663 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: | |
664 | mode = TEGRA_BO_TILING_MODE_BLOCK; | |
665 | ||
666 | if (args->value > 5) | |
667 | return -EINVAL; | |
668 | ||
669 | value = args->value; | |
670 | break; | |
671 | ||
672 | default: | |
673 | return -EINVAL; | |
674 | } | |
675 | ||
a8ad0bd8 | 676 | gem = drm_gem_object_lookup(file, args->handle); |
7678d71f TR |
677 | if (!gem) |
678 | return -ENOENT; | |
679 | ||
680 | bo = to_tegra_bo(gem); | |
681 | ||
682 | bo->tiling.mode = mode; | |
683 | bo->tiling.value = value; | |
684 | ||
11533304 | 685 | drm_gem_object_unreference_unlocked(gem); |
7678d71f TR |
686 | |
687 | return 0; | |
688 | } | |
689 | ||
690 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, | |
691 | struct drm_file *file) | |
692 | { | |
693 | struct drm_tegra_gem_get_tiling *args = data; | |
694 | struct drm_gem_object *gem; | |
695 | struct tegra_bo *bo; | |
696 | int err = 0; | |
697 | ||
a8ad0bd8 | 698 | gem = drm_gem_object_lookup(file, args->handle); |
7678d71f TR |
699 | if (!gem) |
700 | return -ENOENT; | |
701 | ||
702 | bo = to_tegra_bo(gem); | |
703 | ||
704 | switch (bo->tiling.mode) { | |
705 | case TEGRA_BO_TILING_MODE_PITCH: | |
706 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; | |
707 | args->value = 0; | |
708 | break; | |
709 | ||
710 | case TEGRA_BO_TILING_MODE_TILED: | |
711 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; | |
712 | args->value = 0; | |
713 | break; | |
714 | ||
715 | case TEGRA_BO_TILING_MODE_BLOCK: | |
716 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; | |
717 | args->value = bo->tiling.value; | |
718 | break; | |
719 | ||
720 | default: | |
721 | err = -EINVAL; | |
722 | break; | |
723 | } | |
724 | ||
11533304 | 725 | drm_gem_object_unreference_unlocked(gem); |
7678d71f TR |
726 | |
727 | return err; | |
728 | } | |
7b129087 TR |
729 | |
730 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, | |
731 | struct drm_file *file) | |
732 | { | |
733 | struct drm_tegra_gem_set_flags *args = data; | |
734 | struct drm_gem_object *gem; | |
735 | struct tegra_bo *bo; | |
736 | ||
737 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) | |
738 | return -EINVAL; | |
739 | ||
a8ad0bd8 | 740 | gem = drm_gem_object_lookup(file, args->handle); |
7b129087 TR |
741 | if (!gem) |
742 | return -ENOENT; | |
743 | ||
744 | bo = to_tegra_bo(gem); | |
745 | bo->flags = 0; | |
746 | ||
747 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) | |
748 | bo->flags |= TEGRA_BO_BOTTOM_UP; | |
749 | ||
11533304 | 750 | drm_gem_object_unreference_unlocked(gem); |
7b129087 TR |
751 | |
752 | return 0; | |
753 | } | |
754 | ||
755 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, | |
756 | struct drm_file *file) | |
757 | { | |
758 | struct drm_tegra_gem_get_flags *args = data; | |
759 | struct drm_gem_object *gem; | |
760 | struct tegra_bo *bo; | |
761 | ||
a8ad0bd8 | 762 | gem = drm_gem_object_lookup(file, args->handle); |
7b129087 TR |
763 | if (!gem) |
764 | return -ENOENT; | |
765 | ||
766 | bo = to_tegra_bo(gem); | |
767 | args->flags = 0; | |
768 | ||
769 | if (bo->flags & TEGRA_BO_BOTTOM_UP) | |
770 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; | |
771 | ||
11533304 | 772 | drm_gem_object_unreference_unlocked(gem); |
7b129087 TR |
773 | |
774 | return 0; | |
775 | } | |
d43f81cb TB |
776 | #endif |
777 | ||
baa70943 | 778 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
d43f81cb | 779 | #ifdef CONFIG_DRM_TEGRA_STAGING |
f8c47144 DV |
780 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0), |
781 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0), | |
782 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0), | |
783 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0), | |
784 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0), | |
785 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0), | |
786 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0), | |
787 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0), | |
788 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0), | |
789 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0), | |
790 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0), | |
791 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0), | |
792 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0), | |
793 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0), | |
d43f81cb | 794 | #endif |
d8f4a9ed TR |
795 | }; |
796 | ||
797 | static const struct file_operations tegra_drm_fops = { | |
798 | .owner = THIS_MODULE, | |
799 | .open = drm_open, | |
800 | .release = drm_release, | |
801 | .unlocked_ioctl = drm_ioctl, | |
de2ba664 | 802 | .mmap = tegra_drm_mmap, |
d8f4a9ed | 803 | .poll = drm_poll, |
d8f4a9ed | 804 | .read = drm_read, |
d8f4a9ed | 805 | .compat_ioctl = drm_compat_ioctl, |
d8f4a9ed TR |
806 | .llseek = noop_llseek, |
807 | }; | |
808 | ||
ed7dae58 TR |
809 | static struct drm_crtc *tegra_crtc_from_pipe(struct drm_device *drm, |
810 | unsigned int pipe) | |
6e5ff998 TR |
811 | { |
812 | struct drm_crtc *crtc; | |
813 | ||
814 | list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) { | |
ed7dae58 | 815 | if (pipe == drm_crtc_index(crtc)) |
6e5ff998 TR |
816 | return crtc; |
817 | } | |
818 | ||
819 | return NULL; | |
820 | } | |
821 | ||
88e72717 TR |
822 | static u32 tegra_drm_get_vblank_counter(struct drm_device *drm, |
823 | unsigned int pipe) | |
6e5ff998 | 824 | { |
ed7dae58 | 825 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); |
42e9ce05 | 826 | struct tegra_dc *dc = to_tegra_dc(crtc); |
ed7dae58 TR |
827 | |
828 | if (!crtc) | |
829 | return 0; | |
830 | ||
42e9ce05 | 831 | return tegra_dc_get_vblank_counter(dc); |
6e5ff998 TR |
832 | } |
833 | ||
88e72717 | 834 | static int tegra_drm_enable_vblank(struct drm_device *drm, unsigned int pipe) |
6e5ff998 TR |
835 | { |
836 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); | |
837 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
838 | ||
839 | if (!crtc) | |
840 | return -ENODEV; | |
841 | ||
842 | tegra_dc_enable_vblank(dc); | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
88e72717 | 847 | static void tegra_drm_disable_vblank(struct drm_device *drm, unsigned int pipe) |
6e5ff998 TR |
848 | { |
849 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); | |
850 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
851 | ||
852 | if (crtc) | |
853 | tegra_dc_disable_vblank(dc); | |
854 | } | |
855 | ||
3c03c46a TR |
856 | static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file) |
857 | { | |
08943e6c | 858 | struct tegra_drm_file *fpriv = file->driver_priv; |
c88c3630 | 859 | struct tegra_drm_context *context, *tmp; |
3c03c46a | 860 | |
d43f81cb | 861 | list_for_each_entry_safe(context, tmp, &fpriv->contexts, list) |
c88c3630 | 862 | tegra_drm_context_free(context); |
d43f81cb TB |
863 | |
864 | kfree(fpriv); | |
3c03c46a TR |
865 | } |
866 | ||
e450fcc6 TR |
867 | #ifdef CONFIG_DEBUG_FS |
868 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) | |
869 | { | |
870 | struct drm_info_node *node = (struct drm_info_node *)s->private; | |
871 | struct drm_device *drm = node->minor->dev; | |
872 | struct drm_framebuffer *fb; | |
873 | ||
874 | mutex_lock(&drm->mode_config.fb_lock); | |
875 | ||
876 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { | |
877 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", | |
878 | fb->base.id, fb->width, fb->height, fb->depth, | |
879 | fb->bits_per_pixel, | |
747a598f | 880 | drm_framebuffer_read_refcount(fb)); |
e450fcc6 TR |
881 | } |
882 | ||
883 | mutex_unlock(&drm->mode_config.fb_lock); | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
28c23373 TR |
888 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
889 | { | |
890 | struct drm_info_node *node = (struct drm_info_node *)s->private; | |
891 | struct drm_device *drm = node->minor->dev; | |
892 | struct tegra_drm *tegra = drm->dev_private; | |
893 | ||
894 | return drm_mm_dump_table(s, &tegra->mm); | |
895 | } | |
896 | ||
e450fcc6 TR |
897 | static struct drm_info_list tegra_debugfs_list[] = { |
898 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, | |
28c23373 | 899 | { "iova", tegra_debugfs_iova, 0 }, |
e450fcc6 TR |
900 | }; |
901 | ||
902 | static int tegra_debugfs_init(struct drm_minor *minor) | |
903 | { | |
904 | return drm_debugfs_create_files(tegra_debugfs_list, | |
905 | ARRAY_SIZE(tegra_debugfs_list), | |
906 | minor->debugfs_root, minor); | |
907 | } | |
908 | ||
909 | static void tegra_debugfs_cleanup(struct drm_minor *minor) | |
910 | { | |
911 | drm_debugfs_remove_files(tegra_debugfs_list, | |
912 | ARRAY_SIZE(tegra_debugfs_list), minor); | |
913 | } | |
914 | #endif | |
915 | ||
9b57f5f2 | 916 | static struct drm_driver tegra_drm_driver = { |
ad906599 TR |
917 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | |
918 | DRIVER_ATOMIC, | |
d8f4a9ed TR |
919 | .load = tegra_drm_load, |
920 | .unload = tegra_drm_unload, | |
921 | .open = tegra_drm_open, | |
3c03c46a | 922 | .preclose = tegra_drm_preclose, |
d8f4a9ed TR |
923 | .lastclose = tegra_drm_lastclose, |
924 | ||
6e5ff998 TR |
925 | .get_vblank_counter = tegra_drm_get_vblank_counter, |
926 | .enable_vblank = tegra_drm_enable_vblank, | |
927 | .disable_vblank = tegra_drm_disable_vblank, | |
928 | ||
e450fcc6 TR |
929 | #if defined(CONFIG_DEBUG_FS) |
930 | .debugfs_init = tegra_debugfs_init, | |
931 | .debugfs_cleanup = tegra_debugfs_cleanup, | |
932 | #endif | |
933 | ||
1ddbdbd6 | 934 | .gem_free_object_unlocked = tegra_bo_free_object, |
de2ba664 | 935 | .gem_vm_ops = &tegra_bo_vm_ops, |
3800391d TR |
936 | |
937 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
938 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
939 | .gem_prime_export = tegra_gem_prime_export, | |
940 | .gem_prime_import = tegra_gem_prime_import, | |
941 | ||
de2ba664 AM |
942 | .dumb_create = tegra_bo_dumb_create, |
943 | .dumb_map_offset = tegra_bo_dumb_map_offset, | |
43387b37 | 944 | .dumb_destroy = drm_gem_dumb_destroy, |
d8f4a9ed TR |
945 | |
946 | .ioctls = tegra_drm_ioctls, | |
947 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), | |
948 | .fops = &tegra_drm_fops, | |
949 | ||
950 | .name = DRIVER_NAME, | |
951 | .desc = DRIVER_DESC, | |
952 | .date = DRIVER_DATE, | |
953 | .major = DRIVER_MAJOR, | |
954 | .minor = DRIVER_MINOR, | |
955 | .patchlevel = DRIVER_PATCHLEVEL, | |
956 | }; | |
776dc384 TR |
957 | |
958 | int tegra_drm_register_client(struct tegra_drm *tegra, | |
959 | struct tegra_drm_client *client) | |
960 | { | |
961 | mutex_lock(&tegra->clients_lock); | |
962 | list_add_tail(&client->list, &tegra->clients); | |
963 | mutex_unlock(&tegra->clients_lock); | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
968 | int tegra_drm_unregister_client(struct tegra_drm *tegra, | |
969 | struct tegra_drm_client *client) | |
970 | { | |
971 | mutex_lock(&tegra->clients_lock); | |
972 | list_del_init(&client->list); | |
973 | mutex_unlock(&tegra->clients_lock); | |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
9910f5c4 | 978 | static int host1x_drm_probe(struct host1x_device *dev) |
776dc384 | 979 | { |
9910f5c4 TR |
980 | struct drm_driver *driver = &tegra_drm_driver; |
981 | struct drm_device *drm; | |
982 | int err; | |
983 | ||
984 | drm = drm_dev_alloc(driver, &dev->dev); | |
0f288605 TG |
985 | if (IS_ERR(drm)) |
986 | return PTR_ERR(drm); | |
9910f5c4 | 987 | |
9910f5c4 TR |
988 | dev_set_drvdata(&dev->dev, drm); |
989 | ||
990 | err = drm_dev_register(drm, 0); | |
991 | if (err < 0) | |
992 | goto unref; | |
993 | ||
994 | DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name, | |
995 | driver->major, driver->minor, driver->patchlevel, | |
996 | driver->date, drm->primary->index); | |
997 | ||
998 | return 0; | |
999 | ||
1000 | unref: | |
1001 | drm_dev_unref(drm); | |
1002 | return err; | |
776dc384 TR |
1003 | } |
1004 | ||
9910f5c4 | 1005 | static int host1x_drm_remove(struct host1x_device *dev) |
776dc384 | 1006 | { |
9910f5c4 TR |
1007 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
1008 | ||
1009 | drm_dev_unregister(drm); | |
1010 | drm_dev_unref(drm); | |
776dc384 TR |
1011 | |
1012 | return 0; | |
1013 | } | |
1014 | ||
359ae687 TR |
1015 | #ifdef CONFIG_PM_SLEEP |
1016 | static int host1x_drm_suspend(struct device *dev) | |
1017 | { | |
1018 | struct drm_device *drm = dev_get_drvdata(dev); | |
986c58d1 | 1019 | struct tegra_drm *tegra = drm->dev_private; |
359ae687 TR |
1020 | |
1021 | drm_kms_helper_poll_disable(drm); | |
986c58d1 TR |
1022 | tegra_drm_fb_suspend(drm); |
1023 | ||
1024 | tegra->state = drm_atomic_helper_suspend(drm); | |
1025 | if (IS_ERR(tegra->state)) { | |
1026 | tegra_drm_fb_resume(drm); | |
1027 | drm_kms_helper_poll_enable(drm); | |
1028 | return PTR_ERR(tegra->state); | |
1029 | } | |
359ae687 TR |
1030 | |
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | static int host1x_drm_resume(struct device *dev) | |
1035 | { | |
1036 | struct drm_device *drm = dev_get_drvdata(dev); | |
986c58d1 | 1037 | struct tegra_drm *tegra = drm->dev_private; |
359ae687 | 1038 | |
986c58d1 TR |
1039 | drm_atomic_helper_resume(drm, tegra->state); |
1040 | tegra_drm_fb_resume(drm); | |
359ae687 TR |
1041 | drm_kms_helper_poll_enable(drm); |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | #endif | |
1046 | ||
a13f1dc4 TR |
1047 | static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, |
1048 | host1x_drm_resume); | |
359ae687 | 1049 | |
776dc384 TR |
1050 | static const struct of_device_id host1x_drm_subdevs[] = { |
1051 | { .compatible = "nvidia,tegra20-dc", }, | |
1052 | { .compatible = "nvidia,tegra20-hdmi", }, | |
1053 | { .compatible = "nvidia,tegra20-gr2d", }, | |
5f60ed0d | 1054 | { .compatible = "nvidia,tegra20-gr3d", }, |
776dc384 TR |
1055 | { .compatible = "nvidia,tegra30-dc", }, |
1056 | { .compatible = "nvidia,tegra30-hdmi", }, | |
1057 | { .compatible = "nvidia,tegra30-gr2d", }, | |
5f60ed0d | 1058 | { .compatible = "nvidia,tegra30-gr3d", }, |
dec72739 | 1059 | { .compatible = "nvidia,tegra114-dsi", }, |
7d1d28ac | 1060 | { .compatible = "nvidia,tegra114-hdmi", }, |
5f60ed0d | 1061 | { .compatible = "nvidia,tegra114-gr3d", }, |
8620fc62 | 1062 | { .compatible = "nvidia,tegra124-dc", }, |
6b6b6042 | 1063 | { .compatible = "nvidia,tegra124-sor", }, |
fb7be70e | 1064 | { .compatible = "nvidia,tegra124-hdmi", }, |
7d338587 | 1065 | { .compatible = "nvidia,tegra124-dsi", }, |
c06c7930 | 1066 | { .compatible = "nvidia,tegra132-dsi", }, |
5b4f516f | 1067 | { .compatible = "nvidia,tegra210-dc", }, |
ddfb406b | 1068 | { .compatible = "nvidia,tegra210-dsi", }, |
3309ac83 | 1069 | { .compatible = "nvidia,tegra210-sor", }, |
459cc2c6 | 1070 | { .compatible = "nvidia,tegra210-sor1", }, |
776dc384 TR |
1071 | { /* sentinel */ } |
1072 | }; | |
1073 | ||
1074 | static struct host1x_driver host1x_drm_driver = { | |
f4c5cf88 TR |
1075 | .driver = { |
1076 | .name = "drm", | |
359ae687 | 1077 | .pm = &host1x_drm_pm_ops, |
f4c5cf88 | 1078 | }, |
776dc384 TR |
1079 | .probe = host1x_drm_probe, |
1080 | .remove = host1x_drm_remove, | |
1081 | .subdevs = host1x_drm_subdevs, | |
1082 | }; | |
1083 | ||
473112e4 TR |
1084 | static struct platform_driver * const drivers[] = { |
1085 | &tegra_dc_driver, | |
1086 | &tegra_hdmi_driver, | |
1087 | &tegra_dsi_driver, | |
1088 | &tegra_dpaux_driver, | |
1089 | &tegra_sor_driver, | |
1090 | &tegra_gr2d_driver, | |
1091 | &tegra_gr3d_driver, | |
1092 | }; | |
1093 | ||
776dc384 TR |
1094 | static int __init host1x_drm_init(void) |
1095 | { | |
1096 | int err; | |
1097 | ||
1098 | err = host1x_driver_register(&host1x_drm_driver); | |
1099 | if (err < 0) | |
1100 | return err; | |
1101 | ||
473112e4 | 1102 | err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
776dc384 TR |
1103 | if (err < 0) |
1104 | goto unregister_host1x; | |
1105 | ||
776dc384 TR |
1106 | return 0; |
1107 | ||
776dc384 TR |
1108 | unregister_host1x: |
1109 | host1x_driver_unregister(&host1x_drm_driver); | |
1110 | return err; | |
1111 | } | |
1112 | module_init(host1x_drm_init); | |
1113 | ||
1114 | static void __exit host1x_drm_exit(void) | |
1115 | { | |
473112e4 | 1116 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
776dc384 TR |
1117 | host1x_driver_unregister(&host1x_drm_driver); |
1118 | } | |
1119 | module_exit(host1x_drm_exit); | |
1120 | ||
1121 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); | |
1122 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); | |
1123 | MODULE_LICENSE("GPL v2"); |