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drm/tegra: dpaux: Add Tegra194 support
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CommitLineData
d8f4a9ed
TR
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
ad926015 3 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
d8f4a9ed
TR
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
ad926015 10#include <linux/bitops.h>
776dc384 11#include <linux/host1x.h>
bdd2f9cd 12#include <linux/idr.h>
df06b759 13#include <linux/iommu.h>
776dc384 14
1503ca47 15#include <drm/drm_atomic.h>
07866963
TR
16#include <drm/drm_atomic_helper.h>
17
d8f4a9ed 18#include "drm.h"
de2ba664 19#include "gem.h"
d8f4a9ed
TR
20
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
ad926015 28#define CARVEOUT_SZ SZ_64M
368f622c 29#define CDMA_GATHER_FETCHES_MAX_NB 16383
ad926015 30
08943e6c 31struct tegra_drm_file {
bdd2f9cd
TR
32 struct idr contexts;
33 struct mutex lock;
08943e6c
TR
34};
35
ab7d3f58
TR
36static int tegra_atomic_check(struct drm_device *drm,
37 struct drm_atomic_state *state)
1503ca47 38{
ab7d3f58 39 int err;
1503ca47 40
a18301b9 41 err = drm_atomic_helper_check(drm, state);
ab7d3f58
TR
42 if (err < 0)
43 return err;
1503ca47 44
a18301b9 45 return tegra_display_hub_atomic_check(drm, state);
1503ca47
TR
46}
47
31b02cae 48static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
f9914214 49 .fb_create = tegra_fb_create,
b110ef37 50#ifdef CONFIG_DRM_FBDEV_EMULATION
c94bedab 51 .output_poll_changed = drm_fb_helper_output_poll_changed,
f9914214 52#endif
ab7d3f58 53 .atomic_check = tegra_atomic_check,
31b02cae
TR
54 .atomic_commit = drm_atomic_helper_commit,
55};
56
c4755fb9
TR
57static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
58{
59 struct drm_device *drm = old_state->dev;
60 struct tegra_drm *tegra = drm->dev_private;
61
62 if (tegra->hub) {
63 drm_atomic_helper_commit_modeset_disables(drm, old_state);
64 tegra_display_hub_atomic_commit(drm, old_state);
65 drm_atomic_helper_commit_planes(drm, old_state, 0);
66 drm_atomic_helper_commit_modeset_enables(drm, old_state);
67 drm_atomic_helper_commit_hw_done(old_state);
68 drm_atomic_helper_wait_for_vblanks(drm, old_state);
69 drm_atomic_helper_cleanup_planes(drm, old_state);
70 } else {
71 drm_atomic_helper_commit_tail_rpm(old_state);
72 }
73}
74
31b02cae
TR
75static const struct drm_mode_config_helper_funcs
76tegra_drm_mode_config_helpers = {
c4755fb9 77 .atomic_commit_tail = tegra_atomic_commit_tail,
f9914214
TR
78};
79
776dc384 80static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
692e6d7b 81{
776dc384 82 struct host1x_device *device = to_host1x_device(drm->dev);
386a2a71 83 struct tegra_drm *tegra;
692e6d7b
TB
84 int err;
85
776dc384 86 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
386a2a71 87 if (!tegra)
692e6d7b
TB
88 return -ENOMEM;
89
df06b759 90 if (iommu_present(&platform_bus_type)) {
ad926015 91 u64 carveout_start, carveout_end, gem_start, gem_end;
4553f733 92 struct iommu_domain_geometry *geometry;
ad926015 93 unsigned long order;
4553f733 94
df06b759 95 tegra->domain = iommu_domain_alloc(&platform_bus_type);
bf19b885
DC
96 if (!tegra->domain) {
97 err = -ENOMEM;
df06b759
TR
98 goto free;
99 }
100
24cfdc1a
TR
101 err = iova_cache_get();
102 if (err < 0)
103 goto domain;
104
4553f733 105 geometry = &tegra->domain->geometry;
ad926015
MP
106 gem_start = geometry->aperture_start;
107 gem_end = geometry->aperture_end - CARVEOUT_SZ;
108 carveout_start = gem_end + 1;
109 carveout_end = geometry->aperture_end;
110
111 order = __ffs(tegra->domain->pgsize_bitmap);
112 init_iova_domain(&tegra->carveout.domain, 1UL << order,
aa3ac946 113 carveout_start >> order);
4553f733 114
ad926015
MP
115 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
116 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
117
118 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
347ad49d 119 mutex_init(&tegra->mm_lock);
ad926015
MP
120
121 DRM_DEBUG("IOMMU apertures:\n");
122 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
123 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
124 carveout_end);
df06b759
TR
125 }
126
386a2a71
TR
127 mutex_init(&tegra->clients_lock);
128 INIT_LIST_HEAD(&tegra->clients);
1503ca47 129
386a2a71
TR
130 drm->dev_private = tegra;
131 tegra->drm = drm;
d8f4a9ed
TR
132
133 drm_mode_config_init(drm);
134
f9914214
TR
135 drm->mode_config.min_width = 0;
136 drm->mode_config.min_height = 0;
137
138 drm->mode_config.max_width = 4096;
139 drm->mode_config.max_height = 4096;
140
5e91144d
AC
141 drm->mode_config.allow_fb_modifiers = true;
142
a18301b9
PU
143 drm->mode_config.normalize_zpos = true;
144
31b02cae
TR
145 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
146 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
f9914214 147
e2215321
TR
148 err = tegra_drm_fb_prepare(drm);
149 if (err < 0)
1d1e6fe9 150 goto config;
e2215321
TR
151
152 drm_kms_helper_poll_init(drm);
153
776dc384 154 err = host1x_device_init(device);
d8f4a9ed 155 if (err < 0)
1d1e6fe9 156 goto fbdev;
d8f4a9ed 157
c4755fb9
TR
158 if (tegra->hub) {
159 err = tegra_display_hub_prepare(tegra->hub);
160 if (err < 0)
161 goto device;
162 }
163
603f0cc9
TR
164 /*
165 * We don't use the drm_irq_install() helpers provided by the DRM
166 * core, so we need to set this manually in order to allow the
167 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
168 */
4423843c 169 drm->irq_enabled = true;
603f0cc9 170
42e9ce05 171 /* syncpoints are used for full 32-bit hardware VBLANK counters */
42e9ce05
TR
172 drm->max_vblank_count = 0xffffffff;
173
6e5ff998
TR
174 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
175 if (err < 0)
c4755fb9 176 goto hub;
6e5ff998 177
31930d4d
TR
178 drm_mode_config_reset(drm);
179
d8f4a9ed
TR
180 err = tegra_drm_fb_init(drm);
181 if (err < 0)
c4755fb9 182 goto hub;
d8f4a9ed 183
d8f4a9ed 184 return 0;
1d1e6fe9 185
c4755fb9
TR
186hub:
187 if (tegra->hub)
188 tegra_display_hub_cleanup(tegra->hub);
1d1e6fe9
TR
189device:
190 host1x_device_exit(device);
191fbdev:
192 drm_kms_helper_poll_fini(drm);
193 tegra_drm_fb_free(drm);
194config:
195 drm_mode_config_cleanup(drm);
df06b759
TR
196
197 if (tegra->domain) {
347ad49d 198 mutex_destroy(&tegra->mm_lock);
5f43ac8d 199 drm_mm_takedown(&tegra->mm);
ad926015 200 put_iova_domain(&tegra->carveout.domain);
24cfdc1a 201 iova_cache_put();
df06b759 202 }
24cfdc1a
TR
203domain:
204 if (tegra->domain)
205 iommu_domain_free(tegra->domain);
df06b759 206free:
1d1e6fe9
TR
207 kfree(tegra);
208 return err;
d8f4a9ed
TR
209}
210
11b3c20b 211static void tegra_drm_unload(struct drm_device *drm)
d8f4a9ed 212{
776dc384 213 struct host1x_device *device = to_host1x_device(drm->dev);
df06b759 214 struct tegra_drm *tegra = drm->dev_private;
776dc384
TR
215 int err;
216
d8f4a9ed
TR
217 drm_kms_helper_poll_fini(drm);
218 tegra_drm_fb_exit(drm);
192b4af6 219 drm_atomic_helper_shutdown(drm);
f002abc1 220 drm_mode_config_cleanup(drm);
d8f4a9ed 221
776dc384
TR
222 err = host1x_device_exit(device);
223 if (err < 0)
11b3c20b 224 return;
776dc384 225
df06b759 226 if (tegra->domain) {
347ad49d 227 mutex_destroy(&tegra->mm_lock);
5f43ac8d 228 drm_mm_takedown(&tegra->mm);
ad926015 229 put_iova_domain(&tegra->carveout.domain);
24cfdc1a 230 iova_cache_put();
5f43ac8d 231 iommu_domain_free(tegra->domain);
df06b759
TR
232 }
233
1053f4dd 234 kfree(tegra);
d8f4a9ed
TR
235}
236
237static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
238{
08943e6c 239 struct tegra_drm_file *fpriv;
d43f81cb
TB
240
241 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
242 if (!fpriv)
243 return -ENOMEM;
244
bdd2f9cd
TR
245 idr_init(&fpriv->contexts);
246 mutex_init(&fpriv->lock);
d43f81cb
TB
247 filp->driver_priv = fpriv;
248
d8f4a9ed
TR
249 return 0;
250}
251
c88c3630 252static void tegra_drm_context_free(struct tegra_drm_context *context)
d43f81cb
TB
253{
254 context->client->ops->close_channel(context);
255 kfree(context);
256}
257
c40f0f1a 258static struct host1x_bo *
a8ad0bd8 259host1x_bo_lookup(struct drm_file *file, u32 handle)
c40f0f1a
TR
260{
261 struct drm_gem_object *gem;
262 struct tegra_bo *bo;
263
a8ad0bd8 264 gem = drm_gem_object_lookup(file, handle);
c40f0f1a
TR
265 if (!gem)
266 return NULL;
267
c40f0f1a
TR
268 bo = to_tegra_bo(gem);
269 return &bo->base;
270}
271
961e3bea
TR
272static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
273 struct drm_tegra_reloc __user *src,
274 struct drm_device *drm,
275 struct drm_file *file)
276{
277 u32 cmdbuf, target;
278 int err;
279
280 err = get_user(cmdbuf, &src->cmdbuf.handle);
281 if (err < 0)
282 return err;
283
284 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
285 if (err < 0)
286 return err;
287
288 err = get_user(target, &src->target.handle);
289 if (err < 0)
290 return err;
291
31f40f86 292 err = get_user(dest->target.offset, &src->target.offset);
961e3bea
TR
293 if (err < 0)
294 return err;
295
296 err = get_user(dest->shift, &src->shift);
297 if (err < 0)
298 return err;
299
a8ad0bd8 300 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
961e3bea
TR
301 if (!dest->cmdbuf.bo)
302 return -ENOENT;
303
a8ad0bd8 304 dest->target.bo = host1x_bo_lookup(file, target);
961e3bea
TR
305 if (!dest->target.bo)
306 return -ENOENT;
307
308 return 0;
309}
310
c40f0f1a
TR
311int tegra_drm_submit(struct tegra_drm_context *context,
312 struct drm_tegra_submit *args, struct drm_device *drm,
313 struct drm_file *file)
314{
bf3d41cc 315 struct host1x_client *client = &context->client->base;
c40f0f1a
TR
316 unsigned int num_cmdbufs = args->num_cmdbufs;
317 unsigned int num_relocs = args->num_relocs;
a176c67d
MP
318 struct drm_tegra_cmdbuf __user *user_cmdbufs;
319 struct drm_tegra_reloc __user *user_relocs;
a176c67d 320 struct drm_tegra_syncpt __user *user_syncpt;
c40f0f1a 321 struct drm_tegra_syncpt syncpt;
e0b2ce02 322 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
ec73c4cf 323 struct drm_gem_object **refs;
e0b2ce02 324 struct host1x_syncpt *sp;
c40f0f1a 325 struct host1x_job *job;
ec73c4cf 326 unsigned int num_refs;
c40f0f1a
TR
327 int err;
328
a176c67d
MP
329 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
330 user_relocs = u64_to_user_ptr(args->relocs);
a176c67d
MP
331 user_syncpt = u64_to_user_ptr(args->syncpts);
332
c40f0f1a
TR
333 /* We don't yet support other than one syncpt_incr struct per submit */
334 if (args->num_syncpts != 1)
335 return -EINVAL;
336
d0fbbdff
DO
337 /* We don't yet support waitchks */
338 if (args->num_waitchks != 0)
339 return -EINVAL;
340
c40f0f1a 341 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
24c94e16 342 args->num_relocs);
c40f0f1a
TR
343 if (!job)
344 return -ENOMEM;
345
346 job->num_relocs = args->num_relocs;
bf3d41cc
TR
347 job->client = client;
348 job->class = client->class;
c40f0f1a
TR
349 job->serialize = true;
350
ec73c4cf
DO
351 /*
352 * Track referenced BOs so that they can be unreferenced after the
353 * submission is complete.
354 */
24c94e16 355 num_refs = num_cmdbufs + num_relocs * 2;
ec73c4cf
DO
356
357 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
358 if (!refs) {
359 err = -ENOMEM;
360 goto put;
361 }
362
363 /* reuse as an iterator later */
364 num_refs = 0;
365
c40f0f1a
TR
366 while (num_cmdbufs) {
367 struct drm_tegra_cmdbuf cmdbuf;
368 struct host1x_bo *bo;
368f622c
DO
369 struct tegra_bo *obj;
370 u64 offset;
c40f0f1a 371
a176c67d 372 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
9a991600 373 err = -EFAULT;
c40f0f1a 374 goto fail;
9a991600 375 }
c40f0f1a 376
368f622c
DO
377 /*
378 * The maximum number of CDMA gather fetches is 16383, a higher
379 * value means the words count is malformed.
380 */
381 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
382 err = -EINVAL;
383 goto fail;
384 }
385
a8ad0bd8 386 bo = host1x_bo_lookup(file, cmdbuf.handle);
c40f0f1a
TR
387 if (!bo) {
388 err = -ENOENT;
389 goto fail;
390 }
391
368f622c
DO
392 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
393 obj = host1x_to_tegra_bo(bo);
ec73c4cf 394 refs[num_refs++] = &obj->gem;
368f622c
DO
395
396 /*
397 * Gather buffer base address must be 4-bytes aligned,
398 * unaligned offset is malformed and cause commands stream
399 * corruption on the buffer address relocation.
400 */
5265f033 401 if (offset & 3 || offset > obj->gem.size) {
368f622c
DO
402 err = -EINVAL;
403 goto fail;
404 }
405
c40f0f1a
TR
406 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
407 num_cmdbufs--;
a176c67d 408 user_cmdbufs++;
c40f0f1a
TR
409 }
410
961e3bea 411 /* copy and resolve relocations from submit */
c40f0f1a 412 while (num_relocs--) {
368f622c
DO
413 struct host1x_reloc *reloc;
414 struct tegra_bo *obj;
415
06490bb9 416 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
a176c67d 417 &user_relocs[num_relocs], drm,
961e3bea
TR
418 file);
419 if (err < 0)
c40f0f1a 420 goto fail;
368f622c 421
06490bb9 422 reloc = &job->relocs[num_relocs];
368f622c 423 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
ec73c4cf 424 refs[num_refs++] = &obj->gem;
368f622c
DO
425
426 /*
427 * The unaligned cmdbuf offset will cause an unaligned write
428 * during of the relocations patching, corrupting the commands
429 * stream.
430 */
431 if (reloc->cmdbuf.offset & 3 ||
432 reloc->cmdbuf.offset >= obj->gem.size) {
433 err = -EINVAL;
434 goto fail;
435 }
436
437 obj = host1x_to_tegra_bo(reloc->target.bo);
ec73c4cf 438 refs[num_refs++] = &obj->gem;
368f622c
DO
439
440 if (reloc->target.offset >= obj->gem.size) {
441 err = -EINVAL;
442 goto fail;
443 }
c40f0f1a
TR
444 }
445
a176c67d 446 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
9a991600 447 err = -EFAULT;
c40f0f1a 448 goto fail;
9a991600 449 }
c40f0f1a 450
e0b2ce02
DO
451 /* check whether syncpoint ID is valid */
452 sp = host1x_syncpt_get(host1x, syncpt.id);
453 if (!sp) {
454 err = -ENOENT;
455 goto fail;
456 }
457
c40f0f1a 458 job->is_addr_reg = context->client->ops->is_addr_reg;
0f563a4b 459 job->is_valid_class = context->client->ops->is_valid_class;
c40f0f1a
TR
460 job->syncpt_incrs = syncpt.incrs;
461 job->syncpt_id = syncpt.id;
462 job->timeout = 10000;
463
464 if (args->timeout && args->timeout < 10000)
465 job->timeout = args->timeout;
466
467 err = host1x_job_pin(job, context->client->base.dev);
468 if (err)
469 goto fail;
470
471 err = host1x_job_submit(job);
ec73c4cf
DO
472 if (err) {
473 host1x_job_unpin(job);
474 goto fail;
475 }
c40f0f1a
TR
476
477 args->fence = job->syncpt_end;
478
c40f0f1a 479fail:
ec73c4cf
DO
480 while (num_refs--)
481 drm_gem_object_put_unlocked(refs[num_refs]);
482
483 kfree(refs);
484
485put:
c40f0f1a
TR
486 host1x_job_put(job);
487 return err;
488}
489
490
d43f81cb 491#ifdef CONFIG_DRM_TEGRA_STAGING
d43f81cb
TB
492static int tegra_gem_create(struct drm_device *drm, void *data,
493 struct drm_file *file)
494{
495 struct drm_tegra_gem_create *args = data;
496 struct tegra_bo *bo;
497
773af77f 498 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
d43f81cb
TB
499 &args->handle);
500 if (IS_ERR(bo))
501 return PTR_ERR(bo);
502
503 return 0;
504}
505
506static int tegra_gem_mmap(struct drm_device *drm, void *data,
507 struct drm_file *file)
508{
509 struct drm_tegra_gem_mmap *args = data;
510 struct drm_gem_object *gem;
511 struct tegra_bo *bo;
512
a8ad0bd8 513 gem = drm_gem_object_lookup(file, args->handle);
d43f81cb
TB
514 if (!gem)
515 return -EINVAL;
516
517 bo = to_tegra_bo(gem);
518
2bc7b0ca 519 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
d43f81cb 520
7664b2fa 521 drm_gem_object_put_unlocked(gem);
d43f81cb
TB
522
523 return 0;
524}
525
526static int tegra_syncpt_read(struct drm_device *drm, void *data,
527 struct drm_file *file)
528{
776dc384 529 struct host1x *host = dev_get_drvdata(drm->dev->parent);
d43f81cb 530 struct drm_tegra_syncpt_read *args = data;
776dc384 531 struct host1x_syncpt *sp;
d43f81cb 532
776dc384 533 sp = host1x_syncpt_get(host, args->id);
d43f81cb
TB
534 if (!sp)
535 return -EINVAL;
536
537 args->value = host1x_syncpt_read_min(sp);
538 return 0;
539}
540
541static int tegra_syncpt_incr(struct drm_device *drm, void *data,
542 struct drm_file *file)
543{
776dc384 544 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
d43f81cb 545 struct drm_tegra_syncpt_incr *args = data;
776dc384 546 struct host1x_syncpt *sp;
d43f81cb 547
776dc384 548 sp = host1x_syncpt_get(host1x, args->id);
d43f81cb
TB
549 if (!sp)
550 return -EINVAL;
551
ebae30b1 552 return host1x_syncpt_incr(sp);
d43f81cb
TB
553}
554
555static int tegra_syncpt_wait(struct drm_device *drm, void *data,
556 struct drm_file *file)
557{
776dc384 558 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
d43f81cb 559 struct drm_tegra_syncpt_wait *args = data;
776dc384 560 struct host1x_syncpt *sp;
d43f81cb 561
776dc384 562 sp = host1x_syncpt_get(host1x, args->id);
d43f81cb
TB
563 if (!sp)
564 return -EINVAL;
565
4c69ac12
DO
566 return host1x_syncpt_wait(sp, args->thresh,
567 msecs_to_jiffies(args->timeout),
d43f81cb
TB
568 &args->value);
569}
570
bdd2f9cd
TR
571static int tegra_client_open(struct tegra_drm_file *fpriv,
572 struct tegra_drm_client *client,
573 struct tegra_drm_context *context)
574{
575 int err;
576
577 err = client->ops->open_channel(client, context);
578 if (err < 0)
579 return err;
580
d6c153ec 581 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
bdd2f9cd
TR
582 if (err < 0) {
583 client->ops->close_channel(context);
584 return err;
585 }
586
587 context->client = client;
588 context->id = err;
589
590 return 0;
591}
592
d43f81cb
TB
593static int tegra_open_channel(struct drm_device *drm, void *data,
594 struct drm_file *file)
595{
08943e6c 596 struct tegra_drm_file *fpriv = file->driver_priv;
386a2a71 597 struct tegra_drm *tegra = drm->dev_private;
d43f81cb 598 struct drm_tegra_open_channel *args = data;
c88c3630 599 struct tegra_drm_context *context;
53fa7f72 600 struct tegra_drm_client *client;
d43f81cb
TB
601 int err = -ENODEV;
602
603 context = kzalloc(sizeof(*context), GFP_KERNEL);
604 if (!context)
605 return -ENOMEM;
606
bdd2f9cd
TR
607 mutex_lock(&fpriv->lock);
608
776dc384 609 list_for_each_entry(client, &tegra->clients, list)
53fa7f72 610 if (client->base.class == args->client) {
bdd2f9cd
TR
611 err = tegra_client_open(fpriv, client, context);
612 if (err < 0)
d43f81cb
TB
613 break;
614
bdd2f9cd
TR
615 args->context = context->id;
616 break;
d43f81cb
TB
617 }
618
bdd2f9cd
TR
619 if (err < 0)
620 kfree(context);
621
622 mutex_unlock(&fpriv->lock);
d43f81cb
TB
623 return err;
624}
625
626static int tegra_close_channel(struct drm_device *drm, void *data,
627 struct drm_file *file)
628{
08943e6c 629 struct tegra_drm_file *fpriv = file->driver_priv;
776dc384 630 struct drm_tegra_close_channel *args = data;
c88c3630 631 struct tegra_drm_context *context;
bdd2f9cd 632 int err = 0;
c88c3630 633
bdd2f9cd 634 mutex_lock(&fpriv->lock);
d43f81cb 635
1066a895 636 context = idr_find(&fpriv->contexts, args->context);
bdd2f9cd
TR
637 if (!context) {
638 err = -EINVAL;
639 goto unlock;
640 }
d43f81cb 641
bdd2f9cd 642 idr_remove(&fpriv->contexts, context->id);
c88c3630 643 tegra_drm_context_free(context);
d43f81cb 644
bdd2f9cd
TR
645unlock:
646 mutex_unlock(&fpriv->lock);
647 return err;
d43f81cb
TB
648}
649
650static int tegra_get_syncpt(struct drm_device *drm, void *data,
651 struct drm_file *file)
652{
08943e6c 653 struct tegra_drm_file *fpriv = file->driver_priv;
d43f81cb 654 struct drm_tegra_get_syncpt *args = data;
c88c3630 655 struct tegra_drm_context *context;
d43f81cb 656 struct host1x_syncpt *syncpt;
bdd2f9cd 657 int err = 0;
d43f81cb 658
bdd2f9cd 659 mutex_lock(&fpriv->lock);
c88c3630 660
1066a895 661 context = idr_find(&fpriv->contexts, args->context);
bdd2f9cd
TR
662 if (!context) {
663 err = -ENODEV;
664 goto unlock;
665 }
d43f81cb 666
bdd2f9cd
TR
667 if (args->index >= context->client->base.num_syncpts) {
668 err = -EINVAL;
669 goto unlock;
670 }
d43f81cb 671
53fa7f72 672 syncpt = context->client->base.syncpts[args->index];
d43f81cb
TB
673 args->id = host1x_syncpt_id(syncpt);
674
bdd2f9cd
TR
675unlock:
676 mutex_unlock(&fpriv->lock);
677 return err;
d43f81cb
TB
678}
679
680static int tegra_submit(struct drm_device *drm, void *data,
681 struct drm_file *file)
682{
08943e6c 683 struct tegra_drm_file *fpriv = file->driver_priv;
d43f81cb 684 struct drm_tegra_submit *args = data;
c88c3630 685 struct tegra_drm_context *context;
bdd2f9cd 686 int err;
c88c3630 687
bdd2f9cd 688 mutex_lock(&fpriv->lock);
d43f81cb 689
1066a895 690 context = idr_find(&fpriv->contexts, args->context);
bdd2f9cd
TR
691 if (!context) {
692 err = -ENODEV;
693 goto unlock;
694 }
d43f81cb 695
bdd2f9cd 696 err = context->client->ops->submit(context, args, drm, file);
d43f81cb 697
bdd2f9cd
TR
698unlock:
699 mutex_unlock(&fpriv->lock);
700 return err;
d43f81cb 701}
c54a169b
AM
702
703static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
704 struct drm_file *file)
705{
706 struct tegra_drm_file *fpriv = file->driver_priv;
707 struct drm_tegra_get_syncpt_base *args = data;
708 struct tegra_drm_context *context;
709 struct host1x_syncpt_base *base;
710 struct host1x_syncpt *syncpt;
bdd2f9cd 711 int err = 0;
c54a169b 712
bdd2f9cd 713 mutex_lock(&fpriv->lock);
c54a169b 714
1066a895 715 context = idr_find(&fpriv->contexts, args->context);
bdd2f9cd
TR
716 if (!context) {
717 err = -ENODEV;
718 goto unlock;
719 }
c54a169b 720
bdd2f9cd
TR
721 if (args->syncpt >= context->client->base.num_syncpts) {
722 err = -EINVAL;
723 goto unlock;
724 }
c54a169b
AM
725
726 syncpt = context->client->base.syncpts[args->syncpt];
727
728 base = host1x_syncpt_get_base(syncpt);
bdd2f9cd
TR
729 if (!base) {
730 err = -ENXIO;
731 goto unlock;
732 }
c54a169b
AM
733
734 args->id = host1x_syncpt_base_id(base);
735
bdd2f9cd
TR
736unlock:
737 mutex_unlock(&fpriv->lock);
738 return err;
c54a169b 739}
7678d71f
TR
740
741static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
742 struct drm_file *file)
743{
744 struct drm_tegra_gem_set_tiling *args = data;
745 enum tegra_bo_tiling_mode mode;
746 struct drm_gem_object *gem;
747 unsigned long value = 0;
748 struct tegra_bo *bo;
749
750 switch (args->mode) {
751 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
752 mode = TEGRA_BO_TILING_MODE_PITCH;
753
754 if (args->value != 0)
755 return -EINVAL;
756
757 break;
758
759 case DRM_TEGRA_GEM_TILING_MODE_TILED:
760 mode = TEGRA_BO_TILING_MODE_TILED;
761
762 if (args->value != 0)
763 return -EINVAL;
764
765 break;
766
767 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
768 mode = TEGRA_BO_TILING_MODE_BLOCK;
769
770 if (args->value > 5)
771 return -EINVAL;
772
773 value = args->value;
774 break;
775
776 default:
777 return -EINVAL;
778 }
779
a8ad0bd8 780 gem = drm_gem_object_lookup(file, args->handle);
7678d71f
TR
781 if (!gem)
782 return -ENOENT;
783
784 bo = to_tegra_bo(gem);
785
786 bo->tiling.mode = mode;
787 bo->tiling.value = value;
788
7664b2fa 789 drm_gem_object_put_unlocked(gem);
7678d71f
TR
790
791 return 0;
792}
793
794static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
795 struct drm_file *file)
796{
797 struct drm_tegra_gem_get_tiling *args = data;
798 struct drm_gem_object *gem;
799 struct tegra_bo *bo;
800 int err = 0;
801
a8ad0bd8 802 gem = drm_gem_object_lookup(file, args->handle);
7678d71f
TR
803 if (!gem)
804 return -ENOENT;
805
806 bo = to_tegra_bo(gem);
807
808 switch (bo->tiling.mode) {
809 case TEGRA_BO_TILING_MODE_PITCH:
810 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
811 args->value = 0;
812 break;
813
814 case TEGRA_BO_TILING_MODE_TILED:
815 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
816 args->value = 0;
817 break;
818
819 case TEGRA_BO_TILING_MODE_BLOCK:
820 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
821 args->value = bo->tiling.value;
822 break;
823
824 default:
825 err = -EINVAL;
826 break;
827 }
828
7664b2fa 829 drm_gem_object_put_unlocked(gem);
7678d71f
TR
830
831 return err;
832}
7b129087
TR
833
834static int tegra_gem_set_flags(struct drm_device *drm, void *data,
835 struct drm_file *file)
836{
837 struct drm_tegra_gem_set_flags *args = data;
838 struct drm_gem_object *gem;
839 struct tegra_bo *bo;
840
841 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
842 return -EINVAL;
843
a8ad0bd8 844 gem = drm_gem_object_lookup(file, args->handle);
7b129087
TR
845 if (!gem)
846 return -ENOENT;
847
848 bo = to_tegra_bo(gem);
849 bo->flags = 0;
850
851 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
852 bo->flags |= TEGRA_BO_BOTTOM_UP;
853
7664b2fa 854 drm_gem_object_put_unlocked(gem);
7b129087
TR
855
856 return 0;
857}
858
859static int tegra_gem_get_flags(struct drm_device *drm, void *data,
860 struct drm_file *file)
861{
862 struct drm_tegra_gem_get_flags *args = data;
863 struct drm_gem_object *gem;
864 struct tegra_bo *bo;
865
a8ad0bd8 866 gem = drm_gem_object_lookup(file, args->handle);
7b129087
TR
867 if (!gem)
868 return -ENOENT;
869
870 bo = to_tegra_bo(gem);
871 args->flags = 0;
872
873 if (bo->flags & TEGRA_BO_BOTTOM_UP)
874 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
875
7664b2fa 876 drm_gem_object_put_unlocked(gem);
7b129087
TR
877
878 return 0;
879}
d43f81cb
TB
880#endif
881
baa70943 882static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
d43f81cb 883#ifdef CONFIG_DRM_TEGRA_STAGING
6c68b717
TR
884 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
885 DRM_UNLOCKED | DRM_RENDER_ALLOW),
886 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
887 DRM_UNLOCKED | DRM_RENDER_ALLOW),
888 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
889 DRM_UNLOCKED | DRM_RENDER_ALLOW),
890 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
891 DRM_UNLOCKED | DRM_RENDER_ALLOW),
892 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
893 DRM_UNLOCKED | DRM_RENDER_ALLOW),
894 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
895 DRM_UNLOCKED | DRM_RENDER_ALLOW),
896 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
897 DRM_UNLOCKED | DRM_RENDER_ALLOW),
898 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
899 DRM_UNLOCKED | DRM_RENDER_ALLOW),
900 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
901 DRM_UNLOCKED | DRM_RENDER_ALLOW),
902 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
903 DRM_UNLOCKED | DRM_RENDER_ALLOW),
904 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
905 DRM_UNLOCKED | DRM_RENDER_ALLOW),
906 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
907 DRM_UNLOCKED | DRM_RENDER_ALLOW),
908 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
909 DRM_UNLOCKED | DRM_RENDER_ALLOW),
910 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
911 DRM_UNLOCKED | DRM_RENDER_ALLOW),
d43f81cb 912#endif
d8f4a9ed
TR
913};
914
915static const struct file_operations tegra_drm_fops = {
916 .owner = THIS_MODULE,
917 .open = drm_open,
918 .release = drm_release,
919 .unlocked_ioctl = drm_ioctl,
de2ba664 920 .mmap = tegra_drm_mmap,
d8f4a9ed 921 .poll = drm_poll,
d8f4a9ed 922 .read = drm_read,
d8f4a9ed 923 .compat_ioctl = drm_compat_ioctl,
d8f4a9ed
TR
924 .llseek = noop_llseek,
925};
926
bdd2f9cd
TR
927static int tegra_drm_context_cleanup(int id, void *p, void *data)
928{
929 struct tegra_drm_context *context = p;
930
931 tegra_drm_context_free(context);
932
933 return 0;
934}
935
bda0ecc4 936static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
3c03c46a 937{
08943e6c 938 struct tegra_drm_file *fpriv = file->driver_priv;
3c03c46a 939
bdd2f9cd
TR
940 mutex_lock(&fpriv->lock);
941 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
942 mutex_unlock(&fpriv->lock);
d43f81cb 943
bdd2f9cd
TR
944 idr_destroy(&fpriv->contexts);
945 mutex_destroy(&fpriv->lock);
d43f81cb 946 kfree(fpriv);
3c03c46a
TR
947}
948
e450fcc6
TR
949#ifdef CONFIG_DEBUG_FS
950static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
951{
952 struct drm_info_node *node = (struct drm_info_node *)s->private;
953 struct drm_device *drm = node->minor->dev;
954 struct drm_framebuffer *fb;
955
956 mutex_lock(&drm->mode_config.fb_lock);
957
958 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
959 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
b00c600e
VS
960 fb->base.id, fb->width, fb->height,
961 fb->format->depth,
272725c7 962 fb->format->cpp[0] * 8,
747a598f 963 drm_framebuffer_read_refcount(fb));
e450fcc6
TR
964 }
965
966 mutex_unlock(&drm->mode_config.fb_lock);
967
968 return 0;
969}
970
28c23373
TR
971static int tegra_debugfs_iova(struct seq_file *s, void *data)
972{
973 struct drm_info_node *node = (struct drm_info_node *)s->private;
974 struct drm_device *drm = node->minor->dev;
975 struct tegra_drm *tegra = drm->dev_private;
b5c3714f 976 struct drm_printer p = drm_seq_file_printer(s);
28c23373 977
68d890a3
MM
978 if (tegra->domain) {
979 mutex_lock(&tegra->mm_lock);
980 drm_mm_print(&tegra->mm, &p);
981 mutex_unlock(&tegra->mm_lock);
982 }
b5c3714f
DV
983
984 return 0;
28c23373
TR
985}
986
e450fcc6
TR
987static struct drm_info_list tegra_debugfs_list[] = {
988 { "framebuffers", tegra_debugfs_framebuffers, 0 },
28c23373 989 { "iova", tegra_debugfs_iova, 0 },
e450fcc6
TR
990};
991
992static int tegra_debugfs_init(struct drm_minor *minor)
993{
994 return drm_debugfs_create_files(tegra_debugfs_list,
995 ARRAY_SIZE(tegra_debugfs_list),
996 minor->debugfs_root, minor);
997}
e450fcc6
TR
998#endif
999
9b57f5f2 1000static struct drm_driver tegra_drm_driver = {
ad906599 1001 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
6c68b717 1002 DRIVER_ATOMIC | DRIVER_RENDER,
d8f4a9ed
TR
1003 .load = tegra_drm_load,
1004 .unload = tegra_drm_unload,
1005 .open = tegra_drm_open,
bda0ecc4 1006 .postclose = tegra_drm_postclose,
c94bedab 1007 .lastclose = drm_fb_helper_lastclose,
d8f4a9ed 1008
e450fcc6
TR
1009#if defined(CONFIG_DEBUG_FS)
1010 .debugfs_init = tegra_debugfs_init,
e450fcc6
TR
1011#endif
1012
1ddbdbd6 1013 .gem_free_object_unlocked = tegra_bo_free_object,
de2ba664 1014 .gem_vm_ops = &tegra_bo_vm_ops,
3800391d
TR
1015
1016 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1017 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1018 .gem_prime_export = tegra_gem_prime_export,
1019 .gem_prime_import = tegra_gem_prime_import,
1020
de2ba664 1021 .dumb_create = tegra_bo_dumb_create,
d8f4a9ed
TR
1022
1023 .ioctls = tegra_drm_ioctls,
1024 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1025 .fops = &tegra_drm_fops,
1026
1027 .name = DRIVER_NAME,
1028 .desc = DRIVER_DESC,
1029 .date = DRIVER_DATE,
1030 .major = DRIVER_MAJOR,
1031 .minor = DRIVER_MINOR,
1032 .patchlevel = DRIVER_PATCHLEVEL,
1033};
776dc384
TR
1034
1035int tegra_drm_register_client(struct tegra_drm *tegra,
1036 struct tegra_drm_client *client)
1037{
1038 mutex_lock(&tegra->clients_lock);
1039 list_add_tail(&client->list, &tegra->clients);
1040 mutex_unlock(&tegra->clients_lock);
1041
1042 return 0;
1043}
1044
1045int tegra_drm_unregister_client(struct tegra_drm *tegra,
1046 struct tegra_drm_client *client)
1047{
1048 mutex_lock(&tegra->clients_lock);
1049 list_del_init(&client->list);
1050 mutex_unlock(&tegra->clients_lock);
1051
1052 return 0;
1053}
1054
0c407de5
TR
1055struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
1056 bool shared)
1057{
1058 struct drm_device *drm = dev_get_drvdata(client->parent);
1059 struct tegra_drm *tegra = drm->dev_private;
1060 struct iommu_group *group = NULL;
1061 int err;
1062
1063 if (tegra->domain) {
1064 group = iommu_group_get(client->dev);
1065 if (!group) {
1066 dev_err(client->dev, "failed to get IOMMU group\n");
1067 return ERR_PTR(-ENODEV);
1068 }
1069
1070 if (!shared || (shared && (group != tegra->group))) {
1071 err = iommu_attach_group(tegra->domain, group);
1072 if (err < 0) {
1073 iommu_group_put(group);
1074 return ERR_PTR(err);
1075 }
1076
1077 if (shared && !tegra->group)
1078 tegra->group = group;
1079 }
1080 }
1081
1082 return group;
1083}
1084
1085void host1x_client_iommu_detach(struct host1x_client *client,
1086 struct iommu_group *group)
1087{
1088 struct drm_device *drm = dev_get_drvdata(client->parent);
1089 struct tegra_drm *tegra = drm->dev_private;
1090
1091 if (group) {
1092 if (group == tegra->group) {
1093 iommu_detach_group(tegra->domain, group);
1094 tegra->group = NULL;
1095 }
1096
1097 iommu_group_put(group);
1098 }
1099}
1100
67485fb8 1101void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
ad926015
MP
1102{
1103 struct iova *alloc;
1104 void *virt;
1105 gfp_t gfp;
1106 int err;
1107
1108 if (tegra->domain)
1109 size = iova_align(&tegra->carveout.domain, size);
1110 else
1111 size = PAGE_ALIGN(size);
1112
1113 gfp = GFP_KERNEL | __GFP_ZERO;
1114 if (!tegra->domain) {
1115 /*
1116 * Many units only support 32-bit addresses, even on 64-bit
1117 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1118 * virtual address space, force allocations to be in the
1119 * lower 32-bit range.
1120 */
1121 gfp |= GFP_DMA;
1122 }
1123
1124 virt = (void *)__get_free_pages(gfp, get_order(size));
1125 if (!virt)
1126 return ERR_PTR(-ENOMEM);
1127
1128 if (!tegra->domain) {
1129 /*
1130 * If IOMMU is disabled, devices address physical memory
1131 * directly.
1132 */
1133 *dma = virt_to_phys(virt);
1134 return virt;
1135 }
1136
1137 alloc = alloc_iova(&tegra->carveout.domain,
1138 size >> tegra->carveout.shift,
1139 tegra->carveout.limit, true);
1140 if (!alloc) {
1141 err = -EBUSY;
1142 goto free_pages;
1143 }
1144
1145 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1146 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1147 size, IOMMU_READ | IOMMU_WRITE);
1148 if (err < 0)
1149 goto free_iova;
1150
1151 return virt;
1152
1153free_iova:
1154 __free_iova(&tegra->carveout.domain, alloc);
1155free_pages:
1156 free_pages((unsigned long)virt, get_order(size));
1157
1158 return ERR_PTR(err);
1159}
1160
1161void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1162 dma_addr_t dma)
1163{
1164 if (tegra->domain)
1165 size = iova_align(&tegra->carveout.domain, size);
1166 else
1167 size = PAGE_ALIGN(size);
1168
1169 if (tegra->domain) {
1170 iommu_unmap(tegra->domain, dma, size);
1171 free_iova(&tegra->carveout.domain,
1172 iova_pfn(&tegra->carveout.domain, dma));
1173 }
1174
1175 free_pages((unsigned long)virt, get_order(size));
1176}
1177
9910f5c4 1178static int host1x_drm_probe(struct host1x_device *dev)
776dc384 1179{
9910f5c4
TR
1180 struct drm_driver *driver = &tegra_drm_driver;
1181 struct drm_device *drm;
1182 int err;
1183
1184 drm = drm_dev_alloc(driver, &dev->dev);
0f288605
TG
1185 if (IS_ERR(drm))
1186 return PTR_ERR(drm);
9910f5c4 1187
9910f5c4
TR
1188 dev_set_drvdata(&dev->dev, drm);
1189
1190 err = drm_dev_register(drm, 0);
1191 if (err < 0)
1192 goto unref;
1193
9910f5c4
TR
1194 return 0;
1195
1196unref:
1197 drm_dev_unref(drm);
1198 return err;
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1199}
1200
9910f5c4 1201static int host1x_drm_remove(struct host1x_device *dev)
776dc384 1202{
9910f5c4
TR
1203 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1204
1205 drm_dev_unregister(drm);
1206 drm_dev_unref(drm);
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1207
1208 return 0;
1209}
1210
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1211#ifdef CONFIG_PM_SLEEP
1212static int host1x_drm_suspend(struct device *dev)
1213{
1214 struct drm_device *drm = dev_get_drvdata(dev);
359ae687 1215
53f1e062 1216 return drm_mode_config_helper_suspend(drm);
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TR
1217}
1218
1219static int host1x_drm_resume(struct device *dev)
1220{
1221 struct drm_device *drm = dev_get_drvdata(dev);
1222
53f1e062 1223 return drm_mode_config_helper_resume(drm);
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TR
1224}
1225#endif
1226
a13f1dc4
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1227static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1228 host1x_drm_resume);
359ae687 1229
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1230static const struct of_device_id host1x_drm_subdevs[] = {
1231 { .compatible = "nvidia,tegra20-dc", },
1232 { .compatible = "nvidia,tegra20-hdmi", },
1233 { .compatible = "nvidia,tegra20-gr2d", },
5f60ed0d 1234 { .compatible = "nvidia,tegra20-gr3d", },
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1235 { .compatible = "nvidia,tegra30-dc", },
1236 { .compatible = "nvidia,tegra30-hdmi", },
1237 { .compatible = "nvidia,tegra30-gr2d", },
5f60ed0d 1238 { .compatible = "nvidia,tegra30-gr3d", },
dec72739 1239 { .compatible = "nvidia,tegra114-dsi", },
7d1d28ac 1240 { .compatible = "nvidia,tegra114-hdmi", },
5f60ed0d 1241 { .compatible = "nvidia,tegra114-gr3d", },
8620fc62 1242 { .compatible = "nvidia,tegra124-dc", },
6b6b6042 1243 { .compatible = "nvidia,tegra124-sor", },
fb7be70e 1244 { .compatible = "nvidia,tegra124-hdmi", },
7d338587 1245 { .compatible = "nvidia,tegra124-dsi", },
0ae797a8 1246 { .compatible = "nvidia,tegra124-vic", },
c06c7930 1247 { .compatible = "nvidia,tegra132-dsi", },
5b4f516f 1248 { .compatible = "nvidia,tegra210-dc", },
ddfb406b 1249 { .compatible = "nvidia,tegra210-dsi", },
3309ac83 1250 { .compatible = "nvidia,tegra210-sor", },
459cc2c6 1251 { .compatible = "nvidia,tegra210-sor1", },
0ae797a8 1252 { .compatible = "nvidia,tegra210-vic", },
c4755fb9 1253 { .compatible = "nvidia,tegra186-display", },
47307954 1254 { .compatible = "nvidia,tegra186-dc", },
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1255 { .compatible = "nvidia,tegra186-sor", },
1256 { .compatible = "nvidia,tegra186-sor1", },
6e44b9ad 1257 { .compatible = "nvidia,tegra186-vic", },
5725daaa 1258 { .compatible = "nvidia,tegra194-display", },
47443196 1259 { .compatible = "nvidia,tegra194-dc", },
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1260 { /* sentinel */ }
1261};
1262
1263static struct host1x_driver host1x_drm_driver = {
f4c5cf88
TR
1264 .driver = {
1265 .name = "drm",
359ae687 1266 .pm = &host1x_drm_pm_ops,
f4c5cf88 1267 },
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1268 .probe = host1x_drm_probe,
1269 .remove = host1x_drm_remove,
1270 .subdevs = host1x_drm_subdevs,
1271};
1272
473112e4 1273static struct platform_driver * const drivers[] = {
c4755fb9 1274 &tegra_display_hub_driver,
473112e4
TR
1275 &tegra_dc_driver,
1276 &tegra_hdmi_driver,
1277 &tegra_dsi_driver,
1278 &tegra_dpaux_driver,
1279 &tegra_sor_driver,
1280 &tegra_gr2d_driver,
1281 &tegra_gr3d_driver,
0ae797a8 1282 &tegra_vic_driver,
473112e4
TR
1283};
1284
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1285static int __init host1x_drm_init(void)
1286{
1287 int err;
1288
1289 err = host1x_driver_register(&host1x_drm_driver);
1290 if (err < 0)
1291 return err;
1292
473112e4 1293 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
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1294 if (err < 0)
1295 goto unregister_host1x;
1296
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1297 return 0;
1298
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1299unregister_host1x:
1300 host1x_driver_unregister(&host1x_drm_driver);
1301 return err;
1302}
1303module_init(host1x_drm_init);
1304
1305static void __exit host1x_drm_exit(void)
1306{
473112e4 1307 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
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TR
1308 host1x_driver_unregister(&host1x_drm_driver);
1309}
1310module_exit(host1x_drm_exit);
1311
1312MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1313MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1314MODULE_LICENSE("GPL v2");