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drm/tegra: Enable IOVA API when IOMMU support is enabled
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / tegra / drm.c
CommitLineData
d8f4a9ed
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1/*
2 * Copyright (C) 2012 Avionic Design GmbH
d43f81cb 3 * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved.
d8f4a9ed
TR
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
776dc384 10#include <linux/host1x.h>
df06b759 11#include <linux/iommu.h>
776dc384 12
1503ca47 13#include <drm/drm_atomic.h>
07866963
TR
14#include <drm/drm_atomic_helper.h>
15
d8f4a9ed 16#include "drm.h"
de2ba664 17#include "gem.h"
d8f4a9ed
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18
19#define DRIVER_NAME "tegra"
20#define DRIVER_DESC "NVIDIA Tegra graphics"
21#define DRIVER_DATE "20120330"
22#define DRIVER_MAJOR 0
23#define DRIVER_MINOR 0
24#define DRIVER_PATCHLEVEL 0
25
08943e6c
TR
26struct tegra_drm_file {
27 struct list_head contexts;
28};
29
1503ca47
TR
30static void tegra_atomic_schedule(struct tegra_drm *tegra,
31 struct drm_atomic_state *state)
32{
33 tegra->commit.state = state;
34 schedule_work(&tegra->commit.work);
35}
36
37static void tegra_atomic_complete(struct tegra_drm *tegra,
38 struct drm_atomic_state *state)
39{
40 struct drm_device *drm = tegra->drm;
41
42 /*
43 * Everything below can be run asynchronously without the need to grab
44 * any modeset locks at all under one condition: It must be guaranteed
45 * that the asynchronous work has either been cancelled (if the driver
46 * supports it, which at least requires that the framebuffers get
47 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
48 * before the new state gets committed on the software side with
49 * drm_atomic_helper_swap_state().
50 *
51 * This scheme allows new atomic state updates to be prepared and
52 * checked in parallel to the asynchronous completion of the previous
53 * update. Which is important since compositors need to figure out the
54 * composition of the next frame right after having submitted the
55 * current layout.
56 */
57
1af434a9 58 drm_atomic_helper_commit_modeset_disables(drm, state);
1af434a9 59 drm_atomic_helper_commit_modeset_enables(drm, state);
2b58e98d
LY
60 drm_atomic_helper_commit_planes(drm, state,
61 DRM_PLANE_COMMIT_ACTIVE_ONLY);
1503ca47
TR
62
63 drm_atomic_helper_wait_for_vblanks(drm, state);
64
65 drm_atomic_helper_cleanup_planes(drm, state);
0853695c 66 drm_atomic_state_put(state);
1503ca47
TR
67}
68
69static void tegra_atomic_work(struct work_struct *work)
70{
71 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
72 commit.work);
73
74 tegra_atomic_complete(tegra, tegra->commit.state);
75}
76
77static int tegra_atomic_commit(struct drm_device *drm,
2dacdd70 78 struct drm_atomic_state *state, bool nonblock)
1503ca47
TR
79{
80 struct tegra_drm *tegra = drm->dev_private;
81 int err;
82
83 err = drm_atomic_helper_prepare_planes(drm, state);
84 if (err)
85 return err;
86
2dacdd70 87 /* serialize outstanding nonblocking commits */
1503ca47
TR
88 mutex_lock(&tegra->commit.lock);
89 flush_work(&tegra->commit.work);
90
91 /*
92 * This is the point of no return - everything below never fails except
93 * when the hw goes bonghits. Which means we can commit the new state on
94 * the software side now.
95 */
96
5e84c269 97 drm_atomic_helper_swap_state(state, true);
1503ca47 98
0853695c 99 drm_atomic_state_get(state);
2dacdd70 100 if (nonblock)
1503ca47
TR
101 tegra_atomic_schedule(tegra, state);
102 else
103 tegra_atomic_complete(tegra, state);
104
105 mutex_unlock(&tegra->commit.lock);
106 return 0;
107}
108
f9914214
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109static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
110 .fb_create = tegra_fb_create,
b110ef37 111#ifdef CONFIG_DRM_FBDEV_EMULATION
f9914214
TR
112 .output_poll_changed = tegra_fb_output_poll_changed,
113#endif
07866963 114 .atomic_check = drm_atomic_helper_check,
1503ca47 115 .atomic_commit = tegra_atomic_commit,
f9914214
TR
116};
117
776dc384 118static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
692e6d7b 119{
776dc384 120 struct host1x_device *device = to_host1x_device(drm->dev);
386a2a71 121 struct tegra_drm *tegra;
692e6d7b
TB
122 int err;
123
776dc384 124 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
386a2a71 125 if (!tegra)
692e6d7b
TB
126 return -ENOMEM;
127
df06b759 128 if (iommu_present(&platform_bus_type)) {
4553f733
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129 struct iommu_domain_geometry *geometry;
130 u64 start, end;
131
df06b759 132 tegra->domain = iommu_domain_alloc(&platform_bus_type);
bf19b885
DC
133 if (!tegra->domain) {
134 err = -ENOMEM;
df06b759
TR
135 goto free;
136 }
137
4553f733
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138 geometry = &tegra->domain->geometry;
139 start = geometry->aperture_start;
140 end = geometry->aperture_end;
141
d2d8c358
TR
142 DRM_DEBUG_DRIVER("IOMMU aperture initialized (%#llx-%#llx)\n",
143 start, end);
4553f733 144 drm_mm_init(&tegra->mm, start, end - start + 1);
df06b759
TR
145 }
146
386a2a71
TR
147 mutex_init(&tegra->clients_lock);
148 INIT_LIST_HEAD(&tegra->clients);
1503ca47
TR
149
150 mutex_init(&tegra->commit.lock);
151 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
152
386a2a71
TR
153 drm->dev_private = tegra;
154 tegra->drm = drm;
d8f4a9ed
TR
155
156 drm_mode_config_init(drm);
157
f9914214
TR
158 drm->mode_config.min_width = 0;
159 drm->mode_config.min_height = 0;
160
161 drm->mode_config.max_width = 4096;
162 drm->mode_config.max_height = 4096;
163
164 drm->mode_config.funcs = &tegra_drm_mode_funcs;
165
e2215321
TR
166 err = tegra_drm_fb_prepare(drm);
167 if (err < 0)
1d1e6fe9 168 goto config;
e2215321
TR
169
170 drm_kms_helper_poll_init(drm);
171
776dc384 172 err = host1x_device_init(device);
d8f4a9ed 173 if (err < 0)
1d1e6fe9 174 goto fbdev;
d8f4a9ed 175
603f0cc9
TR
176 /*
177 * We don't use the drm_irq_install() helpers provided by the DRM
178 * core, so we need to set this manually in order to allow the
179 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
180 */
4423843c 181 drm->irq_enabled = true;
603f0cc9 182
42e9ce05 183 /* syncpoints are used for full 32-bit hardware VBLANK counters */
42e9ce05
TR
184 drm->max_vblank_count = 0xffffffff;
185
6e5ff998
TR
186 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
187 if (err < 0)
1d1e6fe9 188 goto device;
6e5ff998 189
31930d4d
TR
190 drm_mode_config_reset(drm);
191
d8f4a9ed
TR
192 err = tegra_drm_fb_init(drm);
193 if (err < 0)
1d1e6fe9 194 goto vblank;
d8f4a9ed 195
d8f4a9ed 196 return 0;
1d1e6fe9
TR
197
198vblank:
199 drm_vblank_cleanup(drm);
200device:
201 host1x_device_exit(device);
202fbdev:
203 drm_kms_helper_poll_fini(drm);
204 tegra_drm_fb_free(drm);
205config:
206 drm_mode_config_cleanup(drm);
df06b759
TR
207
208 if (tegra->domain) {
209 iommu_domain_free(tegra->domain);
210 drm_mm_takedown(&tegra->mm);
211 }
212free:
1d1e6fe9
TR
213 kfree(tegra);
214 return err;
d8f4a9ed
TR
215}
216
11b3c20b 217static void tegra_drm_unload(struct drm_device *drm)
d8f4a9ed 218{
776dc384 219 struct host1x_device *device = to_host1x_device(drm->dev);
df06b759 220 struct tegra_drm *tegra = drm->dev_private;
776dc384
TR
221 int err;
222
d8f4a9ed
TR
223 drm_kms_helper_poll_fini(drm);
224 tegra_drm_fb_exit(drm);
f002abc1 225 drm_mode_config_cleanup(drm);
4aa3df71 226 drm_vblank_cleanup(drm);
d8f4a9ed 227
776dc384
TR
228 err = host1x_device_exit(device);
229 if (err < 0)
11b3c20b 230 return;
776dc384 231
df06b759
TR
232 if (tegra->domain) {
233 iommu_domain_free(tegra->domain);
234 drm_mm_takedown(&tegra->mm);
235 }
236
1053f4dd 237 kfree(tegra);
d8f4a9ed
TR
238}
239
240static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
241{
08943e6c 242 struct tegra_drm_file *fpriv;
d43f81cb
TB
243
244 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
245 if (!fpriv)
246 return -ENOMEM;
247
248 INIT_LIST_HEAD(&fpriv->contexts);
249 filp->driver_priv = fpriv;
250
d8f4a9ed
TR
251 return 0;
252}
253
c88c3630 254static void tegra_drm_context_free(struct tegra_drm_context *context)
d43f81cb
TB
255{
256 context->client->ops->close_channel(context);
257 kfree(context);
258}
259
d8f4a9ed
TR
260static void tegra_drm_lastclose(struct drm_device *drm)
261{
b110ef37 262#ifdef CONFIG_DRM_FBDEV_EMULATION
386a2a71 263 struct tegra_drm *tegra = drm->dev_private;
d8f4a9ed 264
386a2a71 265 tegra_fbdev_restore_mode(tegra->fbdev);
60c2f709 266#endif
d8f4a9ed
TR
267}
268
c40f0f1a 269static struct host1x_bo *
a8ad0bd8 270host1x_bo_lookup(struct drm_file *file, u32 handle)
c40f0f1a
TR
271{
272 struct drm_gem_object *gem;
273 struct tegra_bo *bo;
274
a8ad0bd8 275 gem = drm_gem_object_lookup(file, handle);
c40f0f1a
TR
276 if (!gem)
277 return NULL;
278
a07cdfe5 279 drm_gem_object_unreference_unlocked(gem);
c40f0f1a
TR
280
281 bo = to_tegra_bo(gem);
282 return &bo->base;
283}
284
961e3bea
TR
285static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
286 struct drm_tegra_reloc __user *src,
287 struct drm_device *drm,
288 struct drm_file *file)
289{
290 u32 cmdbuf, target;
291 int err;
292
293 err = get_user(cmdbuf, &src->cmdbuf.handle);
294 if (err < 0)
295 return err;
296
297 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
298 if (err < 0)
299 return err;
300
301 err = get_user(target, &src->target.handle);
302 if (err < 0)
303 return err;
304
31f40f86 305 err = get_user(dest->target.offset, &src->target.offset);
961e3bea
TR
306 if (err < 0)
307 return err;
308
309 err = get_user(dest->shift, &src->shift);
310 if (err < 0)
311 return err;
312
a8ad0bd8 313 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
961e3bea
TR
314 if (!dest->cmdbuf.bo)
315 return -ENOENT;
316
a8ad0bd8 317 dest->target.bo = host1x_bo_lookup(file, target);
961e3bea
TR
318 if (!dest->target.bo)
319 return -ENOENT;
320
321 return 0;
322}
323
c40f0f1a
TR
324int tegra_drm_submit(struct tegra_drm_context *context,
325 struct drm_tegra_submit *args, struct drm_device *drm,
326 struct drm_file *file)
327{
328 unsigned int num_cmdbufs = args->num_cmdbufs;
329 unsigned int num_relocs = args->num_relocs;
330 unsigned int num_waitchks = args->num_waitchks;
331 struct drm_tegra_cmdbuf __user *cmdbufs =
a7ed68fc 332 (void __user *)(uintptr_t)args->cmdbufs;
c40f0f1a 333 struct drm_tegra_reloc __user *relocs =
a7ed68fc 334 (void __user *)(uintptr_t)args->relocs;
c40f0f1a 335 struct drm_tegra_waitchk __user *waitchks =
a7ed68fc 336 (void __user *)(uintptr_t)args->waitchks;
c40f0f1a
TR
337 struct drm_tegra_syncpt syncpt;
338 struct host1x_job *job;
339 int err;
340
341 /* We don't yet support other than one syncpt_incr struct per submit */
342 if (args->num_syncpts != 1)
343 return -EINVAL;
344
345 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
346 args->num_relocs, args->num_waitchks);
347 if (!job)
348 return -ENOMEM;
349
350 job->num_relocs = args->num_relocs;
351 job->num_waitchk = args->num_waitchks;
352 job->client = (u32)args->context;
353 job->class = context->client->base.class;
354 job->serialize = true;
355
356 while (num_cmdbufs) {
357 struct drm_tegra_cmdbuf cmdbuf;
358 struct host1x_bo *bo;
359
9a991600
DC
360 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
361 err = -EFAULT;
c40f0f1a 362 goto fail;
9a991600 363 }
c40f0f1a 364
a8ad0bd8 365 bo = host1x_bo_lookup(file, cmdbuf.handle);
c40f0f1a
TR
366 if (!bo) {
367 err = -ENOENT;
368 goto fail;
369 }
370
371 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
372 num_cmdbufs--;
373 cmdbufs++;
374 }
375
961e3bea 376 /* copy and resolve relocations from submit */
c40f0f1a 377 while (num_relocs--) {
961e3bea
TR
378 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
379 &relocs[num_relocs], drm,
380 file);
381 if (err < 0)
c40f0f1a 382 goto fail;
c40f0f1a
TR
383 }
384
9a991600
DC
385 if (copy_from_user(job->waitchk, waitchks,
386 sizeof(*waitchks) * num_waitchks)) {
387 err = -EFAULT;
c40f0f1a 388 goto fail;
9a991600 389 }
c40f0f1a 390
9a991600
DC
391 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
392 sizeof(syncpt))) {
393 err = -EFAULT;
c40f0f1a 394 goto fail;
9a991600 395 }
c40f0f1a
TR
396
397 job->is_addr_reg = context->client->ops->is_addr_reg;
398 job->syncpt_incrs = syncpt.incrs;
399 job->syncpt_id = syncpt.id;
400 job->timeout = 10000;
401
402 if (args->timeout && args->timeout < 10000)
403 job->timeout = args->timeout;
404
405 err = host1x_job_pin(job, context->client->base.dev);
406 if (err)
407 goto fail;
408
409 err = host1x_job_submit(job);
410 if (err)
411 goto fail_submit;
412
413 args->fence = job->syncpt_end;
414
415 host1x_job_put(job);
416 return 0;
417
418fail_submit:
419 host1x_job_unpin(job);
420fail:
421 host1x_job_put(job);
422 return err;
423}
424
425
d43f81cb 426#ifdef CONFIG_DRM_TEGRA_STAGING
c88c3630
TR
427static struct tegra_drm_context *tegra_drm_get_context(__u64 context)
428{
429 return (struct tegra_drm_context *)(uintptr_t)context;
430}
431
08943e6c 432static bool tegra_drm_file_owns_context(struct tegra_drm_file *file,
c88c3630 433 struct tegra_drm_context *context)
d43f81cb 434{
c88c3630 435 struct tegra_drm_context *ctx;
d43f81cb
TB
436
437 list_for_each_entry(ctx, &file->contexts, list)
438 if (ctx == context)
439 return true;
440
441 return false;
442}
443
444static int tegra_gem_create(struct drm_device *drm, void *data,
445 struct drm_file *file)
446{
447 struct drm_tegra_gem_create *args = data;
448 struct tegra_bo *bo;
449
773af77f 450 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
d43f81cb
TB
451 &args->handle);
452 if (IS_ERR(bo))
453 return PTR_ERR(bo);
454
455 return 0;
456}
457
458static int tegra_gem_mmap(struct drm_device *drm, void *data,
459 struct drm_file *file)
460{
461 struct drm_tegra_gem_mmap *args = data;
462 struct drm_gem_object *gem;
463 struct tegra_bo *bo;
464
a8ad0bd8 465 gem = drm_gem_object_lookup(file, args->handle);
d43f81cb
TB
466 if (!gem)
467 return -EINVAL;
468
469 bo = to_tegra_bo(gem);
470
2bc7b0ca 471 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
d43f81cb 472
11533304 473 drm_gem_object_unreference_unlocked(gem);
d43f81cb
TB
474
475 return 0;
476}
477
478static int tegra_syncpt_read(struct drm_device *drm, void *data,
479 struct drm_file *file)
480{
776dc384 481 struct host1x *host = dev_get_drvdata(drm->dev->parent);
d43f81cb 482 struct drm_tegra_syncpt_read *args = data;
776dc384 483 struct host1x_syncpt *sp;
d43f81cb 484
776dc384 485 sp = host1x_syncpt_get(host, args->id);
d43f81cb
TB
486 if (!sp)
487 return -EINVAL;
488
489 args->value = host1x_syncpt_read_min(sp);
490 return 0;
491}
492
493static int tegra_syncpt_incr(struct drm_device *drm, void *data,
494 struct drm_file *file)
495{
776dc384 496 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
d43f81cb 497 struct drm_tegra_syncpt_incr *args = data;
776dc384 498 struct host1x_syncpt *sp;
d43f81cb 499
776dc384 500 sp = host1x_syncpt_get(host1x, args->id);
d43f81cb
TB
501 if (!sp)
502 return -EINVAL;
503
ebae30b1 504 return host1x_syncpt_incr(sp);
d43f81cb
TB
505}
506
507static int tegra_syncpt_wait(struct drm_device *drm, void *data,
508 struct drm_file *file)
509{
776dc384 510 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
d43f81cb 511 struct drm_tegra_syncpt_wait *args = data;
776dc384 512 struct host1x_syncpt *sp;
d43f81cb 513
776dc384 514 sp = host1x_syncpt_get(host1x, args->id);
d43f81cb
TB
515 if (!sp)
516 return -EINVAL;
517
518 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
519 &args->value);
520}
521
522static int tegra_open_channel(struct drm_device *drm, void *data,
523 struct drm_file *file)
524{
08943e6c 525 struct tegra_drm_file *fpriv = file->driver_priv;
386a2a71 526 struct tegra_drm *tegra = drm->dev_private;
d43f81cb 527 struct drm_tegra_open_channel *args = data;
c88c3630 528 struct tegra_drm_context *context;
53fa7f72 529 struct tegra_drm_client *client;
d43f81cb
TB
530 int err = -ENODEV;
531
532 context = kzalloc(sizeof(*context), GFP_KERNEL);
533 if (!context)
534 return -ENOMEM;
535
776dc384 536 list_for_each_entry(client, &tegra->clients, list)
53fa7f72 537 if (client->base.class == args->client) {
d43f81cb
TB
538 err = client->ops->open_channel(client, context);
539 if (err)
540 break;
541
d43f81cb
TB
542 list_add(&context->list, &fpriv->contexts);
543 args->context = (uintptr_t)context;
53fa7f72 544 context->client = client;
d43f81cb
TB
545 return 0;
546 }
547
548 kfree(context);
549 return err;
550}
551
552static int tegra_close_channel(struct drm_device *drm, void *data,
553 struct drm_file *file)
554{
08943e6c 555 struct tegra_drm_file *fpriv = file->driver_priv;
776dc384 556 struct drm_tegra_close_channel *args = data;
c88c3630
TR
557 struct tegra_drm_context *context;
558
559 context = tegra_drm_get_context(args->context);
d43f81cb 560
08943e6c 561 if (!tegra_drm_file_owns_context(fpriv, context))
d43f81cb
TB
562 return -EINVAL;
563
564 list_del(&context->list);
c88c3630 565 tegra_drm_context_free(context);
d43f81cb
TB
566
567 return 0;
568}
569
570static int tegra_get_syncpt(struct drm_device *drm, void *data,
571 struct drm_file *file)
572{
08943e6c 573 struct tegra_drm_file *fpriv = file->driver_priv;
d43f81cb 574 struct drm_tegra_get_syncpt *args = data;
c88c3630 575 struct tegra_drm_context *context;
d43f81cb
TB
576 struct host1x_syncpt *syncpt;
577
c88c3630
TR
578 context = tegra_drm_get_context(args->context);
579
08943e6c 580 if (!tegra_drm_file_owns_context(fpriv, context))
d43f81cb
TB
581 return -ENODEV;
582
53fa7f72 583 if (args->index >= context->client->base.num_syncpts)
d43f81cb
TB
584 return -EINVAL;
585
53fa7f72 586 syncpt = context->client->base.syncpts[args->index];
d43f81cb
TB
587 args->id = host1x_syncpt_id(syncpt);
588
589 return 0;
590}
591
592static int tegra_submit(struct drm_device *drm, void *data,
593 struct drm_file *file)
594{
08943e6c 595 struct tegra_drm_file *fpriv = file->driver_priv;
d43f81cb 596 struct drm_tegra_submit *args = data;
c88c3630
TR
597 struct tegra_drm_context *context;
598
599 context = tegra_drm_get_context(args->context);
d43f81cb 600
08943e6c 601 if (!tegra_drm_file_owns_context(fpriv, context))
d43f81cb
TB
602 return -ENODEV;
603
604 return context->client->ops->submit(context, args, drm, file);
605}
c54a169b
AM
606
607static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
608 struct drm_file *file)
609{
610 struct tegra_drm_file *fpriv = file->driver_priv;
611 struct drm_tegra_get_syncpt_base *args = data;
612 struct tegra_drm_context *context;
613 struct host1x_syncpt_base *base;
614 struct host1x_syncpt *syncpt;
615
616 context = tegra_drm_get_context(args->context);
617
618 if (!tegra_drm_file_owns_context(fpriv, context))
619 return -ENODEV;
620
621 if (args->syncpt >= context->client->base.num_syncpts)
622 return -EINVAL;
623
624 syncpt = context->client->base.syncpts[args->syncpt];
625
626 base = host1x_syncpt_get_base(syncpt);
627 if (!base)
628 return -ENXIO;
629
630 args->id = host1x_syncpt_base_id(base);
631
632 return 0;
633}
7678d71f
TR
634
635static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
636 struct drm_file *file)
637{
638 struct drm_tegra_gem_set_tiling *args = data;
639 enum tegra_bo_tiling_mode mode;
640 struct drm_gem_object *gem;
641 unsigned long value = 0;
642 struct tegra_bo *bo;
643
644 switch (args->mode) {
645 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
646 mode = TEGRA_BO_TILING_MODE_PITCH;
647
648 if (args->value != 0)
649 return -EINVAL;
650
651 break;
652
653 case DRM_TEGRA_GEM_TILING_MODE_TILED:
654 mode = TEGRA_BO_TILING_MODE_TILED;
655
656 if (args->value != 0)
657 return -EINVAL;
658
659 break;
660
661 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
662 mode = TEGRA_BO_TILING_MODE_BLOCK;
663
664 if (args->value > 5)
665 return -EINVAL;
666
667 value = args->value;
668 break;
669
670 default:
671 return -EINVAL;
672 }
673
a8ad0bd8 674 gem = drm_gem_object_lookup(file, args->handle);
7678d71f
TR
675 if (!gem)
676 return -ENOENT;
677
678 bo = to_tegra_bo(gem);
679
680 bo->tiling.mode = mode;
681 bo->tiling.value = value;
682
11533304 683 drm_gem_object_unreference_unlocked(gem);
7678d71f
TR
684
685 return 0;
686}
687
688static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
689 struct drm_file *file)
690{
691 struct drm_tegra_gem_get_tiling *args = data;
692 struct drm_gem_object *gem;
693 struct tegra_bo *bo;
694 int err = 0;
695
a8ad0bd8 696 gem = drm_gem_object_lookup(file, args->handle);
7678d71f
TR
697 if (!gem)
698 return -ENOENT;
699
700 bo = to_tegra_bo(gem);
701
702 switch (bo->tiling.mode) {
703 case TEGRA_BO_TILING_MODE_PITCH:
704 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
705 args->value = 0;
706 break;
707
708 case TEGRA_BO_TILING_MODE_TILED:
709 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
710 args->value = 0;
711 break;
712
713 case TEGRA_BO_TILING_MODE_BLOCK:
714 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
715 args->value = bo->tiling.value;
716 break;
717
718 default:
719 err = -EINVAL;
720 break;
721 }
722
11533304 723 drm_gem_object_unreference_unlocked(gem);
7678d71f
TR
724
725 return err;
726}
7b129087
TR
727
728static int tegra_gem_set_flags(struct drm_device *drm, void *data,
729 struct drm_file *file)
730{
731 struct drm_tegra_gem_set_flags *args = data;
732 struct drm_gem_object *gem;
733 struct tegra_bo *bo;
734
735 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
736 return -EINVAL;
737
a8ad0bd8 738 gem = drm_gem_object_lookup(file, args->handle);
7b129087
TR
739 if (!gem)
740 return -ENOENT;
741
742 bo = to_tegra_bo(gem);
743 bo->flags = 0;
744
745 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
746 bo->flags |= TEGRA_BO_BOTTOM_UP;
747
11533304 748 drm_gem_object_unreference_unlocked(gem);
7b129087
TR
749
750 return 0;
751}
752
753static int tegra_gem_get_flags(struct drm_device *drm, void *data,
754 struct drm_file *file)
755{
756 struct drm_tegra_gem_get_flags *args = data;
757 struct drm_gem_object *gem;
758 struct tegra_bo *bo;
759
a8ad0bd8 760 gem = drm_gem_object_lookup(file, args->handle);
7b129087
TR
761 if (!gem)
762 return -ENOENT;
763
764 bo = to_tegra_bo(gem);
765 args->flags = 0;
766
767 if (bo->flags & TEGRA_BO_BOTTOM_UP)
768 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
769
11533304 770 drm_gem_object_unreference_unlocked(gem);
7b129087
TR
771
772 return 0;
773}
d43f81cb
TB
774#endif
775
baa70943 776static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
d43f81cb 777#ifdef CONFIG_DRM_TEGRA_STAGING
f8c47144
DV
778 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0),
779 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0),
780 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0),
781 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0),
782 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0),
783 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0),
784 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0),
785 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0),
786 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0),
787 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0),
788 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0),
789 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0),
790 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0),
791 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0),
d43f81cb 792#endif
d8f4a9ed
TR
793};
794
795static const struct file_operations tegra_drm_fops = {
796 .owner = THIS_MODULE,
797 .open = drm_open,
798 .release = drm_release,
799 .unlocked_ioctl = drm_ioctl,
de2ba664 800 .mmap = tegra_drm_mmap,
d8f4a9ed 801 .poll = drm_poll,
d8f4a9ed 802 .read = drm_read,
d8f4a9ed 803 .compat_ioctl = drm_compat_ioctl,
d8f4a9ed
TR
804 .llseek = noop_llseek,
805};
806
88e72717
TR
807static u32 tegra_drm_get_vblank_counter(struct drm_device *drm,
808 unsigned int pipe)
6e5ff998 809{
75bcb054 810 struct drm_crtc *crtc = drm_crtc_from_index(drm, pipe);
42e9ce05 811 struct tegra_dc *dc = to_tegra_dc(crtc);
ed7dae58
TR
812
813 if (!crtc)
814 return 0;
815
42e9ce05 816 return tegra_dc_get_vblank_counter(dc);
6e5ff998
TR
817}
818
88e72717 819static int tegra_drm_enable_vblank(struct drm_device *drm, unsigned int pipe)
6e5ff998 820{
75bcb054 821 struct drm_crtc *crtc = drm_crtc_from_index(drm, pipe);
6e5ff998
TR
822 struct tegra_dc *dc = to_tegra_dc(crtc);
823
824 if (!crtc)
825 return -ENODEV;
826
827 tegra_dc_enable_vblank(dc);
828
829 return 0;
830}
831
88e72717 832static void tegra_drm_disable_vblank(struct drm_device *drm, unsigned int pipe)
6e5ff998 833{
75bcb054 834 struct drm_crtc *crtc = drm_crtc_from_index(drm, pipe);
6e5ff998
TR
835 struct tegra_dc *dc = to_tegra_dc(crtc);
836
837 if (crtc)
838 tegra_dc_disable_vblank(dc);
839}
840
3c03c46a
TR
841static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file)
842{
08943e6c 843 struct tegra_drm_file *fpriv = file->driver_priv;
c88c3630 844 struct tegra_drm_context *context, *tmp;
3c03c46a 845
d43f81cb 846 list_for_each_entry_safe(context, tmp, &fpriv->contexts, list)
c88c3630 847 tegra_drm_context_free(context);
d43f81cb
TB
848
849 kfree(fpriv);
3c03c46a
TR
850}
851
e450fcc6
TR
852#ifdef CONFIG_DEBUG_FS
853static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
854{
855 struct drm_info_node *node = (struct drm_info_node *)s->private;
856 struct drm_device *drm = node->minor->dev;
857 struct drm_framebuffer *fb;
858
859 mutex_lock(&drm->mode_config.fb_lock);
860
861 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
862 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
b00c600e
VS
863 fb->base.id, fb->width, fb->height,
864 fb->format->depth,
272725c7 865 fb->format->cpp[0] * 8,
747a598f 866 drm_framebuffer_read_refcount(fb));
e450fcc6
TR
867 }
868
869 mutex_unlock(&drm->mode_config.fb_lock);
870
871 return 0;
872}
873
28c23373
TR
874static int tegra_debugfs_iova(struct seq_file *s, void *data)
875{
876 struct drm_info_node *node = (struct drm_info_node *)s->private;
877 struct drm_device *drm = node->minor->dev;
878 struct tegra_drm *tegra = drm->dev_private;
b5c3714f 879 struct drm_printer p = drm_seq_file_printer(s);
28c23373 880
b5c3714f
DV
881 drm_mm_print(&tegra->mm, &p);
882
883 return 0;
28c23373
TR
884}
885
e450fcc6
TR
886static struct drm_info_list tegra_debugfs_list[] = {
887 { "framebuffers", tegra_debugfs_framebuffers, 0 },
28c23373 888 { "iova", tegra_debugfs_iova, 0 },
e450fcc6
TR
889};
890
891static int tegra_debugfs_init(struct drm_minor *minor)
892{
893 return drm_debugfs_create_files(tegra_debugfs_list,
894 ARRAY_SIZE(tegra_debugfs_list),
895 minor->debugfs_root, minor);
896}
e450fcc6
TR
897#endif
898
9b57f5f2 899static struct drm_driver tegra_drm_driver = {
ad906599
TR
900 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
901 DRIVER_ATOMIC,
d8f4a9ed
TR
902 .load = tegra_drm_load,
903 .unload = tegra_drm_unload,
904 .open = tegra_drm_open,
3c03c46a 905 .preclose = tegra_drm_preclose,
d8f4a9ed
TR
906 .lastclose = tegra_drm_lastclose,
907
6e5ff998
TR
908 .get_vblank_counter = tegra_drm_get_vblank_counter,
909 .enable_vblank = tegra_drm_enable_vblank,
910 .disable_vblank = tegra_drm_disable_vblank,
911
e450fcc6
TR
912#if defined(CONFIG_DEBUG_FS)
913 .debugfs_init = tegra_debugfs_init,
e450fcc6
TR
914#endif
915
1ddbdbd6 916 .gem_free_object_unlocked = tegra_bo_free_object,
de2ba664 917 .gem_vm_ops = &tegra_bo_vm_ops,
3800391d
TR
918
919 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
920 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
921 .gem_prime_export = tegra_gem_prime_export,
922 .gem_prime_import = tegra_gem_prime_import,
923
de2ba664
AM
924 .dumb_create = tegra_bo_dumb_create,
925 .dumb_map_offset = tegra_bo_dumb_map_offset,
43387b37 926 .dumb_destroy = drm_gem_dumb_destroy,
d8f4a9ed
TR
927
928 .ioctls = tegra_drm_ioctls,
929 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
930 .fops = &tegra_drm_fops,
931
932 .name = DRIVER_NAME,
933 .desc = DRIVER_DESC,
934 .date = DRIVER_DATE,
935 .major = DRIVER_MAJOR,
936 .minor = DRIVER_MINOR,
937 .patchlevel = DRIVER_PATCHLEVEL,
938};
776dc384
TR
939
940int tegra_drm_register_client(struct tegra_drm *tegra,
941 struct tegra_drm_client *client)
942{
943 mutex_lock(&tegra->clients_lock);
944 list_add_tail(&client->list, &tegra->clients);
945 mutex_unlock(&tegra->clients_lock);
946
947 return 0;
948}
949
950int tegra_drm_unregister_client(struct tegra_drm *tegra,
951 struct tegra_drm_client *client)
952{
953 mutex_lock(&tegra->clients_lock);
954 list_del_init(&client->list);
955 mutex_unlock(&tegra->clients_lock);
956
957 return 0;
958}
959
9910f5c4 960static int host1x_drm_probe(struct host1x_device *dev)
776dc384 961{
9910f5c4
TR
962 struct drm_driver *driver = &tegra_drm_driver;
963 struct drm_device *drm;
964 int err;
965
966 drm = drm_dev_alloc(driver, &dev->dev);
0f288605
TG
967 if (IS_ERR(drm))
968 return PTR_ERR(drm);
9910f5c4 969
9910f5c4
TR
970 dev_set_drvdata(&dev->dev, drm);
971
972 err = drm_dev_register(drm, 0);
973 if (err < 0)
974 goto unref;
975
9910f5c4
TR
976 return 0;
977
978unref:
979 drm_dev_unref(drm);
980 return err;
776dc384
TR
981}
982
9910f5c4 983static int host1x_drm_remove(struct host1x_device *dev)
776dc384 984{
9910f5c4
TR
985 struct drm_device *drm = dev_get_drvdata(&dev->dev);
986
987 drm_dev_unregister(drm);
988 drm_dev_unref(drm);
776dc384
TR
989
990 return 0;
991}
992
359ae687
TR
993#ifdef CONFIG_PM_SLEEP
994static int host1x_drm_suspend(struct device *dev)
995{
996 struct drm_device *drm = dev_get_drvdata(dev);
986c58d1 997 struct tegra_drm *tegra = drm->dev_private;
359ae687
TR
998
999 drm_kms_helper_poll_disable(drm);
986c58d1
TR
1000 tegra_drm_fb_suspend(drm);
1001
1002 tegra->state = drm_atomic_helper_suspend(drm);
1003 if (IS_ERR(tegra->state)) {
1004 tegra_drm_fb_resume(drm);
1005 drm_kms_helper_poll_enable(drm);
1006 return PTR_ERR(tegra->state);
1007 }
359ae687
TR
1008
1009 return 0;
1010}
1011
1012static int host1x_drm_resume(struct device *dev)
1013{
1014 struct drm_device *drm = dev_get_drvdata(dev);
986c58d1 1015 struct tegra_drm *tegra = drm->dev_private;
359ae687 1016
986c58d1
TR
1017 drm_atomic_helper_resume(drm, tegra->state);
1018 tegra_drm_fb_resume(drm);
359ae687
TR
1019 drm_kms_helper_poll_enable(drm);
1020
1021 return 0;
1022}
1023#endif
1024
a13f1dc4
TR
1025static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1026 host1x_drm_resume);
359ae687 1027
776dc384
TR
1028static const struct of_device_id host1x_drm_subdevs[] = {
1029 { .compatible = "nvidia,tegra20-dc", },
1030 { .compatible = "nvidia,tegra20-hdmi", },
1031 { .compatible = "nvidia,tegra20-gr2d", },
5f60ed0d 1032 { .compatible = "nvidia,tegra20-gr3d", },
776dc384
TR
1033 { .compatible = "nvidia,tegra30-dc", },
1034 { .compatible = "nvidia,tegra30-hdmi", },
1035 { .compatible = "nvidia,tegra30-gr2d", },
5f60ed0d 1036 { .compatible = "nvidia,tegra30-gr3d", },
dec72739 1037 { .compatible = "nvidia,tegra114-dsi", },
7d1d28ac 1038 { .compatible = "nvidia,tegra114-hdmi", },
5f60ed0d 1039 { .compatible = "nvidia,tegra114-gr3d", },
8620fc62 1040 { .compatible = "nvidia,tegra124-dc", },
6b6b6042 1041 { .compatible = "nvidia,tegra124-sor", },
fb7be70e 1042 { .compatible = "nvidia,tegra124-hdmi", },
7d338587 1043 { .compatible = "nvidia,tegra124-dsi", },
c06c7930 1044 { .compatible = "nvidia,tegra132-dsi", },
5b4f516f 1045 { .compatible = "nvidia,tegra210-dc", },
ddfb406b 1046 { .compatible = "nvidia,tegra210-dsi", },
3309ac83 1047 { .compatible = "nvidia,tegra210-sor", },
459cc2c6 1048 { .compatible = "nvidia,tegra210-sor1", },
776dc384
TR
1049 { /* sentinel */ }
1050};
1051
1052static struct host1x_driver host1x_drm_driver = {
f4c5cf88
TR
1053 .driver = {
1054 .name = "drm",
359ae687 1055 .pm = &host1x_drm_pm_ops,
f4c5cf88 1056 },
776dc384
TR
1057 .probe = host1x_drm_probe,
1058 .remove = host1x_drm_remove,
1059 .subdevs = host1x_drm_subdevs,
1060};
1061
473112e4
TR
1062static struct platform_driver * const drivers[] = {
1063 &tegra_dc_driver,
1064 &tegra_hdmi_driver,
1065 &tegra_dsi_driver,
1066 &tegra_dpaux_driver,
1067 &tegra_sor_driver,
1068 &tegra_gr2d_driver,
1069 &tegra_gr3d_driver,
1070};
1071
776dc384
TR
1072static int __init host1x_drm_init(void)
1073{
1074 int err;
1075
1076 err = host1x_driver_register(&host1x_drm_driver);
1077 if (err < 0)
1078 return err;
1079
473112e4 1080 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
776dc384
TR
1081 if (err < 0)
1082 goto unregister_host1x;
1083
776dc384
TR
1084 return 0;
1085
776dc384
TR
1086unregister_host1x:
1087 host1x_driver_unregister(&host1x_drm_driver);
1088 return err;
1089}
1090module_init(host1x_drm_init);
1091
1092static void __exit host1x_drm_exit(void)
1093{
473112e4 1094 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
776dc384
TR
1095 host1x_driver_unregister(&host1x_drm_driver);
1096}
1097module_exit(host1x_drm_exit);
1098
1099MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1100MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1101MODULE_LICENSE("GPL v2");