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Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
d43f81cb | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
d8f4a9ed TR |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
776dc384 | 10 | #include <linux/host1x.h> |
df06b759 | 11 | #include <linux/iommu.h> |
776dc384 | 12 | |
07866963 TR |
13 | #include <drm/drm_atomic_helper.h> |
14 | ||
d8f4a9ed | 15 | #include "drm.h" |
de2ba664 | 16 | #include "gem.h" |
d8f4a9ed TR |
17 | |
18 | #define DRIVER_NAME "tegra" | |
19 | #define DRIVER_DESC "NVIDIA Tegra graphics" | |
20 | #define DRIVER_DATE "20120330" | |
21 | #define DRIVER_MAJOR 0 | |
22 | #define DRIVER_MINOR 0 | |
23 | #define DRIVER_PATCHLEVEL 0 | |
24 | ||
08943e6c TR |
25 | struct tegra_drm_file { |
26 | struct list_head contexts; | |
27 | }; | |
28 | ||
f9914214 TR |
29 | static const struct drm_mode_config_funcs tegra_drm_mode_funcs = { |
30 | .fb_create = tegra_fb_create, | |
31 | #ifdef CONFIG_DRM_TEGRA_FBDEV | |
32 | .output_poll_changed = tegra_fb_output_poll_changed, | |
33 | #endif | |
07866963 TR |
34 | .atomic_check = drm_atomic_helper_check, |
35 | .atomic_commit = drm_atomic_helper_commit, | |
f9914214 TR |
36 | }; |
37 | ||
776dc384 | 38 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
692e6d7b | 39 | { |
776dc384 | 40 | struct host1x_device *device = to_host1x_device(drm->dev); |
386a2a71 | 41 | struct tegra_drm *tegra; |
692e6d7b TB |
42 | int err; |
43 | ||
776dc384 | 44 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
386a2a71 | 45 | if (!tegra) |
692e6d7b TB |
46 | return -ENOMEM; |
47 | ||
df06b759 TR |
48 | if (iommu_present(&platform_bus_type)) { |
49 | tegra->domain = iommu_domain_alloc(&platform_bus_type); | |
bf19b885 DC |
50 | if (!tegra->domain) { |
51 | err = -ENOMEM; | |
df06b759 TR |
52 | goto free; |
53 | } | |
54 | ||
55 | DRM_DEBUG("IOMMU context initialized\n"); | |
56 | drm_mm_init(&tegra->mm, 0, SZ_2G); | |
57 | } | |
58 | ||
386a2a71 TR |
59 | mutex_init(&tegra->clients_lock); |
60 | INIT_LIST_HEAD(&tegra->clients); | |
386a2a71 TR |
61 | drm->dev_private = tegra; |
62 | tegra->drm = drm; | |
d8f4a9ed TR |
63 | |
64 | drm_mode_config_init(drm); | |
65 | ||
f9914214 TR |
66 | drm->mode_config.min_width = 0; |
67 | drm->mode_config.min_height = 0; | |
68 | ||
69 | drm->mode_config.max_width = 4096; | |
70 | drm->mode_config.max_height = 4096; | |
71 | ||
72 | drm->mode_config.funcs = &tegra_drm_mode_funcs; | |
73 | ||
e2215321 TR |
74 | err = tegra_drm_fb_prepare(drm); |
75 | if (err < 0) | |
1d1e6fe9 | 76 | goto config; |
e2215321 TR |
77 | |
78 | drm_kms_helper_poll_init(drm); | |
79 | ||
776dc384 | 80 | err = host1x_device_init(device); |
d8f4a9ed | 81 | if (err < 0) |
1d1e6fe9 | 82 | goto fbdev; |
d8f4a9ed | 83 | |
9d44189f TR |
84 | drm_mode_config_reset(drm); |
85 | ||
603f0cc9 TR |
86 | /* |
87 | * We don't use the drm_irq_install() helpers provided by the DRM | |
88 | * core, so we need to set this manually in order to allow the | |
89 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. | |
90 | */ | |
4423843c | 91 | drm->irq_enabled = true; |
603f0cc9 | 92 | |
6e5ff998 TR |
93 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
94 | if (err < 0) | |
1d1e6fe9 | 95 | goto device; |
6e5ff998 | 96 | |
d8f4a9ed TR |
97 | err = tegra_drm_fb_init(drm); |
98 | if (err < 0) | |
1d1e6fe9 | 99 | goto vblank; |
d8f4a9ed | 100 | |
d8f4a9ed | 101 | return 0; |
1d1e6fe9 TR |
102 | |
103 | vblank: | |
104 | drm_vblank_cleanup(drm); | |
105 | device: | |
106 | host1x_device_exit(device); | |
107 | fbdev: | |
108 | drm_kms_helper_poll_fini(drm); | |
109 | tegra_drm_fb_free(drm); | |
110 | config: | |
111 | drm_mode_config_cleanup(drm); | |
df06b759 TR |
112 | |
113 | if (tegra->domain) { | |
114 | iommu_domain_free(tegra->domain); | |
115 | drm_mm_takedown(&tegra->mm); | |
116 | } | |
117 | free: | |
1d1e6fe9 TR |
118 | kfree(tegra); |
119 | return err; | |
d8f4a9ed TR |
120 | } |
121 | ||
122 | static int tegra_drm_unload(struct drm_device *drm) | |
123 | { | |
776dc384 | 124 | struct host1x_device *device = to_host1x_device(drm->dev); |
df06b759 | 125 | struct tegra_drm *tegra = drm->dev_private; |
776dc384 TR |
126 | int err; |
127 | ||
d8f4a9ed TR |
128 | drm_kms_helper_poll_fini(drm); |
129 | tegra_drm_fb_exit(drm); | |
f002abc1 | 130 | drm_mode_config_cleanup(drm); |
4aa3df71 | 131 | drm_vblank_cleanup(drm); |
d8f4a9ed | 132 | |
776dc384 TR |
133 | err = host1x_device_exit(device); |
134 | if (err < 0) | |
135 | return err; | |
136 | ||
df06b759 TR |
137 | if (tegra->domain) { |
138 | iommu_domain_free(tegra->domain); | |
139 | drm_mm_takedown(&tegra->mm); | |
140 | } | |
141 | ||
1053f4dd TR |
142 | kfree(tegra); |
143 | ||
d8f4a9ed TR |
144 | return 0; |
145 | } | |
146 | ||
147 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) | |
148 | { | |
08943e6c | 149 | struct tegra_drm_file *fpriv; |
d43f81cb TB |
150 | |
151 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
152 | if (!fpriv) | |
153 | return -ENOMEM; | |
154 | ||
155 | INIT_LIST_HEAD(&fpriv->contexts); | |
156 | filp->driver_priv = fpriv; | |
157 | ||
d8f4a9ed TR |
158 | return 0; |
159 | } | |
160 | ||
c88c3630 | 161 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
d43f81cb TB |
162 | { |
163 | context->client->ops->close_channel(context); | |
164 | kfree(context); | |
165 | } | |
166 | ||
d8f4a9ed TR |
167 | static void tegra_drm_lastclose(struct drm_device *drm) |
168 | { | |
6e60163b | 169 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
386a2a71 | 170 | struct tegra_drm *tegra = drm->dev_private; |
d8f4a9ed | 171 | |
386a2a71 | 172 | tegra_fbdev_restore_mode(tegra->fbdev); |
60c2f709 | 173 | #endif |
d8f4a9ed TR |
174 | } |
175 | ||
c40f0f1a TR |
176 | static struct host1x_bo * |
177 | host1x_bo_lookup(struct drm_device *drm, struct drm_file *file, u32 handle) | |
178 | { | |
179 | struct drm_gem_object *gem; | |
180 | struct tegra_bo *bo; | |
181 | ||
182 | gem = drm_gem_object_lookup(drm, file, handle); | |
183 | if (!gem) | |
184 | return NULL; | |
185 | ||
186 | mutex_lock(&drm->struct_mutex); | |
187 | drm_gem_object_unreference(gem); | |
188 | mutex_unlock(&drm->struct_mutex); | |
189 | ||
190 | bo = to_tegra_bo(gem); | |
191 | return &bo->base; | |
192 | } | |
193 | ||
961e3bea TR |
194 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
195 | struct drm_tegra_reloc __user *src, | |
196 | struct drm_device *drm, | |
197 | struct drm_file *file) | |
198 | { | |
199 | u32 cmdbuf, target; | |
200 | int err; | |
201 | ||
202 | err = get_user(cmdbuf, &src->cmdbuf.handle); | |
203 | if (err < 0) | |
204 | return err; | |
205 | ||
206 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); | |
207 | if (err < 0) | |
208 | return err; | |
209 | ||
210 | err = get_user(target, &src->target.handle); | |
211 | if (err < 0) | |
212 | return err; | |
213 | ||
214 | err = get_user(dest->target.offset, &src->cmdbuf.offset); | |
215 | if (err < 0) | |
216 | return err; | |
217 | ||
218 | err = get_user(dest->shift, &src->shift); | |
219 | if (err < 0) | |
220 | return err; | |
221 | ||
222 | dest->cmdbuf.bo = host1x_bo_lookup(drm, file, cmdbuf); | |
223 | if (!dest->cmdbuf.bo) | |
224 | return -ENOENT; | |
225 | ||
226 | dest->target.bo = host1x_bo_lookup(drm, file, target); | |
227 | if (!dest->target.bo) | |
228 | return -ENOENT; | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
c40f0f1a TR |
233 | int tegra_drm_submit(struct tegra_drm_context *context, |
234 | struct drm_tegra_submit *args, struct drm_device *drm, | |
235 | struct drm_file *file) | |
236 | { | |
237 | unsigned int num_cmdbufs = args->num_cmdbufs; | |
238 | unsigned int num_relocs = args->num_relocs; | |
239 | unsigned int num_waitchks = args->num_waitchks; | |
240 | struct drm_tegra_cmdbuf __user *cmdbufs = | |
a7ed68fc | 241 | (void __user *)(uintptr_t)args->cmdbufs; |
c40f0f1a | 242 | struct drm_tegra_reloc __user *relocs = |
a7ed68fc | 243 | (void __user *)(uintptr_t)args->relocs; |
c40f0f1a | 244 | struct drm_tegra_waitchk __user *waitchks = |
a7ed68fc | 245 | (void __user *)(uintptr_t)args->waitchks; |
c40f0f1a TR |
246 | struct drm_tegra_syncpt syncpt; |
247 | struct host1x_job *job; | |
248 | int err; | |
249 | ||
250 | /* We don't yet support other than one syncpt_incr struct per submit */ | |
251 | if (args->num_syncpts != 1) | |
252 | return -EINVAL; | |
253 | ||
254 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, | |
255 | args->num_relocs, args->num_waitchks); | |
256 | if (!job) | |
257 | return -ENOMEM; | |
258 | ||
259 | job->num_relocs = args->num_relocs; | |
260 | job->num_waitchk = args->num_waitchks; | |
261 | job->client = (u32)args->context; | |
262 | job->class = context->client->base.class; | |
263 | job->serialize = true; | |
264 | ||
265 | while (num_cmdbufs) { | |
266 | struct drm_tegra_cmdbuf cmdbuf; | |
267 | struct host1x_bo *bo; | |
268 | ||
9a991600 DC |
269 | if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) { |
270 | err = -EFAULT; | |
c40f0f1a | 271 | goto fail; |
9a991600 | 272 | } |
c40f0f1a TR |
273 | |
274 | bo = host1x_bo_lookup(drm, file, cmdbuf.handle); | |
275 | if (!bo) { | |
276 | err = -ENOENT; | |
277 | goto fail; | |
278 | } | |
279 | ||
280 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); | |
281 | num_cmdbufs--; | |
282 | cmdbufs++; | |
283 | } | |
284 | ||
961e3bea | 285 | /* copy and resolve relocations from submit */ |
c40f0f1a | 286 | while (num_relocs--) { |
961e3bea TR |
287 | err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs], |
288 | &relocs[num_relocs], drm, | |
289 | file); | |
290 | if (err < 0) | |
c40f0f1a | 291 | goto fail; |
c40f0f1a TR |
292 | } |
293 | ||
9a991600 DC |
294 | if (copy_from_user(job->waitchk, waitchks, |
295 | sizeof(*waitchks) * num_waitchks)) { | |
296 | err = -EFAULT; | |
c40f0f1a | 297 | goto fail; |
9a991600 | 298 | } |
c40f0f1a | 299 | |
9a991600 DC |
300 | if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts, |
301 | sizeof(syncpt))) { | |
302 | err = -EFAULT; | |
c40f0f1a | 303 | goto fail; |
9a991600 | 304 | } |
c40f0f1a TR |
305 | |
306 | job->is_addr_reg = context->client->ops->is_addr_reg; | |
307 | job->syncpt_incrs = syncpt.incrs; | |
308 | job->syncpt_id = syncpt.id; | |
309 | job->timeout = 10000; | |
310 | ||
311 | if (args->timeout && args->timeout < 10000) | |
312 | job->timeout = args->timeout; | |
313 | ||
314 | err = host1x_job_pin(job, context->client->base.dev); | |
315 | if (err) | |
316 | goto fail; | |
317 | ||
318 | err = host1x_job_submit(job); | |
319 | if (err) | |
320 | goto fail_submit; | |
321 | ||
322 | args->fence = job->syncpt_end; | |
323 | ||
324 | host1x_job_put(job); | |
325 | return 0; | |
326 | ||
327 | fail_submit: | |
328 | host1x_job_unpin(job); | |
329 | fail: | |
330 | host1x_job_put(job); | |
331 | return err; | |
332 | } | |
333 | ||
334 | ||
d43f81cb | 335 | #ifdef CONFIG_DRM_TEGRA_STAGING |
c88c3630 TR |
336 | static struct tegra_drm_context *tegra_drm_get_context(__u64 context) |
337 | { | |
338 | return (struct tegra_drm_context *)(uintptr_t)context; | |
339 | } | |
340 | ||
08943e6c | 341 | static bool tegra_drm_file_owns_context(struct tegra_drm_file *file, |
c88c3630 | 342 | struct tegra_drm_context *context) |
d43f81cb | 343 | { |
c88c3630 | 344 | struct tegra_drm_context *ctx; |
d43f81cb TB |
345 | |
346 | list_for_each_entry(ctx, &file->contexts, list) | |
347 | if (ctx == context) | |
348 | return true; | |
349 | ||
350 | return false; | |
351 | } | |
352 | ||
353 | static int tegra_gem_create(struct drm_device *drm, void *data, | |
354 | struct drm_file *file) | |
355 | { | |
356 | struct drm_tegra_gem_create *args = data; | |
357 | struct tegra_bo *bo; | |
358 | ||
773af77f | 359 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
d43f81cb TB |
360 | &args->handle); |
361 | if (IS_ERR(bo)) | |
362 | return PTR_ERR(bo); | |
363 | ||
364 | return 0; | |
365 | } | |
366 | ||
367 | static int tegra_gem_mmap(struct drm_device *drm, void *data, | |
368 | struct drm_file *file) | |
369 | { | |
370 | struct drm_tegra_gem_mmap *args = data; | |
371 | struct drm_gem_object *gem; | |
372 | struct tegra_bo *bo; | |
373 | ||
374 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
375 | if (!gem) | |
376 | return -EINVAL; | |
377 | ||
378 | bo = to_tegra_bo(gem); | |
379 | ||
2bc7b0ca | 380 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
d43f81cb TB |
381 | |
382 | drm_gem_object_unreference(gem); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
387 | static int tegra_syncpt_read(struct drm_device *drm, void *data, | |
388 | struct drm_file *file) | |
389 | { | |
776dc384 | 390 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 391 | struct drm_tegra_syncpt_read *args = data; |
776dc384 | 392 | struct host1x_syncpt *sp; |
d43f81cb | 393 | |
776dc384 | 394 | sp = host1x_syncpt_get(host, args->id); |
d43f81cb TB |
395 | if (!sp) |
396 | return -EINVAL; | |
397 | ||
398 | args->value = host1x_syncpt_read_min(sp); | |
399 | return 0; | |
400 | } | |
401 | ||
402 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, | |
403 | struct drm_file *file) | |
404 | { | |
776dc384 | 405 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 406 | struct drm_tegra_syncpt_incr *args = data; |
776dc384 | 407 | struct host1x_syncpt *sp; |
d43f81cb | 408 | |
776dc384 | 409 | sp = host1x_syncpt_get(host1x, args->id); |
d43f81cb TB |
410 | if (!sp) |
411 | return -EINVAL; | |
412 | ||
ebae30b1 | 413 | return host1x_syncpt_incr(sp); |
d43f81cb TB |
414 | } |
415 | ||
416 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, | |
417 | struct drm_file *file) | |
418 | { | |
776dc384 | 419 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 420 | struct drm_tegra_syncpt_wait *args = data; |
776dc384 | 421 | struct host1x_syncpt *sp; |
d43f81cb | 422 | |
776dc384 | 423 | sp = host1x_syncpt_get(host1x, args->id); |
d43f81cb TB |
424 | if (!sp) |
425 | return -EINVAL; | |
426 | ||
427 | return host1x_syncpt_wait(sp, args->thresh, args->timeout, | |
428 | &args->value); | |
429 | } | |
430 | ||
431 | static int tegra_open_channel(struct drm_device *drm, void *data, | |
432 | struct drm_file *file) | |
433 | { | |
08943e6c | 434 | struct tegra_drm_file *fpriv = file->driver_priv; |
386a2a71 | 435 | struct tegra_drm *tegra = drm->dev_private; |
d43f81cb | 436 | struct drm_tegra_open_channel *args = data; |
c88c3630 | 437 | struct tegra_drm_context *context; |
53fa7f72 | 438 | struct tegra_drm_client *client; |
d43f81cb TB |
439 | int err = -ENODEV; |
440 | ||
441 | context = kzalloc(sizeof(*context), GFP_KERNEL); | |
442 | if (!context) | |
443 | return -ENOMEM; | |
444 | ||
776dc384 | 445 | list_for_each_entry(client, &tegra->clients, list) |
53fa7f72 | 446 | if (client->base.class == args->client) { |
d43f81cb TB |
447 | err = client->ops->open_channel(client, context); |
448 | if (err) | |
449 | break; | |
450 | ||
d43f81cb TB |
451 | list_add(&context->list, &fpriv->contexts); |
452 | args->context = (uintptr_t)context; | |
53fa7f72 | 453 | context->client = client; |
d43f81cb TB |
454 | return 0; |
455 | } | |
456 | ||
457 | kfree(context); | |
458 | return err; | |
459 | } | |
460 | ||
461 | static int tegra_close_channel(struct drm_device *drm, void *data, | |
462 | struct drm_file *file) | |
463 | { | |
08943e6c | 464 | struct tegra_drm_file *fpriv = file->driver_priv; |
776dc384 | 465 | struct drm_tegra_close_channel *args = data; |
c88c3630 TR |
466 | struct tegra_drm_context *context; |
467 | ||
468 | context = tegra_drm_get_context(args->context); | |
d43f81cb | 469 | |
08943e6c | 470 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
471 | return -EINVAL; |
472 | ||
473 | list_del(&context->list); | |
c88c3630 | 474 | tegra_drm_context_free(context); |
d43f81cb TB |
475 | |
476 | return 0; | |
477 | } | |
478 | ||
479 | static int tegra_get_syncpt(struct drm_device *drm, void *data, | |
480 | struct drm_file *file) | |
481 | { | |
08943e6c | 482 | struct tegra_drm_file *fpriv = file->driver_priv; |
d43f81cb | 483 | struct drm_tegra_get_syncpt *args = data; |
c88c3630 | 484 | struct tegra_drm_context *context; |
d43f81cb TB |
485 | struct host1x_syncpt *syncpt; |
486 | ||
c88c3630 TR |
487 | context = tegra_drm_get_context(args->context); |
488 | ||
08943e6c | 489 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
490 | return -ENODEV; |
491 | ||
53fa7f72 | 492 | if (args->index >= context->client->base.num_syncpts) |
d43f81cb TB |
493 | return -EINVAL; |
494 | ||
53fa7f72 | 495 | syncpt = context->client->base.syncpts[args->index]; |
d43f81cb TB |
496 | args->id = host1x_syncpt_id(syncpt); |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
501 | static int tegra_submit(struct drm_device *drm, void *data, | |
502 | struct drm_file *file) | |
503 | { | |
08943e6c | 504 | struct tegra_drm_file *fpriv = file->driver_priv; |
d43f81cb | 505 | struct drm_tegra_submit *args = data; |
c88c3630 TR |
506 | struct tegra_drm_context *context; |
507 | ||
508 | context = tegra_drm_get_context(args->context); | |
d43f81cb | 509 | |
08943e6c | 510 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
511 | return -ENODEV; |
512 | ||
513 | return context->client->ops->submit(context, args, drm, file); | |
514 | } | |
c54a169b AM |
515 | |
516 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, | |
517 | struct drm_file *file) | |
518 | { | |
519 | struct tegra_drm_file *fpriv = file->driver_priv; | |
520 | struct drm_tegra_get_syncpt_base *args = data; | |
521 | struct tegra_drm_context *context; | |
522 | struct host1x_syncpt_base *base; | |
523 | struct host1x_syncpt *syncpt; | |
524 | ||
525 | context = tegra_drm_get_context(args->context); | |
526 | ||
527 | if (!tegra_drm_file_owns_context(fpriv, context)) | |
528 | return -ENODEV; | |
529 | ||
530 | if (args->syncpt >= context->client->base.num_syncpts) | |
531 | return -EINVAL; | |
532 | ||
533 | syncpt = context->client->base.syncpts[args->syncpt]; | |
534 | ||
535 | base = host1x_syncpt_get_base(syncpt); | |
536 | if (!base) | |
537 | return -ENXIO; | |
538 | ||
539 | args->id = host1x_syncpt_base_id(base); | |
540 | ||
541 | return 0; | |
542 | } | |
7678d71f TR |
543 | |
544 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, | |
545 | struct drm_file *file) | |
546 | { | |
547 | struct drm_tegra_gem_set_tiling *args = data; | |
548 | enum tegra_bo_tiling_mode mode; | |
549 | struct drm_gem_object *gem; | |
550 | unsigned long value = 0; | |
551 | struct tegra_bo *bo; | |
552 | ||
553 | switch (args->mode) { | |
554 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: | |
555 | mode = TEGRA_BO_TILING_MODE_PITCH; | |
556 | ||
557 | if (args->value != 0) | |
558 | return -EINVAL; | |
559 | ||
560 | break; | |
561 | ||
562 | case DRM_TEGRA_GEM_TILING_MODE_TILED: | |
563 | mode = TEGRA_BO_TILING_MODE_TILED; | |
564 | ||
565 | if (args->value != 0) | |
566 | return -EINVAL; | |
567 | ||
568 | break; | |
569 | ||
570 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: | |
571 | mode = TEGRA_BO_TILING_MODE_BLOCK; | |
572 | ||
573 | if (args->value > 5) | |
574 | return -EINVAL; | |
575 | ||
576 | value = args->value; | |
577 | break; | |
578 | ||
579 | default: | |
580 | return -EINVAL; | |
581 | } | |
582 | ||
583 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
584 | if (!gem) | |
585 | return -ENOENT; | |
586 | ||
587 | bo = to_tegra_bo(gem); | |
588 | ||
589 | bo->tiling.mode = mode; | |
590 | bo->tiling.value = value; | |
591 | ||
592 | drm_gem_object_unreference(gem); | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, | |
598 | struct drm_file *file) | |
599 | { | |
600 | struct drm_tegra_gem_get_tiling *args = data; | |
601 | struct drm_gem_object *gem; | |
602 | struct tegra_bo *bo; | |
603 | int err = 0; | |
604 | ||
605 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
606 | if (!gem) | |
607 | return -ENOENT; | |
608 | ||
609 | bo = to_tegra_bo(gem); | |
610 | ||
611 | switch (bo->tiling.mode) { | |
612 | case TEGRA_BO_TILING_MODE_PITCH: | |
613 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; | |
614 | args->value = 0; | |
615 | break; | |
616 | ||
617 | case TEGRA_BO_TILING_MODE_TILED: | |
618 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; | |
619 | args->value = 0; | |
620 | break; | |
621 | ||
622 | case TEGRA_BO_TILING_MODE_BLOCK: | |
623 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; | |
624 | args->value = bo->tiling.value; | |
625 | break; | |
626 | ||
627 | default: | |
628 | err = -EINVAL; | |
629 | break; | |
630 | } | |
631 | ||
632 | drm_gem_object_unreference(gem); | |
633 | ||
634 | return err; | |
635 | } | |
7b129087 TR |
636 | |
637 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, | |
638 | struct drm_file *file) | |
639 | { | |
640 | struct drm_tegra_gem_set_flags *args = data; | |
641 | struct drm_gem_object *gem; | |
642 | struct tegra_bo *bo; | |
643 | ||
644 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) | |
645 | return -EINVAL; | |
646 | ||
647 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
648 | if (!gem) | |
649 | return -ENOENT; | |
650 | ||
651 | bo = to_tegra_bo(gem); | |
652 | bo->flags = 0; | |
653 | ||
654 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) | |
655 | bo->flags |= TEGRA_BO_BOTTOM_UP; | |
656 | ||
657 | drm_gem_object_unreference(gem); | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
662 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, | |
663 | struct drm_file *file) | |
664 | { | |
665 | struct drm_tegra_gem_get_flags *args = data; | |
666 | struct drm_gem_object *gem; | |
667 | struct tegra_bo *bo; | |
668 | ||
669 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
670 | if (!gem) | |
671 | return -ENOENT; | |
672 | ||
673 | bo = to_tegra_bo(gem); | |
674 | args->flags = 0; | |
675 | ||
676 | if (bo->flags & TEGRA_BO_BOTTOM_UP) | |
677 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; | |
678 | ||
679 | drm_gem_object_unreference(gem); | |
680 | ||
681 | return 0; | |
682 | } | |
d43f81cb TB |
683 | #endif |
684 | ||
baa70943 | 685 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
d43f81cb | 686 | #ifdef CONFIG_DRM_TEGRA_STAGING |
bd4f2360 | 687 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_UNLOCKED), |
d43f81cb TB |
688 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_UNLOCKED), |
689 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, DRM_UNLOCKED), | |
690 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, DRM_UNLOCKED), | |
691 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, DRM_UNLOCKED), | |
692 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, DRM_UNLOCKED), | |
693 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, DRM_UNLOCKED), | |
694 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, DRM_UNLOCKED), | |
695 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, DRM_UNLOCKED), | |
c54a169b | 696 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, DRM_UNLOCKED), |
7678d71f TR |
697 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, DRM_UNLOCKED), |
698 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, DRM_UNLOCKED), | |
7b129087 TR |
699 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, DRM_UNLOCKED), |
700 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, DRM_UNLOCKED), | |
d43f81cb | 701 | #endif |
d8f4a9ed TR |
702 | }; |
703 | ||
704 | static const struct file_operations tegra_drm_fops = { | |
705 | .owner = THIS_MODULE, | |
706 | .open = drm_open, | |
707 | .release = drm_release, | |
708 | .unlocked_ioctl = drm_ioctl, | |
de2ba664 | 709 | .mmap = tegra_drm_mmap, |
d8f4a9ed | 710 | .poll = drm_poll, |
d8f4a9ed TR |
711 | .read = drm_read, |
712 | #ifdef CONFIG_COMPAT | |
713 | .compat_ioctl = drm_compat_ioctl, | |
714 | #endif | |
715 | .llseek = noop_llseek, | |
716 | }; | |
717 | ||
ed7dae58 TR |
718 | static struct drm_crtc *tegra_crtc_from_pipe(struct drm_device *drm, |
719 | unsigned int pipe) | |
6e5ff998 TR |
720 | { |
721 | struct drm_crtc *crtc; | |
722 | ||
723 | list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) { | |
ed7dae58 | 724 | if (pipe == drm_crtc_index(crtc)) |
6e5ff998 TR |
725 | return crtc; |
726 | } | |
727 | ||
728 | return NULL; | |
729 | } | |
730 | ||
ed7dae58 | 731 | static u32 tegra_drm_get_vblank_counter(struct drm_device *drm, int pipe) |
6e5ff998 | 732 | { |
ed7dae58 TR |
733 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); |
734 | ||
735 | if (!crtc) | |
736 | return 0; | |
737 | ||
6e5ff998 | 738 | /* TODO: implement real hardware counter using syncpoints */ |
ed7dae58 | 739 | return drm_crtc_vblank_count(crtc); |
6e5ff998 TR |
740 | } |
741 | ||
742 | static int tegra_drm_enable_vblank(struct drm_device *drm, int pipe) | |
743 | { | |
744 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); | |
745 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
746 | ||
747 | if (!crtc) | |
748 | return -ENODEV; | |
749 | ||
750 | tegra_dc_enable_vblank(dc); | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
755 | static void tegra_drm_disable_vblank(struct drm_device *drm, int pipe) | |
756 | { | |
757 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); | |
758 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
759 | ||
760 | if (crtc) | |
761 | tegra_dc_disable_vblank(dc); | |
762 | } | |
763 | ||
3c03c46a TR |
764 | static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file) |
765 | { | |
08943e6c | 766 | struct tegra_drm_file *fpriv = file->driver_priv; |
c88c3630 | 767 | struct tegra_drm_context *context, *tmp; |
3c03c46a TR |
768 | struct drm_crtc *crtc; |
769 | ||
770 | list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) | |
771 | tegra_dc_cancel_page_flip(crtc, file); | |
d43f81cb TB |
772 | |
773 | list_for_each_entry_safe(context, tmp, &fpriv->contexts, list) | |
c88c3630 | 774 | tegra_drm_context_free(context); |
d43f81cb TB |
775 | |
776 | kfree(fpriv); | |
3c03c46a TR |
777 | } |
778 | ||
e450fcc6 TR |
779 | #ifdef CONFIG_DEBUG_FS |
780 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) | |
781 | { | |
782 | struct drm_info_node *node = (struct drm_info_node *)s->private; | |
783 | struct drm_device *drm = node->minor->dev; | |
784 | struct drm_framebuffer *fb; | |
785 | ||
786 | mutex_lock(&drm->mode_config.fb_lock); | |
787 | ||
788 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { | |
789 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", | |
790 | fb->base.id, fb->width, fb->height, fb->depth, | |
791 | fb->bits_per_pixel, | |
792 | atomic_read(&fb->refcount.refcount)); | |
793 | } | |
794 | ||
795 | mutex_unlock(&drm->mode_config.fb_lock); | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | static struct drm_info_list tegra_debugfs_list[] = { | |
801 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, | |
802 | }; | |
803 | ||
804 | static int tegra_debugfs_init(struct drm_minor *minor) | |
805 | { | |
806 | return drm_debugfs_create_files(tegra_debugfs_list, | |
807 | ARRAY_SIZE(tegra_debugfs_list), | |
808 | minor->debugfs_root, minor); | |
809 | } | |
810 | ||
811 | static void tegra_debugfs_cleanup(struct drm_minor *minor) | |
812 | { | |
813 | drm_debugfs_remove_files(tegra_debugfs_list, | |
814 | ARRAY_SIZE(tegra_debugfs_list), minor); | |
815 | } | |
816 | #endif | |
817 | ||
9b57f5f2 | 818 | static struct drm_driver tegra_drm_driver = { |
3800391d | 819 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, |
d8f4a9ed TR |
820 | .load = tegra_drm_load, |
821 | .unload = tegra_drm_unload, | |
822 | .open = tegra_drm_open, | |
3c03c46a | 823 | .preclose = tegra_drm_preclose, |
d8f4a9ed TR |
824 | .lastclose = tegra_drm_lastclose, |
825 | ||
6e5ff998 TR |
826 | .get_vblank_counter = tegra_drm_get_vblank_counter, |
827 | .enable_vblank = tegra_drm_enable_vblank, | |
828 | .disable_vblank = tegra_drm_disable_vblank, | |
829 | ||
e450fcc6 TR |
830 | #if defined(CONFIG_DEBUG_FS) |
831 | .debugfs_init = tegra_debugfs_init, | |
832 | .debugfs_cleanup = tegra_debugfs_cleanup, | |
833 | #endif | |
834 | ||
de2ba664 AM |
835 | .gem_free_object = tegra_bo_free_object, |
836 | .gem_vm_ops = &tegra_bo_vm_ops, | |
3800391d TR |
837 | |
838 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
839 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
840 | .gem_prime_export = tegra_gem_prime_export, | |
841 | .gem_prime_import = tegra_gem_prime_import, | |
842 | ||
de2ba664 AM |
843 | .dumb_create = tegra_bo_dumb_create, |
844 | .dumb_map_offset = tegra_bo_dumb_map_offset, | |
43387b37 | 845 | .dumb_destroy = drm_gem_dumb_destroy, |
d8f4a9ed TR |
846 | |
847 | .ioctls = tegra_drm_ioctls, | |
848 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), | |
849 | .fops = &tegra_drm_fops, | |
850 | ||
851 | .name = DRIVER_NAME, | |
852 | .desc = DRIVER_DESC, | |
853 | .date = DRIVER_DATE, | |
854 | .major = DRIVER_MAJOR, | |
855 | .minor = DRIVER_MINOR, | |
856 | .patchlevel = DRIVER_PATCHLEVEL, | |
857 | }; | |
776dc384 TR |
858 | |
859 | int tegra_drm_register_client(struct tegra_drm *tegra, | |
860 | struct tegra_drm_client *client) | |
861 | { | |
862 | mutex_lock(&tegra->clients_lock); | |
863 | list_add_tail(&client->list, &tegra->clients); | |
864 | mutex_unlock(&tegra->clients_lock); | |
865 | ||
866 | return 0; | |
867 | } | |
868 | ||
869 | int tegra_drm_unregister_client(struct tegra_drm *tegra, | |
870 | struct tegra_drm_client *client) | |
871 | { | |
872 | mutex_lock(&tegra->clients_lock); | |
873 | list_del_init(&client->list); | |
874 | mutex_unlock(&tegra->clients_lock); | |
875 | ||
876 | return 0; | |
877 | } | |
878 | ||
9910f5c4 | 879 | static int host1x_drm_probe(struct host1x_device *dev) |
776dc384 | 880 | { |
9910f5c4 TR |
881 | struct drm_driver *driver = &tegra_drm_driver; |
882 | struct drm_device *drm; | |
883 | int err; | |
884 | ||
885 | drm = drm_dev_alloc(driver, &dev->dev); | |
886 | if (!drm) | |
887 | return -ENOMEM; | |
888 | ||
889 | drm_dev_set_unique(drm, dev_name(&dev->dev)); | |
890 | dev_set_drvdata(&dev->dev, drm); | |
891 | ||
892 | err = drm_dev_register(drm, 0); | |
893 | if (err < 0) | |
894 | goto unref; | |
895 | ||
896 | DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name, | |
897 | driver->major, driver->minor, driver->patchlevel, | |
898 | driver->date, drm->primary->index); | |
899 | ||
900 | return 0; | |
901 | ||
902 | unref: | |
903 | drm_dev_unref(drm); | |
904 | return err; | |
776dc384 TR |
905 | } |
906 | ||
9910f5c4 | 907 | static int host1x_drm_remove(struct host1x_device *dev) |
776dc384 | 908 | { |
9910f5c4 TR |
909 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
910 | ||
911 | drm_dev_unregister(drm); | |
912 | drm_dev_unref(drm); | |
776dc384 TR |
913 | |
914 | return 0; | |
915 | } | |
916 | ||
917 | static const struct of_device_id host1x_drm_subdevs[] = { | |
918 | { .compatible = "nvidia,tegra20-dc", }, | |
919 | { .compatible = "nvidia,tegra20-hdmi", }, | |
920 | { .compatible = "nvidia,tegra20-gr2d", }, | |
5f60ed0d | 921 | { .compatible = "nvidia,tegra20-gr3d", }, |
776dc384 TR |
922 | { .compatible = "nvidia,tegra30-dc", }, |
923 | { .compatible = "nvidia,tegra30-hdmi", }, | |
924 | { .compatible = "nvidia,tegra30-gr2d", }, | |
5f60ed0d | 925 | { .compatible = "nvidia,tegra30-gr3d", }, |
dec72739 | 926 | { .compatible = "nvidia,tegra114-dsi", }, |
7d1d28ac | 927 | { .compatible = "nvidia,tegra114-hdmi", }, |
5f60ed0d | 928 | { .compatible = "nvidia,tegra114-gr3d", }, |
8620fc62 | 929 | { .compatible = "nvidia,tegra124-dc", }, |
6b6b6042 | 930 | { .compatible = "nvidia,tegra124-sor", }, |
fb7be70e | 931 | { .compatible = "nvidia,tegra124-hdmi", }, |
776dc384 TR |
932 | { /* sentinel */ } |
933 | }; | |
934 | ||
935 | static struct host1x_driver host1x_drm_driver = { | |
f4c5cf88 TR |
936 | .driver = { |
937 | .name = "drm", | |
938 | }, | |
776dc384 TR |
939 | .probe = host1x_drm_probe, |
940 | .remove = host1x_drm_remove, | |
941 | .subdevs = host1x_drm_subdevs, | |
942 | }; | |
943 | ||
944 | static int __init host1x_drm_init(void) | |
945 | { | |
946 | int err; | |
947 | ||
948 | err = host1x_driver_register(&host1x_drm_driver); | |
949 | if (err < 0) | |
950 | return err; | |
951 | ||
952 | err = platform_driver_register(&tegra_dc_driver); | |
953 | if (err < 0) | |
954 | goto unregister_host1x; | |
955 | ||
dec72739 | 956 | err = platform_driver_register(&tegra_dsi_driver); |
776dc384 TR |
957 | if (err < 0) |
958 | goto unregister_dc; | |
959 | ||
6b6b6042 | 960 | err = platform_driver_register(&tegra_sor_driver); |
dec72739 TR |
961 | if (err < 0) |
962 | goto unregister_dsi; | |
963 | ||
6b6b6042 TR |
964 | err = platform_driver_register(&tegra_hdmi_driver); |
965 | if (err < 0) | |
966 | goto unregister_sor; | |
967 | ||
968 | err = platform_driver_register(&tegra_dpaux_driver); | |
776dc384 TR |
969 | if (err < 0) |
970 | goto unregister_hdmi; | |
971 | ||
6b6b6042 TR |
972 | err = platform_driver_register(&tegra_gr2d_driver); |
973 | if (err < 0) | |
974 | goto unregister_dpaux; | |
975 | ||
5f60ed0d TR |
976 | err = platform_driver_register(&tegra_gr3d_driver); |
977 | if (err < 0) | |
978 | goto unregister_gr2d; | |
979 | ||
776dc384 TR |
980 | return 0; |
981 | ||
5f60ed0d TR |
982 | unregister_gr2d: |
983 | platform_driver_unregister(&tegra_gr2d_driver); | |
6b6b6042 TR |
984 | unregister_dpaux: |
985 | platform_driver_unregister(&tegra_dpaux_driver); | |
776dc384 TR |
986 | unregister_hdmi: |
987 | platform_driver_unregister(&tegra_hdmi_driver); | |
6b6b6042 TR |
988 | unregister_sor: |
989 | platform_driver_unregister(&tegra_sor_driver); | |
dec72739 TR |
990 | unregister_dsi: |
991 | platform_driver_unregister(&tegra_dsi_driver); | |
776dc384 TR |
992 | unregister_dc: |
993 | platform_driver_unregister(&tegra_dc_driver); | |
994 | unregister_host1x: | |
995 | host1x_driver_unregister(&host1x_drm_driver); | |
996 | return err; | |
997 | } | |
998 | module_init(host1x_drm_init); | |
999 | ||
1000 | static void __exit host1x_drm_exit(void) | |
1001 | { | |
5f60ed0d | 1002 | platform_driver_unregister(&tegra_gr3d_driver); |
776dc384 | 1003 | platform_driver_unregister(&tegra_gr2d_driver); |
6b6b6042 | 1004 | platform_driver_unregister(&tegra_dpaux_driver); |
776dc384 | 1005 | platform_driver_unregister(&tegra_hdmi_driver); |
6b6b6042 | 1006 | platform_driver_unregister(&tegra_sor_driver); |
dec72739 | 1007 | platform_driver_unregister(&tegra_dsi_driver); |
776dc384 TR |
1008 | platform_driver_unregister(&tegra_dc_driver); |
1009 | host1x_driver_unregister(&host1x_drm_driver); | |
1010 | } | |
1011 | module_exit(host1x_drm_exit); | |
1012 | ||
1013 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); | |
1014 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); | |
1015 | MODULE_LICENSE("GPL v2"); |