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CommitLineData
d8f4a9ed
TR
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
ad926015 3 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
d8f4a9ed
TR
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
ad926015 10#include <linux/bitops.h>
776dc384 11#include <linux/host1x.h>
bdd2f9cd 12#include <linux/idr.h>
df06b759 13#include <linux/iommu.h>
776dc384 14
1503ca47 15#include <drm/drm_atomic.h>
07866963
TR
16#include <drm/drm_atomic_helper.h>
17
d8f4a9ed 18#include "drm.h"
de2ba664 19#include "gem.h"
d8f4a9ed
TR
20
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
ad926015 28#define CARVEOUT_SZ SZ_64M
368f622c 29#define CDMA_GATHER_FETCHES_MAX_NB 16383
ad926015 30
08943e6c 31struct tegra_drm_file {
bdd2f9cd
TR
32 struct idr contexts;
33 struct mutex lock;
08943e6c
TR
34};
35
1503ca47
TR
36static void tegra_atomic_schedule(struct tegra_drm *tegra,
37 struct drm_atomic_state *state)
38{
39 tegra->commit.state = state;
40 schedule_work(&tegra->commit.work);
41}
42
43static void tegra_atomic_complete(struct tegra_drm *tegra,
44 struct drm_atomic_state *state)
45{
46 struct drm_device *drm = tegra->drm;
47
48 /*
49 * Everything below can be run asynchronously without the need to grab
50 * any modeset locks at all under one condition: It must be guaranteed
51 * that the asynchronous work has either been cancelled (if the driver
52 * supports it, which at least requires that the framebuffers get
53 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
54 * before the new state gets committed on the software side with
55 * drm_atomic_helper_swap_state().
56 *
57 * This scheme allows new atomic state updates to be prepared and
58 * checked in parallel to the asynchronous completion of the previous
59 * update. Which is important since compositors need to figure out the
60 * composition of the next frame right after having submitted the
61 * current layout.
62 */
63
1af434a9 64 drm_atomic_helper_commit_modeset_disables(drm, state);
1af434a9 65 drm_atomic_helper_commit_modeset_enables(drm, state);
2b58e98d
LY
66 drm_atomic_helper_commit_planes(drm, state,
67 DRM_PLANE_COMMIT_ACTIVE_ONLY);
1503ca47
TR
68
69 drm_atomic_helper_wait_for_vblanks(drm, state);
70
71 drm_atomic_helper_cleanup_planes(drm, state);
0853695c 72 drm_atomic_state_put(state);
1503ca47
TR
73}
74
75static void tegra_atomic_work(struct work_struct *work)
76{
77 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
78 commit.work);
79
80 tegra_atomic_complete(tegra, tegra->commit.state);
81}
82
83static int tegra_atomic_commit(struct drm_device *drm,
2dacdd70 84 struct drm_atomic_state *state, bool nonblock)
1503ca47
TR
85{
86 struct tegra_drm *tegra = drm->dev_private;
87 int err;
88
89 err = drm_atomic_helper_prepare_planes(drm, state);
90 if (err)
91 return err;
92
2dacdd70 93 /* serialize outstanding nonblocking commits */
1503ca47
TR
94 mutex_lock(&tegra->commit.lock);
95 flush_work(&tegra->commit.work);
96
97 /*
98 * This is the point of no return - everything below never fails except
99 * when the hw goes bonghits. Which means we can commit the new state on
100 * the software side now.
101 */
102
5e84c269 103 drm_atomic_helper_swap_state(state, true);
1503ca47 104
0853695c 105 drm_atomic_state_get(state);
2dacdd70 106 if (nonblock)
1503ca47
TR
107 tegra_atomic_schedule(tegra, state);
108 else
109 tegra_atomic_complete(tegra, state);
110
111 mutex_unlock(&tegra->commit.lock);
112 return 0;
113}
114
f9914214
TR
115static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
116 .fb_create = tegra_fb_create,
b110ef37 117#ifdef CONFIG_DRM_FBDEV_EMULATION
f9914214
TR
118 .output_poll_changed = tegra_fb_output_poll_changed,
119#endif
07866963 120 .atomic_check = drm_atomic_helper_check,
1503ca47 121 .atomic_commit = tegra_atomic_commit,
f9914214
TR
122};
123
776dc384 124static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
692e6d7b 125{
776dc384 126 struct host1x_device *device = to_host1x_device(drm->dev);
386a2a71 127 struct tegra_drm *tegra;
692e6d7b
TB
128 int err;
129
776dc384 130 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
386a2a71 131 if (!tegra)
692e6d7b
TB
132 return -ENOMEM;
133
df06b759 134 if (iommu_present(&platform_bus_type)) {
ad926015 135 u64 carveout_start, carveout_end, gem_start, gem_end;
4553f733 136 struct iommu_domain_geometry *geometry;
ad926015 137 unsigned long order;
4553f733 138
df06b759 139 tegra->domain = iommu_domain_alloc(&platform_bus_type);
bf19b885
DC
140 if (!tegra->domain) {
141 err = -ENOMEM;
df06b759
TR
142 goto free;
143 }
144
4553f733 145 geometry = &tegra->domain->geometry;
ad926015
MP
146 gem_start = geometry->aperture_start;
147 gem_end = geometry->aperture_end - CARVEOUT_SZ;
148 carveout_start = gem_end + 1;
149 carveout_end = geometry->aperture_end;
150
151 order = __ffs(tegra->domain->pgsize_bitmap);
152 init_iova_domain(&tegra->carveout.domain, 1UL << order,
153 carveout_start >> order,
154 carveout_end >> order);
4553f733 155
ad926015
MP
156 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
157 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
158
159 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
347ad49d 160 mutex_init(&tegra->mm_lock);
ad926015
MP
161
162 DRM_DEBUG("IOMMU apertures:\n");
163 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
164 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
165 carveout_end);
df06b759
TR
166 }
167
386a2a71
TR
168 mutex_init(&tegra->clients_lock);
169 INIT_LIST_HEAD(&tegra->clients);
1503ca47
TR
170
171 mutex_init(&tegra->commit.lock);
172 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
173
386a2a71
TR
174 drm->dev_private = tegra;
175 tegra->drm = drm;
d8f4a9ed
TR
176
177 drm_mode_config_init(drm);
178
f9914214
TR
179 drm->mode_config.min_width = 0;
180 drm->mode_config.min_height = 0;
181
182 drm->mode_config.max_width = 4096;
183 drm->mode_config.max_height = 4096;
184
5e91144d
AC
185 drm->mode_config.allow_fb_modifiers = true;
186
f9914214
TR
187 drm->mode_config.funcs = &tegra_drm_mode_funcs;
188
e2215321
TR
189 err = tegra_drm_fb_prepare(drm);
190 if (err < 0)
1d1e6fe9 191 goto config;
e2215321
TR
192
193 drm_kms_helper_poll_init(drm);
194
776dc384 195 err = host1x_device_init(device);
d8f4a9ed 196 if (err < 0)
1d1e6fe9 197 goto fbdev;
d8f4a9ed 198
603f0cc9
TR
199 /*
200 * We don't use the drm_irq_install() helpers provided by the DRM
201 * core, so we need to set this manually in order to allow the
202 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
203 */
4423843c 204 drm->irq_enabled = true;
603f0cc9 205
42e9ce05 206 /* syncpoints are used for full 32-bit hardware VBLANK counters */
42e9ce05
TR
207 drm->max_vblank_count = 0xffffffff;
208
6e5ff998
TR
209 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
210 if (err < 0)
1d1e6fe9 211 goto device;
6e5ff998 212
31930d4d
TR
213 drm_mode_config_reset(drm);
214
d8f4a9ed
TR
215 err = tegra_drm_fb_init(drm);
216 if (err < 0)
1d1e6fe9 217 goto vblank;
d8f4a9ed 218
d8f4a9ed 219 return 0;
1d1e6fe9
TR
220
221vblank:
222 drm_vblank_cleanup(drm);
223device:
224 host1x_device_exit(device);
225fbdev:
226 drm_kms_helper_poll_fini(drm);
227 tegra_drm_fb_free(drm);
228config:
229 drm_mode_config_cleanup(drm);
df06b759
TR
230
231 if (tegra->domain) {
232 iommu_domain_free(tegra->domain);
233 drm_mm_takedown(&tegra->mm);
347ad49d 234 mutex_destroy(&tegra->mm_lock);
ad926015 235 put_iova_domain(&tegra->carveout.domain);
df06b759
TR
236 }
237free:
1d1e6fe9
TR
238 kfree(tegra);
239 return err;
d8f4a9ed
TR
240}
241
11b3c20b 242static void tegra_drm_unload(struct drm_device *drm)
d8f4a9ed 243{
776dc384 244 struct host1x_device *device = to_host1x_device(drm->dev);
df06b759 245 struct tegra_drm *tegra = drm->dev_private;
776dc384
TR
246 int err;
247
d8f4a9ed
TR
248 drm_kms_helper_poll_fini(drm);
249 tegra_drm_fb_exit(drm);
f002abc1 250 drm_mode_config_cleanup(drm);
4aa3df71 251 drm_vblank_cleanup(drm);
d8f4a9ed 252
776dc384
TR
253 err = host1x_device_exit(device);
254 if (err < 0)
11b3c20b 255 return;
776dc384 256
df06b759
TR
257 if (tegra->domain) {
258 iommu_domain_free(tegra->domain);
259 drm_mm_takedown(&tegra->mm);
347ad49d 260 mutex_destroy(&tegra->mm_lock);
ad926015 261 put_iova_domain(&tegra->carveout.domain);
df06b759
TR
262 }
263
1053f4dd 264 kfree(tegra);
d8f4a9ed
TR
265}
266
267static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
268{
08943e6c 269 struct tegra_drm_file *fpriv;
d43f81cb
TB
270
271 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
272 if (!fpriv)
273 return -ENOMEM;
274
bdd2f9cd
TR
275 idr_init(&fpriv->contexts);
276 mutex_init(&fpriv->lock);
d43f81cb
TB
277 filp->driver_priv = fpriv;
278
d8f4a9ed
TR
279 return 0;
280}
281
c88c3630 282static void tegra_drm_context_free(struct tegra_drm_context *context)
d43f81cb
TB
283{
284 context->client->ops->close_channel(context);
285 kfree(context);
286}
287
d8f4a9ed
TR
288static void tegra_drm_lastclose(struct drm_device *drm)
289{
b110ef37 290#ifdef CONFIG_DRM_FBDEV_EMULATION
386a2a71 291 struct tegra_drm *tegra = drm->dev_private;
d8f4a9ed 292
386a2a71 293 tegra_fbdev_restore_mode(tegra->fbdev);
60c2f709 294#endif
d8f4a9ed
TR
295}
296
c40f0f1a 297static struct host1x_bo *
a8ad0bd8 298host1x_bo_lookup(struct drm_file *file, u32 handle)
c40f0f1a
TR
299{
300 struct drm_gem_object *gem;
301 struct tegra_bo *bo;
302
a8ad0bd8 303 gem = drm_gem_object_lookup(file, handle);
c40f0f1a
TR
304 if (!gem)
305 return NULL;
306
a07cdfe5 307 drm_gem_object_unreference_unlocked(gem);
c40f0f1a
TR
308
309 bo = to_tegra_bo(gem);
310 return &bo->base;
311}
312
961e3bea
TR
313static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
314 struct drm_tegra_reloc __user *src,
315 struct drm_device *drm,
316 struct drm_file *file)
317{
318 u32 cmdbuf, target;
319 int err;
320
321 err = get_user(cmdbuf, &src->cmdbuf.handle);
322 if (err < 0)
323 return err;
324
325 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
326 if (err < 0)
327 return err;
328
329 err = get_user(target, &src->target.handle);
330 if (err < 0)
331 return err;
332
31f40f86 333 err = get_user(dest->target.offset, &src->target.offset);
961e3bea
TR
334 if (err < 0)
335 return err;
336
337 err = get_user(dest->shift, &src->shift);
338 if (err < 0)
339 return err;
340
a8ad0bd8 341 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
961e3bea
TR
342 if (!dest->cmdbuf.bo)
343 return -ENOENT;
344
a8ad0bd8 345 dest->target.bo = host1x_bo_lookup(file, target);
961e3bea
TR
346 if (!dest->target.bo)
347 return -ENOENT;
348
349 return 0;
350}
351
d0fbbdff
DO
352static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
353 struct drm_tegra_waitchk __user *src,
354 struct drm_file *file)
355{
356 u32 cmdbuf;
357 int err;
358
359 err = get_user(cmdbuf, &src->handle);
360 if (err < 0)
361 return err;
362
363 err = get_user(dest->offset, &src->offset);
364 if (err < 0)
365 return err;
366
367 err = get_user(dest->syncpt_id, &src->syncpt);
368 if (err < 0)
369 return err;
370
371 err = get_user(dest->thresh, &src->thresh);
372 if (err < 0)
373 return err;
374
375 dest->bo = host1x_bo_lookup(file, cmdbuf);
376 if (!dest->bo)
377 return -ENOENT;
378
379 return 0;
380}
381
c40f0f1a
TR
382int tegra_drm_submit(struct tegra_drm_context *context,
383 struct drm_tegra_submit *args, struct drm_device *drm,
384 struct drm_file *file)
385{
386 unsigned int num_cmdbufs = args->num_cmdbufs;
387 unsigned int num_relocs = args->num_relocs;
388 unsigned int num_waitchks = args->num_waitchks;
389 struct drm_tegra_cmdbuf __user *cmdbufs =
a7ed68fc 390 (void __user *)(uintptr_t)args->cmdbufs;
c40f0f1a 391 struct drm_tegra_reloc __user *relocs =
a7ed68fc 392 (void __user *)(uintptr_t)args->relocs;
c40f0f1a 393 struct drm_tegra_waitchk __user *waitchks =
a7ed68fc 394 (void __user *)(uintptr_t)args->waitchks;
c40f0f1a 395 struct drm_tegra_syncpt syncpt;
e0b2ce02
DO
396 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
397 struct host1x_syncpt *sp;
c40f0f1a
TR
398 struct host1x_job *job;
399 int err;
400
401 /* We don't yet support other than one syncpt_incr struct per submit */
402 if (args->num_syncpts != 1)
403 return -EINVAL;
404
d0fbbdff
DO
405 /* We don't yet support waitchks */
406 if (args->num_waitchks != 0)
407 return -EINVAL;
408
c40f0f1a
TR
409 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
410 args->num_relocs, args->num_waitchks);
411 if (!job)
412 return -ENOMEM;
413
414 job->num_relocs = args->num_relocs;
415 job->num_waitchk = args->num_waitchks;
416 job->client = (u32)args->context;
417 job->class = context->client->base.class;
418 job->serialize = true;
419
420 while (num_cmdbufs) {
421 struct drm_tegra_cmdbuf cmdbuf;
422 struct host1x_bo *bo;
368f622c
DO
423 struct tegra_bo *obj;
424 u64 offset;
c40f0f1a 425
9a991600
DC
426 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
427 err = -EFAULT;
c40f0f1a 428 goto fail;
9a991600 429 }
c40f0f1a 430
368f622c
DO
431 /*
432 * The maximum number of CDMA gather fetches is 16383, a higher
433 * value means the words count is malformed.
434 */
435 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
436 err = -EINVAL;
437 goto fail;
438 }
439
a8ad0bd8 440 bo = host1x_bo_lookup(file, cmdbuf.handle);
c40f0f1a
TR
441 if (!bo) {
442 err = -ENOENT;
443 goto fail;
444 }
445
368f622c
DO
446 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
447 obj = host1x_to_tegra_bo(bo);
448
449 /*
450 * Gather buffer base address must be 4-bytes aligned,
451 * unaligned offset is malformed and cause commands stream
452 * corruption on the buffer address relocation.
453 */
454 if (offset & 3 || offset >= obj->gem.size) {
455 err = -EINVAL;
456 goto fail;
457 }
458
c40f0f1a
TR
459 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
460 num_cmdbufs--;
461 cmdbufs++;
462 }
463
961e3bea 464 /* copy and resolve relocations from submit */
c40f0f1a 465 while (num_relocs--) {
368f622c
DO
466 struct host1x_reloc *reloc;
467 struct tegra_bo *obj;
468
961e3bea
TR
469 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
470 &relocs[num_relocs], drm,
471 file);
472 if (err < 0)
c40f0f1a 473 goto fail;
368f622c
DO
474
475 reloc = &job->relocarray[num_relocs];
476 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
477
478 /*
479 * The unaligned cmdbuf offset will cause an unaligned write
480 * during of the relocations patching, corrupting the commands
481 * stream.
482 */
483 if (reloc->cmdbuf.offset & 3 ||
484 reloc->cmdbuf.offset >= obj->gem.size) {
485 err = -EINVAL;
486 goto fail;
487 }
488
489 obj = host1x_to_tegra_bo(reloc->target.bo);
490
491 if (reloc->target.offset >= obj->gem.size) {
492 err = -EINVAL;
493 goto fail;
494 }
c40f0f1a
TR
495 }
496
d0fbbdff
DO
497 /* copy and resolve waitchks from submit */
498 while (num_waitchks--) {
499 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
500 struct tegra_bo *obj;
501
502 err = host1x_waitchk_copy_from_user(wait,
503 &waitchks[num_waitchks],
504 file);
505 if (err < 0)
506 goto fail;
507
508 obj = host1x_to_tegra_bo(wait->bo);
509
510 /*
511 * The unaligned offset will cause an unaligned write during
512 * of the waitchks patching, corrupting the commands stream.
513 */
514 if (wait->offset & 3 ||
515 wait->offset >= obj->gem.size) {
516 err = -EINVAL;
517 goto fail;
518 }
9a991600 519 }
c40f0f1a 520
9a991600
DC
521 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
522 sizeof(syncpt))) {
523 err = -EFAULT;
c40f0f1a 524 goto fail;
9a991600 525 }
c40f0f1a 526
e0b2ce02
DO
527 /* check whether syncpoint ID is valid */
528 sp = host1x_syncpt_get(host1x, syncpt.id);
529 if (!sp) {
530 err = -ENOENT;
531 goto fail;
532 }
533
c40f0f1a 534 job->is_addr_reg = context->client->ops->is_addr_reg;
0f563a4b 535 job->is_valid_class = context->client->ops->is_valid_class;
c40f0f1a
TR
536 job->syncpt_incrs = syncpt.incrs;
537 job->syncpt_id = syncpt.id;
538 job->timeout = 10000;
539
540 if (args->timeout && args->timeout < 10000)
541 job->timeout = args->timeout;
542
543 err = host1x_job_pin(job, context->client->base.dev);
544 if (err)
545 goto fail;
546
547 err = host1x_job_submit(job);
548 if (err)
549 goto fail_submit;
550
551 args->fence = job->syncpt_end;
552
553 host1x_job_put(job);
554 return 0;
555
556fail_submit:
557 host1x_job_unpin(job);
558fail:
559 host1x_job_put(job);
560 return err;
561}
562
563
d43f81cb 564#ifdef CONFIG_DRM_TEGRA_STAGING
d43f81cb
TB
565static int tegra_gem_create(struct drm_device *drm, void *data,
566 struct drm_file *file)
567{
568 struct drm_tegra_gem_create *args = data;
569 struct tegra_bo *bo;
570
773af77f 571 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
d43f81cb
TB
572 &args->handle);
573 if (IS_ERR(bo))
574 return PTR_ERR(bo);
575
576 return 0;
577}
578
579static int tegra_gem_mmap(struct drm_device *drm, void *data,
580 struct drm_file *file)
581{
582 struct drm_tegra_gem_mmap *args = data;
583 struct drm_gem_object *gem;
584 struct tegra_bo *bo;
585
a8ad0bd8 586 gem = drm_gem_object_lookup(file, args->handle);
d43f81cb
TB
587 if (!gem)
588 return -EINVAL;
589
590 bo = to_tegra_bo(gem);
591
2bc7b0ca 592 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
d43f81cb 593
11533304 594 drm_gem_object_unreference_unlocked(gem);
d43f81cb
TB
595
596 return 0;
597}
598
599static int tegra_syncpt_read(struct drm_device *drm, void *data,
600 struct drm_file *file)
601{
776dc384 602 struct host1x *host = dev_get_drvdata(drm->dev->parent);
d43f81cb 603 struct drm_tegra_syncpt_read *args = data;
776dc384 604 struct host1x_syncpt *sp;
d43f81cb 605
776dc384 606 sp = host1x_syncpt_get(host, args->id);
d43f81cb
TB
607 if (!sp)
608 return -EINVAL;
609
610 args->value = host1x_syncpt_read_min(sp);
611 return 0;
612}
613
614static int tegra_syncpt_incr(struct drm_device *drm, void *data,
615 struct drm_file *file)
616{
776dc384 617 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
d43f81cb 618 struct drm_tegra_syncpt_incr *args = data;
776dc384 619 struct host1x_syncpt *sp;
d43f81cb 620
776dc384 621 sp = host1x_syncpt_get(host1x, args->id);
d43f81cb
TB
622 if (!sp)
623 return -EINVAL;
624
ebae30b1 625 return host1x_syncpt_incr(sp);
d43f81cb
TB
626}
627
628static int tegra_syncpt_wait(struct drm_device *drm, void *data,
629 struct drm_file *file)
630{
776dc384 631 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
d43f81cb 632 struct drm_tegra_syncpt_wait *args = data;
776dc384 633 struct host1x_syncpt *sp;
d43f81cb 634
776dc384 635 sp = host1x_syncpt_get(host1x, args->id);
d43f81cb
TB
636 if (!sp)
637 return -EINVAL;
638
639 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
640 &args->value);
641}
642
bdd2f9cd
TR
643static int tegra_client_open(struct tegra_drm_file *fpriv,
644 struct tegra_drm_client *client,
645 struct tegra_drm_context *context)
646{
647 int err;
648
649 err = client->ops->open_channel(client, context);
650 if (err < 0)
651 return err;
652
d6c153ec 653 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
bdd2f9cd
TR
654 if (err < 0) {
655 client->ops->close_channel(context);
656 return err;
657 }
658
659 context->client = client;
660 context->id = err;
661
662 return 0;
663}
664
d43f81cb
TB
665static int tegra_open_channel(struct drm_device *drm, void *data,
666 struct drm_file *file)
667{
08943e6c 668 struct tegra_drm_file *fpriv = file->driver_priv;
386a2a71 669 struct tegra_drm *tegra = drm->dev_private;
d43f81cb 670 struct drm_tegra_open_channel *args = data;
c88c3630 671 struct tegra_drm_context *context;
53fa7f72 672 struct tegra_drm_client *client;
d43f81cb
TB
673 int err = -ENODEV;
674
675 context = kzalloc(sizeof(*context), GFP_KERNEL);
676 if (!context)
677 return -ENOMEM;
678
bdd2f9cd
TR
679 mutex_lock(&fpriv->lock);
680
776dc384 681 list_for_each_entry(client, &tegra->clients, list)
53fa7f72 682 if (client->base.class == args->client) {
bdd2f9cd
TR
683 err = tegra_client_open(fpriv, client, context);
684 if (err < 0)
d43f81cb
TB
685 break;
686
bdd2f9cd
TR
687 args->context = context->id;
688 break;
d43f81cb
TB
689 }
690
bdd2f9cd
TR
691 if (err < 0)
692 kfree(context);
693
694 mutex_unlock(&fpriv->lock);
d43f81cb
TB
695 return err;
696}
697
698static int tegra_close_channel(struct drm_device *drm, void *data,
699 struct drm_file *file)
700{
08943e6c 701 struct tegra_drm_file *fpriv = file->driver_priv;
776dc384 702 struct drm_tegra_close_channel *args = data;
c88c3630 703 struct tegra_drm_context *context;
bdd2f9cd 704 int err = 0;
c88c3630 705
bdd2f9cd 706 mutex_lock(&fpriv->lock);
d43f81cb 707
1066a895 708 context = idr_find(&fpriv->contexts, args->context);
bdd2f9cd
TR
709 if (!context) {
710 err = -EINVAL;
711 goto unlock;
712 }
d43f81cb 713
bdd2f9cd 714 idr_remove(&fpriv->contexts, context->id);
c88c3630 715 tegra_drm_context_free(context);
d43f81cb 716
bdd2f9cd
TR
717unlock:
718 mutex_unlock(&fpriv->lock);
719 return err;
d43f81cb
TB
720}
721
722static int tegra_get_syncpt(struct drm_device *drm, void *data,
723 struct drm_file *file)
724{
08943e6c 725 struct tegra_drm_file *fpriv = file->driver_priv;
d43f81cb 726 struct drm_tegra_get_syncpt *args = data;
c88c3630 727 struct tegra_drm_context *context;
d43f81cb 728 struct host1x_syncpt *syncpt;
bdd2f9cd 729 int err = 0;
d43f81cb 730
bdd2f9cd 731 mutex_lock(&fpriv->lock);
c88c3630 732
1066a895 733 context = idr_find(&fpriv->contexts, args->context);
bdd2f9cd
TR
734 if (!context) {
735 err = -ENODEV;
736 goto unlock;
737 }
d43f81cb 738
bdd2f9cd
TR
739 if (args->index >= context->client->base.num_syncpts) {
740 err = -EINVAL;
741 goto unlock;
742 }
d43f81cb 743
53fa7f72 744 syncpt = context->client->base.syncpts[args->index];
d43f81cb
TB
745 args->id = host1x_syncpt_id(syncpt);
746
bdd2f9cd
TR
747unlock:
748 mutex_unlock(&fpriv->lock);
749 return err;
d43f81cb
TB
750}
751
752static int tegra_submit(struct drm_device *drm, void *data,
753 struct drm_file *file)
754{
08943e6c 755 struct tegra_drm_file *fpriv = file->driver_priv;
d43f81cb 756 struct drm_tegra_submit *args = data;
c88c3630 757 struct tegra_drm_context *context;
bdd2f9cd 758 int err;
c88c3630 759
bdd2f9cd 760 mutex_lock(&fpriv->lock);
d43f81cb 761
1066a895 762 context = idr_find(&fpriv->contexts, args->context);
bdd2f9cd
TR
763 if (!context) {
764 err = -ENODEV;
765 goto unlock;
766 }
d43f81cb 767
bdd2f9cd 768 err = context->client->ops->submit(context, args, drm, file);
d43f81cb 769
bdd2f9cd
TR
770unlock:
771 mutex_unlock(&fpriv->lock);
772 return err;
d43f81cb 773}
c54a169b
AM
774
775static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
776 struct drm_file *file)
777{
778 struct tegra_drm_file *fpriv = file->driver_priv;
779 struct drm_tegra_get_syncpt_base *args = data;
780 struct tegra_drm_context *context;
781 struct host1x_syncpt_base *base;
782 struct host1x_syncpt *syncpt;
bdd2f9cd 783 int err = 0;
c54a169b 784
bdd2f9cd 785 mutex_lock(&fpriv->lock);
c54a169b 786
1066a895 787 context = idr_find(&fpriv->contexts, args->context);
bdd2f9cd
TR
788 if (!context) {
789 err = -ENODEV;
790 goto unlock;
791 }
c54a169b 792
bdd2f9cd
TR
793 if (args->syncpt >= context->client->base.num_syncpts) {
794 err = -EINVAL;
795 goto unlock;
796 }
c54a169b
AM
797
798 syncpt = context->client->base.syncpts[args->syncpt];
799
800 base = host1x_syncpt_get_base(syncpt);
bdd2f9cd
TR
801 if (!base) {
802 err = -ENXIO;
803 goto unlock;
804 }
c54a169b
AM
805
806 args->id = host1x_syncpt_base_id(base);
807
bdd2f9cd
TR
808unlock:
809 mutex_unlock(&fpriv->lock);
810 return err;
c54a169b 811}
7678d71f
TR
812
813static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
814 struct drm_file *file)
815{
816 struct drm_tegra_gem_set_tiling *args = data;
817 enum tegra_bo_tiling_mode mode;
818 struct drm_gem_object *gem;
819 unsigned long value = 0;
820 struct tegra_bo *bo;
821
822 switch (args->mode) {
823 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
824 mode = TEGRA_BO_TILING_MODE_PITCH;
825
826 if (args->value != 0)
827 return -EINVAL;
828
829 break;
830
831 case DRM_TEGRA_GEM_TILING_MODE_TILED:
832 mode = TEGRA_BO_TILING_MODE_TILED;
833
834 if (args->value != 0)
835 return -EINVAL;
836
837 break;
838
839 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
840 mode = TEGRA_BO_TILING_MODE_BLOCK;
841
842 if (args->value > 5)
843 return -EINVAL;
844
845 value = args->value;
846 break;
847
848 default:
849 return -EINVAL;
850 }
851
a8ad0bd8 852 gem = drm_gem_object_lookup(file, args->handle);
7678d71f
TR
853 if (!gem)
854 return -ENOENT;
855
856 bo = to_tegra_bo(gem);
857
858 bo->tiling.mode = mode;
859 bo->tiling.value = value;
860
11533304 861 drm_gem_object_unreference_unlocked(gem);
7678d71f
TR
862
863 return 0;
864}
865
866static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
867 struct drm_file *file)
868{
869 struct drm_tegra_gem_get_tiling *args = data;
870 struct drm_gem_object *gem;
871 struct tegra_bo *bo;
872 int err = 0;
873
a8ad0bd8 874 gem = drm_gem_object_lookup(file, args->handle);
7678d71f
TR
875 if (!gem)
876 return -ENOENT;
877
878 bo = to_tegra_bo(gem);
879
880 switch (bo->tiling.mode) {
881 case TEGRA_BO_TILING_MODE_PITCH:
882 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
883 args->value = 0;
884 break;
885
886 case TEGRA_BO_TILING_MODE_TILED:
887 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
888 args->value = 0;
889 break;
890
891 case TEGRA_BO_TILING_MODE_BLOCK:
892 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
893 args->value = bo->tiling.value;
894 break;
895
896 default:
897 err = -EINVAL;
898 break;
899 }
900
11533304 901 drm_gem_object_unreference_unlocked(gem);
7678d71f
TR
902
903 return err;
904}
7b129087
TR
905
906static int tegra_gem_set_flags(struct drm_device *drm, void *data,
907 struct drm_file *file)
908{
909 struct drm_tegra_gem_set_flags *args = data;
910 struct drm_gem_object *gem;
911 struct tegra_bo *bo;
912
913 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
914 return -EINVAL;
915
a8ad0bd8 916 gem = drm_gem_object_lookup(file, args->handle);
7b129087
TR
917 if (!gem)
918 return -ENOENT;
919
920 bo = to_tegra_bo(gem);
921 bo->flags = 0;
922
923 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
924 bo->flags |= TEGRA_BO_BOTTOM_UP;
925
11533304 926 drm_gem_object_unreference_unlocked(gem);
7b129087
TR
927
928 return 0;
929}
930
931static int tegra_gem_get_flags(struct drm_device *drm, void *data,
932 struct drm_file *file)
933{
934 struct drm_tegra_gem_get_flags *args = data;
935 struct drm_gem_object *gem;
936 struct tegra_bo *bo;
937
a8ad0bd8 938 gem = drm_gem_object_lookup(file, args->handle);
7b129087
TR
939 if (!gem)
940 return -ENOENT;
941
942 bo = to_tegra_bo(gem);
943 args->flags = 0;
944
945 if (bo->flags & TEGRA_BO_BOTTOM_UP)
946 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
947
11533304 948 drm_gem_object_unreference_unlocked(gem);
7b129087
TR
949
950 return 0;
951}
d43f81cb
TB
952#endif
953
baa70943 954static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
d43f81cb 955#ifdef CONFIG_DRM_TEGRA_STAGING
f8c47144
DV
956 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0),
957 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0),
958 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0),
959 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0),
960 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0),
961 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0),
962 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0),
963 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0),
964 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0),
965 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0),
966 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0),
967 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0),
968 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0),
969 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0),
d43f81cb 970#endif
d8f4a9ed
TR
971};
972
973static const struct file_operations tegra_drm_fops = {
974 .owner = THIS_MODULE,
975 .open = drm_open,
976 .release = drm_release,
977 .unlocked_ioctl = drm_ioctl,
de2ba664 978 .mmap = tegra_drm_mmap,
d8f4a9ed 979 .poll = drm_poll,
d8f4a9ed 980 .read = drm_read,
d8f4a9ed 981 .compat_ioctl = drm_compat_ioctl,
d8f4a9ed
TR
982 .llseek = noop_llseek,
983};
984
bdd2f9cd
TR
985static int tegra_drm_context_cleanup(int id, void *p, void *data)
986{
987 struct tegra_drm_context *context = p;
988
989 tegra_drm_context_free(context);
990
991 return 0;
992}
993
bda0ecc4 994static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
3c03c46a 995{
08943e6c 996 struct tegra_drm_file *fpriv = file->driver_priv;
3c03c46a 997
bdd2f9cd
TR
998 mutex_lock(&fpriv->lock);
999 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
1000 mutex_unlock(&fpriv->lock);
d43f81cb 1001
bdd2f9cd
TR
1002 idr_destroy(&fpriv->contexts);
1003 mutex_destroy(&fpriv->lock);
d43f81cb 1004 kfree(fpriv);
3c03c46a
TR
1005}
1006
e450fcc6
TR
1007#ifdef CONFIG_DEBUG_FS
1008static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1009{
1010 struct drm_info_node *node = (struct drm_info_node *)s->private;
1011 struct drm_device *drm = node->minor->dev;
1012 struct drm_framebuffer *fb;
1013
1014 mutex_lock(&drm->mode_config.fb_lock);
1015
1016 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1017 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
b00c600e
VS
1018 fb->base.id, fb->width, fb->height,
1019 fb->format->depth,
272725c7 1020 fb->format->cpp[0] * 8,
747a598f 1021 drm_framebuffer_read_refcount(fb));
e450fcc6
TR
1022 }
1023
1024 mutex_unlock(&drm->mode_config.fb_lock);
1025
1026 return 0;
1027}
1028
28c23373
TR
1029static int tegra_debugfs_iova(struct seq_file *s, void *data)
1030{
1031 struct drm_info_node *node = (struct drm_info_node *)s->private;
1032 struct drm_device *drm = node->minor->dev;
1033 struct tegra_drm *tegra = drm->dev_private;
b5c3714f 1034 struct drm_printer p = drm_seq_file_printer(s);
28c23373 1035
347ad49d 1036 mutex_lock(&tegra->mm_lock);
b5c3714f 1037 drm_mm_print(&tegra->mm, &p);
347ad49d 1038 mutex_unlock(&tegra->mm_lock);
b5c3714f
DV
1039
1040 return 0;
28c23373
TR
1041}
1042
e450fcc6
TR
1043static struct drm_info_list tegra_debugfs_list[] = {
1044 { "framebuffers", tegra_debugfs_framebuffers, 0 },
28c23373 1045 { "iova", tegra_debugfs_iova, 0 },
e450fcc6
TR
1046};
1047
1048static int tegra_debugfs_init(struct drm_minor *minor)
1049{
1050 return drm_debugfs_create_files(tegra_debugfs_list,
1051 ARRAY_SIZE(tegra_debugfs_list),
1052 minor->debugfs_root, minor);
1053}
e450fcc6
TR
1054#endif
1055
9b57f5f2 1056static struct drm_driver tegra_drm_driver = {
ad906599
TR
1057 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
1058 DRIVER_ATOMIC,
d8f4a9ed
TR
1059 .load = tegra_drm_load,
1060 .unload = tegra_drm_unload,
1061 .open = tegra_drm_open,
bda0ecc4 1062 .postclose = tegra_drm_postclose,
d8f4a9ed
TR
1063 .lastclose = tegra_drm_lastclose,
1064
e450fcc6
TR
1065#if defined(CONFIG_DEBUG_FS)
1066 .debugfs_init = tegra_debugfs_init,
e450fcc6
TR
1067#endif
1068
1ddbdbd6 1069 .gem_free_object_unlocked = tegra_bo_free_object,
de2ba664 1070 .gem_vm_ops = &tegra_bo_vm_ops,
3800391d
TR
1071
1072 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1073 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1074 .gem_prime_export = tegra_gem_prime_export,
1075 .gem_prime_import = tegra_gem_prime_import,
1076
de2ba664
AM
1077 .dumb_create = tegra_bo_dumb_create,
1078 .dumb_map_offset = tegra_bo_dumb_map_offset,
43387b37 1079 .dumb_destroy = drm_gem_dumb_destroy,
d8f4a9ed
TR
1080
1081 .ioctls = tegra_drm_ioctls,
1082 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1083 .fops = &tegra_drm_fops,
1084
1085 .name = DRIVER_NAME,
1086 .desc = DRIVER_DESC,
1087 .date = DRIVER_DATE,
1088 .major = DRIVER_MAJOR,
1089 .minor = DRIVER_MINOR,
1090 .patchlevel = DRIVER_PATCHLEVEL,
1091};
776dc384
TR
1092
1093int tegra_drm_register_client(struct tegra_drm *tegra,
1094 struct tegra_drm_client *client)
1095{
1096 mutex_lock(&tegra->clients_lock);
1097 list_add_tail(&client->list, &tegra->clients);
1098 mutex_unlock(&tegra->clients_lock);
1099
1100 return 0;
1101}
1102
1103int tegra_drm_unregister_client(struct tegra_drm *tegra,
1104 struct tegra_drm_client *client)
1105{
1106 mutex_lock(&tegra->clients_lock);
1107 list_del_init(&client->list);
1108 mutex_unlock(&tegra->clients_lock);
1109
1110 return 0;
1111}
1112
ad926015
MP
1113void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size,
1114 dma_addr_t *dma)
1115{
1116 struct iova *alloc;
1117 void *virt;
1118 gfp_t gfp;
1119 int err;
1120
1121 if (tegra->domain)
1122 size = iova_align(&tegra->carveout.domain, size);
1123 else
1124 size = PAGE_ALIGN(size);
1125
1126 gfp = GFP_KERNEL | __GFP_ZERO;
1127 if (!tegra->domain) {
1128 /*
1129 * Many units only support 32-bit addresses, even on 64-bit
1130 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1131 * virtual address space, force allocations to be in the
1132 * lower 32-bit range.
1133 */
1134 gfp |= GFP_DMA;
1135 }
1136
1137 virt = (void *)__get_free_pages(gfp, get_order(size));
1138 if (!virt)
1139 return ERR_PTR(-ENOMEM);
1140
1141 if (!tegra->domain) {
1142 /*
1143 * If IOMMU is disabled, devices address physical memory
1144 * directly.
1145 */
1146 *dma = virt_to_phys(virt);
1147 return virt;
1148 }
1149
1150 alloc = alloc_iova(&tegra->carveout.domain,
1151 size >> tegra->carveout.shift,
1152 tegra->carveout.limit, true);
1153 if (!alloc) {
1154 err = -EBUSY;
1155 goto free_pages;
1156 }
1157
1158 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1159 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1160 size, IOMMU_READ | IOMMU_WRITE);
1161 if (err < 0)
1162 goto free_iova;
1163
1164 return virt;
1165
1166free_iova:
1167 __free_iova(&tegra->carveout.domain, alloc);
1168free_pages:
1169 free_pages((unsigned long)virt, get_order(size));
1170
1171 return ERR_PTR(err);
1172}
1173
1174void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1175 dma_addr_t dma)
1176{
1177 if (tegra->domain)
1178 size = iova_align(&tegra->carveout.domain, size);
1179 else
1180 size = PAGE_ALIGN(size);
1181
1182 if (tegra->domain) {
1183 iommu_unmap(tegra->domain, dma, size);
1184 free_iova(&tegra->carveout.domain,
1185 iova_pfn(&tegra->carveout.domain, dma));
1186 }
1187
1188 free_pages((unsigned long)virt, get_order(size));
1189}
1190
9910f5c4 1191static int host1x_drm_probe(struct host1x_device *dev)
776dc384 1192{
9910f5c4
TR
1193 struct drm_driver *driver = &tegra_drm_driver;
1194 struct drm_device *drm;
1195 int err;
1196
1197 drm = drm_dev_alloc(driver, &dev->dev);
0f288605
TG
1198 if (IS_ERR(drm))
1199 return PTR_ERR(drm);
9910f5c4 1200
9910f5c4
TR
1201 dev_set_drvdata(&dev->dev, drm);
1202
1203 err = drm_dev_register(drm, 0);
1204 if (err < 0)
1205 goto unref;
1206
9910f5c4
TR
1207 return 0;
1208
1209unref:
1210 drm_dev_unref(drm);
1211 return err;
776dc384
TR
1212}
1213
9910f5c4 1214static int host1x_drm_remove(struct host1x_device *dev)
776dc384 1215{
9910f5c4
TR
1216 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1217
1218 drm_dev_unregister(drm);
1219 drm_dev_unref(drm);
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1220
1221 return 0;
1222}
1223
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1224#ifdef CONFIG_PM_SLEEP
1225static int host1x_drm_suspend(struct device *dev)
1226{
1227 struct drm_device *drm = dev_get_drvdata(dev);
986c58d1 1228 struct tegra_drm *tegra = drm->dev_private;
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1229
1230 drm_kms_helper_poll_disable(drm);
986c58d1
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1231 tegra_drm_fb_suspend(drm);
1232
1233 tegra->state = drm_atomic_helper_suspend(drm);
1234 if (IS_ERR(tegra->state)) {
1235 tegra_drm_fb_resume(drm);
1236 drm_kms_helper_poll_enable(drm);
1237 return PTR_ERR(tegra->state);
1238 }
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1239
1240 return 0;
1241}
1242
1243static int host1x_drm_resume(struct device *dev)
1244{
1245 struct drm_device *drm = dev_get_drvdata(dev);
986c58d1 1246 struct tegra_drm *tegra = drm->dev_private;
359ae687 1247
986c58d1
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1248 drm_atomic_helper_resume(drm, tegra->state);
1249 tegra_drm_fb_resume(drm);
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1250 drm_kms_helper_poll_enable(drm);
1251
1252 return 0;
1253}
1254#endif
1255
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1256static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1257 host1x_drm_resume);
359ae687 1258
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1259static const struct of_device_id host1x_drm_subdevs[] = {
1260 { .compatible = "nvidia,tegra20-dc", },
1261 { .compatible = "nvidia,tegra20-hdmi", },
1262 { .compatible = "nvidia,tegra20-gr2d", },
5f60ed0d 1263 { .compatible = "nvidia,tegra20-gr3d", },
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1264 { .compatible = "nvidia,tegra30-dc", },
1265 { .compatible = "nvidia,tegra30-hdmi", },
1266 { .compatible = "nvidia,tegra30-gr2d", },
5f60ed0d 1267 { .compatible = "nvidia,tegra30-gr3d", },
dec72739 1268 { .compatible = "nvidia,tegra114-dsi", },
7d1d28ac 1269 { .compatible = "nvidia,tegra114-hdmi", },
5f60ed0d 1270 { .compatible = "nvidia,tegra114-gr3d", },
8620fc62 1271 { .compatible = "nvidia,tegra124-dc", },
6b6b6042 1272 { .compatible = "nvidia,tegra124-sor", },
fb7be70e 1273 { .compatible = "nvidia,tegra124-hdmi", },
7d338587 1274 { .compatible = "nvidia,tegra124-dsi", },
0ae797a8 1275 { .compatible = "nvidia,tegra124-vic", },
c06c7930 1276 { .compatible = "nvidia,tegra132-dsi", },
5b4f516f 1277 { .compatible = "nvidia,tegra210-dc", },
ddfb406b 1278 { .compatible = "nvidia,tegra210-dsi", },
3309ac83 1279 { .compatible = "nvidia,tegra210-sor", },
459cc2c6 1280 { .compatible = "nvidia,tegra210-sor1", },
0ae797a8 1281 { .compatible = "nvidia,tegra210-vic", },
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1282 { /* sentinel */ }
1283};
1284
1285static struct host1x_driver host1x_drm_driver = {
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1286 .driver = {
1287 .name = "drm",
359ae687 1288 .pm = &host1x_drm_pm_ops,
f4c5cf88 1289 },
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1290 .probe = host1x_drm_probe,
1291 .remove = host1x_drm_remove,
1292 .subdevs = host1x_drm_subdevs,
1293};
1294
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1295static struct platform_driver * const drivers[] = {
1296 &tegra_dc_driver,
1297 &tegra_hdmi_driver,
1298 &tegra_dsi_driver,
1299 &tegra_dpaux_driver,
1300 &tegra_sor_driver,
1301 &tegra_gr2d_driver,
1302 &tegra_gr3d_driver,
0ae797a8 1303 &tegra_vic_driver,
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1304};
1305
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1306static int __init host1x_drm_init(void)
1307{
1308 int err;
1309
1310 err = host1x_driver_register(&host1x_drm_driver);
1311 if (err < 0)
1312 return err;
1313
473112e4 1314 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
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1315 if (err < 0)
1316 goto unregister_host1x;
1317
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1318 return 0;
1319
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1320unregister_host1x:
1321 host1x_driver_unregister(&host1x_drm_driver);
1322 return err;
1323}
1324module_init(host1x_drm_init);
1325
1326static void __exit host1x_drm_exit(void)
1327{
473112e4 1328 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
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1329 host1x_driver_unregister(&host1x_drm_driver);
1330}
1331module_exit(host1x_drm_exit);
1332
1333MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1334MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1335MODULE_LICENSE("GPL v2");