[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / tegra / drm.h

/*
 * Copyright (C) 2012 Avionic Design GmbH
 * Copyright (C) 2012-2013 NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef HOST1X_DRM_H
#define HOST1X_DRM_H 1

#include <uapi/drm/tegra_drm.h>
#include <linux/host1x.h>

#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_fixed.h>

struct reset_control;

struct tegra_fb {
	struct drm_framebuffer base;
	struct tegra_bo **planes;
	unsigned int num_planes;
};

#ifdef CONFIG_DRM_TEGRA_FBDEV
struct tegra_fbdev {
	struct drm_fb_helper base;
	struct tegra_fb *fb;
};
#endif

struct tegra_drm {
	struct drm_device *drm;

	struct mutex clients_lock;
	struct list_head clients;

#ifdef CONFIG_DRM_TEGRA_FBDEV
	struct tegra_fbdev *fbdev;
#endif
};

struct tegra_drm_client;

struct tegra_drm_context {
	struct tegra_drm_client *client;
	struct host1x_channel *channel;
	struct list_head list;
};

struct tegra_drm_client_ops {
	int (*open_channel)(struct tegra_drm_client *client,
			    struct tegra_drm_context *context);
	void (*close_channel)(struct tegra_drm_context *context);
	int (*is_addr_reg)(struct device *dev, u32 class, u32 offset);
	int (*submit)(struct tegra_drm_context *context,
		      struct drm_tegra_submit *args, struct drm_device *drm,
		      struct drm_file *file);
};

int tegra_drm_submit(struct tegra_drm_context *context,
		     struct drm_tegra_submit *args, struct drm_device *drm,
		     struct drm_file *file);

struct tegra_drm_client {
	struct host1x_client base;
	struct list_head list;

	const struct tegra_drm_client_ops *ops;
};

static inline struct tegra_drm_client *
host1x_to_drm_client(struct host1x_client *client)
{
	return container_of(client, struct tegra_drm_client, base);
}

extern int tegra_drm_register_client(struct tegra_drm *tegra,
				     struct tegra_drm_client *client);
extern int tegra_drm_unregister_client(struct tegra_drm *tegra,
				       struct tegra_drm_client *client);

extern int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm);
extern int tegra_drm_exit(struct tegra_drm *tegra);

struct tegra_dc_soc_info;
struct tegra_output;

struct tegra_dc {
	struct host1x_client client;
	struct device *dev;
	spinlock_t lock;

	struct drm_crtc base;
	int pipe;

	struct clk *clk;
	struct reset_control *rst;
	void __iomem *regs;
	int irq;

	struct tegra_output *rgb;

	struct list_head list;

	struct drm_info_list *debugfs_files;
	struct drm_minor *minor;
	struct dentry *debugfs;

	/* page-flip handling */
	struct drm_pending_vblank_event *event;

	const struct tegra_dc_soc_info *soc;
};

static inline struct tegra_dc *
host1x_client_to_dc(struct host1x_client *client)
{
	return container_of(client, struct tegra_dc, client);
}

static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
{
	return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
}

static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value,
				   unsigned long reg)
{
	writel(value, dc->regs + (reg << 2));
}

static inline unsigned long tegra_dc_readl(struct tegra_dc *dc,
					   unsigned long reg)
{
	return readl(dc->regs + (reg << 2));
}

struct tegra_dc_window {
	struct {
		unsigned int x;
		unsigned int y;
		unsigned int w;
		unsigned int h;
	} src;
	struct {
		unsigned int x;
		unsigned int y;
		unsigned int w;
		unsigned int h;
	} dst;
	unsigned int bits_per_pixel;
	unsigned int format;
	unsigned int stride[2];
	unsigned long base[3];
	bool bottom_up;
	bool tiled;
};

/* from dc.c */
extern unsigned int tegra_dc_format(uint32_t format);
extern int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
				 const struct tegra_dc_window *window);
extern void tegra_dc_enable_vblank(struct tegra_dc *dc);
extern void tegra_dc_disable_vblank(struct tegra_dc *dc);
extern void tegra_dc_cancel_page_flip(struct drm_crtc *crtc,
				      struct drm_file *file);

struct tegra_output_ops {
	int (*enable)(struct tegra_output *output);
	int (*disable)(struct tegra_output *output);
	int (*setup_clock)(struct tegra_output *output, struct clk *clk,
			   unsigned long pclk);
	int (*check_mode)(struct tegra_output *output,
			  struct drm_display_mode *mode,
			  enum drm_mode_status *status);
	enum drm_connector_status (*detect)(struct tegra_output *output);
};

enum tegra_output_type {
	TEGRA_OUTPUT_RGB,
	TEGRA_OUTPUT_HDMI,
	TEGRA_OUTPUT_DSI,
	TEGRA_OUTPUT_EDP,
};

struct tegra_output {
	struct device_node *of_node;
	struct device *dev;

	const struct tegra_output_ops *ops;
	enum tegra_output_type type;

	struct drm_panel *panel;
	struct i2c_adapter *ddc;
	const struct edid *edid;
	unsigned int hpd_irq;
	int hpd_gpio;

	struct drm_encoder encoder;
	struct drm_connector connector;
};

static inline struct tegra_output *encoder_to_output(struct drm_encoder *e)
{
	return container_of(e, struct tegra_output, encoder);
}

static inline struct tegra_output *connector_to_output(struct drm_connector *c)
{
	return container_of(c, struct tegra_output, connector);
}

static inline int tegra_output_enable(struct tegra_output *output)
{
	if (output && output->ops && output->ops->enable)
		return output->ops->enable(output);

	return output ? -ENOSYS : -EINVAL;
}

static inline int tegra_output_disable(struct tegra_output *output)
{
	if (output && output->ops && output->ops->disable)
		return output->ops->disable(output);

	return output ? -ENOSYS : -EINVAL;
}

static inline int tegra_output_setup_clock(struct tegra_output *output,
					   struct clk *clk, unsigned long pclk)
{
	if (output && output->ops && output->ops->setup_clock)
		return output->ops->setup_clock(output, clk, pclk);

	return output ? -ENOSYS : -EINVAL;
}

static inline int tegra_output_check_mode(struct tegra_output *output,
					  struct drm_display_mode *mode,
					  enum drm_mode_status *status)
{
	if (output && output->ops && output->ops->check_mode)
		return output->ops->check_mode(output, mode, status);

	return output ? -ENOSYS : -EINVAL;
}

/* from bus.c */
int drm_host1x_init(struct drm_driver *driver, struct host1x_device *device);
void drm_host1x_exit(struct drm_driver *driver, struct host1x_device *device);

/* from rgb.c */
extern int tegra_dc_rgb_probe(struct tegra_dc *dc);
extern int tegra_dc_rgb_remove(struct tegra_dc *dc);
extern int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
extern int tegra_dc_rgb_exit(struct tegra_dc *dc);

/* from output.c */
extern int tegra_output_probe(struct tegra_output *output);
extern int tegra_output_remove(struct tegra_output *output);
extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output);
extern int tegra_output_exit(struct tegra_output *output);

/* from dpaux.c */

struct tegra_dpaux;
struct drm_dp_link;
struct drm_dp_aux;

struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np);
enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux);
int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output);
int tegra_dpaux_detach(struct tegra_dpaux *dpaux);
int tegra_dpaux_enable(struct tegra_dpaux *dpaux);
int tegra_dpaux_disable(struct tegra_dpaux *dpaux);
int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding);
int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
		      u8 pattern);

/* from fb.c */
struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
				    unsigned int index);
bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer);
bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer);
extern int tegra_drm_fb_init(struct drm_device *drm);
extern void tegra_drm_fb_exit(struct drm_device *drm);
#ifdef CONFIG_DRM_TEGRA_FBDEV
extern void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev);
#endif

extern struct platform_driver tegra_dc_driver;
extern struct platform_driver tegra_dsi_driver;
extern struct platform_driver tegra_sor_driver;
extern struct platform_driver tegra_hdmi_driver;
extern struct platform_driver tegra_dpaux_driver;
extern struct platform_driver tegra_gr2d_driver;
extern struct platform_driver tegra_gr3d_driver;

#endif /* HOST1X_DRM_H */
Commit	Line	Data
d8f4a9ed TR	1	/*
d8f4a9ed TR	2	* Copyright (C) 2012 Avionic Design GmbH
d43f81cb	3	* Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved.
d8f4a9ed TR	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*/
	9
4231c6b0 TB	10	#ifndef HOST1X_DRM_H
4231c6b0 TB	11	#define HOST1X_DRM_H 1
d8f4a9ed	12
e1e90644 TR	13	#include <uapi/drm/tegra_drm.h>
	14	#include <linux/host1x.h>
	15
d8f4a9ed TR	16	#include <drm/drmP.h>
	17	#include <drm/drm_crtc_helper.h>
	18	#include <drm/drm_edid.h>
	19	#include <drm/drm_fb_helper.h>
d8f4a9ed TR	20	#include <drm/drm_fixed.h>
d8f4a9ed TR	21
ca48080a SW	22	struct reset_control;
ca48080a SW	23
de2ba664 AM	24	struct tegra_fb {
	25	struct drm_framebuffer base;
	26	struct tegra_bo **planes;
	27	unsigned int num_planes;
	28	};
	29
60c2f709	30	#ifdef CONFIG_DRM_TEGRA_FBDEV
de2ba664 AM	31	struct tegra_fbdev {
	32	struct drm_fb_helper base;
	33	struct tegra_fb *fb;
	34	};
60c2f709	35	#endif
de2ba664	36
386a2a71	37	struct tegra_drm {
d8f4a9ed	38	struct drm_device *drm;
d8f4a9ed TR	39
	40	struct mutex clients_lock;
	41	struct list_head clients;
	42
60c2f709	43	#ifdef CONFIG_DRM_TEGRA_FBDEV
de2ba664	44	struct tegra_fbdev *fbdev;
60c2f709	45	#endif
d8f4a9ed TR	46	};
d8f4a9ed TR	47
53fa7f72	48	struct tegra_drm_client;
d8f4a9ed	49
c88c3630	50	struct tegra_drm_context {
53fa7f72	51	struct tegra_drm_client *client;
d43f81cb TB	52	struct host1x_channel *channel;
	53	struct list_head list;
	54	};
	55
53fa7f72 TR	56	struct tegra_drm_client_ops {
53fa7f72 TR	57	int (open_channel)(struct tegra_drm_client client,
c88c3630 TR	58	struct tegra_drm_context *context);
c88c3630 TR	59	void (close_channel)(struct tegra_drm_context context);
c40f0f1a	60	int (is_addr_reg)(struct device dev, u32 class, u32 offset);
c88c3630	61	int (submit)(struct tegra_drm_context context,
d43f81cb TB	62	struct drm_tegra_submit args, struct drm_device drm,
	63	struct drm_file *file);
	64	};
	65
c40f0f1a TR	66	int tegra_drm_submit(struct tegra_drm_context *context,
	67	struct drm_tegra_submit args, struct drm_device drm,
	68	struct drm_file *file);
	69
53fa7f72 TR	70	struct tegra_drm_client {
53fa7f72 TR	71	struct host1x_client base;
776dc384	72	struct list_head list;
d43f81cb	73
53fa7f72	74	const struct tegra_drm_client_ops *ops;
d8f4a9ed TR	75	};
d8f4a9ed TR	76
53fa7f72	77	static inline struct tegra_drm_client *
776dc384	78	host1x_to_drm_client(struct host1x_client *client)
53fa7f72 TR	79	{
	80	return container_of(client, struct tegra_drm_client, base);
	81	}
	82
776dc384 TR	83	extern int tegra_drm_register_client(struct tegra_drm *tegra,
	84	struct tegra_drm_client *client);
	85	extern int tegra_drm_unregister_client(struct tegra_drm *tegra,
	86	struct tegra_drm_client *client);
	87
386a2a71 TR	88	extern int tegra_drm_init(struct tegra_drm tegra, struct drm_device drm);
386a2a71 TR	89	extern int tegra_drm_exit(struct tegra_drm *tegra);
d8f4a9ed	90
8620fc62	91	struct tegra_dc_soc_info;
d8f4a9ed TR	92	struct tegra_output;
	93
	94	struct tegra_dc {
776dc384	95	struct host1x_client client;
d8f4a9ed	96	struct device *dev;
d18d3033	97	spinlock_t lock;
d8f4a9ed TR	98
	99	struct drm_crtc base;
	100	int pipe;
	101
	102	struct clk *clk;
ca48080a	103	struct reset_control *rst;
d8f4a9ed TR	104	void __iomem *regs;
	105	int irq;
	106
	107	struct tegra_output *rgb;
	108
	109	struct list_head list;
	110
	111	struct drm_info_list *debugfs_files;
	112	struct drm_minor *minor;
	113	struct dentry *debugfs;
3c03c46a TR	114
	115	/* page-flip handling */
	116	struct drm_pending_vblank_event *event;
8620fc62 TR	117
8620fc62 TR	118	const struct tegra_dc_soc_info *soc;
d8f4a9ed TR	119	};
d8f4a9ed TR	120
53fa7f72	121	static inline struct tegra_dc *
776dc384	122	host1x_client_to_dc(struct host1x_client *client)
d8f4a9ed TR	123	{
	124	return container_of(client, struct tegra_dc, client);
	125	}
	126
	127	static inline struct tegra_dc to_tegra_dc(struct drm_crtc crtc)
	128	{
37826519	129	return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
d8f4a9ed TR	130	}
	131
	132	static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value,
	133	unsigned long reg)
	134	{
	135	writel(value, dc->regs + (reg << 2));
	136	}
	137
	138	static inline unsigned long tegra_dc_readl(struct tegra_dc *dc,
	139	unsigned long reg)
	140	{
	141	return readl(dc->regs + (reg << 2));
	142	}
	143
f34bc787 TR	144	struct tegra_dc_window {
	145	struct {
	146	unsigned int x;
	147	unsigned int y;
	148	unsigned int w;
	149	unsigned int h;
	150	} src;
	151	struct {
	152	unsigned int x;
	153	unsigned int y;
	154	unsigned int w;
	155	unsigned int h;
	156	} dst;
	157	unsigned int bits_per_pixel;
	158	unsigned int format;
	159	unsigned int stride[2];
	160	unsigned long base[3];
db7fbdfd	161	bool bottom_up;
773af77f	162	bool tiled;
f34bc787 TR	163	};
	164
	165	/* from dc.c */
	166	extern unsigned int tegra_dc_format(uint32_t format);
	167	extern int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
	168	const struct tegra_dc_window *window);
6e5ff998 TR	169	extern void tegra_dc_enable_vblank(struct tegra_dc *dc);
6e5ff998 TR	170	extern void tegra_dc_disable_vblank(struct tegra_dc *dc);
3c03c46a TR	171	extern void tegra_dc_cancel_page_flip(struct drm_crtc *crtc,
3c03c46a TR	172	struct drm_file *file);
f34bc787	173
d8f4a9ed TR	174	struct tegra_output_ops {
	175	int (enable)(struct tegra_output output);
	176	int (disable)(struct tegra_output output);
	177	int (setup_clock)(struct tegra_output output, struct clk *clk,
	178	unsigned long pclk);
	179	int (check_mode)(struct tegra_output output,
	180	struct drm_display_mode *mode,
	181	enum drm_mode_status *status);
6b6b6042	182	enum drm_connector_status (detect)(struct tegra_output output);
d8f4a9ed TR	183	};
	184
	185	enum tegra_output_type {
	186	TEGRA_OUTPUT_RGB,
edec4af4	187	TEGRA_OUTPUT_HDMI,
dec72739	188	TEGRA_OUTPUT_DSI,
6b6b6042	189	TEGRA_OUTPUT_EDP,
d8f4a9ed TR	190	};
	191
	192	struct tegra_output {
	193	struct device_node *of_node;
	194	struct device *dev;
	195
	196	const struct tegra_output_ops *ops;
	197	enum tegra_output_type type;
	198
9be7d864	199	struct drm_panel *panel;
d8f4a9ed TR	200	struct i2c_adapter *ddc;
	201	const struct edid *edid;
	202	unsigned int hpd_irq;
	203	int hpd_gpio;
	204
	205	struct drm_encoder encoder;
	206	struct drm_connector connector;
	207	};
	208
	209	static inline struct tegra_output encoder_to_output(struct drm_encoder e)
	210	{
	211	return container_of(e, struct tegra_output, encoder);
	212	}
	213
	214	static inline struct tegra_output connector_to_output(struct drm_connector c)
	215	{
	216	return container_of(c, struct tegra_output, connector);
	217	}
	218
	219	static inline int tegra_output_enable(struct tegra_output *output)
	220	{
	221	if (output && output->ops && output->ops->enable)
	222	return output->ops->enable(output);
	223
	224	return output ? -ENOSYS : -EINVAL;
	225	}
	226
	227	static inline int tegra_output_disable(struct tegra_output *output)
	228	{
	229	if (output && output->ops && output->ops->disable)
	230	return output->ops->disable(output);
	231
	232	return output ? -ENOSYS : -EINVAL;
	233	}
	234
	235	static inline int tegra_output_setup_clock(struct tegra_output *output,
	236	struct clk *clk, unsigned long pclk)
	237	{
	238	if (output && output->ops && output->ops->setup_clock)
	239	return output->ops->setup_clock(output, clk, pclk);
	240
	241	return output ? -ENOSYS : -EINVAL;
	242	}
	243
	244	static inline int tegra_output_check_mode(struct tegra_output *output,
	245	struct drm_display_mode *mode,
	246	enum drm_mode_status *status)
	247	{
	248	if (output && output->ops && output->ops->check_mode)
	249	return output->ops->check_mode(output, mode, status);
	250
	251	return output ? -ENOSYS : -EINVAL;
	252	}
	253
776dc384 TR	254	/* from bus.c */
	255	int drm_host1x_init(struct drm_driver driver, struct host1x_device device);
	256	void drm_host1x_exit(struct drm_driver driver, struct host1x_device device);
	257
d8f4a9ed TR	258	/* from rgb.c */
d8f4a9ed TR	259	extern int tegra_dc_rgb_probe(struct tegra_dc *dc);
59d29c0e	260	extern int tegra_dc_rgb_remove(struct tegra_dc *dc);
d8f4a9ed TR	261	extern int tegra_dc_rgb_init(struct drm_device drm, struct tegra_dc dc);
	262	extern int tegra_dc_rgb_exit(struct tegra_dc *dc);
	263
	264	/* from output.c */
59d29c0e TR	265	extern int tegra_output_probe(struct tegra_output *output);
59d29c0e TR	266	extern int tegra_output_remove(struct tegra_output *output);
d8f4a9ed TR	267	extern int tegra_output_init(struct drm_device drm, struct tegra_output output);
	268	extern int tegra_output_exit(struct tegra_output *output);
	269
6b6b6042 TR	270	/* from dpaux.c */
	271
	272	struct tegra_dpaux;
	273	struct drm_dp_link;
	274	struct drm_dp_aux;
	275
	276	struct tegra_dpaux tegra_dpaux_find_by_of_node(struct device_node np);
	277	enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux);
	278	int tegra_dpaux_attach(struct tegra_dpaux dpaux, struct tegra_output output);
	279	int tegra_dpaux_detach(struct tegra_dpaux *dpaux);
	280	int tegra_dpaux_enable(struct tegra_dpaux *dpaux);
	281	int tegra_dpaux_disable(struct tegra_dpaux *dpaux);
	282	int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding);
	283	int tegra_dpaux_train(struct tegra_dpaux dpaux, struct drm_dp_link link,
	284	u8 pattern);
	285
d8f4a9ed	286	/* from fb.c */
de2ba664 AM	287	struct tegra_bo tegra_fb_get_plane(struct drm_framebuffer framebuffer,
de2ba664 AM	288	unsigned int index);
db7fbdfd	289	bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer);
773af77f	290	bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer);
d8f4a9ed TR	291	extern int tegra_drm_fb_init(struct drm_device *drm);
d8f4a9ed TR	292	extern void tegra_drm_fb_exit(struct drm_device *drm);
60c2f709	293	#ifdef CONFIG_DRM_TEGRA_FBDEV
de2ba664	294	extern void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev);
60c2f709	295	#endif
d8f4a9ed	296
776dc384	297	extern struct platform_driver tegra_dc_driver;
dec72739	298	extern struct platform_driver tegra_dsi_driver;
6b6b6042	299	extern struct platform_driver tegra_sor_driver;
776dc384	300	extern struct platform_driver tegra_hdmi_driver;
6b6b6042	301	extern struct platform_driver tegra_dpaux_driver;
776dc384	302	extern struct platform_driver tegra_gr2d_driver;
5f60ed0d	303	extern struct platform_driver tegra_gr3d_driver;
d8f4a9ed	304
4231c6b0	305	#endif /* HOST1X_DRM_H */