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drm/tegra: dc: Do not needlessly deassert reset
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / tegra / dsi.c
CommitLineData
dec72739
TR		 1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
9a2ac2dc
TR		 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
dec72739
TR		 7 */
8
9#include <linux/clk.h>
10#include <linux/debugfs.h>
11#include <linux/host1x.h>
12#include <linux/module.h>
13#include <linux/of.h>
e94236cd 14#include <linux/of_platform.h>
dec72739
TR		 15#include <linux/platform_device.h>
16#include <linux/reset.h>
17
3b077afb
TR		 18#include <linux/regulator/consumer.h>
19
dec72739
TR		 20#include <drm/drm_mipi_dsi.h>
21#include <drm/drm_panel.h>
22
23#include <video/mipi_display.h>
24
25#include "dc.h"
26#include "drm.h"
27#include "dsi.h"
28#include "mipi-phy.h"
29
dec72739
TR		 30struct tegra_dsi {
31 struct host1x_client client;
32 struct tegra_output output;
33 struct device *dev;
34
35 void __iomem *regs;
36
37 struct reset_control *rst;
38 struct clk *clk_parent;
39 struct clk *clk_lp;
40 struct clk *clk;
41
42 struct drm_info_list *debugfs_files;
43 struct drm_minor *minor;
44 struct dentry *debugfs;
45
17297a28 46 unsigned long flags;
dec72739
TR		 47 enum mipi_dsi_pixel_format format;
48 unsigned int lanes;
49
50 struct tegra_mipi_device *mipi;
51 struct mipi_dsi_host host;
3b077afb
TR		 52
53 struct regulator *vdd;
976cebc3
TR		 54
55 unsigned int video_fifo_depth;
56 unsigned int host_fifo_depth;
e94236cd
TR		 57
58 /* for ganged-mode support */
59 struct tegra_dsi *master;
60 struct tegra_dsi *slave;
dec72739
TR		 61};
62
63static inline struct tegra_dsi *
64host1x_client_to_dsi(struct host1x_client *client)
65{
66 return container_of(client, struct tegra_dsi, client);
67}
68
69static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
70{
71 return container_of(host, struct tegra_dsi, host);
72}
73
74static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
75{
76 return container_of(output, struct tegra_dsi, output);
77}
78
9c0b4ca1 79static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg)
dec72739
TR		 80{
81 return readl(dsi->regs + (reg << 2));
82}
83
9c0b4ca1 84static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
dec72739
TR		 85 unsigned long reg)
86{
87 writel(value, dsi->regs + (reg << 2));
88}
89
90static int tegra_dsi_show_regs(struct seq_file *s, void *data)
91{
92 struct drm_info_node *node = s->private;
93 struct tegra_dsi *dsi = node->info_ent->data;
94
95#define DUMP_REG(name) \
9c0b4ca1 96 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
dec72739
TR		 97 tegra_dsi_readl(dsi, name))
98
99 DUMP_REG(DSI_INCR_SYNCPT);
100 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
101 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
102 DUMP_REG(DSI_CTXSW);
103 DUMP_REG(DSI_RD_DATA);
104 DUMP_REG(DSI_WR_DATA);
105 DUMP_REG(DSI_POWER_CONTROL);
106 DUMP_REG(DSI_INT_ENABLE);
107 DUMP_REG(DSI_INT_STATUS);
108 DUMP_REG(DSI_INT_MASK);
109 DUMP_REG(DSI_HOST_CONTROL);
110 DUMP_REG(DSI_CONTROL);
111 DUMP_REG(DSI_SOL_DELAY);
112 DUMP_REG(DSI_MAX_THRESHOLD);
113 DUMP_REG(DSI_TRIGGER);
114 DUMP_REG(DSI_TX_CRC);
115 DUMP_REG(DSI_STATUS);
116
117 DUMP_REG(DSI_INIT_SEQ_CONTROL);
118 DUMP_REG(DSI_INIT_SEQ_DATA_0);
119 DUMP_REG(DSI_INIT_SEQ_DATA_1);
120 DUMP_REG(DSI_INIT_SEQ_DATA_2);
121 DUMP_REG(DSI_INIT_SEQ_DATA_3);
122 DUMP_REG(DSI_INIT_SEQ_DATA_4);
123 DUMP_REG(DSI_INIT_SEQ_DATA_5);
124 DUMP_REG(DSI_INIT_SEQ_DATA_6);
125 DUMP_REG(DSI_INIT_SEQ_DATA_7);
126
127 DUMP_REG(DSI_PKT_SEQ_0_LO);
128 DUMP_REG(DSI_PKT_SEQ_0_HI);
129 DUMP_REG(DSI_PKT_SEQ_1_LO);
130 DUMP_REG(DSI_PKT_SEQ_1_HI);
131 DUMP_REG(DSI_PKT_SEQ_2_LO);
132 DUMP_REG(DSI_PKT_SEQ_2_HI);
133 DUMP_REG(DSI_PKT_SEQ_3_LO);
134 DUMP_REG(DSI_PKT_SEQ_3_HI);
135 DUMP_REG(DSI_PKT_SEQ_4_LO);
136 DUMP_REG(DSI_PKT_SEQ_4_HI);
137 DUMP_REG(DSI_PKT_SEQ_5_LO);
138 DUMP_REG(DSI_PKT_SEQ_5_HI);
139
140 DUMP_REG(DSI_DCS_CMDS);
141
142 DUMP_REG(DSI_PKT_LEN_0_1);
143 DUMP_REG(DSI_PKT_LEN_2_3);
144 DUMP_REG(DSI_PKT_LEN_4_5);
145 DUMP_REG(DSI_PKT_LEN_6_7);
146
147 DUMP_REG(DSI_PHY_TIMING_0);
148 DUMP_REG(DSI_PHY_TIMING_1);
149 DUMP_REG(DSI_PHY_TIMING_2);
150 DUMP_REG(DSI_BTA_TIMING);
151
152 DUMP_REG(DSI_TIMEOUT_0);
153 DUMP_REG(DSI_TIMEOUT_1);
154 DUMP_REG(DSI_TO_TALLY);
155
156 DUMP_REG(DSI_PAD_CONTROL_0);
157 DUMP_REG(DSI_PAD_CONTROL_CD);
158 DUMP_REG(DSI_PAD_CD_STATUS);
159 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
160 DUMP_REG(DSI_PAD_CONTROL_1);
161 DUMP_REG(DSI_PAD_CONTROL_2);
162 DUMP_REG(DSI_PAD_CONTROL_3);
163 DUMP_REG(DSI_PAD_CONTROL_4);
164
165 DUMP_REG(DSI_GANGED_MODE_CONTROL);
166 DUMP_REG(DSI_GANGED_MODE_START);
167 DUMP_REG(DSI_GANGED_MODE_SIZE);
168
169 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
170 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
171
172 DUMP_REG(DSI_INIT_SEQ_DATA_8);
173 DUMP_REG(DSI_INIT_SEQ_DATA_9);
174 DUMP_REG(DSI_INIT_SEQ_DATA_10);
175 DUMP_REG(DSI_INIT_SEQ_DATA_11);
176 DUMP_REG(DSI_INIT_SEQ_DATA_12);
177 DUMP_REG(DSI_INIT_SEQ_DATA_13);
178 DUMP_REG(DSI_INIT_SEQ_DATA_14);
179 DUMP_REG(DSI_INIT_SEQ_DATA_15);
180
181#undef DUMP_REG
182
183 return 0;
184}
185
186static struct drm_info_list debugfs_files[] = {
187 { "regs", tegra_dsi_show_regs, 0, NULL },
188};
189
190static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
191 struct drm_minor *minor)
192{
193 const char *name = dev_name(dsi->dev);
194 unsigned int i;
195 int err;
196
197 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
198 if (!dsi->debugfs)
199 return -ENOMEM;
200
201 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
202 GFP_KERNEL);
203 if (!dsi->debugfs_files) {
204 err = -ENOMEM;
205 goto remove;
206 }
207
208 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
209 dsi->debugfs_files[i].data = dsi;
210
211 err = drm_debugfs_create_files(dsi->debugfs_files,
212 ARRAY_SIZE(debugfs_files),
213 dsi->debugfs, minor);
214 if (err < 0)
215 goto free;
216
217 dsi->minor = minor;
218
219 return 0;
220
221free:
222 kfree(dsi->debugfs_files);
223 dsi->debugfs_files = NULL;
224remove:
225 debugfs_remove(dsi->debugfs);
226 dsi->debugfs = NULL;
227
228 return err;
229}
230
4009c224 231static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
dec72739
TR		 232{
233 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
234 dsi->minor);
235 dsi->minor = NULL;
236
237 kfree(dsi->debugfs_files);
238 dsi->debugfs_files = NULL;
239
240 debugfs_remove(dsi->debugfs);
241 dsi->debugfs = NULL;
dec72739
TR		 242}
243
244#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
245#define PKT_LEN0(len) (((len) & 0x07) << 0)
246#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
247#define PKT_LEN1(len) (((len) & 0x07) << 10)
248#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
249#define PKT_LEN2(len) (((len) & 0x07) << 20)
250
251#define PKT_LP (1 << 30)
252#define NUM_PKT_SEQ 12
253
17297a28
TR		 254/*
255 * non-burst mode with sync pulses
256 */
257static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
dec72739
TR		 258 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
259 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
260 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
261 PKT_LP,
262 [ 1] = 0,
263 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
264 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
265 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
266 PKT_LP,
267 [ 3] = 0,
268 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
269 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
270 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
271 PKT_LP,
272 [ 5] = 0,
273 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
274 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
275 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
276 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
277 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
278 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
279 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
280 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
281 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
282 PKT_LP,
283 [ 9] = 0,
284 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
285 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
286 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
287 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
288 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
289 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
290};
291
17297a28
TR		 292/*
293 * non-burst mode with sync events
294 */
295static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
296 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
297 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
298 PKT_LP,
299 [ 1] = 0,
300 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
301 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
302 PKT_LP,
303 [ 3] = 0,
304 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
305 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
306 PKT_LP,
307 [ 5] = 0,
308 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
309 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
310 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
311 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
312 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
313 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
314 PKT_LP,
315 [ 9] = 0,
316 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
317 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
318 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
319 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
320};
321
337b443d
TR		 322static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
323 [ 0] = 0,
324 [ 1] = 0,
325 [ 2] = 0,
326 [ 3] = 0,
327 [ 4] = 0,
328 [ 5] = 0,
329 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
330 [ 7] = 0,
331 [ 8] = 0,
332 [ 9] = 0,
333 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
334 [11] = 0,
335};
336
dec72739
TR		 337static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
338{
339 struct mipi_dphy_timing timing;
9c0b4ca1
TR		 340 unsigned long period;
341 u32 value;
dec72739
TR		 342 long rate;
343 int err;
344
345 rate = clk_get_rate(dsi->clk);
346 if (rate < 0)
347 return rate;
348
369bc65b 349 period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate * 2);
dec72739
TR		 350
351 err = mipi_dphy_timing_get_default(&timing, period);
352 if (err < 0)
353 return err;
354
355 err = mipi_dphy_timing_validate(&timing, period);
356 if (err < 0) {
357 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
358 return err;
359 }
360
361 /*
362 * The D-PHY timing fields below are expressed in byte-clock cycles,
363 * so multiply the period by 8.
364 */
365 period *= 8;
366
367 value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
368 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
369 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
370 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
371 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
372
373 value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
374 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
375 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
376 DSI_TIMING_FIELD(timing.lpx, period, 1);
377 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
378
379 value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
380 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
381 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
382 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
383
384 value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
385 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
386 DSI_TIMING_FIELD(timing.tago, period, 1);
387 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
388
7e3bc3a9
SP		 389 if (dsi->slave)
390 return tegra_dsi_set_phy_timing(dsi->slave);
391
dec72739
TR		 392 return 0;
393}
394
395static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
396 unsigned int *mulp, unsigned int *divp)
397{
398 switch (format) {
399 case MIPI_DSI_FMT_RGB666_PACKED:
400 case MIPI_DSI_FMT_RGB888:
401 *mulp = 3;
402 *divp = 1;
403 break;
404
405 case MIPI_DSI_FMT_RGB565:
406 *mulp = 2;
407 *divp = 1;
408 break;
409
410 case MIPI_DSI_FMT_RGB666:
411 *mulp = 9;
412 *divp = 4;
413 break;
414
415 default:
416 return -EINVAL;
417 }
418
419 return 0;
420}
421
f7d6889b
TR		 422static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
423 enum tegra_dsi_format *fmt)
424{
425 switch (format) {
426 case MIPI_DSI_FMT_RGB888:
427 *fmt = TEGRA_DSI_FORMAT_24P;
428 break;
429
430 case MIPI_DSI_FMT_RGB666:
431 *fmt = TEGRA_DSI_FORMAT_18NP;
432 break;
433
434 case MIPI_DSI_FMT_RGB666_PACKED:
435 *fmt = TEGRA_DSI_FORMAT_18P;
436 break;
437
438 case MIPI_DSI_FMT_RGB565:
439 *fmt = TEGRA_DSI_FORMAT_16P;
440 break;
441
442 default:
443 return -EINVAL;
444 }
445
446 return 0;
447}
448
e94236cd
TR		 449static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
450 unsigned int size)
451{
452 u32 value;
453
454 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
455 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
456
457 value = DSI_GANGED_MODE_CONTROL_ENABLE;
458 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
459}
460
563eff1f
TR		 461static void tegra_dsi_enable(struct tegra_dsi *dsi)
462{
463 u32 value;
464
465 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
466 value |= DSI_POWER_CONTROL_ENABLE;
467 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
e94236cd
TR		 468
469 if (dsi->slave)
470 tegra_dsi_enable(dsi->slave);
471}
472
473static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
474{
475 if (dsi->master)
476 return dsi->master->lanes + dsi->lanes;
477
478 if (dsi->slave)
479 return dsi->lanes + dsi->slave->lanes;
480
481 return dsi->lanes;
563eff1f
TR		 482}
483
484static int tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
485 const struct drm_display_mode *mode)
dec72739 486{
dec72739 487 unsigned int hact, hsw, hbp, hfp, i, mul, div;
f7d6889b 488 enum tegra_dsi_format format;
17297a28 489 const u32 *pkt_seq;
563eff1f 490 u32 value;
dec72739
TR		 491 int err;
492
17297a28
TR		 493 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
494 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
495 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
337b443d 496 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
17297a28
TR		 497 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
498 pkt_seq = pkt_seq_video_non_burst_sync_events;
337b443d
TR		 499 } else {
500 DRM_DEBUG_KMS("Command mode\n");
501 pkt_seq = pkt_seq_command_mode;
17297a28
TR		 502 }
503
dec72739
TR		 504 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
505 if (err < 0)
506 return err;
507
f7d6889b
TR		 508 err = tegra_dsi_get_format(dsi->format, &format);
509 if (err < 0)
510 return err;
511
f7d6889b 512 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
dec72739 513 DSI_CONTROL_LANES(dsi->lanes - 1) |
563eff1f 514 DSI_CONTROL_SOURCE(pipe);
dec72739
TR		 515 tegra_dsi_writel(dsi, value, DSI_CONTROL);
516
976cebc3 517 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
dec72739 518
563eff1f 519 value = DSI_HOST_CONTROL_HS;
dec72739
TR		 520 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
521
522 value = tegra_dsi_readl(dsi, DSI_CONTROL);
563eff1f 523
0c6b1e4b
AC		 524 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
525 value |= DSI_CONTROL_HS_CLK_CTRL;
563eff1f 526
dec72739 527 value &= ~DSI_CONTROL_TX_TRIG(3);
337b443d
TR		 528
529 /* enable DCS commands for command mode */
530 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
531 value &= ~DSI_CONTROL_DCS_ENABLE;
532 else
533 value |= DSI_CONTROL_DCS_ENABLE;
534
dec72739
TR		 535 value |= DSI_CONTROL_VIDEO_ENABLE;
536 value &= ~DSI_CONTROL_HOST_ENABLE;
537 tegra_dsi_writel(dsi, value, DSI_CONTROL);
538
dec72739
TR		 539 for (i = 0; i < NUM_PKT_SEQ; i++)
540 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
541
337b443d
TR		 542 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
543 /* horizontal active pixels */
544 hact = mode->hdisplay * mul / div;
545
546 /* horizontal sync width */
547 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
548 hsw -= 10;
549
550 /* horizontal back porch */
551 hbp = (mode->htotal - mode->hsync_end) * mul / div;
552 hbp -= 14;
553
554 /* horizontal front porch */
555 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
556 hfp -= 8;
dec72739 557
337b443d
TR		 558 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
559 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
560 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
561 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
dec72739 562
337b443d
TR		 563 /* set SOL delay (for non-burst mode only) */
564 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
e94236cd
TR		 565
566 /* TODO: implement ganged mode */
337b443d
TR		 567 } else {
568 u16 bytes;
569
e94236cd
TR		 570 if (dsi->master || dsi->slave) {
571 /*
572 * For ganged mode, assume symmetric left-right mode.
573 */
574 bytes = 1 + (mode->hdisplay / 2) * mul / div;
575 } else {
576 /* 1 byte (DCS command) + pixel data */
577 bytes = 1 + mode->hdisplay * mul / div;
578 }
dec72739 579
337b443d
TR		 580 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
581 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
582 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
583 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
dec72739 584
337b443d
TR		 585 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
586 MIPI_DCS_WRITE_MEMORY_CONTINUE;
587 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
dec72739 588
e94236cd
TR		 589 /* set SOL delay */
590 if (dsi->master || dsi->slave) {
591 unsigned int lanes = tegra_dsi_get_lanes(dsi);
592 unsigned long delay, bclk, bclk_ganged;
593
594 /* SOL to valid, valid to FIFO and FIFO write delay */
595 delay = 4 + 4 + 2;
596 delay = DIV_ROUND_UP(delay * mul, div * lanes);
597 /* FIFO read delay */
598 delay = delay + 6;
599
600 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
601 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
602 value = bclk - bclk_ganged + delay + 20;
603 } else {
604 /* TODO: revisit for non-ganged mode */
605 value = 8 * mul / div;
606 }
337b443d
TR		 607
608 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
609 }
dec72739 610
e94236cd
TR		 611 if (dsi->slave) {
612 err = tegra_dsi_configure(dsi->slave, pipe, mode);
613 if (err < 0)
614 return err;
615
616 /*
617 * TODO: Support modes other than symmetrical left-right
618 * split.
619 */
620 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
621 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
622 mode->hdisplay / 2);
623 }
624
563eff1f
TR		 625 return 0;
626}
627
563eff1f
TR		 628static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
629{
630 u32 value;
631
632 timeout = jiffies + msecs_to_jiffies(timeout);
633
634 while (time_before(jiffies, timeout)) {
635 value = tegra_dsi_readl(dsi, DSI_STATUS);
636 if (value & DSI_STATUS_IDLE)
637 return 0;
638
639 usleep_range(1000, 2000);
640 }
641
642 return -ETIMEDOUT;
643}
644
645static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
646{
647 u32 value;
648
649 value = tegra_dsi_readl(dsi, DSI_CONTROL);
650 value &= ~DSI_CONTROL_VIDEO_ENABLE;
651 tegra_dsi_writel(dsi, value, DSI_CONTROL);
e94236cd
TR		 652
653 if (dsi->slave)
654 tegra_dsi_video_disable(dsi->slave);
655}
656
657static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
658{
659 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
660 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
661 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
563eff1f
TR		 662}
663
5b901e78
TR		 664static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
665 unsigned int vrefresh)
666{
667 unsigned int timeout;
668 u32 value;
669
670 /* one frame high-speed transmission timeout */
671 timeout = (bclk / vrefresh) / 512;
672 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
673 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
674
675 /* 2 ms peripheral timeout for panel */
676 timeout = 2 * bclk / 512 * 1000;
677 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
678 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
679
680 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
681 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
682
683 if (dsi->slave)
684 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
685}
686
563eff1f
TR		 687static void tegra_dsi_disable(struct tegra_dsi *dsi)
688{
689 u32 value;
690
e94236cd
TR		 691 if (dsi->slave) {
692 tegra_dsi_ganged_disable(dsi->slave);
693 tegra_dsi_ganged_disable(dsi);
694 }
695
563eff1f
TR		 696 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
697 value &= ~DSI_POWER_CONTROL_ENABLE;
698 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
699
e94236cd
TR		 700 if (dsi->slave)
701 tegra_dsi_disable(dsi->slave);
702
563eff1f
TR		 703 usleep_range(5000, 10000);
704}
705
92f0e073
TR		 706static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
707{
708 u32 value;
709
710 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
711 value &= ~DSI_POWER_CONTROL_ENABLE;
712 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
713
714 usleep_range(300, 1000);
715
716 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
717 value |= DSI_POWER_CONTROL_ENABLE;
718 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
719
720 usleep_range(300, 1000);
721
722 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
723 if (value)
724 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
725
726 if (dsi->slave)
727 tegra_dsi_soft_reset(dsi->slave);
728}
729
5b901e78 730static void tegra_dsi_connector_dpms(struct drm_connector *connector, int mode)
dec72739 731{
dec72739
TR		 732}
733
5b901e78
TR		 734static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
735 .dpms = tegra_dsi_connector_dpms,
736 .detect = tegra_output_connector_detect,
737 .fill_modes = drm_helper_probe_single_connector_modes,
738 .destroy = tegra_output_connector_destroy,
739};
3f6b406f 740
5b901e78
TR		 741static enum drm_mode_status
742tegra_dsi_connector_mode_valid(struct drm_connector *connector,
743 struct drm_display_mode *mode)
744{
745 return MODE_OK;
746}
3f6b406f 747
5b901e78
TR		 748static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
749 .get_modes = tegra_output_connector_get_modes,
750 .mode_valid = tegra_dsi_connector_mode_valid,
751 .best_encoder = tegra_output_connector_best_encoder,
752};
3f6b406f 753
5b901e78
TR		 754static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
755 .destroy = tegra_output_encoder_destroy,
756};
e94236cd 757
5b901e78
TR		 758static void tegra_dsi_encoder_dpms(struct drm_encoder *encoder, int mode)
759{
3f6b406f
TR		 760}
761
5b901e78
TR		 762static bool tegra_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
763 const struct drm_display_mode *mode,
764 struct drm_display_mode *adjusted)
dec72739 765{
5b901e78
TR		 766 struct tegra_output *output = encoder_to_output(encoder);
767 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
768 unsigned int mul, div, scdiv, vrefresh, lanes;
dec72739 769 struct tegra_dsi *dsi = to_dsi(output);
5b901e78 770 unsigned long pclk, bclk, plld;
dec72739
TR		 771 int err;
772
e94236cd 773 lanes = tegra_dsi_get_lanes(dsi);
5b901e78 774 pclk = mode->clock * 1000;
e94236cd 775
dec72739
TR		 776 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
777 if (err < 0)
778 return err;
779
e94236cd 780 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, lanes);
dec72739 781 vrefresh = drm_mode_vrefresh(mode);
91eded9b 782 DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh);
dec72739 783
91eded9b 784 /* compute byte clock */
e94236cd 785 bclk = (pclk * mul) / (div * lanes);
91eded9b
TR		 786
787 /*
788 * Compute bit clock and round up to the next MHz.
789 */
030611ec 790 plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
91eded9b
TR		 791
792 /*
793 * We divide the frequency by two here, but we make up for that by
794 * setting the shift clock divider (further below) to half of the
795 * correct value.
796 */
797 plld /= 2;
dec72739 798
91eded9b
TR		 799 /*
800 * Derive pixel clock from bit clock using the shift clock divider.
801 * Note that this is only half of what we would expect, but we need
802 * that to make up for the fact that we divided the bit clock by a
803 * factor of two above.
804 *
805 * It's not clear exactly why this is necessary, but the display is
806 * not working properly otherwise. Perhaps the PLLs cannot generate
807 * frequencies sufficiently high.
808 */
5b901e78
TR		 809 scdiv = ((8 * mul) / (div * lanes)) - 2;
810
811 err = tegra_dc_setup_clock(dc, dsi->clk_parent, plld, scdiv);
812 if (err < 0) {
813 dev_err(output->dev, "failed to setup DC clock: %d\n", err);
814 return false;
815 }
816
817 err = clk_set_rate(dsi->clk_parent, plld);
818 if (err < 0) {
819 dev_err(dsi->dev, "failed to set clock rate to %lu Hz\n",
820 plld);
821 return false;
822 }
91eded9b 823
3f6b406f 824 tegra_dsi_set_timeout(dsi, bclk, vrefresh);
dec72739 825
7e3bc3a9 826 err = tegra_dsi_set_phy_timing(dsi);
5b901e78
TR		 827 if (err < 0) {
828 dev_err(dsi->dev, "failed to setup D-PHY timing: %d\n", err);
829 return false;
830 }
7e3bc3a9 831
5b901e78
TR		 832 return true;
833}
834
835static void tegra_dsi_encoder_prepare(struct drm_encoder *encoder)
836{
837}
838
839static void tegra_dsi_encoder_commit(struct drm_encoder *encoder)
840{
dec72739
TR		 841}
842
5b901e78 843static void tegra_dsi_encoder_mode_set(struct drm_encoder *encoder,
dec72739 844 struct drm_display_mode *mode,
5b901e78
TR		 845 struct drm_display_mode *adjusted)
846{
847 struct tegra_output *output = encoder_to_output(encoder);
848 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
849 struct tegra_dsi *dsi = to_dsi(output);
850 u32 value;
851 int err;
852
853
854 err = tegra_dsi_configure(dsi, dc->pipe, mode);
855 if (err < 0) {
856 dev_err(dsi->dev, "failed to configure DSI: %d\n", err);
857 return;
858 }
859
860 if (output->panel)
861 drm_panel_prepare(output->panel);
862
863 /* enable display controller */
864 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
865 value |= DSI_ENABLE;
866 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
867
868 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
869 value &= ~DISP_CTRL_MODE_MASK;
870 value |= DISP_CTRL_MODE_C_DISPLAY;
871 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
872
873 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
874 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
875 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
876 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
877
878 tegra_dc_commit(dc);
879
880 /* enable DSI controller */
881 tegra_dsi_enable(dsi);
882
883 if (output->panel)
884 drm_panel_enable(output->panel);
885
886 return;
887}
888
889static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
dec72739 890{
5b901e78
TR		 891 struct tegra_output *output = encoder_to_output(encoder);
892 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
893 struct tegra_dsi *dsi = to_dsi(output);
894 u32 value;
895 int err;
896
897 if (output->panel)
898 drm_panel_disable(output->panel);
899
900 tegra_dsi_video_disable(dsi);
901
dec72739 902 /*
5b901e78
TR		 903 * The following accesses registers of the display controller, so make
904 * sure it's only executed when the output is attached to one.
dec72739 905 */
5b901e78
TR		 906 if (dc) {
907 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
908 value &= ~DSI_ENABLE;
909 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dec72739 910
5b901e78
TR		 911 tegra_dc_commit(dc);
912 }
dec72739 913
5b901e78
TR		 914 err = tegra_dsi_wait_idle(dsi, 100);
915 if (err < 0)
916 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
917
918 tegra_dsi_soft_reset(dsi);
919
920 if (output->panel)
921 drm_panel_unprepare(output->panel);
922
923 tegra_dsi_disable(dsi);
924
925 return;
dec72739
TR		 926}
927
5b901e78
TR		 928static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
929 .dpms = tegra_dsi_encoder_dpms,
930 .mode_fixup = tegra_dsi_encoder_mode_fixup,
931 .prepare = tegra_dsi_encoder_prepare,
932 .commit = tegra_dsi_encoder_commit,
933 .mode_set = tegra_dsi_encoder_mode_set,
934 .disable = tegra_dsi_encoder_disable,
dec72739
TR		 935};
936
937static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
938{
9c0b4ca1 939 u32 value;
dec72739
TR		 940
941 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
942 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
943
944 return 0;
945}
946
947static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
948{
183ef288 949 u32 value;
dec72739
TR		 950
951 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
952 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
953 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
954 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
955 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
956
957 /* start calibration */
958 tegra_dsi_pad_enable(dsi);
959
960 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
961 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
962 DSI_PAD_OUT_CLK(0x0);
963 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
964
965 return tegra_mipi_calibrate(dsi->mipi);
966}
967
968static int tegra_dsi_init(struct host1x_client *client)
969{
9910f5c4 970 struct drm_device *drm = dev_get_drvdata(client->parent);
dec72739 971 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
dec72739
TR		 972 int err;
973
201106d8
TR		 974 reset_control_deassert(dsi->rst);
975
976 err = tegra_dsi_pad_calibrate(dsi);
977 if (err < 0) {
978 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
979 goto reset;
980 }
981
e94236cd
TR		 982 /* Gangsters must not register their own outputs. */
983 if (!dsi->master) {
e94236cd 984 dsi->output.dev = client->dev;
e94236cd 985
5b901e78
TR		 986 drm_connector_init(drm, &dsi->output.connector,
987 &tegra_dsi_connector_funcs,
988 DRM_MODE_CONNECTOR_DSI);
989 drm_connector_helper_add(&dsi->output.connector,
990 &tegra_dsi_connector_helper_funcs);
991 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
992
5b901e78
TR		 993 drm_encoder_init(drm, &dsi->output.encoder,
994 &tegra_dsi_encoder_funcs,
995 DRM_MODE_ENCODER_DSI);
996 drm_encoder_helper_add(&dsi->output.encoder,
997 &tegra_dsi_encoder_helper_funcs);
998
999 drm_mode_connector_attach_encoder(&dsi->output.connector,
1000 &dsi->output.encoder);
1001 drm_connector_register(&dsi->output.connector);
1002
ea130b24
TR		 1003 err = tegra_output_init(drm, &dsi->output);
1004 if (err < 0) {
1005 dev_err(client->dev,
1006 "failed to initialize output: %d\n",
1007 err);
1008 goto reset;
1009 }
1010
5b901e78 1011 dsi->output.encoder.possible_crtcs = 0x3;
dec72739
TR		 1012 }
1013
1014 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1015 err = tegra_dsi_debugfs_init(dsi, drm->primary);
dec72739
TR		 1016 if (err < 0)
1017 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
1018 }
1019
dec72739 1020 return 0;
201106d8
TR		 1021
1022reset:
1023 reset_control_assert(dsi->rst);
1024 return err;
dec72739
TR		 1025}
1026
1027static int tegra_dsi_exit(struct host1x_client *client)
1028{
1029 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
dec72739 1030
5b901e78
TR		 1031 tegra_output_exit(&dsi->output);
1032
4009c224
TR		 1033 if (IS_ENABLED(CONFIG_DEBUG_FS))
1034 tegra_dsi_debugfs_exit(dsi);
dec72739 1035
201106d8
TR		 1036 reset_control_assert(dsi->rst);
1037
dec72739
TR		 1038 return 0;
1039}
1040
1041static const struct host1x_client_ops dsi_client_ops = {
1042 .init = tegra_dsi_init,
1043 .exit = tegra_dsi_exit,
1044};
1045
1046static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1047{
1048 struct clk *parent;
1049 int err;
1050
1051 parent = clk_get_parent(dsi->clk);
1052 if (!parent)
1053 return -EINVAL;
1054
1055 err = clk_set_parent(parent, dsi->clk_parent);
1056 if (err < 0)
1057 return err;
1058
1059 return 0;
1060}
1061
0fffdf6c
TR		 1062static const char * const error_report[16] = {
1063 "SoT Error",
1064 "SoT Sync Error",
1065 "EoT Sync Error",
1066 "Escape Mode Entry Command Error",
1067 "Low-Power Transmit Sync Error",
1068 "Peripheral Timeout Error",
1069 "False Control Error",
1070 "Contention Detected",
1071 "ECC Error, single-bit",
1072 "ECC Error, multi-bit",
1073 "Checksum Error",
1074 "DSI Data Type Not Recognized",
1075 "DSI VC ID Invalid",
1076 "Invalid Transmission Length",
1077 "Reserved",
1078 "DSI Protocol Violation",
1079};
1080
1081static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1082 const struct mipi_dsi_msg *msg,
1083 size_t count)
1084{
1085 u8 *rx = msg->rx_buf;
1086 unsigned int i, j, k;
1087 size_t size = 0;
1088 u16 errors;
1089 u32 value;
1090
1091 /* read and parse packet header */
1092 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1093
1094 switch (value & 0x3f) {
1095 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1096 errors = (value >> 8) & 0xffff;
1097 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1098 errors);
1099 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1100 if (errors & BIT(i))
1101 dev_dbg(dsi->dev, " %2u: %s\n", i,
1102 error_report[i]);
1103 break;
1104
1105 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1106 rx[0] = (value >> 8) & 0xff;
1107 size = 1;
1108 break;
1109
1110 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1111 rx[0] = (value >> 8) & 0xff;
1112 rx[1] = (value >> 16) & 0xff;
1113 size = 2;
1114 break;
1115
1116 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1117 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1118 break;
1119
1120 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1121 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1122 break;
1123
1124 default:
1125 dev_err(dsi->dev, "unhandled response type: %02x\n",
1126 value & 0x3f);
1127 return -EPROTO;
1128 }
1129
1130 size = min(size, msg->rx_len);
1131
1132 if (msg->rx_buf && size > 0) {
1133 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1134 u8 *rx = msg->rx_buf + j;
1135
1136 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1137
1138 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1139 rx[j + k] = (value >> (k << 3)) & 0xff;
1140 }
1141 }
1142
1143 return size;
1144}
1145
1146static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1147{
1148 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1149
1150 timeout = jiffies + msecs_to_jiffies(timeout);
1151
1152 while (time_before(jiffies, timeout)) {
1153 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1154 if ((value & DSI_TRIGGER_HOST) == 0)
1155 return 0;
1156
1157 usleep_range(1000, 2000);
1158 }
1159
1160 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1161 return -ETIMEDOUT;
1162}
1163
1164static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1165 unsigned long timeout)
1166{
1167 timeout = jiffies + msecs_to_jiffies(250);
1168
1169 while (time_before(jiffies, timeout)) {
1170 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1171 u8 count = value & 0x1f;
1172
1173 if (count > 0)
1174 return count;
1175
1176 usleep_range(1000, 2000);
1177 }
1178
1179 DRM_DEBUG_KMS("peripheral returned no data\n");
1180 return -ETIMEDOUT;
1181}
1182
1183static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1184 const void *buffer, size_t size)
1185{
1186 const u8 *buf = buffer;
1187 size_t i, j;
1188 u32 value;
1189
1190 for (j = 0; j < size; j += 4) {
1191 value = 0;
1192
1193 for (i = 0; i < 4 && j + i < size; i++)
1194 value |= buf[j + i] << (i << 3);
1195
1196 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1197 }
1198}
1199
1200static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1201 const struct mipi_dsi_msg *msg)
1202{
1203 struct tegra_dsi *dsi = host_to_tegra(host);
1204 struct mipi_dsi_packet packet;
1205 const u8 *header;
1206 size_t count;
1207 ssize_t err;
1208 u32 value;
1209
1210 err = mipi_dsi_create_packet(&packet, msg);
1211 if (err < 0)
1212 return err;
1213
1214 header = packet.header;
1215
1216 /* maximum FIFO depth is 1920 words */
1217 if (packet.size > dsi->video_fifo_depth * 4)
1218 return -ENOSPC;
1219
1220 /* reset underflow/overflow flags */
1221 value = tegra_dsi_readl(dsi, DSI_STATUS);
1222 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1223 value = DSI_HOST_CONTROL_FIFO_RESET;
1224 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1225 usleep_range(10, 20);
1226 }
1227
1228 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1229 value |= DSI_POWER_CONTROL_ENABLE;
1230 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1231
1232 usleep_range(5000, 10000);
1233
1234 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1235 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1236
1237 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1238 value |= DSI_HOST_CONTROL_HS;
1239
1240 /*
1241 * The host FIFO has a maximum of 64 words, so larger transmissions
1242 * need to use the video FIFO.
1243 */
1244 if (packet.size > dsi->host_fifo_depth * 4)
1245 value |= DSI_HOST_CONTROL_FIFO_SEL;
1246
1247 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1248
1249 /*
1250 * For reads and messages with explicitly requested ACK, generate a
1251 * BTA sequence after the transmission of the packet.
1252 */
1253 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1254 (msg->rx_buf && msg->rx_len > 0)) {
1255 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1256 value |= DSI_HOST_CONTROL_PKT_BTA;
1257 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1258 }
1259
1260 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1261 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1262
1263 /* write packet header, ECC is generated by hardware */
1264 value = header[2] << 16 | header[1] << 8 | header[0];
1265 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1266
1267 /* write payload (if any) */
1268 if (packet.payload_length > 0)
1269 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1270 packet.payload_length);
1271
1272 err = tegra_dsi_transmit(dsi, 250);
1273 if (err < 0)
1274 return err;
1275
1276 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1277 (msg->rx_buf && msg->rx_len > 0)) {
1278 err = tegra_dsi_wait_for_response(dsi, 250);
1279 if (err < 0)
1280 return err;
1281
1282 count = err;
1283
1284 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1285 switch (value) {
1286 case 0x84:
1287 /*
1288 dev_dbg(dsi->dev, "ACK\n");
1289 */
1290 break;
1291
1292 case 0x87:
1293 /*
1294 dev_dbg(dsi->dev, "ESCAPE\n");
1295 */
1296 break;
1297
1298 default:
1299 dev_err(dsi->dev, "unknown status: %08x\n", value);
1300 break;
1301 }
1302
1303 if (count > 1) {
1304 err = tegra_dsi_read_response(dsi, msg, count);
1305 if (err < 0)
1306 dev_err(dsi->dev,
1307 "failed to parse response: %zd\n",
1308 err);
1309 else {
1310 /*
1311 * For read commands, return the number of
1312 * bytes returned by the peripheral.
1313 */
1314 count = err;
1315 }
1316 }
1317 } else {
1318 /*
1319 * For write commands, we have transmitted the 4-byte header
1320 * plus the variable-length payload.
1321 */
1322 count = 4 + packet.payload_length;
1323 }
1324
1325 return count;
1326}
1327
e94236cd
TR		 1328static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1329{
1330 struct clk *parent;
1331 int err;
1332
1333 /* make sure both DSI controllers share the same PLL */
1334 parent = clk_get_parent(dsi->slave->clk);
1335 if (!parent)
1336 return -EINVAL;
1337
1338 err = clk_set_parent(parent, dsi->clk_parent);
1339 if (err < 0)
1340 return err;
1341
1342 return 0;
1343}
1344
dec72739
TR		 1345static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1346 struct mipi_dsi_device *device)
1347{
1348 struct tegra_dsi *dsi = host_to_tegra(host);
dec72739 1349
17297a28 1350 dsi->flags = device->mode_flags;
dec72739
TR		 1351 dsi->format = device->format;
1352 dsi->lanes = device->lanes;
1353
e94236cd
TR		 1354 if (dsi->slave) {
1355 int err;
1356
1357 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1358 dev_name(&device->dev));
1359
1360 err = tegra_dsi_ganged_setup(dsi);
1361 if (err < 0) {
1362 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1363 err);
1364 return err;
1365 }
1366 }
1367
1368 /*
1369 * Slaves don't have a panel associated with them, so they provide
1370 * merely the second channel.
1371 */
1372 if (!dsi->master) {
1373 struct tegra_output *output = &dsi->output;
1374
1375 output->panel = of_drm_find_panel(device->dev.of_node);
1376 if (output->panel && output->connector.dev) {
1377 drm_panel_attach(output->panel, &output->connector);
dec72739 1378 drm_helper_hpd_irq_event(output->connector.dev);
e94236cd 1379 }
dec72739
TR		 1380 }
1381
1382 return 0;
1383}
1384
1385static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1386 struct mipi_dsi_device *device)
1387{
1388 struct tegra_dsi *dsi = host_to_tegra(host);
1389 struct tegra_output *output = &dsi->output;
1390
1391 if (output->panel && &device->dev == output->panel->dev) {
ba3df979
TR		 1392 output->panel = NULL;
1393
dec72739
TR		 1394 if (output->connector.dev)
1395 drm_helper_hpd_irq_event(output->connector.dev);
dec72739
TR		 1396 }
1397
1398 return 0;
1399}
1400
1401static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1402 .attach = tegra_dsi_host_attach,
1403 .detach = tegra_dsi_host_detach,
0fffdf6c 1404 .transfer = tegra_dsi_host_transfer,
dec72739
TR		 1405};
1406
e94236cd
TR		 1407static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1408{
1409 struct device_node *np;
1410
1411 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1412 if (np) {
1413 struct platform_device *gangster = of_find_device_by_node(np);
1414
1415 dsi->slave = platform_get_drvdata(gangster);
1416 of_node_put(np);
1417
1418 if (!dsi->slave)
1419 return -EPROBE_DEFER;
1420
1421 dsi->slave->master = dsi;
1422 }
1423
1424 return 0;
1425}
1426
dec72739
TR		 1427static int tegra_dsi_probe(struct platform_device *pdev)
1428{
1429 struct tegra_dsi *dsi;
1430 struct resource *regs;
1431 int err;
1432
1433 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1434 if (!dsi)
1435 return -ENOMEM;
1436
1437 dsi->output.dev = dsi->dev = &pdev->dev;
976cebc3
TR		 1438 dsi->video_fifo_depth = 1920;
1439 dsi->host_fifo_depth = 64;
dec72739 1440
e94236cd
TR		 1441 err = tegra_dsi_ganged_probe(dsi);
1442 if (err < 0)
1443 return err;
1444
dec72739
TR		 1445 err = tegra_output_probe(&dsi->output);
1446 if (err < 0)
1447 return err;
1448
ba3df979
TR		 1449 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1450
dec72739
TR		 1451 /*
1452 * Assume these values by default. When a DSI peripheral driver
1453 * attaches to the DSI host, the parameters will be taken from
1454 * the attached device.
1455 */
17297a28 1456 dsi->flags = MIPI_DSI_MODE_VIDEO;
dec72739
TR		 1457 dsi->format = MIPI_DSI_FMT_RGB888;
1458 dsi->lanes = 4;
1459
1460 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1461 if (IS_ERR(dsi->rst))
1462 return PTR_ERR(dsi->rst);
1463
1464 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1465 if (IS_ERR(dsi->clk)) {
1466 dev_err(&pdev->dev, "cannot get DSI clock\n");
d2d0a9d2
TR		 1467 err = PTR_ERR(dsi->clk);
1468 goto reset;
dec72739
TR		 1469 }
1470
1471 err = clk_prepare_enable(dsi->clk);
1472 if (err < 0) {
1473 dev_err(&pdev->dev, "cannot enable DSI clock\n");
d2d0a9d2 1474 goto reset;
dec72739
TR		 1475 }
1476
1477 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1478 if (IS_ERR(dsi->clk_lp)) {
1479 dev_err(&pdev->dev, "cannot get low-power clock\n");
d2d0a9d2
TR		 1480 err = PTR_ERR(dsi->clk_lp);
1481 goto disable_clk;
dec72739
TR		 1482 }
1483
1484 err = clk_prepare_enable(dsi->clk_lp);
1485 if (err < 0) {
1486 dev_err(&pdev->dev, "cannot enable low-power clock\n");
d2d0a9d2 1487 goto disable_clk;
dec72739
TR		 1488 }
1489
1490 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1491 if (IS_ERR(dsi->clk_parent)) {
1492 dev_err(&pdev->dev, "cannot get parent clock\n");
d2d0a9d2
TR		 1493 err = PTR_ERR(dsi->clk_parent);
1494 goto disable_clk_lp;
dec72739
TR		 1495 }
1496
3b077afb
TR		 1497 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1498 if (IS_ERR(dsi->vdd)) {
1499 dev_err(&pdev->dev, "cannot get VDD supply\n");
d2d0a9d2
TR		 1500 err = PTR_ERR(dsi->vdd);
1501 goto disable_clk_lp;
3b077afb
TR		 1502 }
1503
1504 err = regulator_enable(dsi->vdd);
1505 if (err < 0) {
1506 dev_err(&pdev->dev, "cannot enable VDD supply\n");
d2d0a9d2 1507 goto disable_clk_lp;
3b077afb
TR		 1508 }
1509
dec72739
TR		 1510 err = tegra_dsi_setup_clocks(dsi);
1511 if (err < 0) {
1512 dev_err(&pdev->dev, "cannot setup clocks\n");
d2d0a9d2 1513 goto disable_vdd;
dec72739
TR		 1514 }
1515
1516 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1517 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
d2d0a9d2
TR		 1518 if (IS_ERR(dsi->regs)) {
1519 err = PTR_ERR(dsi->regs);
1520 goto disable_vdd;
1521 }
dec72739 1522
dec72739 1523 dsi->mipi = tegra_mipi_request(&pdev->dev);
d2d0a9d2
TR		 1524 if (IS_ERR(dsi->mipi)) {
1525 err = PTR_ERR(dsi->mipi);
1526 goto disable_vdd;
1527 }
dec72739
TR		 1528
1529 dsi->host.ops = &tegra_dsi_host_ops;
1530 dsi->host.dev = &pdev->dev;
1531
1532 err = mipi_dsi_host_register(&dsi->host);
1533 if (err < 0) {
1534 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
d2d0a9d2 1535 goto mipi_free;
dec72739
TR		 1536 }
1537
1538 INIT_LIST_HEAD(&dsi->client.list);
1539 dsi->client.ops = &dsi_client_ops;
1540 dsi->client.dev = &pdev->dev;
1541
1542 err = host1x_client_register(&dsi->client);
1543 if (err < 0) {
1544 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1545 err);
d2d0a9d2 1546 goto unregister;
dec72739
TR		 1547 }
1548
1549 platform_set_drvdata(pdev, dsi);
1550
1551 return 0;
d2d0a9d2
TR		 1552
1553unregister:
1554 mipi_dsi_host_unregister(&dsi->host);
1555mipi_free:
1556 tegra_mipi_free(dsi->mipi);
1557disable_vdd:
1558 regulator_disable(dsi->vdd);
1559disable_clk_lp:
1560 clk_disable_unprepare(dsi->clk_lp);
1561disable_clk:
1562 clk_disable_unprepare(dsi->clk);
1563reset:
1564 reset_control_assert(dsi->rst);
1565 return err;
dec72739
TR		 1566}
1567
1568static int tegra_dsi_remove(struct platform_device *pdev)
1569{
1570 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1571 int err;
1572
1573 err = host1x_client_unregister(&dsi->client);
1574 if (err < 0) {
1575 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1576 err);
1577 return err;
1578 }
1579
328ec69e 1580 tegra_output_remove(&dsi->output);
5b901e78 1581
dec72739
TR		 1582 mipi_dsi_host_unregister(&dsi->host);
1583 tegra_mipi_free(dsi->mipi);
1584
3b077afb 1585 regulator_disable(dsi->vdd);
dec72739
TR		 1586 clk_disable_unprepare(dsi->clk_lp);
1587 clk_disable_unprepare(dsi->clk);
cb825d89 1588 reset_control_assert(dsi->rst);
dec72739 1589
dec72739
TR		 1590 return 0;
1591}
1592
1593static const struct of_device_id tegra_dsi_of_match[] = {
1594 { .compatible = "nvidia,tegra114-dsi", },
1595 { },
1596};
ef70728c 1597MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
dec72739
TR		 1598
1599struct platform_driver tegra_dsi_driver = {
1600 .driver = {
1601 .name = "tegra-dsi",
1602 .of_match_table = tegra_dsi_of_match,
1603 },
1604 .probe = tegra_dsi_probe,
1605 .remove = tegra_dsi_remove,
1606};
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