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drm/tegra: rgb: Implement ->atomic_check()
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / tegra / dsi.c
CommitLineData
dec72739
TR		 1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
9a2ac2dc
TR		 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
dec72739
TR		 7 */
8
9#include <linux/clk.h>
10#include <linux/debugfs.h>
11#include <linux/host1x.h>
12#include <linux/module.h>
13#include <linux/of.h>
e94236cd 14#include <linux/of_platform.h>
dec72739
TR		 15#include <linux/platform_device.h>
16#include <linux/reset.h>
17
3b077afb
TR		 18#include <linux/regulator/consumer.h>
19
4aa3df71 20#include <drm/drm_atomic_helper.h>
dec72739
TR		 21#include <drm/drm_mipi_dsi.h>
22#include <drm/drm_panel.h>
23
24#include <video/mipi_display.h>
25
26#include "dc.h"
27#include "drm.h"
28#include "dsi.h"
29#include "mipi-phy.h"
30
dec72739
TR		 31struct tegra_dsi {
32 struct host1x_client client;
33 struct tegra_output output;
34 struct device *dev;
35
36 void __iomem *regs;
37
38 struct reset_control *rst;
39 struct clk *clk_parent;
40 struct clk *clk_lp;
41 struct clk *clk;
42
43 struct drm_info_list *debugfs_files;
44 struct drm_minor *minor;
45 struct dentry *debugfs;
46
17297a28 47 unsigned long flags;
dec72739
TR		 48 enum mipi_dsi_pixel_format format;
49 unsigned int lanes;
50
51 struct tegra_mipi_device *mipi;
52 struct mipi_dsi_host host;
3b077afb
TR		 53
54 struct regulator *vdd;
976cebc3
TR		 55
56 unsigned int video_fifo_depth;
57 unsigned int host_fifo_depth;
e94236cd
TR		 58
59 /* for ganged-mode support */
60 struct tegra_dsi *master;
61 struct tegra_dsi *slave;
dec72739
TR		 62};
63
64static inline struct tegra_dsi *
65host1x_client_to_dsi(struct host1x_client *client)
66{
67 return container_of(client, struct tegra_dsi, client);
68}
69
70static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
71{
72 return container_of(host, struct tegra_dsi, host);
73}
74
75static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
76{
77 return container_of(output, struct tegra_dsi, output);
78}
79
9c0b4ca1 80static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg)
dec72739
TR		 81{
82 return readl(dsi->regs + (reg << 2));
83}
84
9c0b4ca1 85static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
dec72739
TR		 86 unsigned long reg)
87{
88 writel(value, dsi->regs + (reg << 2));
89}
90
91static int tegra_dsi_show_regs(struct seq_file *s, void *data)
92{
93 struct drm_info_node *node = s->private;
94 struct tegra_dsi *dsi = node->info_ent->data;
95
96#define DUMP_REG(name) \
9c0b4ca1 97 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
dec72739
TR		 98 tegra_dsi_readl(dsi, name))
99
100 DUMP_REG(DSI_INCR_SYNCPT);
101 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
102 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
103 DUMP_REG(DSI_CTXSW);
104 DUMP_REG(DSI_RD_DATA);
105 DUMP_REG(DSI_WR_DATA);
106 DUMP_REG(DSI_POWER_CONTROL);
107 DUMP_REG(DSI_INT_ENABLE);
108 DUMP_REG(DSI_INT_STATUS);
109 DUMP_REG(DSI_INT_MASK);
110 DUMP_REG(DSI_HOST_CONTROL);
111 DUMP_REG(DSI_CONTROL);
112 DUMP_REG(DSI_SOL_DELAY);
113 DUMP_REG(DSI_MAX_THRESHOLD);
114 DUMP_REG(DSI_TRIGGER);
115 DUMP_REG(DSI_TX_CRC);
116 DUMP_REG(DSI_STATUS);
117
118 DUMP_REG(DSI_INIT_SEQ_CONTROL);
119 DUMP_REG(DSI_INIT_SEQ_DATA_0);
120 DUMP_REG(DSI_INIT_SEQ_DATA_1);
121 DUMP_REG(DSI_INIT_SEQ_DATA_2);
122 DUMP_REG(DSI_INIT_SEQ_DATA_3);
123 DUMP_REG(DSI_INIT_SEQ_DATA_4);
124 DUMP_REG(DSI_INIT_SEQ_DATA_5);
125 DUMP_REG(DSI_INIT_SEQ_DATA_6);
126 DUMP_REG(DSI_INIT_SEQ_DATA_7);
127
128 DUMP_REG(DSI_PKT_SEQ_0_LO);
129 DUMP_REG(DSI_PKT_SEQ_0_HI);
130 DUMP_REG(DSI_PKT_SEQ_1_LO);
131 DUMP_REG(DSI_PKT_SEQ_1_HI);
132 DUMP_REG(DSI_PKT_SEQ_2_LO);
133 DUMP_REG(DSI_PKT_SEQ_2_HI);
134 DUMP_REG(DSI_PKT_SEQ_3_LO);
135 DUMP_REG(DSI_PKT_SEQ_3_HI);
136 DUMP_REG(DSI_PKT_SEQ_4_LO);
137 DUMP_REG(DSI_PKT_SEQ_4_HI);
138 DUMP_REG(DSI_PKT_SEQ_5_LO);
139 DUMP_REG(DSI_PKT_SEQ_5_HI);
140
141 DUMP_REG(DSI_DCS_CMDS);
142
143 DUMP_REG(DSI_PKT_LEN_0_1);
144 DUMP_REG(DSI_PKT_LEN_2_3);
145 DUMP_REG(DSI_PKT_LEN_4_5);
146 DUMP_REG(DSI_PKT_LEN_6_7);
147
148 DUMP_REG(DSI_PHY_TIMING_0);
149 DUMP_REG(DSI_PHY_TIMING_1);
150 DUMP_REG(DSI_PHY_TIMING_2);
151 DUMP_REG(DSI_BTA_TIMING);
152
153 DUMP_REG(DSI_TIMEOUT_0);
154 DUMP_REG(DSI_TIMEOUT_1);
155 DUMP_REG(DSI_TO_TALLY);
156
157 DUMP_REG(DSI_PAD_CONTROL_0);
158 DUMP_REG(DSI_PAD_CONTROL_CD);
159 DUMP_REG(DSI_PAD_CD_STATUS);
160 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
161 DUMP_REG(DSI_PAD_CONTROL_1);
162 DUMP_REG(DSI_PAD_CONTROL_2);
163 DUMP_REG(DSI_PAD_CONTROL_3);
164 DUMP_REG(DSI_PAD_CONTROL_4);
165
166 DUMP_REG(DSI_GANGED_MODE_CONTROL);
167 DUMP_REG(DSI_GANGED_MODE_START);
168 DUMP_REG(DSI_GANGED_MODE_SIZE);
169
170 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
171 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
172
173 DUMP_REG(DSI_INIT_SEQ_DATA_8);
174 DUMP_REG(DSI_INIT_SEQ_DATA_9);
175 DUMP_REG(DSI_INIT_SEQ_DATA_10);
176 DUMP_REG(DSI_INIT_SEQ_DATA_11);
177 DUMP_REG(DSI_INIT_SEQ_DATA_12);
178 DUMP_REG(DSI_INIT_SEQ_DATA_13);
179 DUMP_REG(DSI_INIT_SEQ_DATA_14);
180 DUMP_REG(DSI_INIT_SEQ_DATA_15);
181
182#undef DUMP_REG
183
184 return 0;
185}
186
187static struct drm_info_list debugfs_files[] = {
188 { "regs", tegra_dsi_show_regs, 0, NULL },
189};
190
191static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
192 struct drm_minor *minor)
193{
194 const char *name = dev_name(dsi->dev);
195 unsigned int i;
196 int err;
197
198 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
199 if (!dsi->debugfs)
200 return -ENOMEM;
201
202 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
203 GFP_KERNEL);
204 if (!dsi->debugfs_files) {
205 err = -ENOMEM;
206 goto remove;
207 }
208
209 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
210 dsi->debugfs_files[i].data = dsi;
211
212 err = drm_debugfs_create_files(dsi->debugfs_files,
213 ARRAY_SIZE(debugfs_files),
214 dsi->debugfs, minor);
215 if (err < 0)
216 goto free;
217
218 dsi->minor = minor;
219
220 return 0;
221
222free:
223 kfree(dsi->debugfs_files);
224 dsi->debugfs_files = NULL;
225remove:
226 debugfs_remove(dsi->debugfs);
227 dsi->debugfs = NULL;
228
229 return err;
230}
231
4009c224 232static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
dec72739
TR		 233{
234 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
235 dsi->minor);
236 dsi->minor = NULL;
237
238 kfree(dsi->debugfs_files);
239 dsi->debugfs_files = NULL;
240
241 debugfs_remove(dsi->debugfs);
242 dsi->debugfs = NULL;
dec72739
TR		 243}
244
245#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
246#define PKT_LEN0(len) (((len) & 0x07) << 0)
247#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
248#define PKT_LEN1(len) (((len) & 0x07) << 10)
249#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
250#define PKT_LEN2(len) (((len) & 0x07) << 20)
251
252#define PKT_LP (1 << 30)
253#define NUM_PKT_SEQ 12
254
17297a28
TR		 255/*
256 * non-burst mode with sync pulses
257 */
258static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
dec72739
TR		 259 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
260 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
261 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
262 PKT_LP,
263 [ 1] = 0,
264 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
265 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
266 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
267 PKT_LP,
268 [ 3] = 0,
269 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
270 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
271 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
272 PKT_LP,
273 [ 5] = 0,
274 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
275 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
276 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
277 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
278 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
279 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
280 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
281 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
282 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
283 PKT_LP,
284 [ 9] = 0,
285 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
286 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
287 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
288 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
289 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
290 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
291};
292
17297a28
TR		 293/*
294 * non-burst mode with sync events
295 */
296static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
297 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
298 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
299 PKT_LP,
300 [ 1] = 0,
301 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
302 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
303 PKT_LP,
304 [ 3] = 0,
305 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
306 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
307 PKT_LP,
308 [ 5] = 0,
309 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
310 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
311 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
312 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
313 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
314 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
315 PKT_LP,
316 [ 9] = 0,
317 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
318 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
319 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
320 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
321};
322
337b443d
TR		 323static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
324 [ 0] = 0,
325 [ 1] = 0,
326 [ 2] = 0,
327 [ 3] = 0,
328 [ 4] = 0,
329 [ 5] = 0,
330 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
331 [ 7] = 0,
332 [ 8] = 0,
333 [ 9] = 0,
334 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
335 [11] = 0,
336};
337
dec72739
TR		 338static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
339{
340 struct mipi_dphy_timing timing;
9c0b4ca1
TR		 341 unsigned long period;
342 u32 value;
dec72739
TR		 343 long rate;
344 int err;
345
346 rate = clk_get_rate(dsi->clk);
347 if (rate < 0)
348 return rate;
349
369bc65b 350 period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate * 2);
dec72739
TR		 351
352 err = mipi_dphy_timing_get_default(&timing, period);
353 if (err < 0)
354 return err;
355
356 err = mipi_dphy_timing_validate(&timing, period);
357 if (err < 0) {
358 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
359 return err;
360 }
361
362 /*
363 * The D-PHY timing fields below are expressed in byte-clock cycles,
364 * so multiply the period by 8.
365 */
366 period *= 8;
367
368 value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
369 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
370 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
371 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
372 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
373
374 value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
375 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
376 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
377 DSI_TIMING_FIELD(timing.lpx, period, 1);
378 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
379
380 value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
381 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
382 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
383 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
384
385 value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
386 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
387 DSI_TIMING_FIELD(timing.tago, period, 1);
388 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
389
7e3bc3a9
SP		 390 if (dsi->slave)
391 return tegra_dsi_set_phy_timing(dsi->slave);
392
dec72739
TR		 393 return 0;
394}
395
396static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
397 unsigned int *mulp, unsigned int *divp)
398{
399 switch (format) {
400 case MIPI_DSI_FMT_RGB666_PACKED:
401 case MIPI_DSI_FMT_RGB888:
402 *mulp = 3;
403 *divp = 1;
404 break;
405
406 case MIPI_DSI_FMT_RGB565:
407 *mulp = 2;
408 *divp = 1;
409 break;
410
411 case MIPI_DSI_FMT_RGB666:
412 *mulp = 9;
413 *divp = 4;
414 break;
415
416 default:
417 return -EINVAL;
418 }
419
420 return 0;
421}
422
f7d6889b
TR		 423static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
424 enum tegra_dsi_format *fmt)
425{
426 switch (format) {
427 case MIPI_DSI_FMT_RGB888:
428 *fmt = TEGRA_DSI_FORMAT_24P;
429 break;
430
431 case MIPI_DSI_FMT_RGB666:
432 *fmt = TEGRA_DSI_FORMAT_18NP;
433 break;
434
435 case MIPI_DSI_FMT_RGB666_PACKED:
436 *fmt = TEGRA_DSI_FORMAT_18P;
437 break;
438
439 case MIPI_DSI_FMT_RGB565:
440 *fmt = TEGRA_DSI_FORMAT_16P;
441 break;
442
443 default:
444 return -EINVAL;
445 }
446
447 return 0;
448}
449
e94236cd
TR		 450static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
451 unsigned int size)
452{
453 u32 value;
454
455 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
456 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
457
458 value = DSI_GANGED_MODE_CONTROL_ENABLE;
459 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
460}
461
563eff1f
TR		 462static void tegra_dsi_enable(struct tegra_dsi *dsi)
463{
464 u32 value;
465
466 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
467 value |= DSI_POWER_CONTROL_ENABLE;
468 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
e94236cd
TR		 469
470 if (dsi->slave)
471 tegra_dsi_enable(dsi->slave);
472}
473
474static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
475{
476 if (dsi->master)
477 return dsi->master->lanes + dsi->lanes;
478
479 if (dsi->slave)
480 return dsi->lanes + dsi->slave->lanes;
481
482 return dsi->lanes;
563eff1f
TR		 483}
484
485static int tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
486 const struct drm_display_mode *mode)
dec72739 487{
dec72739 488 unsigned int hact, hsw, hbp, hfp, i, mul, div;
f7d6889b 489 enum tegra_dsi_format format;
17297a28 490 const u32 *pkt_seq;
563eff1f 491 u32 value;
dec72739
TR		 492 int err;
493
17297a28
TR		 494 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
495 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
496 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
337b443d 497 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
17297a28
TR		 498 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
499 pkt_seq = pkt_seq_video_non_burst_sync_events;
337b443d
TR		 500 } else {
501 DRM_DEBUG_KMS("Command mode\n");
502 pkt_seq = pkt_seq_command_mode;
17297a28
TR		 503 }
504
dec72739
TR		 505 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
506 if (err < 0)
507 return err;
508
f7d6889b
TR		 509 err = tegra_dsi_get_format(dsi->format, &format);
510 if (err < 0)
511 return err;
512
f7d6889b 513 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
dec72739 514 DSI_CONTROL_LANES(dsi->lanes - 1) |
563eff1f 515 DSI_CONTROL_SOURCE(pipe);
dec72739
TR		 516 tegra_dsi_writel(dsi, value, DSI_CONTROL);
517
976cebc3 518 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
dec72739 519
563eff1f 520 value = DSI_HOST_CONTROL_HS;
dec72739
TR		 521 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
522
523 value = tegra_dsi_readl(dsi, DSI_CONTROL);
563eff1f 524
0c6b1e4b
AC		 525 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
526 value |= DSI_CONTROL_HS_CLK_CTRL;
563eff1f 527
dec72739 528 value &= ~DSI_CONTROL_TX_TRIG(3);
337b443d
TR		 529
530 /* enable DCS commands for command mode */
531 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
532 value &= ~DSI_CONTROL_DCS_ENABLE;
533 else
534 value |= DSI_CONTROL_DCS_ENABLE;
535
dec72739
TR		 536 value |= DSI_CONTROL_VIDEO_ENABLE;
537 value &= ~DSI_CONTROL_HOST_ENABLE;
538 tegra_dsi_writel(dsi, value, DSI_CONTROL);
539
dec72739
TR		 540 for (i = 0; i < NUM_PKT_SEQ; i++)
541 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
542
337b443d
TR		 543 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
544 /* horizontal active pixels */
545 hact = mode->hdisplay * mul / div;
546
547 /* horizontal sync width */
548 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
549 hsw -= 10;
550
551 /* horizontal back porch */
552 hbp = (mode->htotal - mode->hsync_end) * mul / div;
553 hbp -= 14;
554
555 /* horizontal front porch */
556 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
557 hfp -= 8;
dec72739 558
337b443d
TR		 559 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
560 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
561 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
562 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
dec72739 563
337b443d
TR		 564 /* set SOL delay (for non-burst mode only) */
565 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
e94236cd
TR		 566
567 /* TODO: implement ganged mode */
337b443d
TR		 568 } else {
569 u16 bytes;
570
e94236cd
TR		 571 if (dsi->master || dsi->slave) {
572 /*
573 * For ganged mode, assume symmetric left-right mode.
574 */
575 bytes = 1 + (mode->hdisplay / 2) * mul / div;
576 } else {
577 /* 1 byte (DCS command) + pixel data */
578 bytes = 1 + mode->hdisplay * mul / div;
579 }
dec72739 580
337b443d
TR		 581 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
582 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
583 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
584 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
dec72739 585
337b443d
TR		 586 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
587 MIPI_DCS_WRITE_MEMORY_CONTINUE;
588 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
dec72739 589
e94236cd
TR		 590 /* set SOL delay */
591 if (dsi->master || dsi->slave) {
592 unsigned int lanes = tegra_dsi_get_lanes(dsi);
593 unsigned long delay, bclk, bclk_ganged;
594
595 /* SOL to valid, valid to FIFO and FIFO write delay */
596 delay = 4 + 4 + 2;
597 delay = DIV_ROUND_UP(delay * mul, div * lanes);
598 /* FIFO read delay */
599 delay = delay + 6;
600
601 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
602 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
603 value = bclk - bclk_ganged + delay + 20;
604 } else {
605 /* TODO: revisit for non-ganged mode */
606 value = 8 * mul / div;
607 }
337b443d
TR		 608
609 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
610 }
dec72739 611
e94236cd
TR		 612 if (dsi->slave) {
613 err = tegra_dsi_configure(dsi->slave, pipe, mode);
614 if (err < 0)
615 return err;
616
617 /*
618 * TODO: Support modes other than symmetrical left-right
619 * split.
620 */
621 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
622 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
623 mode->hdisplay / 2);
624 }
625
563eff1f
TR		 626 return 0;
627}
628
563eff1f
TR		 629static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
630{
631 u32 value;
632
633 timeout = jiffies + msecs_to_jiffies(timeout);
634
635 while (time_before(jiffies, timeout)) {
636 value = tegra_dsi_readl(dsi, DSI_STATUS);
637 if (value & DSI_STATUS_IDLE)
638 return 0;
639
640 usleep_range(1000, 2000);
641 }
642
643 return -ETIMEDOUT;
644}
645
646static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
647{
648 u32 value;
649
650 value = tegra_dsi_readl(dsi, DSI_CONTROL);
651 value &= ~DSI_CONTROL_VIDEO_ENABLE;
652 tegra_dsi_writel(dsi, value, DSI_CONTROL);
e94236cd
TR		 653
654 if (dsi->slave)
655 tegra_dsi_video_disable(dsi->slave);
656}
657
658static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
659{
660 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
661 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
662 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
563eff1f
TR		 663}
664
5b901e78
TR		 665static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
666 unsigned int vrefresh)
667{
668 unsigned int timeout;
669 u32 value;
670
671 /* one frame high-speed transmission timeout */
672 timeout = (bclk / vrefresh) / 512;
673 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
674 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
675
676 /* 2 ms peripheral timeout for panel */
677 timeout = 2 * bclk / 512 * 1000;
678 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
679 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
680
681 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
682 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
683
684 if (dsi->slave)
685 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
686}
687
563eff1f
TR		 688static void tegra_dsi_disable(struct tegra_dsi *dsi)
689{
690 u32 value;
691
e94236cd
TR		 692 if (dsi->slave) {
693 tegra_dsi_ganged_disable(dsi->slave);
694 tegra_dsi_ganged_disable(dsi);
695 }
696
563eff1f
TR		 697 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
698 value &= ~DSI_POWER_CONTROL_ENABLE;
699 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
700
e94236cd
TR		 701 if (dsi->slave)
702 tegra_dsi_disable(dsi->slave);
703
563eff1f
TR		 704 usleep_range(5000, 10000);
705}
706
92f0e073
TR		 707static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
708{
709 u32 value;
710
711 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
712 value &= ~DSI_POWER_CONTROL_ENABLE;
713 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
714
715 usleep_range(300, 1000);
716
717 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
718 value |= DSI_POWER_CONTROL_ENABLE;
719 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
720
721 usleep_range(300, 1000);
722
723 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
724 if (value)
725 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
726
727 if (dsi->slave)
728 tegra_dsi_soft_reset(dsi->slave);
729}
730
5b901e78 731static void tegra_dsi_connector_dpms(struct drm_connector *connector, int mode)
dec72739 732{
dec72739
TR		 733}
734
5b901e78
TR		 735static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
736 .dpms = tegra_dsi_connector_dpms,
9d44189f 737 .reset = drm_atomic_helper_connector_reset,
5b901e78
TR		 738 .detect = tegra_output_connector_detect,
739 .fill_modes = drm_helper_probe_single_connector_modes,
740 .destroy = tegra_output_connector_destroy,
9d44189f 741 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4aa3df71 742 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5b901e78 743};
3f6b406f 744
5b901e78
TR		 745static enum drm_mode_status
746tegra_dsi_connector_mode_valid(struct drm_connector *connector,
747 struct drm_display_mode *mode)
748{
749 return MODE_OK;
750}
3f6b406f 751
5b901e78
TR		 752static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
753 .get_modes = tegra_output_connector_get_modes,
754 .mode_valid = tegra_dsi_connector_mode_valid,
755 .best_encoder = tegra_output_connector_best_encoder,
756};
3f6b406f 757
5b901e78
TR		 758static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
759 .destroy = tegra_output_encoder_destroy,
760};
e94236cd 761
5b901e78
TR		 762static void tegra_dsi_encoder_dpms(struct drm_encoder *encoder, int mode)
763{
3f6b406f
TR		 764}
765
5b901e78
TR		 766static bool tegra_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
767 const struct drm_display_mode *mode,
768 struct drm_display_mode *adjusted)
dec72739 769{
5b901e78
TR		 770 struct tegra_output *output = encoder_to_output(encoder);
771 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
772 unsigned int mul, div, scdiv, vrefresh, lanes;
dec72739 773 struct tegra_dsi *dsi = to_dsi(output);
5b901e78 774 unsigned long pclk, bclk, plld;
dec72739
TR		 775 int err;
776
e94236cd 777 lanes = tegra_dsi_get_lanes(dsi);
5b901e78 778 pclk = mode->clock * 1000;
e94236cd 779
dec72739
TR		 780 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
781 if (err < 0)
782 return err;
783
e94236cd 784 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, lanes);
dec72739 785 vrefresh = drm_mode_vrefresh(mode);
91eded9b 786 DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh);
dec72739 787
91eded9b 788 /* compute byte clock */
e94236cd 789 bclk = (pclk * mul) / (div * lanes);
91eded9b
TR		 790
791 /*
792 * Compute bit clock and round up to the next MHz.
793 */
030611ec 794 plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
91eded9b
TR		 795
796 /*
797 * We divide the frequency by two here, but we make up for that by
798 * setting the shift clock divider (further below) to half of the
799 * correct value.
800 */
801 plld /= 2;
dec72739 802
91eded9b
TR		 803 /*
804 * Derive pixel clock from bit clock using the shift clock divider.
805 * Note that this is only half of what we would expect, but we need
806 * that to make up for the fact that we divided the bit clock by a
807 * factor of two above.
808 *
809 * It's not clear exactly why this is necessary, but the display is
810 * not working properly otherwise. Perhaps the PLLs cannot generate
811 * frequencies sufficiently high.
812 */
5b901e78
TR		 813 scdiv = ((8 * mul) / (div * lanes)) - 2;
814
815 err = tegra_dc_setup_clock(dc, dsi->clk_parent, plld, scdiv);
816 if (err < 0) {
817 dev_err(output->dev, "failed to setup DC clock: %d\n", err);
818 return false;
819 }
820
821 err = clk_set_rate(dsi->clk_parent, plld);
822 if (err < 0) {
823 dev_err(dsi->dev, "failed to set clock rate to %lu Hz\n",
824 plld);
825 return false;
826 }
91eded9b 827
3f6b406f 828 tegra_dsi_set_timeout(dsi, bclk, vrefresh);
dec72739 829
7e3bc3a9 830 err = tegra_dsi_set_phy_timing(dsi);
5b901e78
TR		 831 if (err < 0) {
832 dev_err(dsi->dev, "failed to setup D-PHY timing: %d\n", err);
833 return false;
834 }
7e3bc3a9 835
5b901e78
TR		 836 return true;
837}
838
839static void tegra_dsi_encoder_prepare(struct drm_encoder *encoder)
840{
841}
842
843static void tegra_dsi_encoder_commit(struct drm_encoder *encoder)
844{
dec72739
TR		 845}
846
5b901e78 847static void tegra_dsi_encoder_mode_set(struct drm_encoder *encoder,
dec72739 848 struct drm_display_mode *mode,
5b901e78
TR		 849 struct drm_display_mode *adjusted)
850{
851 struct tegra_output *output = encoder_to_output(encoder);
852 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
853 struct tegra_dsi *dsi = to_dsi(output);
854 u32 value;
855 int err;
856
857
858 err = tegra_dsi_configure(dsi, dc->pipe, mode);
859 if (err < 0) {
860 dev_err(dsi->dev, "failed to configure DSI: %d\n", err);
861 return;
862 }
863
864 if (output->panel)
865 drm_panel_prepare(output->panel);
866
867 /* enable display controller */
868 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
869 value |= DSI_ENABLE;
870 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
871
872 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
873 value &= ~DISP_CTRL_MODE_MASK;
874 value |= DISP_CTRL_MODE_C_DISPLAY;
875 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
876
877 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
878 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
879 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
880 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
881
882 tegra_dc_commit(dc);
883
884 /* enable DSI controller */
885 tegra_dsi_enable(dsi);
886
887 if (output->panel)
888 drm_panel_enable(output->panel);
889
890 return;
891}
892
893static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
dec72739 894{
5b901e78
TR		 895 struct tegra_output *output = encoder_to_output(encoder);
896 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
897 struct tegra_dsi *dsi = to_dsi(output);
898 u32 value;
899 int err;
900
901 if (output->panel)
902 drm_panel_disable(output->panel);
903
904 tegra_dsi_video_disable(dsi);
905
dec72739 906 /*
5b901e78
TR		 907 * The following accesses registers of the display controller, so make
908 * sure it's only executed when the output is attached to one.
dec72739 909 */
5b901e78
TR		 910 if (dc) {
911 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
912 value &= ~DSI_ENABLE;
913 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dec72739 914
5b901e78
TR		 915 tegra_dc_commit(dc);
916 }
dec72739 917
5b901e78
TR		 918 err = tegra_dsi_wait_idle(dsi, 100);
919 if (err < 0)
920 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
921
922 tegra_dsi_soft_reset(dsi);
923
924 if (output->panel)
925 drm_panel_unprepare(output->panel);
926
927 tegra_dsi_disable(dsi);
928
929 return;
dec72739
TR		 930}
931
5b901e78
TR		 932static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
933 .dpms = tegra_dsi_encoder_dpms,
934 .mode_fixup = tegra_dsi_encoder_mode_fixup,
935 .prepare = tegra_dsi_encoder_prepare,
936 .commit = tegra_dsi_encoder_commit,
937 .mode_set = tegra_dsi_encoder_mode_set,
938 .disable = tegra_dsi_encoder_disable,
dec72739
TR		 939};
940
941static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
942{
9c0b4ca1 943 u32 value;
dec72739
TR		 944
945 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
946 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
947
948 return 0;
949}
950
951static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
952{
183ef288 953 u32 value;
dec72739
TR		 954
955 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
956 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
957 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
958 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
959 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
960
961 /* start calibration */
962 tegra_dsi_pad_enable(dsi);
963
964 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
965 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
966 DSI_PAD_OUT_CLK(0x0);
967 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
968
969 return tegra_mipi_calibrate(dsi->mipi);
970}
971
972static int tegra_dsi_init(struct host1x_client *client)
973{
9910f5c4 974 struct drm_device *drm = dev_get_drvdata(client->parent);
dec72739 975 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
dec72739
TR		 976 int err;
977
201106d8
TR		 978 reset_control_deassert(dsi->rst);
979
980 err = tegra_dsi_pad_calibrate(dsi);
981 if (err < 0) {
982 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
983 goto reset;
984 }
985
e94236cd
TR		 986 /* Gangsters must not register their own outputs. */
987 if (!dsi->master) {
e94236cd 988 dsi->output.dev = client->dev;
e94236cd 989
5b901e78
TR		 990 drm_connector_init(drm, &dsi->output.connector,
991 &tegra_dsi_connector_funcs,
992 DRM_MODE_CONNECTOR_DSI);
993 drm_connector_helper_add(&dsi->output.connector,
994 &tegra_dsi_connector_helper_funcs);
995 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
996
5b901e78
TR		 997 drm_encoder_init(drm, &dsi->output.encoder,
998 &tegra_dsi_encoder_funcs,
999 DRM_MODE_ENCODER_DSI);
1000 drm_encoder_helper_add(&dsi->output.encoder,
1001 &tegra_dsi_encoder_helper_funcs);
1002
1003 drm_mode_connector_attach_encoder(&dsi->output.connector,
1004 &dsi->output.encoder);
1005 drm_connector_register(&dsi->output.connector);
1006
ea130b24
TR		 1007 err = tegra_output_init(drm, &dsi->output);
1008 if (err < 0) {
1009 dev_err(client->dev,
1010 "failed to initialize output: %d\n",
1011 err);
1012 goto reset;
1013 }
1014
5b901e78 1015 dsi->output.encoder.possible_crtcs = 0x3;
dec72739
TR		 1016 }
1017
1018 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1019 err = tegra_dsi_debugfs_init(dsi, drm->primary);
dec72739
TR		 1020 if (err < 0)
1021 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
1022 }
1023
dec72739 1024 return 0;
201106d8
TR		 1025
1026reset:
1027 reset_control_assert(dsi->rst);
1028 return err;
dec72739
TR		 1029}
1030
1031static int tegra_dsi_exit(struct host1x_client *client)
1032{
1033 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
dec72739 1034
5b901e78
TR		 1035 tegra_output_exit(&dsi->output);
1036
4009c224
TR		 1037 if (IS_ENABLED(CONFIG_DEBUG_FS))
1038 tegra_dsi_debugfs_exit(dsi);
dec72739 1039
201106d8
TR		 1040 reset_control_assert(dsi->rst);
1041
dec72739
TR		 1042 return 0;
1043}
1044
1045static const struct host1x_client_ops dsi_client_ops = {
1046 .init = tegra_dsi_init,
1047 .exit = tegra_dsi_exit,
1048};
1049
1050static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1051{
1052 struct clk *parent;
1053 int err;
1054
1055 parent = clk_get_parent(dsi->clk);
1056 if (!parent)
1057 return -EINVAL;
1058
1059 err = clk_set_parent(parent, dsi->clk_parent);
1060 if (err < 0)
1061 return err;
1062
1063 return 0;
1064}
1065
0fffdf6c
TR		 1066static const char * const error_report[16] = {
1067 "SoT Error",
1068 "SoT Sync Error",
1069 "EoT Sync Error",
1070 "Escape Mode Entry Command Error",
1071 "Low-Power Transmit Sync Error",
1072 "Peripheral Timeout Error",
1073 "False Control Error",
1074 "Contention Detected",
1075 "ECC Error, single-bit",
1076 "ECC Error, multi-bit",
1077 "Checksum Error",
1078 "DSI Data Type Not Recognized",
1079 "DSI VC ID Invalid",
1080 "Invalid Transmission Length",
1081 "Reserved",
1082 "DSI Protocol Violation",
1083};
1084
1085static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1086 const struct mipi_dsi_msg *msg,
1087 size_t count)
1088{
1089 u8 *rx = msg->rx_buf;
1090 unsigned int i, j, k;
1091 size_t size = 0;
1092 u16 errors;
1093 u32 value;
1094
1095 /* read and parse packet header */
1096 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1097
1098 switch (value & 0x3f) {
1099 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1100 errors = (value >> 8) & 0xffff;
1101 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1102 errors);
1103 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1104 if (errors & BIT(i))
1105 dev_dbg(dsi->dev, " %2u: %s\n", i,
1106 error_report[i]);
1107 break;
1108
1109 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1110 rx[0] = (value >> 8) & 0xff;
1111 size = 1;
1112 break;
1113
1114 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1115 rx[0] = (value >> 8) & 0xff;
1116 rx[1] = (value >> 16) & 0xff;
1117 size = 2;
1118 break;
1119
1120 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1121 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1122 break;
1123
1124 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1125 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1126 break;
1127
1128 default:
1129 dev_err(dsi->dev, "unhandled response type: %02x\n",
1130 value & 0x3f);
1131 return -EPROTO;
1132 }
1133
1134 size = min(size, msg->rx_len);
1135
1136 if (msg->rx_buf && size > 0) {
1137 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1138 u8 *rx = msg->rx_buf + j;
1139
1140 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1141
1142 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1143 rx[j + k] = (value >> (k << 3)) & 0xff;
1144 }
1145 }
1146
1147 return size;
1148}
1149
1150static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1151{
1152 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1153
1154 timeout = jiffies + msecs_to_jiffies(timeout);
1155
1156 while (time_before(jiffies, timeout)) {
1157 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1158 if ((value & DSI_TRIGGER_HOST) == 0)
1159 return 0;
1160
1161 usleep_range(1000, 2000);
1162 }
1163
1164 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1165 return -ETIMEDOUT;
1166}
1167
1168static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1169 unsigned long timeout)
1170{
1171 timeout = jiffies + msecs_to_jiffies(250);
1172
1173 while (time_before(jiffies, timeout)) {
1174 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1175 u8 count = value & 0x1f;
1176
1177 if (count > 0)
1178 return count;
1179
1180 usleep_range(1000, 2000);
1181 }
1182
1183 DRM_DEBUG_KMS("peripheral returned no data\n");
1184 return -ETIMEDOUT;
1185}
1186
1187static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1188 const void *buffer, size_t size)
1189{
1190 const u8 *buf = buffer;
1191 size_t i, j;
1192 u32 value;
1193
1194 for (j = 0; j < size; j += 4) {
1195 value = 0;
1196
1197 for (i = 0; i < 4 && j + i < size; i++)
1198 value |= buf[j + i] << (i << 3);
1199
1200 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1201 }
1202}
1203
1204static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1205 const struct mipi_dsi_msg *msg)
1206{
1207 struct tegra_dsi *dsi = host_to_tegra(host);
1208 struct mipi_dsi_packet packet;
1209 const u8 *header;
1210 size_t count;
1211 ssize_t err;
1212 u32 value;
1213
1214 err = mipi_dsi_create_packet(&packet, msg);
1215 if (err < 0)
1216 return err;
1217
1218 header = packet.header;
1219
1220 /* maximum FIFO depth is 1920 words */
1221 if (packet.size > dsi->video_fifo_depth * 4)
1222 return -ENOSPC;
1223
1224 /* reset underflow/overflow flags */
1225 value = tegra_dsi_readl(dsi, DSI_STATUS);
1226 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1227 value = DSI_HOST_CONTROL_FIFO_RESET;
1228 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1229 usleep_range(10, 20);
1230 }
1231
1232 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1233 value |= DSI_POWER_CONTROL_ENABLE;
1234 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1235
1236 usleep_range(5000, 10000);
1237
1238 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1239 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1240
1241 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1242 value |= DSI_HOST_CONTROL_HS;
1243
1244 /*
1245 * The host FIFO has a maximum of 64 words, so larger transmissions
1246 * need to use the video FIFO.
1247 */
1248 if (packet.size > dsi->host_fifo_depth * 4)
1249 value |= DSI_HOST_CONTROL_FIFO_SEL;
1250
1251 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1252
1253 /*
1254 * For reads and messages with explicitly requested ACK, generate a
1255 * BTA sequence after the transmission of the packet.
1256 */
1257 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1258 (msg->rx_buf && msg->rx_len > 0)) {
1259 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1260 value |= DSI_HOST_CONTROL_PKT_BTA;
1261 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1262 }
1263
1264 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1265 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1266
1267 /* write packet header, ECC is generated by hardware */
1268 value = header[2] << 16 | header[1] << 8 | header[0];
1269 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1270
1271 /* write payload (if any) */
1272 if (packet.payload_length > 0)
1273 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1274 packet.payload_length);
1275
1276 err = tegra_dsi_transmit(dsi, 250);
1277 if (err < 0)
1278 return err;
1279
1280 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1281 (msg->rx_buf && msg->rx_len > 0)) {
1282 err = tegra_dsi_wait_for_response(dsi, 250);
1283 if (err < 0)
1284 return err;
1285
1286 count = err;
1287
1288 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1289 switch (value) {
1290 case 0x84:
1291 /*
1292 dev_dbg(dsi->dev, "ACK\n");
1293 */
1294 break;
1295
1296 case 0x87:
1297 /*
1298 dev_dbg(dsi->dev, "ESCAPE\n");
1299 */
1300 break;
1301
1302 default:
1303 dev_err(dsi->dev, "unknown status: %08x\n", value);
1304 break;
1305 }
1306
1307 if (count > 1) {
1308 err = tegra_dsi_read_response(dsi, msg, count);
1309 if (err < 0)
1310 dev_err(dsi->dev,
1311 "failed to parse response: %zd\n",
1312 err);
1313 else {
1314 /*
1315 * For read commands, return the number of
1316 * bytes returned by the peripheral.
1317 */
1318 count = err;
1319 }
1320 }
1321 } else {
1322 /*
1323 * For write commands, we have transmitted the 4-byte header
1324 * plus the variable-length payload.
1325 */
1326 count = 4 + packet.payload_length;
1327 }
1328
1329 return count;
1330}
1331
e94236cd
TR		 1332static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1333{
1334 struct clk *parent;
1335 int err;
1336
1337 /* make sure both DSI controllers share the same PLL */
1338 parent = clk_get_parent(dsi->slave->clk);
1339 if (!parent)
1340 return -EINVAL;
1341
1342 err = clk_set_parent(parent, dsi->clk_parent);
1343 if (err < 0)
1344 return err;
1345
1346 return 0;
1347}
1348
dec72739
TR		 1349static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1350 struct mipi_dsi_device *device)
1351{
1352 struct tegra_dsi *dsi = host_to_tegra(host);
dec72739 1353
17297a28 1354 dsi->flags = device->mode_flags;
dec72739
TR		 1355 dsi->format = device->format;
1356 dsi->lanes = device->lanes;
1357
e94236cd
TR		 1358 if (dsi->slave) {
1359 int err;
1360
1361 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1362 dev_name(&device->dev));
1363
1364 err = tegra_dsi_ganged_setup(dsi);
1365 if (err < 0) {
1366 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1367 err);
1368 return err;
1369 }
1370 }
1371
1372 /*
1373 * Slaves don't have a panel associated with them, so they provide
1374 * merely the second channel.
1375 */
1376 if (!dsi->master) {
1377 struct tegra_output *output = &dsi->output;
1378
1379 output->panel = of_drm_find_panel(device->dev.of_node);
1380 if (output->panel && output->connector.dev) {
1381 drm_panel_attach(output->panel, &output->connector);
dec72739 1382 drm_helper_hpd_irq_event(output->connector.dev);
e94236cd 1383 }
dec72739
TR		 1384 }
1385
1386 return 0;
1387}
1388
1389static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1390 struct mipi_dsi_device *device)
1391{
1392 struct tegra_dsi *dsi = host_to_tegra(host);
1393 struct tegra_output *output = &dsi->output;
1394
1395 if (output->panel && &device->dev == output->panel->dev) {
ba3df979
TR		 1396 output->panel = NULL;
1397
dec72739
TR		 1398 if (output->connector.dev)
1399 drm_helper_hpd_irq_event(output->connector.dev);
dec72739
TR		 1400 }
1401
1402 return 0;
1403}
1404
1405static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1406 .attach = tegra_dsi_host_attach,
1407 .detach = tegra_dsi_host_detach,
0fffdf6c 1408 .transfer = tegra_dsi_host_transfer,
dec72739
TR		 1409};
1410
e94236cd
TR		 1411static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1412{
1413 struct device_node *np;
1414
1415 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1416 if (np) {
1417 struct platform_device *gangster = of_find_device_by_node(np);
1418
1419 dsi->slave = platform_get_drvdata(gangster);
1420 of_node_put(np);
1421
1422 if (!dsi->slave)
1423 return -EPROBE_DEFER;
1424
1425 dsi->slave->master = dsi;
1426 }
1427
1428 return 0;
1429}
1430
dec72739
TR		 1431static int tegra_dsi_probe(struct platform_device *pdev)
1432{
1433 struct tegra_dsi *dsi;
1434 struct resource *regs;
1435 int err;
1436
1437 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1438 if (!dsi)
1439 return -ENOMEM;
1440
1441 dsi->output.dev = dsi->dev = &pdev->dev;
976cebc3
TR		 1442 dsi->video_fifo_depth = 1920;
1443 dsi->host_fifo_depth = 64;
dec72739 1444
e94236cd
TR		 1445 err = tegra_dsi_ganged_probe(dsi);
1446 if (err < 0)
1447 return err;
1448
dec72739
TR		 1449 err = tegra_output_probe(&dsi->output);
1450 if (err < 0)
1451 return err;
1452
ba3df979
TR		 1453 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1454
dec72739
TR		 1455 /*
1456 * Assume these values by default. When a DSI peripheral driver
1457 * attaches to the DSI host, the parameters will be taken from
1458 * the attached device.
1459 */
17297a28 1460 dsi->flags = MIPI_DSI_MODE_VIDEO;
dec72739
TR		 1461 dsi->format = MIPI_DSI_FMT_RGB888;
1462 dsi->lanes = 4;
1463
1464 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1465 if (IS_ERR(dsi->rst))
1466 return PTR_ERR(dsi->rst);
1467
1468 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1469 if (IS_ERR(dsi->clk)) {
1470 dev_err(&pdev->dev, "cannot get DSI clock\n");
d2d0a9d2
TR		 1471 err = PTR_ERR(dsi->clk);
1472 goto reset;
dec72739
TR		 1473 }
1474
1475 err = clk_prepare_enable(dsi->clk);
1476 if (err < 0) {
1477 dev_err(&pdev->dev, "cannot enable DSI clock\n");
d2d0a9d2 1478 goto reset;
dec72739
TR		 1479 }
1480
1481 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1482 if (IS_ERR(dsi->clk_lp)) {
1483 dev_err(&pdev->dev, "cannot get low-power clock\n");
d2d0a9d2
TR		 1484 err = PTR_ERR(dsi->clk_lp);
1485 goto disable_clk;
dec72739
TR		 1486 }
1487
1488 err = clk_prepare_enable(dsi->clk_lp);
1489 if (err < 0) {
1490 dev_err(&pdev->dev, "cannot enable low-power clock\n");
d2d0a9d2 1491 goto disable_clk;
dec72739
TR		 1492 }
1493
1494 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1495 if (IS_ERR(dsi->clk_parent)) {
1496 dev_err(&pdev->dev, "cannot get parent clock\n");
d2d0a9d2
TR		 1497 err = PTR_ERR(dsi->clk_parent);
1498 goto disable_clk_lp;
dec72739
TR		 1499 }
1500
3b077afb
TR		 1501 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1502 if (IS_ERR(dsi->vdd)) {
1503 dev_err(&pdev->dev, "cannot get VDD supply\n");
d2d0a9d2
TR		 1504 err = PTR_ERR(dsi->vdd);
1505 goto disable_clk_lp;
3b077afb
TR		 1506 }
1507
1508 err = regulator_enable(dsi->vdd);
1509 if (err < 0) {
1510 dev_err(&pdev->dev, "cannot enable VDD supply\n");
d2d0a9d2 1511 goto disable_clk_lp;
3b077afb
TR		 1512 }
1513
dec72739
TR		 1514 err = tegra_dsi_setup_clocks(dsi);
1515 if (err < 0) {
1516 dev_err(&pdev->dev, "cannot setup clocks\n");
d2d0a9d2 1517 goto disable_vdd;
dec72739
TR		 1518 }
1519
1520 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1521 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
d2d0a9d2
TR		 1522 if (IS_ERR(dsi->regs)) {
1523 err = PTR_ERR(dsi->regs);
1524 goto disable_vdd;
1525 }
dec72739 1526
dec72739 1527 dsi->mipi = tegra_mipi_request(&pdev->dev);
d2d0a9d2
TR		 1528 if (IS_ERR(dsi->mipi)) {
1529 err = PTR_ERR(dsi->mipi);
1530 goto disable_vdd;
1531 }
dec72739
TR		 1532
1533 dsi->host.ops = &tegra_dsi_host_ops;
1534 dsi->host.dev = &pdev->dev;
1535
1536 err = mipi_dsi_host_register(&dsi->host);
1537 if (err < 0) {
1538 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
d2d0a9d2 1539 goto mipi_free;
dec72739
TR		 1540 }
1541
1542 INIT_LIST_HEAD(&dsi->client.list);
1543 dsi->client.ops = &dsi_client_ops;
1544 dsi->client.dev = &pdev->dev;
1545
1546 err = host1x_client_register(&dsi->client);
1547 if (err < 0) {
1548 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1549 err);
d2d0a9d2 1550 goto unregister;
dec72739
TR		 1551 }
1552
1553 platform_set_drvdata(pdev, dsi);
1554
1555 return 0;
d2d0a9d2
TR		 1556
1557unregister:
1558 mipi_dsi_host_unregister(&dsi->host);
1559mipi_free:
1560 tegra_mipi_free(dsi->mipi);
1561disable_vdd:
1562 regulator_disable(dsi->vdd);
1563disable_clk_lp:
1564 clk_disable_unprepare(dsi->clk_lp);
1565disable_clk:
1566 clk_disable_unprepare(dsi->clk);
1567reset:
1568 reset_control_assert(dsi->rst);
1569 return err;
dec72739
TR		 1570}
1571
1572static int tegra_dsi_remove(struct platform_device *pdev)
1573{
1574 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1575 int err;
1576
1577 err = host1x_client_unregister(&dsi->client);
1578 if (err < 0) {
1579 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1580 err);
1581 return err;
1582 }
1583
328ec69e 1584 tegra_output_remove(&dsi->output);
5b901e78 1585
dec72739
TR		 1586 mipi_dsi_host_unregister(&dsi->host);
1587 tegra_mipi_free(dsi->mipi);
1588
3b077afb 1589 regulator_disable(dsi->vdd);
dec72739
TR		 1590 clk_disable_unprepare(dsi->clk_lp);
1591 clk_disable_unprepare(dsi->clk);
cb825d89 1592 reset_control_assert(dsi->rst);
dec72739 1593
dec72739
TR		 1594 return 0;
1595}
1596
1597static const struct of_device_id tegra_dsi_of_match[] = {
1598 { .compatible = "nvidia,tegra114-dsi", },
1599 { },
1600};
ef70728c 1601MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
dec72739
TR		 1602
1603struct platform_driver tegra_dsi_driver = {
1604 .driver = {
1605 .name = "tegra-dsi",
1606 .of_match_table = tegra_dsi_of_match,
1607 },
1608 .probe = tegra_dsi_probe,
1609 .remove = tegra_dsi_remove,
1610};
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