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Commit | Line | Data |
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6b6b6042 TR |
1 | /* |
2 | * Copyright (C) 2013 NVIDIA Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
a82752e1 | 10 | #include <linux/debugfs.h> |
6fad8f66 | 11 | #include <linux/gpio.h> |
6b6b6042 TR |
12 | #include <linux/io.h> |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/reset.h> | |
306a7f91 | 15 | |
7232398a | 16 | #include <soc/tegra/pmc.h> |
6b6b6042 | 17 | |
4aa3df71 | 18 | #include <drm/drm_atomic_helper.h> |
6b6b6042 | 19 | #include <drm/drm_dp_helper.h> |
6fad8f66 | 20 | #include <drm/drm_panel.h> |
6b6b6042 TR |
21 | |
22 | #include "dc.h" | |
23 | #include "drm.h" | |
24 | #include "sor.h" | |
25 | ||
26 | struct tegra_sor { | |
27 | struct host1x_client client; | |
28 | struct tegra_output output; | |
29 | struct device *dev; | |
30 | ||
31 | void __iomem *regs; | |
32 | ||
33 | struct reset_control *rst; | |
34 | struct clk *clk_parent; | |
35 | struct clk *clk_safe; | |
36 | struct clk *clk_dp; | |
37 | struct clk *clk; | |
38 | ||
39 | struct tegra_dpaux *dpaux; | |
40 | ||
86f5c52d | 41 | struct mutex lock; |
6b6b6042 | 42 | bool enabled; |
a82752e1 | 43 | |
dab16336 TR |
44 | struct drm_info_list *debugfs_files; |
45 | struct drm_minor *minor; | |
a82752e1 | 46 | struct dentry *debugfs; |
6b6b6042 TR |
47 | }; |
48 | ||
34fa183b TR |
49 | struct tegra_sor_config { |
50 | u32 bits_per_pixel; | |
51 | ||
52 | u32 active_polarity; | |
53 | u32 active_count; | |
54 | u32 tu_size; | |
55 | u32 active_frac; | |
56 | u32 watermark; | |
7890b576 TR |
57 | |
58 | u32 hblank_symbols; | |
59 | u32 vblank_symbols; | |
34fa183b TR |
60 | }; |
61 | ||
6b6b6042 TR |
62 | static inline struct tegra_sor * |
63 | host1x_client_to_sor(struct host1x_client *client) | |
64 | { | |
65 | return container_of(client, struct tegra_sor, client); | |
66 | } | |
67 | ||
68 | static inline struct tegra_sor *to_sor(struct tegra_output *output) | |
69 | { | |
70 | return container_of(output, struct tegra_sor, output); | |
71 | } | |
72 | ||
28fe2076 | 73 | static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) |
6b6b6042 TR |
74 | { |
75 | return readl(sor->regs + (offset << 2)); | |
76 | } | |
77 | ||
28fe2076 | 78 | static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, |
6b6b6042 TR |
79 | unsigned long offset) |
80 | { | |
81 | writel(value, sor->regs + (offset << 2)); | |
82 | } | |
83 | ||
84 | static int tegra_sor_dp_train_fast(struct tegra_sor *sor, | |
85 | struct drm_dp_link *link) | |
86 | { | |
6b6b6042 TR |
87 | unsigned int i; |
88 | u8 pattern; | |
28fe2076 | 89 | u32 value; |
6b6b6042 TR |
90 | int err; |
91 | ||
92 | /* setup lane parameters */ | |
93 | value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | | |
94 | SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | | |
95 | SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | | |
96 | SOR_LANE_DRIVE_CURRENT_LANE0(0x40); | |
a9a9e4fd | 97 | tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); |
6b6b6042 TR |
98 | |
99 | value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | | |
100 | SOR_LANE_PREEMPHASIS_LANE2(0x0f) | | |
101 | SOR_LANE_PREEMPHASIS_LANE1(0x0f) | | |
102 | SOR_LANE_PREEMPHASIS_LANE0(0x0f); | |
a9a9e4fd | 103 | tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); |
6b6b6042 | 104 | |
a9a9e4fd TR |
105 | value = SOR_LANE_POSTCURSOR_LANE3(0x00) | |
106 | SOR_LANE_POSTCURSOR_LANE2(0x00) | | |
107 | SOR_LANE_POSTCURSOR_LANE1(0x00) | | |
108 | SOR_LANE_POSTCURSOR_LANE0(0x00); | |
109 | tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); | |
6b6b6042 TR |
110 | |
111 | /* disable LVDS mode */ | |
112 | tegra_sor_writel(sor, 0, SOR_LVDS); | |
113 | ||
a9a9e4fd | 114 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6b6b6042 TR |
115 | value |= SOR_DP_PADCTL_TX_PU_ENABLE; |
116 | value &= ~SOR_DP_PADCTL_TX_PU_MASK; | |
117 | value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ | |
a9a9e4fd | 118 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 | 119 | |
a9a9e4fd | 120 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6b6b6042 TR |
121 | value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | |
122 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; | |
a9a9e4fd | 123 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 TR |
124 | |
125 | usleep_range(10, 100); | |
126 | ||
a9a9e4fd | 127 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6b6b6042 TR |
128 | value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | |
129 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); | |
a9a9e4fd | 130 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 TR |
131 | |
132 | err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B); | |
133 | if (err < 0) | |
134 | return err; | |
135 | ||
136 | for (i = 0, value = 0; i < link->num_lanes; i++) { | |
137 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | | |
138 | SOR_DP_TPG_SCRAMBLER_NONE | | |
139 | SOR_DP_TPG_PATTERN_TRAIN1; | |
140 | value = (value << 8) | lane; | |
141 | } | |
142 | ||
143 | tegra_sor_writel(sor, value, SOR_DP_TPG); | |
144 | ||
145 | pattern = DP_TRAINING_PATTERN_1; | |
146 | ||
147 | err = tegra_dpaux_train(sor->dpaux, link, pattern); | |
148 | if (err < 0) | |
149 | return err; | |
150 | ||
a9a9e4fd | 151 | value = tegra_sor_readl(sor, SOR_DP_SPARE0); |
6b6b6042 TR |
152 | value |= SOR_DP_SPARE_SEQ_ENABLE; |
153 | value &= ~SOR_DP_SPARE_PANEL_INTERNAL; | |
154 | value |= SOR_DP_SPARE_MACRO_SOR_CLK; | |
a9a9e4fd | 155 | tegra_sor_writel(sor, value, SOR_DP_SPARE0); |
6b6b6042 TR |
156 | |
157 | for (i = 0, value = 0; i < link->num_lanes; i++) { | |
158 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | | |
159 | SOR_DP_TPG_SCRAMBLER_NONE | | |
160 | SOR_DP_TPG_PATTERN_TRAIN2; | |
161 | value = (value << 8) | lane; | |
162 | } | |
163 | ||
164 | tegra_sor_writel(sor, value, SOR_DP_TPG); | |
165 | ||
166 | pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; | |
167 | ||
168 | err = tegra_dpaux_train(sor->dpaux, link, pattern); | |
169 | if (err < 0) | |
170 | return err; | |
171 | ||
172 | for (i = 0, value = 0; i < link->num_lanes; i++) { | |
173 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | | |
174 | SOR_DP_TPG_SCRAMBLER_GALIOS | | |
175 | SOR_DP_TPG_PATTERN_NONE; | |
176 | value = (value << 8) | lane; | |
177 | } | |
178 | ||
179 | tegra_sor_writel(sor, value, SOR_DP_TPG); | |
180 | ||
181 | pattern = DP_TRAINING_PATTERN_DISABLE; | |
182 | ||
183 | err = tegra_dpaux_train(sor->dpaux, link, pattern); | |
184 | if (err < 0) | |
185 | return err; | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
190 | static void tegra_sor_super_update(struct tegra_sor *sor) | |
191 | { | |
a9a9e4fd TR |
192 | tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); |
193 | tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); | |
194 | tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); | |
6b6b6042 TR |
195 | } |
196 | ||
197 | static void tegra_sor_update(struct tegra_sor *sor) | |
198 | { | |
a9a9e4fd TR |
199 | tegra_sor_writel(sor, 0, SOR_STATE0); |
200 | tegra_sor_writel(sor, 1, SOR_STATE0); | |
201 | tegra_sor_writel(sor, 0, SOR_STATE0); | |
6b6b6042 TR |
202 | } |
203 | ||
204 | static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) | |
205 | { | |
28fe2076 | 206 | u32 value; |
6b6b6042 TR |
207 | |
208 | value = tegra_sor_readl(sor, SOR_PWM_DIV); | |
209 | value &= ~SOR_PWM_DIV_MASK; | |
210 | value |= 0x400; /* period */ | |
211 | tegra_sor_writel(sor, value, SOR_PWM_DIV); | |
212 | ||
213 | value = tegra_sor_readl(sor, SOR_PWM_CTL); | |
214 | value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; | |
215 | value |= 0x400; /* duty cycle */ | |
216 | value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ | |
217 | value |= SOR_PWM_CTL_TRIGGER; | |
218 | tegra_sor_writel(sor, value, SOR_PWM_CTL); | |
219 | ||
220 | timeout = jiffies + msecs_to_jiffies(timeout); | |
221 | ||
222 | while (time_before(jiffies, timeout)) { | |
223 | value = tegra_sor_readl(sor, SOR_PWM_CTL); | |
224 | if ((value & SOR_PWM_CTL_TRIGGER) == 0) | |
225 | return 0; | |
226 | ||
227 | usleep_range(25, 100); | |
228 | } | |
229 | ||
230 | return -ETIMEDOUT; | |
231 | } | |
232 | ||
233 | static int tegra_sor_attach(struct tegra_sor *sor) | |
234 | { | |
235 | unsigned long value, timeout; | |
236 | ||
237 | /* wake up in normal mode */ | |
a9a9e4fd | 238 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
6b6b6042 TR |
239 | value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; |
240 | value |= SOR_SUPER_STATE_MODE_NORMAL; | |
a9a9e4fd | 241 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
6b6b6042 TR |
242 | tegra_sor_super_update(sor); |
243 | ||
244 | /* attach */ | |
a9a9e4fd | 245 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
6b6b6042 | 246 | value |= SOR_SUPER_STATE_ATTACHED; |
a9a9e4fd | 247 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
6b6b6042 TR |
248 | tegra_sor_super_update(sor); |
249 | ||
250 | timeout = jiffies + msecs_to_jiffies(250); | |
251 | ||
252 | while (time_before(jiffies, timeout)) { | |
253 | value = tegra_sor_readl(sor, SOR_TEST); | |
254 | if ((value & SOR_TEST_ATTACHED) != 0) | |
255 | return 0; | |
256 | ||
257 | usleep_range(25, 100); | |
258 | } | |
259 | ||
260 | return -ETIMEDOUT; | |
261 | } | |
262 | ||
263 | static int tegra_sor_wakeup(struct tegra_sor *sor) | |
264 | { | |
6b6b6042 TR |
265 | unsigned long value, timeout; |
266 | ||
6b6b6042 TR |
267 | timeout = jiffies + msecs_to_jiffies(250); |
268 | ||
269 | /* wait for head to wake up */ | |
270 | while (time_before(jiffies, timeout)) { | |
271 | value = tegra_sor_readl(sor, SOR_TEST); | |
272 | value &= SOR_TEST_HEAD_MODE_MASK; | |
273 | ||
274 | if (value == SOR_TEST_HEAD_MODE_AWAKE) | |
275 | return 0; | |
276 | ||
277 | usleep_range(25, 100); | |
278 | } | |
279 | ||
280 | return -ETIMEDOUT; | |
281 | } | |
282 | ||
283 | static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) | |
284 | { | |
28fe2076 | 285 | u32 value; |
6b6b6042 TR |
286 | |
287 | value = tegra_sor_readl(sor, SOR_PWR); | |
288 | value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; | |
289 | tegra_sor_writel(sor, value, SOR_PWR); | |
290 | ||
291 | timeout = jiffies + msecs_to_jiffies(timeout); | |
292 | ||
293 | while (time_before(jiffies, timeout)) { | |
294 | value = tegra_sor_readl(sor, SOR_PWR); | |
295 | if ((value & SOR_PWR_TRIGGER) == 0) | |
296 | return 0; | |
297 | ||
298 | usleep_range(25, 100); | |
299 | } | |
300 | ||
301 | return -ETIMEDOUT; | |
302 | } | |
303 | ||
34fa183b TR |
304 | struct tegra_sor_params { |
305 | /* number of link clocks per line */ | |
306 | unsigned int num_clocks; | |
307 | /* ratio between input and output */ | |
308 | u64 ratio; | |
309 | /* precision factor */ | |
310 | u64 precision; | |
311 | ||
312 | unsigned int active_polarity; | |
313 | unsigned int active_count; | |
314 | unsigned int active_frac; | |
315 | unsigned int tu_size; | |
316 | unsigned int error; | |
317 | }; | |
318 | ||
319 | static int tegra_sor_compute_params(struct tegra_sor *sor, | |
320 | struct tegra_sor_params *params, | |
321 | unsigned int tu_size) | |
322 | { | |
323 | u64 active_sym, active_count, frac, approx; | |
324 | u32 active_polarity, active_frac = 0; | |
325 | const u64 f = params->precision; | |
326 | s64 error; | |
327 | ||
328 | active_sym = params->ratio * tu_size; | |
329 | active_count = div_u64(active_sym, f) * f; | |
330 | frac = active_sym - active_count; | |
331 | ||
332 | /* fraction < 0.5 */ | |
333 | if (frac >= (f / 2)) { | |
334 | active_polarity = 1; | |
335 | frac = f - frac; | |
336 | } else { | |
337 | active_polarity = 0; | |
338 | } | |
339 | ||
340 | if (frac != 0) { | |
341 | frac = div_u64(f * f, frac); /* 1/fraction */ | |
342 | if (frac <= (15 * f)) { | |
343 | active_frac = div_u64(frac, f); | |
344 | ||
345 | /* round up */ | |
346 | if (active_polarity) | |
347 | active_frac++; | |
348 | } else { | |
349 | active_frac = active_polarity ? 1 : 15; | |
350 | } | |
351 | } | |
352 | ||
353 | if (active_frac == 1) | |
354 | active_polarity = 0; | |
355 | ||
356 | if (active_polarity == 1) { | |
357 | if (active_frac) { | |
358 | approx = active_count + (active_frac * (f - 1)) * f; | |
359 | approx = div_u64(approx, active_frac * f); | |
360 | } else { | |
361 | approx = active_count + f; | |
362 | } | |
363 | } else { | |
364 | if (active_frac) | |
365 | approx = active_count + div_u64(f, active_frac); | |
366 | else | |
367 | approx = active_count; | |
368 | } | |
369 | ||
370 | error = div_s64(active_sym - approx, tu_size); | |
371 | error *= params->num_clocks; | |
372 | ||
373 | if (error <= 0 && abs64(error) < params->error) { | |
374 | params->active_count = div_u64(active_count, f); | |
375 | params->active_polarity = active_polarity; | |
376 | params->active_frac = active_frac; | |
377 | params->error = abs64(error); | |
378 | params->tu_size = tu_size; | |
379 | ||
380 | if (error == 0) | |
381 | return true; | |
382 | } | |
383 | ||
384 | return false; | |
385 | } | |
386 | ||
387 | static int tegra_sor_calc_config(struct tegra_sor *sor, | |
388 | struct drm_display_mode *mode, | |
389 | struct tegra_sor_config *config, | |
390 | struct drm_dp_link *link) | |
391 | { | |
392 | const u64 f = 100000, link_rate = link->rate * 1000; | |
393 | const u64 pclk = mode->clock * 1000; | |
7890b576 | 394 | u64 input, output, watermark, num; |
34fa183b | 395 | struct tegra_sor_params params; |
34fa183b TR |
396 | u32 num_syms_per_line; |
397 | unsigned int i; | |
398 | ||
399 | if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) | |
400 | return -EINVAL; | |
401 | ||
402 | output = link_rate * 8 * link->num_lanes; | |
403 | input = pclk * config->bits_per_pixel; | |
404 | ||
405 | if (input >= output) | |
406 | return -ERANGE; | |
407 | ||
408 | memset(¶ms, 0, sizeof(params)); | |
409 | params.ratio = div64_u64(input * f, output); | |
410 | params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); | |
411 | params.precision = f; | |
412 | params.error = 64 * f; | |
413 | params.tu_size = 64; | |
414 | ||
415 | for (i = params.tu_size; i >= 32; i--) | |
416 | if (tegra_sor_compute_params(sor, ¶ms, i)) | |
417 | break; | |
418 | ||
419 | if (params.active_frac == 0) { | |
420 | config->active_polarity = 0; | |
421 | config->active_count = params.active_count; | |
422 | ||
423 | if (!params.active_polarity) | |
424 | config->active_count--; | |
425 | ||
426 | config->tu_size = params.tu_size; | |
427 | config->active_frac = 1; | |
428 | } else { | |
429 | config->active_polarity = params.active_polarity; | |
430 | config->active_count = params.active_count; | |
431 | config->active_frac = params.active_frac; | |
432 | config->tu_size = params.tu_size; | |
433 | } | |
434 | ||
435 | dev_dbg(sor->dev, | |
436 | "polarity: %d active count: %d tu size: %d active frac: %d\n", | |
437 | config->active_polarity, config->active_count, | |
438 | config->tu_size, config->active_frac); | |
439 | ||
440 | watermark = params.ratio * config->tu_size * (f - params.ratio); | |
441 | watermark = div_u64(watermark, f); | |
442 | ||
443 | watermark = div_u64(watermark + params.error, f); | |
444 | config->watermark = watermark + (config->bits_per_pixel / 8) + 2; | |
445 | num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * | |
446 | (link->num_lanes * 8); | |
447 | ||
448 | if (config->watermark > 30) { | |
449 | config->watermark = 30; | |
450 | dev_err(sor->dev, | |
451 | "unable to compute TU size, forcing watermark to %u\n", | |
452 | config->watermark); | |
453 | } else if (config->watermark > num_syms_per_line) { | |
454 | config->watermark = num_syms_per_line; | |
455 | dev_err(sor->dev, "watermark too high, forcing to %u\n", | |
456 | config->watermark); | |
457 | } | |
458 | ||
7890b576 TR |
459 | /* compute the number of symbols per horizontal blanking interval */ |
460 | num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; | |
461 | config->hblank_symbols = div_u64(num, pclk); | |
462 | ||
463 | if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) | |
464 | config->hblank_symbols -= 3; | |
465 | ||
466 | config->hblank_symbols -= 12 / link->num_lanes; | |
467 | ||
468 | /* compute the number of symbols per vertical blanking interval */ | |
469 | num = (mode->hdisplay - 25) * link_rate; | |
470 | config->vblank_symbols = div_u64(num, pclk); | |
471 | config->vblank_symbols -= 36 / link->num_lanes + 4; | |
472 | ||
473 | dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, | |
474 | config->vblank_symbols); | |
475 | ||
34fa183b TR |
476 | return 0; |
477 | } | |
478 | ||
6fad8f66 TR |
479 | static int tegra_sor_detach(struct tegra_sor *sor) |
480 | { | |
481 | unsigned long value, timeout; | |
482 | ||
483 | /* switch to safe mode */ | |
a9a9e4fd | 484 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
6fad8f66 | 485 | value &= ~SOR_SUPER_STATE_MODE_NORMAL; |
a9a9e4fd | 486 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
6fad8f66 TR |
487 | tegra_sor_super_update(sor); |
488 | ||
489 | timeout = jiffies + msecs_to_jiffies(250); | |
490 | ||
491 | while (time_before(jiffies, timeout)) { | |
492 | value = tegra_sor_readl(sor, SOR_PWR); | |
493 | if (value & SOR_PWR_MODE_SAFE) | |
494 | break; | |
495 | } | |
496 | ||
497 | if ((value & SOR_PWR_MODE_SAFE) == 0) | |
498 | return -ETIMEDOUT; | |
499 | ||
500 | /* go to sleep */ | |
a9a9e4fd | 501 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
6fad8f66 | 502 | value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; |
a9a9e4fd | 503 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
6fad8f66 TR |
504 | tegra_sor_super_update(sor); |
505 | ||
506 | /* detach */ | |
a9a9e4fd | 507 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
6fad8f66 | 508 | value &= ~SOR_SUPER_STATE_ATTACHED; |
a9a9e4fd | 509 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
6fad8f66 TR |
510 | tegra_sor_super_update(sor); |
511 | ||
512 | timeout = jiffies + msecs_to_jiffies(250); | |
513 | ||
514 | while (time_before(jiffies, timeout)) { | |
515 | value = tegra_sor_readl(sor, SOR_TEST); | |
516 | if ((value & SOR_TEST_ATTACHED) == 0) | |
517 | break; | |
518 | ||
519 | usleep_range(25, 100); | |
520 | } | |
521 | ||
522 | if ((value & SOR_TEST_ATTACHED) != 0) | |
523 | return -ETIMEDOUT; | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
528 | static int tegra_sor_power_down(struct tegra_sor *sor) | |
529 | { | |
530 | unsigned long value, timeout; | |
531 | int err; | |
532 | ||
533 | value = tegra_sor_readl(sor, SOR_PWR); | |
534 | value &= ~SOR_PWR_NORMAL_STATE_PU; | |
535 | value |= SOR_PWR_TRIGGER; | |
536 | tegra_sor_writel(sor, value, SOR_PWR); | |
537 | ||
538 | timeout = jiffies + msecs_to_jiffies(250); | |
539 | ||
540 | while (time_before(jiffies, timeout)) { | |
541 | value = tegra_sor_readl(sor, SOR_PWR); | |
542 | if ((value & SOR_PWR_TRIGGER) == 0) | |
543 | return 0; | |
544 | ||
545 | usleep_range(25, 100); | |
546 | } | |
547 | ||
548 | if ((value & SOR_PWR_TRIGGER) != 0) | |
549 | return -ETIMEDOUT; | |
550 | ||
551 | err = clk_set_parent(sor->clk, sor->clk_safe); | |
552 | if (err < 0) | |
553 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); | |
554 | ||
a9a9e4fd | 555 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6fad8f66 TR |
556 | value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | |
557 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); | |
a9a9e4fd | 558 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6fad8f66 TR |
559 | |
560 | /* stop lane sequencer */ | |
561 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | | |
562 | SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; | |
563 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); | |
564 | ||
565 | timeout = jiffies + msecs_to_jiffies(250); | |
566 | ||
567 | while (time_before(jiffies, timeout)) { | |
568 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); | |
569 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) | |
570 | break; | |
571 | ||
572 | usleep_range(25, 100); | |
573 | } | |
574 | ||
575 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) | |
576 | return -ETIMEDOUT; | |
577 | ||
a9a9e4fd TR |
578 | value = tegra_sor_readl(sor, SOR_PLL2); |
579 | value |= SOR_PLL2_PORT_POWERDOWN; | |
580 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6fad8f66 TR |
581 | |
582 | usleep_range(20, 100); | |
583 | ||
a9a9e4fd TR |
584 | value = tegra_sor_readl(sor, SOR_PLL0); |
585 | value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; | |
586 | tegra_sor_writel(sor, value, SOR_PLL0); | |
6fad8f66 | 587 | |
a9a9e4fd TR |
588 | value = tegra_sor_readl(sor, SOR_PLL2); |
589 | value |= SOR_PLL2_SEQ_PLLCAPPD; | |
590 | value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; | |
591 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6fad8f66 TR |
592 | |
593 | usleep_range(20, 100); | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
598 | static int tegra_sor_crc_open(struct inode *inode, struct file *file) | |
599 | { | |
600 | file->private_data = inode->i_private; | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static int tegra_sor_crc_release(struct inode *inode, struct file *file) | |
606 | { | |
607 | return 0; | |
608 | } | |
609 | ||
610 | static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) | |
611 | { | |
612 | u32 value; | |
613 | ||
614 | timeout = jiffies + msecs_to_jiffies(timeout); | |
615 | ||
616 | while (time_before(jiffies, timeout)) { | |
a9a9e4fd TR |
617 | value = tegra_sor_readl(sor, SOR_CRCA); |
618 | if (value & SOR_CRCA_VALID) | |
6fad8f66 TR |
619 | return 0; |
620 | ||
621 | usleep_range(100, 200); | |
622 | } | |
623 | ||
624 | return -ETIMEDOUT; | |
625 | } | |
626 | ||
627 | static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer, | |
628 | size_t size, loff_t *ppos) | |
629 | { | |
630 | struct tegra_sor *sor = file->private_data; | |
631 | ssize_t num, err; | |
632 | char buf[10]; | |
633 | u32 value; | |
634 | ||
635 | mutex_lock(&sor->lock); | |
636 | ||
637 | if (!sor->enabled) { | |
638 | err = -EAGAIN; | |
639 | goto unlock; | |
640 | } | |
641 | ||
a9a9e4fd | 642 | value = tegra_sor_readl(sor, SOR_STATE1); |
6fad8f66 | 643 | value &= ~SOR_STATE_ASY_CRC_MODE_MASK; |
a9a9e4fd | 644 | tegra_sor_writel(sor, value, SOR_STATE1); |
6fad8f66 TR |
645 | |
646 | value = tegra_sor_readl(sor, SOR_CRC_CNTRL); | |
647 | value |= SOR_CRC_CNTRL_ENABLE; | |
648 | tegra_sor_writel(sor, value, SOR_CRC_CNTRL); | |
649 | ||
650 | value = tegra_sor_readl(sor, SOR_TEST); | |
651 | value &= ~SOR_TEST_CRC_POST_SERIALIZE; | |
652 | tegra_sor_writel(sor, value, SOR_TEST); | |
653 | ||
654 | err = tegra_sor_crc_wait(sor, 100); | |
655 | if (err < 0) | |
656 | goto unlock; | |
657 | ||
a9a9e4fd TR |
658 | tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); |
659 | value = tegra_sor_readl(sor, SOR_CRCB); | |
6fad8f66 TR |
660 | |
661 | num = scnprintf(buf, sizeof(buf), "%08x\n", value); | |
662 | ||
663 | err = simple_read_from_buffer(buffer, size, ppos, buf, num); | |
664 | ||
665 | unlock: | |
666 | mutex_unlock(&sor->lock); | |
667 | return err; | |
668 | } | |
669 | ||
670 | static const struct file_operations tegra_sor_crc_fops = { | |
671 | .owner = THIS_MODULE, | |
672 | .open = tegra_sor_crc_open, | |
673 | .read = tegra_sor_crc_read, | |
674 | .release = tegra_sor_crc_release, | |
675 | }; | |
676 | ||
dab16336 TR |
677 | static int tegra_sor_show_regs(struct seq_file *s, void *data) |
678 | { | |
679 | struct drm_info_node *node = s->private; | |
680 | struct tegra_sor *sor = node->info_ent->data; | |
681 | ||
682 | #define DUMP_REG(name) \ | |
683 | seq_printf(s, "%-38s %#05x %08x\n", #name, name, \ | |
684 | tegra_sor_readl(sor, name)) | |
685 | ||
686 | DUMP_REG(SOR_CTXSW); | |
a9a9e4fd TR |
687 | DUMP_REG(SOR_SUPER_STATE0); |
688 | DUMP_REG(SOR_SUPER_STATE1); | |
689 | DUMP_REG(SOR_STATE0); | |
690 | DUMP_REG(SOR_STATE1); | |
691 | DUMP_REG(SOR_HEAD_STATE0(0)); | |
692 | DUMP_REG(SOR_HEAD_STATE0(1)); | |
693 | DUMP_REG(SOR_HEAD_STATE1(0)); | |
694 | DUMP_REG(SOR_HEAD_STATE1(1)); | |
695 | DUMP_REG(SOR_HEAD_STATE2(0)); | |
696 | DUMP_REG(SOR_HEAD_STATE2(1)); | |
697 | DUMP_REG(SOR_HEAD_STATE3(0)); | |
698 | DUMP_REG(SOR_HEAD_STATE3(1)); | |
699 | DUMP_REG(SOR_HEAD_STATE4(0)); | |
700 | DUMP_REG(SOR_HEAD_STATE4(1)); | |
701 | DUMP_REG(SOR_HEAD_STATE5(0)); | |
702 | DUMP_REG(SOR_HEAD_STATE5(1)); | |
dab16336 TR |
703 | DUMP_REG(SOR_CRC_CNTRL); |
704 | DUMP_REG(SOR_DP_DEBUG_MVID); | |
705 | DUMP_REG(SOR_CLK_CNTRL); | |
706 | DUMP_REG(SOR_CAP); | |
707 | DUMP_REG(SOR_PWR); | |
708 | DUMP_REG(SOR_TEST); | |
a9a9e4fd TR |
709 | DUMP_REG(SOR_PLL0); |
710 | DUMP_REG(SOR_PLL1); | |
711 | DUMP_REG(SOR_PLL2); | |
712 | DUMP_REG(SOR_PLL3); | |
dab16336 TR |
713 | DUMP_REG(SOR_CSTM); |
714 | DUMP_REG(SOR_LVDS); | |
a9a9e4fd TR |
715 | DUMP_REG(SOR_CRCA); |
716 | DUMP_REG(SOR_CRCB); | |
dab16336 TR |
717 | DUMP_REG(SOR_BLANK); |
718 | DUMP_REG(SOR_SEQ_CTL); | |
719 | DUMP_REG(SOR_LANE_SEQ_CTL); | |
720 | DUMP_REG(SOR_SEQ_INST(0)); | |
721 | DUMP_REG(SOR_SEQ_INST(1)); | |
722 | DUMP_REG(SOR_SEQ_INST(2)); | |
723 | DUMP_REG(SOR_SEQ_INST(3)); | |
724 | DUMP_REG(SOR_SEQ_INST(4)); | |
725 | DUMP_REG(SOR_SEQ_INST(5)); | |
726 | DUMP_REG(SOR_SEQ_INST(6)); | |
727 | DUMP_REG(SOR_SEQ_INST(7)); | |
728 | DUMP_REG(SOR_SEQ_INST(8)); | |
729 | DUMP_REG(SOR_SEQ_INST(9)); | |
730 | DUMP_REG(SOR_SEQ_INST(10)); | |
731 | DUMP_REG(SOR_SEQ_INST(11)); | |
732 | DUMP_REG(SOR_SEQ_INST(12)); | |
733 | DUMP_REG(SOR_SEQ_INST(13)); | |
734 | DUMP_REG(SOR_SEQ_INST(14)); | |
735 | DUMP_REG(SOR_SEQ_INST(15)); | |
736 | DUMP_REG(SOR_PWM_DIV); | |
737 | DUMP_REG(SOR_PWM_CTL); | |
a9a9e4fd TR |
738 | DUMP_REG(SOR_VCRC_A0); |
739 | DUMP_REG(SOR_VCRC_A1); | |
740 | DUMP_REG(SOR_VCRC_B0); | |
741 | DUMP_REG(SOR_VCRC_B1); | |
742 | DUMP_REG(SOR_CCRC_A0); | |
743 | DUMP_REG(SOR_CCRC_A1); | |
744 | DUMP_REG(SOR_CCRC_B0); | |
745 | DUMP_REG(SOR_CCRC_B1); | |
746 | DUMP_REG(SOR_EDATA_A0); | |
747 | DUMP_REG(SOR_EDATA_A1); | |
748 | DUMP_REG(SOR_EDATA_B0); | |
749 | DUMP_REG(SOR_EDATA_B1); | |
750 | DUMP_REG(SOR_COUNT_A0); | |
751 | DUMP_REG(SOR_COUNT_A1); | |
752 | DUMP_REG(SOR_COUNT_B0); | |
753 | DUMP_REG(SOR_COUNT_B1); | |
754 | DUMP_REG(SOR_DEBUG_A0); | |
755 | DUMP_REG(SOR_DEBUG_A1); | |
756 | DUMP_REG(SOR_DEBUG_B0); | |
757 | DUMP_REG(SOR_DEBUG_B1); | |
dab16336 TR |
758 | DUMP_REG(SOR_TRIG); |
759 | DUMP_REG(SOR_MSCHECK); | |
760 | DUMP_REG(SOR_XBAR_CTRL); | |
761 | DUMP_REG(SOR_XBAR_POL); | |
a9a9e4fd TR |
762 | DUMP_REG(SOR_DP_LINKCTL0); |
763 | DUMP_REG(SOR_DP_LINKCTL1); | |
764 | DUMP_REG(SOR_LANE_DRIVE_CURRENT0); | |
765 | DUMP_REG(SOR_LANE_DRIVE_CURRENT1); | |
766 | DUMP_REG(SOR_LANE4_DRIVE_CURRENT0); | |
767 | DUMP_REG(SOR_LANE4_DRIVE_CURRENT1); | |
768 | DUMP_REG(SOR_LANE_PREEMPHASIS0); | |
769 | DUMP_REG(SOR_LANE_PREEMPHASIS1); | |
770 | DUMP_REG(SOR_LANE4_PREEMPHASIS0); | |
771 | DUMP_REG(SOR_LANE4_PREEMPHASIS1); | |
772 | DUMP_REG(SOR_LANE_POSTCURSOR0); | |
773 | DUMP_REG(SOR_LANE_POSTCURSOR1); | |
774 | DUMP_REG(SOR_DP_CONFIG0); | |
775 | DUMP_REG(SOR_DP_CONFIG1); | |
776 | DUMP_REG(SOR_DP_MN0); | |
777 | DUMP_REG(SOR_DP_MN1); | |
778 | DUMP_REG(SOR_DP_PADCTL0); | |
779 | DUMP_REG(SOR_DP_PADCTL1); | |
780 | DUMP_REG(SOR_DP_DEBUG0); | |
781 | DUMP_REG(SOR_DP_DEBUG1); | |
782 | DUMP_REG(SOR_DP_SPARE0); | |
783 | DUMP_REG(SOR_DP_SPARE1); | |
dab16336 TR |
784 | DUMP_REG(SOR_DP_AUDIO_CTRL); |
785 | DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS); | |
786 | DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS); | |
787 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER); | |
a9a9e4fd TR |
788 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0); |
789 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1); | |
790 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2); | |
791 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3); | |
792 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4); | |
793 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5); | |
794 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6); | |
dab16336 TR |
795 | DUMP_REG(SOR_DP_TPG); |
796 | DUMP_REG(SOR_DP_TPG_CONFIG); | |
a9a9e4fd TR |
797 | DUMP_REG(SOR_DP_LQ_CSTM0); |
798 | DUMP_REG(SOR_DP_LQ_CSTM1); | |
799 | DUMP_REG(SOR_DP_LQ_CSTM2); | |
dab16336 TR |
800 | |
801 | #undef DUMP_REG | |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
806 | static const struct drm_info_list debugfs_files[] = { | |
807 | { "regs", tegra_sor_show_regs, 0, NULL }, | |
808 | }; | |
809 | ||
6fad8f66 TR |
810 | static int tegra_sor_debugfs_init(struct tegra_sor *sor, |
811 | struct drm_minor *minor) | |
6b6b6042 | 812 | { |
6fad8f66 | 813 | struct dentry *entry; |
dab16336 | 814 | unsigned int i; |
6fad8f66 TR |
815 | int err = 0; |
816 | ||
817 | sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root); | |
818 | if (!sor->debugfs) | |
819 | return -ENOMEM; | |
820 | ||
dab16336 TR |
821 | sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), |
822 | GFP_KERNEL); | |
823 | if (!sor->debugfs_files) { | |
824 | err = -ENOMEM; | |
825 | goto remove; | |
826 | } | |
827 | ||
828 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
829 | sor->debugfs_files[i].data = sor; | |
830 | ||
831 | err = drm_debugfs_create_files(sor->debugfs_files, | |
832 | ARRAY_SIZE(debugfs_files), | |
833 | sor->debugfs, minor); | |
834 | if (err < 0) | |
835 | goto free; | |
836 | ||
6fad8f66 TR |
837 | entry = debugfs_create_file("crc", 0644, sor->debugfs, sor, |
838 | &tegra_sor_crc_fops); | |
839 | if (!entry) { | |
6fad8f66 | 840 | err = -ENOMEM; |
dab16336 | 841 | goto free; |
6fad8f66 TR |
842 | } |
843 | ||
3ff1f22c TR |
844 | sor->minor = minor; |
845 | ||
6fad8f66 TR |
846 | return err; |
847 | ||
dab16336 TR |
848 | free: |
849 | kfree(sor->debugfs_files); | |
850 | sor->debugfs_files = NULL; | |
6fad8f66 | 851 | remove: |
dab16336 | 852 | debugfs_remove_recursive(sor->debugfs); |
6fad8f66 TR |
853 | sor->debugfs = NULL; |
854 | return err; | |
855 | } | |
856 | ||
4009c224 | 857 | static void tegra_sor_debugfs_exit(struct tegra_sor *sor) |
6fad8f66 | 858 | { |
dab16336 TR |
859 | drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files), |
860 | sor->minor); | |
861 | sor->minor = NULL; | |
862 | ||
863 | kfree(sor->debugfs_files); | |
6fad8f66 | 864 | sor->debugfs = NULL; |
dab16336 TR |
865 | |
866 | debugfs_remove_recursive(sor->debugfs); | |
867 | sor->debugfs_files = NULL; | |
6fad8f66 TR |
868 | } |
869 | ||
870 | static void tegra_sor_connector_dpms(struct drm_connector *connector, int mode) | |
871 | { | |
872 | } | |
873 | ||
874 | static enum drm_connector_status | |
875 | tegra_sor_connector_detect(struct drm_connector *connector, bool force) | |
876 | { | |
877 | struct tegra_output *output = connector_to_output(connector); | |
878 | struct tegra_sor *sor = to_sor(output); | |
879 | ||
880 | if (sor->dpaux) | |
881 | return tegra_dpaux_detect(sor->dpaux); | |
882 | ||
883 | return connector_status_unknown; | |
884 | } | |
885 | ||
886 | static const struct drm_connector_funcs tegra_sor_connector_funcs = { | |
887 | .dpms = tegra_sor_connector_dpms, | |
9d44189f | 888 | .reset = drm_atomic_helper_connector_reset, |
6fad8f66 TR |
889 | .detect = tegra_sor_connector_detect, |
890 | .fill_modes = drm_helper_probe_single_connector_modes, | |
891 | .destroy = tegra_output_connector_destroy, | |
9d44189f | 892 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4aa3df71 | 893 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
6fad8f66 TR |
894 | }; |
895 | ||
896 | static int tegra_sor_connector_get_modes(struct drm_connector *connector) | |
897 | { | |
898 | struct tegra_output *output = connector_to_output(connector); | |
899 | struct tegra_sor *sor = to_sor(output); | |
900 | int err; | |
901 | ||
902 | if (sor->dpaux) | |
903 | tegra_dpaux_enable(sor->dpaux); | |
904 | ||
905 | err = tegra_output_connector_get_modes(connector); | |
906 | ||
907 | if (sor->dpaux) | |
908 | tegra_dpaux_disable(sor->dpaux); | |
909 | ||
910 | return err; | |
911 | } | |
912 | ||
913 | static enum drm_mode_status | |
914 | tegra_sor_connector_mode_valid(struct drm_connector *connector, | |
915 | struct drm_display_mode *mode) | |
916 | { | |
917 | return MODE_OK; | |
918 | } | |
919 | ||
920 | static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { | |
921 | .get_modes = tegra_sor_connector_get_modes, | |
922 | .mode_valid = tegra_sor_connector_mode_valid, | |
923 | .best_encoder = tegra_output_connector_best_encoder, | |
924 | }; | |
925 | ||
926 | static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { | |
927 | .destroy = tegra_output_encoder_destroy, | |
928 | }; | |
929 | ||
930 | static void tegra_sor_encoder_dpms(struct drm_encoder *encoder, int mode) | |
931 | { | |
932 | } | |
933 | ||
6fad8f66 TR |
934 | static void tegra_sor_encoder_prepare(struct drm_encoder *encoder) |
935 | { | |
936 | } | |
937 | ||
938 | static void tegra_sor_encoder_commit(struct drm_encoder *encoder) | |
939 | { | |
940 | } | |
941 | ||
942 | static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder, | |
943 | struct drm_display_mode *mode, | |
944 | struct drm_display_mode *adjusted) | |
945 | { | |
946 | struct tegra_output *output = encoder_to_output(encoder); | |
947 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); | |
6b6b6042 TR |
948 | unsigned int vbe, vse, hbe, hse, vbs, hbs, i; |
949 | struct tegra_sor *sor = to_sor(output); | |
34fa183b TR |
950 | struct tegra_sor_config config; |
951 | struct drm_dp_link link; | |
952 | struct drm_dp_aux *aux; | |
86f5c52d | 953 | int err = 0; |
28fe2076 | 954 | u32 value; |
86f5c52d TR |
955 | |
956 | mutex_lock(&sor->lock); | |
6b6b6042 TR |
957 | |
958 | if (sor->enabled) | |
86f5c52d | 959 | goto unlock; |
6b6b6042 TR |
960 | |
961 | err = clk_prepare_enable(sor->clk); | |
962 | if (err < 0) | |
86f5c52d | 963 | goto unlock; |
6b6b6042 TR |
964 | |
965 | reset_control_deassert(sor->rst); | |
966 | ||
6fad8f66 TR |
967 | if (output->panel) |
968 | drm_panel_prepare(output->panel); | |
969 | ||
34fa183b TR |
970 | /* FIXME: properly convert to struct drm_dp_aux */ |
971 | aux = (struct drm_dp_aux *)sor->dpaux; | |
972 | ||
6b6b6042 TR |
973 | if (sor->dpaux) { |
974 | err = tegra_dpaux_enable(sor->dpaux); | |
975 | if (err < 0) | |
976 | dev_err(sor->dev, "failed to enable DP: %d\n", err); | |
34fa183b TR |
977 | |
978 | err = drm_dp_link_probe(aux, &link); | |
979 | if (err < 0) { | |
980 | dev_err(sor->dev, "failed to probe eDP link: %d\n", | |
981 | err); | |
2263c460 | 982 | goto unlock; |
34fa183b | 983 | } |
6b6b6042 TR |
984 | } |
985 | ||
986 | err = clk_set_parent(sor->clk, sor->clk_safe); | |
987 | if (err < 0) | |
988 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); | |
989 | ||
34fa183b | 990 | memset(&config, 0, sizeof(config)); |
054b1bd1 | 991 | config.bits_per_pixel = output->connector.display_info.bpc * 3; |
34fa183b TR |
992 | |
993 | err = tegra_sor_calc_config(sor, mode, &config, &link); | |
994 | if (err < 0) | |
995 | dev_err(sor->dev, "failed to compute link configuration: %d\n", | |
996 | err); | |
997 | ||
6b6b6042 TR |
998 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
999 | value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; | |
1000 | value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; | |
1001 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); | |
1002 | ||
a9a9e4fd TR |
1003 | value = tegra_sor_readl(sor, SOR_PLL2); |
1004 | value &= ~SOR_PLL2_BANDGAP_POWERDOWN; | |
1005 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 TR |
1006 | usleep_range(20, 100); |
1007 | ||
a9a9e4fd TR |
1008 | value = tegra_sor_readl(sor, SOR_PLL3); |
1009 | value |= SOR_PLL3_PLL_VDD_MODE_3V3; | |
1010 | tegra_sor_writel(sor, value, SOR_PLL3); | |
6b6b6042 | 1011 | |
a9a9e4fd TR |
1012 | value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | |
1013 | SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; | |
1014 | tegra_sor_writel(sor, value, SOR_PLL0); | |
6b6b6042 | 1015 | |
a9a9e4fd TR |
1016 | value = tegra_sor_readl(sor, SOR_PLL2); |
1017 | value |= SOR_PLL2_SEQ_PLLCAPPD; | |
1018 | value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; | |
1019 | value |= SOR_PLL2_LVDS_ENABLE; | |
1020 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 | 1021 | |
a9a9e4fd TR |
1022 | value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; |
1023 | tegra_sor_writel(sor, value, SOR_PLL1); | |
6b6b6042 TR |
1024 | |
1025 | while (true) { | |
a9a9e4fd TR |
1026 | value = tegra_sor_readl(sor, SOR_PLL2); |
1027 | if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) | |
6b6b6042 TR |
1028 | break; |
1029 | ||
1030 | usleep_range(250, 1000); | |
1031 | } | |
1032 | ||
a9a9e4fd TR |
1033 | value = tegra_sor_readl(sor, SOR_PLL2); |
1034 | value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; | |
1035 | value &= ~SOR_PLL2_PORT_POWERDOWN; | |
1036 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 TR |
1037 | |
1038 | /* | |
1039 | * power up | |
1040 | */ | |
1041 | ||
1042 | /* set safe link bandwidth (1.62 Gbps) */ | |
1043 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); | |
1044 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; | |
1045 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; | |
1046 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); | |
1047 | ||
1048 | /* step 1 */ | |
a9a9e4fd TR |
1049 | value = tegra_sor_readl(sor, SOR_PLL2); |
1050 | value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | | |
1051 | SOR_PLL2_BANDGAP_POWERDOWN; | |
1052 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 | 1053 | |
a9a9e4fd TR |
1054 | value = tegra_sor_readl(sor, SOR_PLL0); |
1055 | value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; | |
1056 | tegra_sor_writel(sor, value, SOR_PLL0); | |
6b6b6042 | 1057 | |
a9a9e4fd | 1058 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6b6b6042 | 1059 | value &= ~SOR_DP_PADCTL_PAD_CAL_PD; |
a9a9e4fd | 1060 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 TR |
1061 | |
1062 | /* step 2 */ | |
1063 | err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); | |
1064 | if (err < 0) { | |
1065 | dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); | |
86f5c52d | 1066 | goto unlock; |
6b6b6042 TR |
1067 | } |
1068 | ||
1069 | usleep_range(5, 100); | |
1070 | ||
1071 | /* step 3 */ | |
a9a9e4fd TR |
1072 | value = tegra_sor_readl(sor, SOR_PLL2); |
1073 | value &= ~SOR_PLL2_BANDGAP_POWERDOWN; | |
1074 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 TR |
1075 | |
1076 | usleep_range(20, 100); | |
1077 | ||
1078 | /* step 4 */ | |
a9a9e4fd TR |
1079 | value = tegra_sor_readl(sor, SOR_PLL0); |
1080 | value &= ~SOR_PLL0_VCOPD; | |
1081 | value &= ~SOR_PLL0_PWR; | |
1082 | tegra_sor_writel(sor, value, SOR_PLL0); | |
6b6b6042 | 1083 | |
a9a9e4fd TR |
1084 | value = tegra_sor_readl(sor, SOR_PLL2); |
1085 | value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; | |
1086 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 TR |
1087 | |
1088 | usleep_range(200, 1000); | |
1089 | ||
1090 | /* step 5 */ | |
a9a9e4fd TR |
1091 | value = tegra_sor_readl(sor, SOR_PLL2); |
1092 | value &= ~SOR_PLL2_PORT_POWERDOWN; | |
1093 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 TR |
1094 | |
1095 | /* switch to DP clock */ | |
1096 | err = clk_set_parent(sor->clk, sor->clk_dp); | |
1097 | if (err < 0) | |
1098 | dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); | |
1099 | ||
899451b7 | 1100 | /* power DP lanes */ |
a9a9e4fd | 1101 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
899451b7 TR |
1102 | |
1103 | if (link.num_lanes <= 2) | |
1104 | value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); | |
1105 | else | |
1106 | value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; | |
1107 | ||
1108 | if (link.num_lanes <= 1) | |
1109 | value &= ~SOR_DP_PADCTL_PD_TXD_1; | |
1110 | else | |
1111 | value |= SOR_DP_PADCTL_PD_TXD_1; | |
1112 | ||
1113 | if (link.num_lanes == 0) | |
1114 | value &= ~SOR_DP_PADCTL_PD_TXD_0; | |
1115 | else | |
1116 | value |= SOR_DP_PADCTL_PD_TXD_0; | |
1117 | ||
a9a9e4fd | 1118 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 | 1119 | |
a9a9e4fd | 1120 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); |
6b6b6042 | 1121 | value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; |
0c90a184 | 1122 | value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); |
a9a9e4fd | 1123 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); |
6b6b6042 TR |
1124 | |
1125 | /* start lane sequencer */ | |
1126 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | | |
1127 | SOR_LANE_SEQ_CTL_POWER_STATE_UP; | |
1128 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); | |
1129 | ||
1130 | while (true) { | |
1131 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); | |
1132 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) | |
1133 | break; | |
1134 | ||
1135 | usleep_range(250, 1000); | |
1136 | } | |
1137 | ||
a4263fed | 1138 | /* set link bandwidth */ |
6b6b6042 TR |
1139 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
1140 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; | |
a4263fed | 1141 | value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; |
6b6b6042 TR |
1142 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
1143 | ||
1144 | /* set linkctl */ | |
a9a9e4fd | 1145 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); |
6b6b6042 TR |
1146 | value |= SOR_DP_LINKCTL_ENABLE; |
1147 | ||
1148 | value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; | |
34fa183b | 1149 | value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size); |
6b6b6042 TR |
1150 | |
1151 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; | |
a9a9e4fd | 1152 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); |
6b6b6042 TR |
1153 | |
1154 | for (i = 0, value = 0; i < 4; i++) { | |
1155 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | | |
1156 | SOR_DP_TPG_SCRAMBLER_GALIOS | | |
1157 | SOR_DP_TPG_PATTERN_NONE; | |
1158 | value = (value << 8) | lane; | |
1159 | } | |
1160 | ||
1161 | tegra_sor_writel(sor, value, SOR_DP_TPG); | |
1162 | ||
a9a9e4fd | 1163 | value = tegra_sor_readl(sor, SOR_DP_CONFIG0); |
6b6b6042 | 1164 | value &= ~SOR_DP_CONFIG_WATERMARK_MASK; |
34fa183b | 1165 | value |= SOR_DP_CONFIG_WATERMARK(config.watermark); |
6b6b6042 TR |
1166 | |
1167 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; | |
34fa183b | 1168 | value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count); |
6b6b6042 TR |
1169 | |
1170 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; | |
34fa183b | 1171 | value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac); |
6b6b6042 | 1172 | |
34fa183b TR |
1173 | if (config.active_polarity) |
1174 | value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; | |
1175 | else | |
1176 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; | |
6b6b6042 TR |
1177 | |
1178 | value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; | |
1f64ae7c | 1179 | value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; |
a9a9e4fd | 1180 | tegra_sor_writel(sor, value, SOR_DP_CONFIG0); |
6b6b6042 TR |
1181 | |
1182 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); | |
1183 | value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; | |
7890b576 | 1184 | value |= config.hblank_symbols & 0xffff; |
6b6b6042 TR |
1185 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); |
1186 | ||
1187 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); | |
1188 | value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; | |
7890b576 | 1189 | value |= config.vblank_symbols & 0xffff; |
6b6b6042 TR |
1190 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); |
1191 | ||
1192 | /* enable pad calibration logic */ | |
a9a9e4fd | 1193 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6b6b6042 | 1194 | value |= SOR_DP_PADCTL_PAD_CAL_PD; |
a9a9e4fd | 1195 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 TR |
1196 | |
1197 | if (sor->dpaux) { | |
6b6b6042 TR |
1198 | u8 rate, lanes; |
1199 | ||
1200 | err = drm_dp_link_probe(aux, &link); | |
1201 | if (err < 0) { | |
1202 | dev_err(sor->dev, "failed to probe eDP link: %d\n", | |
1203 | err); | |
86f5c52d | 1204 | goto unlock; |
6b6b6042 TR |
1205 | } |
1206 | ||
1207 | err = drm_dp_link_power_up(aux, &link); | |
1208 | if (err < 0) { | |
1209 | dev_err(sor->dev, "failed to power up eDP link: %d\n", | |
1210 | err); | |
86f5c52d | 1211 | goto unlock; |
6b6b6042 TR |
1212 | } |
1213 | ||
1214 | err = drm_dp_link_configure(aux, &link); | |
1215 | if (err < 0) { | |
1216 | dev_err(sor->dev, "failed to configure eDP link: %d\n", | |
1217 | err); | |
86f5c52d | 1218 | goto unlock; |
6b6b6042 TR |
1219 | } |
1220 | ||
1221 | rate = drm_dp_link_rate_to_bw_code(link.rate); | |
1222 | lanes = link.num_lanes; | |
1223 | ||
1224 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); | |
1225 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; | |
1226 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); | |
1227 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); | |
1228 | ||
a9a9e4fd | 1229 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); |
6b6b6042 TR |
1230 | value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; |
1231 | value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); | |
1232 | ||
1233 | if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) | |
1234 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; | |
1235 | ||
a9a9e4fd | 1236 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); |
6b6b6042 TR |
1237 | |
1238 | /* disable training pattern generator */ | |
1239 | ||
1240 | for (i = 0; i < link.num_lanes; i++) { | |
1241 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | | |
1242 | SOR_DP_TPG_SCRAMBLER_GALIOS | | |
1243 | SOR_DP_TPG_PATTERN_NONE; | |
1244 | value = (value << 8) | lane; | |
1245 | } | |
1246 | ||
1247 | tegra_sor_writel(sor, value, SOR_DP_TPG); | |
1248 | ||
1249 | err = tegra_sor_dp_train_fast(sor, &link); | |
1250 | if (err < 0) { | |
1251 | dev_err(sor->dev, "DP fast link training failed: %d\n", | |
1252 | err); | |
86f5c52d | 1253 | goto unlock; |
6b6b6042 TR |
1254 | } |
1255 | ||
1256 | dev_dbg(sor->dev, "fast link training succeeded\n"); | |
1257 | } | |
1258 | ||
1259 | err = tegra_sor_power_up(sor, 250); | |
1260 | if (err < 0) { | |
1261 | dev_err(sor->dev, "failed to power up SOR: %d\n", err); | |
86f5c52d | 1262 | goto unlock; |
6b6b6042 TR |
1263 | } |
1264 | ||
6b6b6042 TR |
1265 | /* |
1266 | * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete | |
1267 | * raster, associate with display controller) | |
1268 | */ | |
3f4f3b5f | 1269 | value = SOR_STATE_ASY_PROTOCOL_DP_A | |
6b6b6042 TR |
1270 | SOR_STATE_ASY_CRC_MODE_COMPLETE | |
1271 | SOR_STATE_ASY_OWNER(dc->pipe + 1); | |
34fa183b | 1272 | |
3f4f3b5f TR |
1273 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
1274 | value &= ~SOR_STATE_ASY_HSYNCPOL; | |
1275 | ||
1276 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1277 | value |= SOR_STATE_ASY_HSYNCPOL; | |
1278 | ||
1279 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1280 | value &= ~SOR_STATE_ASY_VSYNCPOL; | |
1281 | ||
1282 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1283 | value |= SOR_STATE_ASY_VSYNCPOL; | |
1284 | ||
34fa183b TR |
1285 | switch (config.bits_per_pixel) { |
1286 | case 24: | |
1287 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; | |
1288 | break; | |
1289 | ||
1290 | case 18: | |
1291 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; | |
1292 | break; | |
1293 | ||
1294 | default: | |
1295 | BUG(); | |
1296 | break; | |
1297 | } | |
1298 | ||
a9a9e4fd | 1299 | tegra_sor_writel(sor, value, SOR_STATE1); |
6b6b6042 TR |
1300 | |
1301 | /* | |
1302 | * TODO: The video timing programming below doesn't seem to match the | |
1303 | * register definitions. | |
1304 | */ | |
1305 | ||
1306 | value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); | |
a9a9e4fd | 1307 | tegra_sor_writel(sor, value, SOR_HEAD_STATE1(0)); |
6b6b6042 TR |
1308 | |
1309 | vse = mode->vsync_end - mode->vsync_start - 1; | |
1310 | hse = mode->hsync_end - mode->hsync_start - 1; | |
1311 | ||
1312 | value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); | |
a9a9e4fd | 1313 | tegra_sor_writel(sor, value, SOR_HEAD_STATE2(0)); |
6b6b6042 TR |
1314 | |
1315 | vbe = vse + (mode->vsync_start - mode->vdisplay); | |
1316 | hbe = hse + (mode->hsync_start - mode->hdisplay); | |
1317 | ||
1318 | value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); | |
a9a9e4fd | 1319 | tegra_sor_writel(sor, value, SOR_HEAD_STATE3(0)); |
6b6b6042 TR |
1320 | |
1321 | vbs = vbe + mode->vdisplay; | |
1322 | hbs = hbe + mode->hdisplay; | |
1323 | ||
1324 | value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); | |
a9a9e4fd | 1325 | tegra_sor_writel(sor, value, SOR_HEAD_STATE4(0)); |
6b6b6042 | 1326 | |
6fad8f66 TR |
1327 | /* CSTM (LVDS, link A/B, upper) */ |
1328 | value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | | |
1329 | SOR_CSTM_UPPER; | |
1330 | tegra_sor_writel(sor, value, SOR_CSTM); | |
1331 | ||
1332 | /* PWM setup */ | |
1333 | err = tegra_sor_setup_pwm(sor, 250); | |
1334 | if (err < 0) { | |
1335 | dev_err(sor->dev, "failed to setup PWM: %d\n", err); | |
1336 | goto unlock; | |
6b6b6042 TR |
1337 | } |
1338 | ||
666cb873 TR |
1339 | tegra_sor_update(sor); |
1340 | ||
6fad8f66 TR |
1341 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
1342 | value |= SOR_ENABLE; | |
1343 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
6b6b6042 | 1344 | |
666cb873 | 1345 | tegra_dc_commit(dc); |
6b6b6042 | 1346 | |
6fad8f66 TR |
1347 | err = tegra_sor_attach(sor); |
1348 | if (err < 0) { | |
1349 | dev_err(sor->dev, "failed to attach SOR: %d\n", err); | |
1350 | goto unlock; | |
1351 | } | |
6b6b6042 | 1352 | |
6fad8f66 TR |
1353 | err = tegra_sor_wakeup(sor); |
1354 | if (err < 0) { | |
1355 | dev_err(sor->dev, "failed to enable DC: %d\n", err); | |
1356 | goto unlock; | |
1357 | } | |
6b6b6042 | 1358 | |
6fad8f66 TR |
1359 | if (output->panel) |
1360 | drm_panel_enable(output->panel); | |
6b6b6042 | 1361 | |
6fad8f66 | 1362 | sor->enabled = true; |
6b6b6042 | 1363 | |
6fad8f66 TR |
1364 | unlock: |
1365 | mutex_unlock(&sor->lock); | |
6b6b6042 TR |
1366 | } |
1367 | ||
6fad8f66 | 1368 | static void tegra_sor_encoder_disable(struct drm_encoder *encoder) |
6b6b6042 | 1369 | { |
6fad8f66 TR |
1370 | struct tegra_output *output = encoder_to_output(encoder); |
1371 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); | |
6b6b6042 | 1372 | struct tegra_sor *sor = to_sor(output); |
6fad8f66 TR |
1373 | u32 value; |
1374 | int err; | |
86f5c52d TR |
1375 | |
1376 | mutex_lock(&sor->lock); | |
6b6b6042 TR |
1377 | |
1378 | if (!sor->enabled) | |
86f5c52d | 1379 | goto unlock; |
6b6b6042 | 1380 | |
6fad8f66 TR |
1381 | if (output->panel) |
1382 | drm_panel_disable(output->panel); | |
1383 | ||
6b6b6042 TR |
1384 | err = tegra_sor_detach(sor); |
1385 | if (err < 0) { | |
1386 | dev_err(sor->dev, "failed to detach SOR: %d\n", err); | |
86f5c52d | 1387 | goto unlock; |
6b6b6042 TR |
1388 | } |
1389 | ||
a9a9e4fd | 1390 | tegra_sor_writel(sor, 0, SOR_STATE1); |
6b6b6042 TR |
1391 | tegra_sor_update(sor); |
1392 | ||
1393 | /* | |
1394 | * The following accesses registers of the display controller, so make | |
1395 | * sure it's only executed when the output is attached to one. | |
1396 | */ | |
1397 | if (dc) { | |
6b6b6042 TR |
1398 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
1399 | value &= ~SOR_ENABLE; | |
1400 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
1401 | ||
62b9e063 | 1402 | tegra_dc_commit(dc); |
6b6b6042 TR |
1403 | } |
1404 | ||
1405 | err = tegra_sor_power_down(sor); | |
1406 | if (err < 0) { | |
1407 | dev_err(sor->dev, "failed to power down SOR: %d\n", err); | |
86f5c52d | 1408 | goto unlock; |
6b6b6042 TR |
1409 | } |
1410 | ||
1411 | if (sor->dpaux) { | |
1412 | err = tegra_dpaux_disable(sor->dpaux); | |
1413 | if (err < 0) { | |
1414 | dev_err(sor->dev, "failed to disable DP: %d\n", err); | |
86f5c52d | 1415 | goto unlock; |
6b6b6042 TR |
1416 | } |
1417 | } | |
1418 | ||
1419 | err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); | |
1420 | if (err < 0) { | |
1421 | dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); | |
86f5c52d | 1422 | goto unlock; |
6b6b6042 TR |
1423 | } |
1424 | ||
6fad8f66 TR |
1425 | if (output->panel) |
1426 | drm_panel_unprepare(output->panel); | |
1427 | ||
6b6b6042 | 1428 | clk_disable_unprepare(sor->clk); |
6fad8f66 | 1429 | reset_control_assert(sor->rst); |
6b6b6042 TR |
1430 | |
1431 | sor->enabled = false; | |
1432 | ||
86f5c52d TR |
1433 | unlock: |
1434 | mutex_unlock(&sor->lock); | |
a82752e1 TR |
1435 | } |
1436 | ||
82f1511c TR |
1437 | static int |
1438 | tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, | |
1439 | struct drm_crtc_state *crtc_state, | |
1440 | struct drm_connector_state *conn_state) | |
1441 | { | |
1442 | struct tegra_output *output = encoder_to_output(encoder); | |
1443 | struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); | |
1444 | unsigned long pclk = crtc_state->mode.clock * 1000; | |
1445 | struct tegra_sor *sor = to_sor(output); | |
1446 | int err; | |
1447 | ||
1448 | err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, | |
1449 | pclk, 0); | |
1450 | if (err < 0) { | |
1451 | dev_err(output->dev, "failed to setup CRTC state: %d\n", err); | |
1452 | return err; | |
1453 | } | |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
6fad8f66 TR |
1458 | static const struct drm_encoder_helper_funcs tegra_sor_encoder_helper_funcs = { |
1459 | .dpms = tegra_sor_encoder_dpms, | |
6fad8f66 TR |
1460 | .prepare = tegra_sor_encoder_prepare, |
1461 | .commit = tegra_sor_encoder_commit, | |
1462 | .mode_set = tegra_sor_encoder_mode_set, | |
1463 | .disable = tegra_sor_encoder_disable, | |
82f1511c | 1464 | .atomic_check = tegra_sor_encoder_atomic_check, |
a82752e1 TR |
1465 | }; |
1466 | ||
6b6b6042 TR |
1467 | static int tegra_sor_init(struct host1x_client *client) |
1468 | { | |
9910f5c4 | 1469 | struct drm_device *drm = dev_get_drvdata(client->parent); |
6b6b6042 TR |
1470 | struct tegra_sor *sor = host1x_client_to_sor(client); |
1471 | int err; | |
1472 | ||
1473 | if (!sor->dpaux) | |
1474 | return -ENODEV; | |
1475 | ||
6b6b6042 | 1476 | sor->output.dev = sor->dev; |
6b6b6042 | 1477 | |
6fad8f66 TR |
1478 | drm_connector_init(drm, &sor->output.connector, |
1479 | &tegra_sor_connector_funcs, | |
1480 | DRM_MODE_CONNECTOR_eDP); | |
1481 | drm_connector_helper_add(&sor->output.connector, | |
1482 | &tegra_sor_connector_helper_funcs); | |
1483 | sor->output.connector.dpms = DRM_MODE_DPMS_OFF; | |
1484 | ||
6fad8f66 TR |
1485 | drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, |
1486 | DRM_MODE_ENCODER_TMDS); | |
1487 | drm_encoder_helper_add(&sor->output.encoder, | |
1488 | &tegra_sor_encoder_helper_funcs); | |
1489 | ||
1490 | drm_mode_connector_attach_encoder(&sor->output.connector, | |
1491 | &sor->output.encoder); | |
1492 | drm_connector_register(&sor->output.connector); | |
1493 | ||
ea130b24 TR |
1494 | err = tegra_output_init(drm, &sor->output); |
1495 | if (err < 0) { | |
1496 | dev_err(client->dev, "failed to initialize output: %d\n", err); | |
1497 | return err; | |
1498 | } | |
6fad8f66 | 1499 | |
ea130b24 | 1500 | sor->output.encoder.possible_crtcs = 0x3; |
6b6b6042 | 1501 | |
a82752e1 | 1502 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
1b0c7b48 | 1503 | err = tegra_sor_debugfs_init(sor, drm->primary); |
a82752e1 TR |
1504 | if (err < 0) |
1505 | dev_err(sor->dev, "debugfs setup failed: %d\n", err); | |
1506 | } | |
1507 | ||
6b6b6042 TR |
1508 | if (sor->dpaux) { |
1509 | err = tegra_dpaux_attach(sor->dpaux, &sor->output); | |
1510 | if (err < 0) { | |
1511 | dev_err(sor->dev, "failed to attach DP: %d\n", err); | |
1512 | return err; | |
1513 | } | |
1514 | } | |
1515 | ||
535a65db TV |
1516 | /* |
1517 | * XXX: Remove this reset once proper hand-over from firmware to | |
1518 | * kernel is possible. | |
1519 | */ | |
1520 | err = reset_control_assert(sor->rst); | |
1521 | if (err < 0) { | |
1522 | dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); | |
1523 | return err; | |
1524 | } | |
1525 | ||
6fad8f66 TR |
1526 | err = clk_prepare_enable(sor->clk); |
1527 | if (err < 0) { | |
1528 | dev_err(sor->dev, "failed to enable clock: %d\n", err); | |
1529 | return err; | |
1530 | } | |
1531 | ||
535a65db TV |
1532 | usleep_range(1000, 3000); |
1533 | ||
1534 | err = reset_control_deassert(sor->rst); | |
1535 | if (err < 0) { | |
1536 | dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); | |
1537 | return err; | |
1538 | } | |
1539 | ||
6fad8f66 TR |
1540 | err = clk_prepare_enable(sor->clk_safe); |
1541 | if (err < 0) | |
1542 | return err; | |
1543 | ||
1544 | err = clk_prepare_enable(sor->clk_dp); | |
1545 | if (err < 0) | |
1546 | return err; | |
1547 | ||
6b6b6042 TR |
1548 | return 0; |
1549 | } | |
1550 | ||
1551 | static int tegra_sor_exit(struct host1x_client *client) | |
1552 | { | |
1553 | struct tegra_sor *sor = host1x_client_to_sor(client); | |
1554 | int err; | |
1555 | ||
328ec69e TR |
1556 | tegra_output_exit(&sor->output); |
1557 | ||
6b6b6042 TR |
1558 | if (sor->dpaux) { |
1559 | err = tegra_dpaux_detach(sor->dpaux); | |
1560 | if (err < 0) { | |
1561 | dev_err(sor->dev, "failed to detach DP: %d\n", err); | |
1562 | return err; | |
1563 | } | |
1564 | } | |
1565 | ||
6fad8f66 TR |
1566 | clk_disable_unprepare(sor->clk_safe); |
1567 | clk_disable_unprepare(sor->clk_dp); | |
1568 | clk_disable_unprepare(sor->clk); | |
1569 | ||
4009c224 TR |
1570 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
1571 | tegra_sor_debugfs_exit(sor); | |
a82752e1 | 1572 | |
6b6b6042 TR |
1573 | return 0; |
1574 | } | |
1575 | ||
1576 | static const struct host1x_client_ops sor_client_ops = { | |
1577 | .init = tegra_sor_init, | |
1578 | .exit = tegra_sor_exit, | |
1579 | }; | |
1580 | ||
1581 | static int tegra_sor_probe(struct platform_device *pdev) | |
1582 | { | |
1583 | struct device_node *np; | |
1584 | struct tegra_sor *sor; | |
1585 | struct resource *regs; | |
1586 | int err; | |
1587 | ||
1588 | sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); | |
1589 | if (!sor) | |
1590 | return -ENOMEM; | |
1591 | ||
1592 | sor->output.dev = sor->dev = &pdev->dev; | |
1593 | ||
1594 | np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); | |
1595 | if (np) { | |
1596 | sor->dpaux = tegra_dpaux_find_by_of_node(np); | |
1597 | of_node_put(np); | |
1598 | ||
1599 | if (!sor->dpaux) | |
1600 | return -EPROBE_DEFER; | |
1601 | } | |
1602 | ||
1603 | err = tegra_output_probe(&sor->output); | |
4dbdc740 TR |
1604 | if (err < 0) { |
1605 | dev_err(&pdev->dev, "failed to probe output: %d\n", err); | |
6b6b6042 | 1606 | return err; |
4dbdc740 | 1607 | } |
6b6b6042 TR |
1608 | |
1609 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1610 | sor->regs = devm_ioremap_resource(&pdev->dev, regs); | |
1611 | if (IS_ERR(sor->regs)) | |
1612 | return PTR_ERR(sor->regs); | |
1613 | ||
1614 | sor->rst = devm_reset_control_get(&pdev->dev, "sor"); | |
4dbdc740 TR |
1615 | if (IS_ERR(sor->rst)) { |
1616 | dev_err(&pdev->dev, "failed to get reset control: %ld\n", | |
1617 | PTR_ERR(sor->rst)); | |
6b6b6042 | 1618 | return PTR_ERR(sor->rst); |
4dbdc740 | 1619 | } |
6b6b6042 TR |
1620 | |
1621 | sor->clk = devm_clk_get(&pdev->dev, NULL); | |
4dbdc740 TR |
1622 | if (IS_ERR(sor->clk)) { |
1623 | dev_err(&pdev->dev, "failed to get module clock: %ld\n", | |
1624 | PTR_ERR(sor->clk)); | |
6b6b6042 | 1625 | return PTR_ERR(sor->clk); |
4dbdc740 | 1626 | } |
6b6b6042 TR |
1627 | |
1628 | sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); | |
4dbdc740 TR |
1629 | if (IS_ERR(sor->clk_parent)) { |
1630 | dev_err(&pdev->dev, "failed to get parent clock: %ld\n", | |
1631 | PTR_ERR(sor->clk_parent)); | |
6b6b6042 | 1632 | return PTR_ERR(sor->clk_parent); |
4dbdc740 | 1633 | } |
6b6b6042 | 1634 | |
6b6b6042 | 1635 | sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); |
4dbdc740 TR |
1636 | if (IS_ERR(sor->clk_safe)) { |
1637 | dev_err(&pdev->dev, "failed to get safe clock: %ld\n", | |
1638 | PTR_ERR(sor->clk_safe)); | |
6b6b6042 | 1639 | return PTR_ERR(sor->clk_safe); |
4dbdc740 | 1640 | } |
6b6b6042 | 1641 | |
6b6b6042 | 1642 | sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); |
4dbdc740 TR |
1643 | if (IS_ERR(sor->clk_dp)) { |
1644 | dev_err(&pdev->dev, "failed to get DP clock: %ld\n", | |
1645 | PTR_ERR(sor->clk_dp)); | |
6b6b6042 | 1646 | return PTR_ERR(sor->clk_dp); |
4dbdc740 | 1647 | } |
6b6b6042 | 1648 | |
6b6b6042 TR |
1649 | INIT_LIST_HEAD(&sor->client.list); |
1650 | sor->client.ops = &sor_client_ops; | |
1651 | sor->client.dev = &pdev->dev; | |
1652 | ||
86f5c52d TR |
1653 | mutex_init(&sor->lock); |
1654 | ||
6b6b6042 TR |
1655 | err = host1x_client_register(&sor->client); |
1656 | if (err < 0) { | |
1657 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
1658 | err); | |
1659 | return err; | |
1660 | } | |
1661 | ||
1662 | platform_set_drvdata(pdev, sor); | |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | static int tegra_sor_remove(struct platform_device *pdev) | |
1668 | { | |
1669 | struct tegra_sor *sor = platform_get_drvdata(pdev); | |
1670 | int err; | |
1671 | ||
1672 | err = host1x_client_unregister(&sor->client); | |
1673 | if (err < 0) { | |
1674 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
1675 | err); | |
1676 | return err; | |
1677 | } | |
1678 | ||
328ec69e | 1679 | tegra_output_remove(&sor->output); |
6b6b6042 TR |
1680 | |
1681 | return 0; | |
1682 | } | |
1683 | ||
1684 | static const struct of_device_id tegra_sor_of_match[] = { | |
1685 | { .compatible = "nvidia,tegra124-sor", }, | |
1686 | { }, | |
1687 | }; | |
ef70728c | 1688 | MODULE_DEVICE_TABLE(of, tegra_sor_of_match); |
6b6b6042 TR |
1689 | |
1690 | struct platform_driver tegra_sor_driver = { | |
1691 | .driver = { | |
1692 | .name = "tegra-sor", | |
1693 | .of_match_table = tegra_sor_of_match, | |
1694 | }, | |
1695 | .probe = tegra_sor_probe, | |
1696 | .remove = tegra_sor_remove, | |
1697 | }; |