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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / tegra / sor.c
CommitLineData
6b6b6042
TR		 1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
a82752e1 10#include <linux/debugfs.h>
6fad8f66 11#include <linux/gpio.h>
6b6b6042 12#include <linux/io.h>
459cc2c6 13#include <linux/of_device.h>
6b6b6042 14#include <linux/platform_device.h>
459cc2c6 15#include <linux/regulator/consumer.h>
6b6b6042 16#include <linux/reset.h>
306a7f91 17
7232398a 18#include <soc/tegra/pmc.h>
6b6b6042 19
4aa3df71 20#include <drm/drm_atomic_helper.h>
6b6b6042 21#include <drm/drm_dp_helper.h>
6fad8f66 22#include <drm/drm_panel.h>
6b6b6042
TR		 23
24#include "dc.h"
25#include "drm.h"
26#include "sor.h"
27
459cc2c6
TR		 28#define SOR_REKEY 0x38
29
30struct tegra_sor_hdmi_settings {
31 unsigned long frequency;
32
33 u8 vcocap;
34 u8 ichpmp;
35 u8 loadadj;
36 u8 termadj;
37 u8 tx_pu;
38 u8 bg_vref;
39
40 u8 drive_current[4];
41 u8 preemphasis[4];
42};
43
44#if 1
45static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
46 {
47 .frequency = 54000000,
48 .vcocap = 0x0,
49 .ichpmp = 0x1,
50 .loadadj = 0x3,
51 .termadj = 0x9,
52 .tx_pu = 0x10,
53 .bg_vref = 0x8,
54 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
55 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
56 }, {
57 .frequency = 75000000,
58 .vcocap = 0x3,
59 .ichpmp = 0x1,
60 .loadadj = 0x3,
61 .termadj = 0x9,
62 .tx_pu = 0x40,
63 .bg_vref = 0x8,
64 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
65 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
66 }, {
67 .frequency = 150000000,
68 .vcocap = 0x3,
69 .ichpmp = 0x1,
70 .loadadj = 0x3,
71 .termadj = 0x9,
72 .tx_pu = 0x66,
73 .bg_vref = 0x8,
74 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
75 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
76 }, {
77 .frequency = 300000000,
78 .vcocap = 0x3,
79 .ichpmp = 0x1,
80 .loadadj = 0x3,
81 .termadj = 0x9,
82 .tx_pu = 0x66,
83 .bg_vref = 0xa,
84 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
85 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
86 }, {
87 .frequency = 600000000,
88 .vcocap = 0x3,
89 .ichpmp = 0x1,
90 .loadadj = 0x3,
91 .termadj = 0x9,
92 .tx_pu = 0x66,
93 .bg_vref = 0x8,
94 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
95 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
96 },
97};
98#else
99static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
100 {
101 .frequency = 75000000,
102 .vcocap = 0x3,
103 .ichpmp = 0x1,
104 .loadadj = 0x3,
105 .termadj = 0x9,
106 .tx_pu = 0x40,
107 .bg_vref = 0x8,
108 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
109 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
110 }, {
111 .frequency = 150000000,
112 .vcocap = 0x3,
113 .ichpmp = 0x1,
114 .loadadj = 0x3,
115 .termadj = 0x9,
116 .tx_pu = 0x66,
117 .bg_vref = 0x8,
118 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
119 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
120 }, {
121 .frequency = 300000000,
122 .vcocap = 0x3,
123 .ichpmp = 0x6,
124 .loadadj = 0x3,
125 .termadj = 0x9,
126 .tx_pu = 0x66,
127 .bg_vref = 0xf,
128 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
129 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
130 }, {
131 .frequency = 600000000,
132 .vcocap = 0x3,
133 .ichpmp = 0xa,
134 .loadadj = 0x3,
135 .termadj = 0xb,
136 .tx_pu = 0x66,
137 .bg_vref = 0xe,
138 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
139 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
140 },
141};
142#endif
143
144struct tegra_sor_soc {
145 bool supports_edp;
146 bool supports_lvds;
147 bool supports_hdmi;
148 bool supports_dp;
149
150 const struct tegra_sor_hdmi_settings *settings;
151 unsigned int num_settings;
152};
153
154struct tegra_sor;
155
156struct tegra_sor_ops {
157 const char *name;
158 int (*probe)(struct tegra_sor *sor);
159 int (*remove)(struct tegra_sor *sor);
160};
161
6b6b6042
TR		 162struct tegra_sor {
163 struct host1x_client client;
164 struct tegra_output output;
165 struct device *dev;
166
459cc2c6 167 const struct tegra_sor_soc *soc;
6b6b6042
TR		 168 void __iomem *regs;
169
170 struct reset_control *rst;
171 struct clk *clk_parent;
172 struct clk *clk_safe;
173 struct clk *clk_dp;
174 struct clk *clk;
175
176 struct tegra_dpaux *dpaux;
177
dab16336
TR		 178 struct drm_info_list *debugfs_files;
179 struct drm_minor *minor;
a82752e1 180 struct dentry *debugfs;
459cc2c6
TR		 181
182 const struct tegra_sor_ops *ops;
183
184 /* for HDMI 2.0 */
185 struct tegra_sor_hdmi_settings *settings;
186 unsigned int num_settings;
187
188 struct regulator *avdd_io_supply;
189 struct regulator *vdd_pll_supply;
190 struct regulator *hdmi_supply;
6b6b6042
TR		 191};
192
34fa183b
TR		 193struct tegra_sor_config {
194 u32 bits_per_pixel;
195
196 u32 active_polarity;
197 u32 active_count;
198 u32 tu_size;
199 u32 active_frac;
200 u32 watermark;
7890b576
TR		 201
202 u32 hblank_symbols;
203 u32 vblank_symbols;
34fa183b
TR		 204};
205
6b6b6042
TR		 206static inline struct tegra_sor *
207host1x_client_to_sor(struct host1x_client *client)
208{
209 return container_of(client, struct tegra_sor, client);
210}
211
212static inline struct tegra_sor *to_sor(struct tegra_output *output)
213{
214 return container_of(output, struct tegra_sor, output);
215}
216
28fe2076 217static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset)
6b6b6042
TR		 218{
219 return readl(sor->regs + (offset << 2));
220}
221
28fe2076 222static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
6b6b6042
TR		 223 unsigned long offset)
224{
225 writel(value, sor->regs + (offset << 2));
226}
227
228static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
229 struct drm_dp_link *link)
230{
6b6b6042
TR		 231 unsigned int i;
232 u8 pattern;
28fe2076 233 u32 value;
6b6b6042
TR		 234 int err;
235
236 /* setup lane parameters */
237 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
238 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
239 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
240 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
a9a9e4fd 241 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
6b6b6042
TR		 242
243 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
244 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
245 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
246 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
a9a9e4fd 247 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
6b6b6042 248
a9a9e4fd
TR		 249 value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
250 SOR_LANE_POSTCURSOR_LANE2(0x00) |
251 SOR_LANE_POSTCURSOR_LANE1(0x00) |
252 SOR_LANE_POSTCURSOR_LANE0(0x00);
253 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
6b6b6042
TR		 254
255 /* disable LVDS mode */
256 tegra_sor_writel(sor, 0, SOR_LVDS);
257
a9a9e4fd 258 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
6b6b6042
TR		 259 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
260 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
261 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
a9a9e4fd 262 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
6b6b6042 263
a9a9e4fd 264 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
6b6b6042
TR		 265 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
266 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
a9a9e4fd 267 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
6b6b6042
TR		 268
269 usleep_range(10, 100);
270
a9a9e4fd 271 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
6b6b6042
TR		 272 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
273 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
a9a9e4fd 274 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
6b6b6042
TR		 275
276 err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B);
277 if (err < 0)
278 return err;
279
280 for (i = 0, value = 0; i < link->num_lanes; i++) {
281 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
282 SOR_DP_TPG_SCRAMBLER_NONE |
283 SOR_DP_TPG_PATTERN_TRAIN1;
284 value = (value << 8) | lane;
285 }
286
287 tegra_sor_writel(sor, value, SOR_DP_TPG);
288
289 pattern = DP_TRAINING_PATTERN_1;
290
291 err = tegra_dpaux_train(sor->dpaux, link, pattern);
292 if (err < 0)
293 return err;
294
a9a9e4fd 295 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
6b6b6042
TR		 296 value |= SOR_DP_SPARE_SEQ_ENABLE;
297 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
298 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
a9a9e4fd 299 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
6b6b6042
TR		 300
301 for (i = 0, value = 0; i < link->num_lanes; i++) {
302 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
303 SOR_DP_TPG_SCRAMBLER_NONE |
304 SOR_DP_TPG_PATTERN_TRAIN2;
305 value = (value << 8) | lane;
306 }
307
308 tegra_sor_writel(sor, value, SOR_DP_TPG);
309
310 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
311
312 err = tegra_dpaux_train(sor->dpaux, link, pattern);
313 if (err < 0)
314 return err;
315
316 for (i = 0, value = 0; i < link->num_lanes; i++) {
317 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
318 SOR_DP_TPG_SCRAMBLER_GALIOS |
319 SOR_DP_TPG_PATTERN_NONE;
320 value = (value << 8) | lane;
321 }
322
323 tegra_sor_writel(sor, value, SOR_DP_TPG);
324
325 pattern = DP_TRAINING_PATTERN_DISABLE;
326
327 err = tegra_dpaux_train(sor->dpaux, link, pattern);
328 if (err < 0)
329 return err;
330
331 return 0;
332}
333
459cc2c6
TR		 334static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
335{
336 u32 mask = 0x08, adj = 0, value;
337
338 /* enable pad calibration logic */
339 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
340 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
341 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
342
343 value = tegra_sor_readl(sor, SOR_PLL1);
344 value |= SOR_PLL1_TMDS_TERM;
345 tegra_sor_writel(sor, value, SOR_PLL1);
346
347 while (mask) {
348 adj |= mask;
349
350 value = tegra_sor_readl(sor, SOR_PLL1);
351 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
352 value |= SOR_PLL1_TMDS_TERMADJ(adj);
353 tegra_sor_writel(sor, value, SOR_PLL1);
354
355 usleep_range(100, 200);
356
357 value = tegra_sor_readl(sor, SOR_PLL1);
358 if (value & SOR_PLL1_TERM_COMPOUT)
359 adj &= ~mask;
360
361 mask >>= 1;
362 }
363
364 value = tegra_sor_readl(sor, SOR_PLL1);
365 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
366 value |= SOR_PLL1_TMDS_TERMADJ(adj);
367 tegra_sor_writel(sor, value, SOR_PLL1);
368
369 /* disable pad calibration logic */
370 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
371 value |= SOR_DP_PADCTL_PAD_CAL_PD;
372 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
373}
374
6b6b6042
TR		 375static void tegra_sor_super_update(struct tegra_sor *sor)
376{
a9a9e4fd
TR		 377 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
378 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
379 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
6b6b6042
TR		 380}
381
382static void tegra_sor_update(struct tegra_sor *sor)
383{
a9a9e4fd
TR		 384 tegra_sor_writel(sor, 0, SOR_STATE0);
385 tegra_sor_writel(sor, 1, SOR_STATE0);
386 tegra_sor_writel(sor, 0, SOR_STATE0);
6b6b6042
TR		 387}
388
389static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
390{
28fe2076 391 u32 value;
6b6b6042
TR		 392
393 value = tegra_sor_readl(sor, SOR_PWM_DIV);
394 value &= ~SOR_PWM_DIV_MASK;
395 value |= 0x400; /* period */
396 tegra_sor_writel(sor, value, SOR_PWM_DIV);
397
398 value = tegra_sor_readl(sor, SOR_PWM_CTL);
399 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
400 value |= 0x400; /* duty cycle */
401 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
402 value |= SOR_PWM_CTL_TRIGGER;
403 tegra_sor_writel(sor, value, SOR_PWM_CTL);
404
405 timeout = jiffies + msecs_to_jiffies(timeout);
406
407 while (time_before(jiffies, timeout)) {
408 value = tegra_sor_readl(sor, SOR_PWM_CTL);
409 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
410 return 0;
411
412 usleep_range(25, 100);
413 }
414
415 return -ETIMEDOUT;
416}
417
418static int tegra_sor_attach(struct tegra_sor *sor)
419{
420 unsigned long value, timeout;
421
422 /* wake up in normal mode */
a9a9e4fd 423 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
6b6b6042
TR		 424 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
425 value |= SOR_SUPER_STATE_MODE_NORMAL;
a9a9e4fd 426 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
6b6b6042
TR		 427 tegra_sor_super_update(sor);
428
429 /* attach */
a9a9e4fd 430 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
6b6b6042 431 value |= SOR_SUPER_STATE_ATTACHED;
a9a9e4fd 432 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
6b6b6042
TR		 433 tegra_sor_super_update(sor);
434
435 timeout = jiffies + msecs_to_jiffies(250);
436
437 while (time_before(jiffies, timeout)) {
438 value = tegra_sor_readl(sor, SOR_TEST);
439 if ((value & SOR_TEST_ATTACHED) != 0)
440 return 0;
441
442 usleep_range(25, 100);
443 }
444
445 return -ETIMEDOUT;
446}
447
448static int tegra_sor_wakeup(struct tegra_sor *sor)
449{
6b6b6042
TR		 450 unsigned long value, timeout;
451
6b6b6042
TR		 452 timeout = jiffies + msecs_to_jiffies(250);
453
454 /* wait for head to wake up */
455 while (time_before(jiffies, timeout)) {
456 value = tegra_sor_readl(sor, SOR_TEST);
457 value &= SOR_TEST_HEAD_MODE_MASK;
458
459 if (value == SOR_TEST_HEAD_MODE_AWAKE)
460 return 0;
461
462 usleep_range(25, 100);
463 }
464
465 return -ETIMEDOUT;
466}
467
468static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
469{
28fe2076 470 u32 value;
6b6b6042
TR		 471
472 value = tegra_sor_readl(sor, SOR_PWR);
473 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
474 tegra_sor_writel(sor, value, SOR_PWR);
475
476 timeout = jiffies + msecs_to_jiffies(timeout);
477
478 while (time_before(jiffies, timeout)) {
479 value = tegra_sor_readl(sor, SOR_PWR);
480 if ((value & SOR_PWR_TRIGGER) == 0)
481 return 0;
482
483 usleep_range(25, 100);
484 }
485
486 return -ETIMEDOUT;
487}
488
34fa183b
TR		 489struct tegra_sor_params {
490 /* number of link clocks per line */
491 unsigned int num_clocks;
492 /* ratio between input and output */
493 u64 ratio;
494 /* precision factor */
495 u64 precision;
496
497 unsigned int active_polarity;
498 unsigned int active_count;
499 unsigned int active_frac;
500 unsigned int tu_size;
501 unsigned int error;
502};
503
504static int tegra_sor_compute_params(struct tegra_sor *sor,
505 struct tegra_sor_params *params,
506 unsigned int tu_size)
507{
508 u64 active_sym, active_count, frac, approx;
509 u32 active_polarity, active_frac = 0;
510 const u64 f = params->precision;
511 s64 error;
512
513 active_sym = params->ratio * tu_size;
514 active_count = div_u64(active_sym, f) * f;
515 frac = active_sym - active_count;
516
517 /* fraction < 0.5 */
518 if (frac >= (f / 2)) {
519 active_polarity = 1;
520 frac = f - frac;
521 } else {
522 active_polarity = 0;
523 }
524
525 if (frac != 0) {
526 frac = div_u64(f * f, frac); /* 1/fraction */
527 if (frac <= (15 * f)) {
528 active_frac = div_u64(frac, f);
529
530 /* round up */
531 if (active_polarity)
532 active_frac++;
533 } else {
534 active_frac = active_polarity ? 1 : 15;
535 }
536 }
537
538 if (active_frac == 1)
539 active_polarity = 0;
540
541 if (active_polarity == 1) {
542 if (active_frac) {
543 approx = active_count + (active_frac * (f - 1)) * f;
544 approx = div_u64(approx, active_frac * f);
545 } else {
546 approx = active_count + f;
547 }
548 } else {
549 if (active_frac)
550 approx = active_count + div_u64(f, active_frac);
551 else
552 approx = active_count;
553 }
554
555 error = div_s64(active_sym - approx, tu_size);
556 error *= params->num_clocks;
557
79211c8e 558 if (error <= 0 && abs(error) < params->error) {
34fa183b
TR		 559 params->active_count = div_u64(active_count, f);
560 params->active_polarity = active_polarity;
561 params->active_frac = active_frac;
79211c8e 562 params->error = abs(error);
34fa183b
TR		 563 params->tu_size = tu_size;
564
565 if (error == 0)
566 return true;
567 }
568
569 return false;
570}
571
572static int tegra_sor_calc_config(struct tegra_sor *sor,
80444495 573 const struct drm_display_mode *mode,
34fa183b
TR		 574 struct tegra_sor_config *config,
575 struct drm_dp_link *link)
576{
577 const u64 f = 100000, link_rate = link->rate * 1000;
578 const u64 pclk = mode->clock * 1000;
7890b576 579 u64 input, output, watermark, num;
34fa183b 580 struct tegra_sor_params params;
34fa183b
TR		 581 u32 num_syms_per_line;
582 unsigned int i;
583
584 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
585 return -EINVAL;
586
587 output = link_rate * 8 * link->num_lanes;
588 input = pclk * config->bits_per_pixel;
589
590 if (input >= output)
591 return -ERANGE;
592
593 memset(&params, 0, sizeof(params));
594 params.ratio = div64_u64(input * f, output);
595 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
596 params.precision = f;
597 params.error = 64 * f;
598 params.tu_size = 64;
599
600 for (i = params.tu_size; i >= 32; i--)
601 if (tegra_sor_compute_params(sor, &params, i))
602 break;
603
604 if (params.active_frac == 0) {
605 config->active_polarity = 0;
606 config->active_count = params.active_count;
607
608 if (!params.active_polarity)
609 config->active_count--;
610
611 config->tu_size = params.tu_size;
612 config->active_frac = 1;
613 } else {
614 config->active_polarity = params.active_polarity;
615 config->active_count = params.active_count;
616 config->active_frac = params.active_frac;
617 config->tu_size = params.tu_size;
618 }
619
620 dev_dbg(sor->dev,
621 "polarity: %d active count: %d tu size: %d active frac: %d\n",
622 config->active_polarity, config->active_count,
623 config->tu_size, config->active_frac);
624
625 watermark = params.ratio * config->tu_size * (f - params.ratio);
626 watermark = div_u64(watermark, f);
627
628 watermark = div_u64(watermark + params.error, f);
629 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
630 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
631 (link->num_lanes * 8);
632
633 if (config->watermark > 30) {
634 config->watermark = 30;
635 dev_err(sor->dev,
636 "unable to compute TU size, forcing watermark to %u\n",
637 config->watermark);
638 } else if (config->watermark > num_syms_per_line) {
639 config->watermark = num_syms_per_line;
640 dev_err(sor->dev, "watermark too high, forcing to %u\n",
641 config->watermark);
642 }
643
7890b576
TR		 644 /* compute the number of symbols per horizontal blanking interval */
645 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
646 config->hblank_symbols = div_u64(num, pclk);
647
648 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
649 config->hblank_symbols -= 3;
650
651 config->hblank_symbols -= 12 / link->num_lanes;
652
653 /* compute the number of symbols per vertical blanking interval */
654 num = (mode->hdisplay - 25) * link_rate;
655 config->vblank_symbols = div_u64(num, pclk);
656 config->vblank_symbols -= 36 / link->num_lanes + 4;
657
658 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
659 config->vblank_symbols);
660
34fa183b
TR		 661 return 0;
662}
663
6fad8f66
TR		 664static int tegra_sor_detach(struct tegra_sor *sor)
665{
666 unsigned long value, timeout;
667
668 /* switch to safe mode */
a9a9e4fd 669 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
6fad8f66 670 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
a9a9e4fd 671 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
6fad8f66
TR		 672 tegra_sor_super_update(sor);
673
674 timeout = jiffies + msecs_to_jiffies(250);
675
676 while (time_before(jiffies, timeout)) {
677 value = tegra_sor_readl(sor, SOR_PWR);
678 if (value & SOR_PWR_MODE_SAFE)
679 break;
680 }
681
682 if ((value & SOR_PWR_MODE_SAFE) == 0)
683 return -ETIMEDOUT;
684
685 /* go to sleep */
a9a9e4fd 686 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
6fad8f66 687 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
a9a9e4fd 688 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
6fad8f66
TR		 689 tegra_sor_super_update(sor);
690
691 /* detach */
a9a9e4fd 692 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
6fad8f66 693 value &= ~SOR_SUPER_STATE_ATTACHED;
a9a9e4fd 694 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
6fad8f66
TR		 695 tegra_sor_super_update(sor);
696
697 timeout = jiffies + msecs_to_jiffies(250);
698
699 while (time_before(jiffies, timeout)) {
700 value = tegra_sor_readl(sor, SOR_TEST);
701 if ((value & SOR_TEST_ATTACHED) == 0)
702 break;
703
704 usleep_range(25, 100);
705 }
706
707 if ((value & SOR_TEST_ATTACHED) != 0)
708 return -ETIMEDOUT;
709
710 return 0;
711}
712
713static int tegra_sor_power_down(struct tegra_sor *sor)
714{
715 unsigned long value, timeout;
716 int err;
717
718 value = tegra_sor_readl(sor, SOR_PWR);
719 value &= ~SOR_PWR_NORMAL_STATE_PU;
720 value |= SOR_PWR_TRIGGER;
721 tegra_sor_writel(sor, value, SOR_PWR);
722
723 timeout = jiffies + msecs_to_jiffies(250);
724
725 while (time_before(jiffies, timeout)) {
726 value = tegra_sor_readl(sor, SOR_PWR);
727 if ((value & SOR_PWR_TRIGGER) == 0)
728 return 0;
729
730 usleep_range(25, 100);
731 }
732
733 if ((value & SOR_PWR_TRIGGER) != 0)
734 return -ETIMEDOUT;
735
736 err = clk_set_parent(sor->clk, sor->clk_safe);
737 if (err < 0)
738 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
739
a9a9e4fd 740 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
6fad8f66
TR		 741 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
742 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
a9a9e4fd 743 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
6fad8f66
TR		 744
745 /* stop lane sequencer */
746 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
747 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
748 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
749
750 timeout = jiffies + msecs_to_jiffies(250);
751
752 while (time_before(jiffies, timeout)) {
753 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
754 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
755 break;
756
757 usleep_range(25, 100);
758 }
759
760 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
761 return -ETIMEDOUT;
762
a9a9e4fd
TR		 763 value = tegra_sor_readl(sor, SOR_PLL2);
764 value |= SOR_PLL2_PORT_POWERDOWN;
765 tegra_sor_writel(sor, value, SOR_PLL2);
6fad8f66
TR		 766
767 usleep_range(20, 100);
768
a9a9e4fd
TR		 769 value = tegra_sor_readl(sor, SOR_PLL0);
770 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
771 tegra_sor_writel(sor, value, SOR_PLL0);
6fad8f66 772
a9a9e4fd
TR		 773 value = tegra_sor_readl(sor, SOR_PLL2);
774 value |= SOR_PLL2_SEQ_PLLCAPPD;
775 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
776 tegra_sor_writel(sor, value, SOR_PLL2);
6fad8f66
TR		 777
778 usleep_range(20, 100);
779
780 return 0;
781}
782
6fad8f66
TR		 783static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
784{
785 u32 value;
786
787 timeout = jiffies + msecs_to_jiffies(timeout);
788
789 while (time_before(jiffies, timeout)) {
a9a9e4fd
TR		 790 value = tegra_sor_readl(sor, SOR_CRCA);
791 if (value & SOR_CRCA_VALID)
6fad8f66
TR		 792 return 0;
793
794 usleep_range(100, 200);
795 }
796
797 return -ETIMEDOUT;
798}
799
530239a8 800static int tegra_sor_show_crc(struct seq_file *s, void *data)
6fad8f66 801{
530239a8
TR		 802 struct drm_info_node *node = s->private;
803 struct tegra_sor *sor = node->info_ent->data;
850bab44
TR		 804 struct drm_crtc *crtc = sor->output.encoder.crtc;
805 struct drm_device *drm = node->minor->dev;
530239a8 806 int err = 0;
6fad8f66
TR		 807 u32 value;
808
850bab44 809 drm_modeset_lock_all(drm);
6fad8f66 810
850bab44
TR		 811 if (!crtc || !crtc->state->active) {
812 err = -EBUSY;
6fad8f66
TR		 813 goto unlock;
814 }
815
a9a9e4fd 816 value = tegra_sor_readl(sor, SOR_STATE1);
6fad8f66 817 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
a9a9e4fd 818 tegra_sor_writel(sor, value, SOR_STATE1);
6fad8f66
TR		 819
820 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
821 value |= SOR_CRC_CNTRL_ENABLE;
822 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
823
824 value = tegra_sor_readl(sor, SOR_TEST);
825 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
826 tegra_sor_writel(sor, value, SOR_TEST);
827
828 err = tegra_sor_crc_wait(sor, 100);
829 if (err < 0)
830 goto unlock;
831
a9a9e4fd
TR		 832 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
833 value = tegra_sor_readl(sor, SOR_CRCB);
6fad8f66 834
530239a8 835 seq_printf(s, "%08x\n", value);
6fad8f66
TR		 836
837unlock:
850bab44 838 drm_modeset_unlock_all(drm);
6fad8f66
TR		 839 return err;
840}
841
dab16336
TR		 842static int tegra_sor_show_regs(struct seq_file *s, void *data)
843{
844 struct drm_info_node *node = s->private;
845 struct tegra_sor *sor = node->info_ent->data;
850bab44
TR		 846 struct drm_crtc *crtc = sor->output.encoder.crtc;
847 struct drm_device *drm = node->minor->dev;
848 int err = 0;
849
850 drm_modeset_lock_all(drm);
851
852 if (!crtc || !crtc->state->active) {
853 err = -EBUSY;
854 goto unlock;
855 }
dab16336
TR		 856
857#define DUMP_REG(name) \
858 seq_printf(s, "%-38s %#05x %08x\n", #name, name, \
859 tegra_sor_readl(sor, name))
860
861 DUMP_REG(SOR_CTXSW);
a9a9e4fd
TR		 862 DUMP_REG(SOR_SUPER_STATE0);
863 DUMP_REG(SOR_SUPER_STATE1);
864 DUMP_REG(SOR_STATE0);
865 DUMP_REG(SOR_STATE1);
866 DUMP_REG(SOR_HEAD_STATE0(0));
867 DUMP_REG(SOR_HEAD_STATE0(1));
868 DUMP_REG(SOR_HEAD_STATE1(0));
869 DUMP_REG(SOR_HEAD_STATE1(1));
870 DUMP_REG(SOR_HEAD_STATE2(0));
871 DUMP_REG(SOR_HEAD_STATE2(1));
872 DUMP_REG(SOR_HEAD_STATE3(0));
873 DUMP_REG(SOR_HEAD_STATE3(1));
874 DUMP_REG(SOR_HEAD_STATE4(0));
875 DUMP_REG(SOR_HEAD_STATE4(1));
876 DUMP_REG(SOR_HEAD_STATE5(0));
877 DUMP_REG(SOR_HEAD_STATE5(1));
dab16336
TR		 878 DUMP_REG(SOR_CRC_CNTRL);
879 DUMP_REG(SOR_DP_DEBUG_MVID);
880 DUMP_REG(SOR_CLK_CNTRL);
881 DUMP_REG(SOR_CAP);
882 DUMP_REG(SOR_PWR);
883 DUMP_REG(SOR_TEST);
a9a9e4fd
TR		 884 DUMP_REG(SOR_PLL0);
885 DUMP_REG(SOR_PLL1);
886 DUMP_REG(SOR_PLL2);
887 DUMP_REG(SOR_PLL3);
dab16336
TR		 888 DUMP_REG(SOR_CSTM);
889 DUMP_REG(SOR_LVDS);
a9a9e4fd
TR		 890 DUMP_REG(SOR_CRCA);
891 DUMP_REG(SOR_CRCB);
dab16336
TR		 892 DUMP_REG(SOR_BLANK);
893 DUMP_REG(SOR_SEQ_CTL);
894 DUMP_REG(SOR_LANE_SEQ_CTL);
895 DUMP_REG(SOR_SEQ_INST(0));
896 DUMP_REG(SOR_SEQ_INST(1));
897 DUMP_REG(SOR_SEQ_INST(2));
898 DUMP_REG(SOR_SEQ_INST(3));
899 DUMP_REG(SOR_SEQ_INST(4));
900 DUMP_REG(SOR_SEQ_INST(5));
901 DUMP_REG(SOR_SEQ_INST(6));
902 DUMP_REG(SOR_SEQ_INST(7));
903 DUMP_REG(SOR_SEQ_INST(8));
904 DUMP_REG(SOR_SEQ_INST(9));
905 DUMP_REG(SOR_SEQ_INST(10));
906 DUMP_REG(SOR_SEQ_INST(11));
907 DUMP_REG(SOR_SEQ_INST(12));
908 DUMP_REG(SOR_SEQ_INST(13));
909 DUMP_REG(SOR_SEQ_INST(14));
910 DUMP_REG(SOR_SEQ_INST(15));
911 DUMP_REG(SOR_PWM_DIV);
912 DUMP_REG(SOR_PWM_CTL);
a9a9e4fd
TR		 913 DUMP_REG(SOR_VCRC_A0);
914 DUMP_REG(SOR_VCRC_A1);
915 DUMP_REG(SOR_VCRC_B0);
916 DUMP_REG(SOR_VCRC_B1);
917 DUMP_REG(SOR_CCRC_A0);
918 DUMP_REG(SOR_CCRC_A1);
919 DUMP_REG(SOR_CCRC_B0);
920 DUMP_REG(SOR_CCRC_B1);
921 DUMP_REG(SOR_EDATA_A0);
922 DUMP_REG(SOR_EDATA_A1);
923 DUMP_REG(SOR_EDATA_B0);
924 DUMP_REG(SOR_EDATA_B1);
925 DUMP_REG(SOR_COUNT_A0);
926 DUMP_REG(SOR_COUNT_A1);
927 DUMP_REG(SOR_COUNT_B0);
928 DUMP_REG(SOR_COUNT_B1);
929 DUMP_REG(SOR_DEBUG_A0);
930 DUMP_REG(SOR_DEBUG_A1);
931 DUMP_REG(SOR_DEBUG_B0);
932 DUMP_REG(SOR_DEBUG_B1);
dab16336
TR		 933 DUMP_REG(SOR_TRIG);
934 DUMP_REG(SOR_MSCHECK);
935 DUMP_REG(SOR_XBAR_CTRL);
936 DUMP_REG(SOR_XBAR_POL);
a9a9e4fd
TR		 937 DUMP_REG(SOR_DP_LINKCTL0);
938 DUMP_REG(SOR_DP_LINKCTL1);
939 DUMP_REG(SOR_LANE_DRIVE_CURRENT0);
940 DUMP_REG(SOR_LANE_DRIVE_CURRENT1);
941 DUMP_REG(SOR_LANE4_DRIVE_CURRENT0);
942 DUMP_REG(SOR_LANE4_DRIVE_CURRENT1);
943 DUMP_REG(SOR_LANE_PREEMPHASIS0);
944 DUMP_REG(SOR_LANE_PREEMPHASIS1);
945 DUMP_REG(SOR_LANE4_PREEMPHASIS0);
946 DUMP_REG(SOR_LANE4_PREEMPHASIS1);
947 DUMP_REG(SOR_LANE_POSTCURSOR0);
948 DUMP_REG(SOR_LANE_POSTCURSOR1);
949 DUMP_REG(SOR_DP_CONFIG0);
950 DUMP_REG(SOR_DP_CONFIG1);
951 DUMP_REG(SOR_DP_MN0);
952 DUMP_REG(SOR_DP_MN1);
953 DUMP_REG(SOR_DP_PADCTL0);
954 DUMP_REG(SOR_DP_PADCTL1);
955 DUMP_REG(SOR_DP_DEBUG0);
956 DUMP_REG(SOR_DP_DEBUG1);
957 DUMP_REG(SOR_DP_SPARE0);
958 DUMP_REG(SOR_DP_SPARE1);
dab16336
TR		 959 DUMP_REG(SOR_DP_AUDIO_CTRL);
960 DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS);
961 DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS);
962 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER);
a9a9e4fd
TR		 963 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0);
964 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1);
965 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2);
966 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3);
967 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4);
968 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5);
969 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6);
dab16336
TR		 970 DUMP_REG(SOR_DP_TPG);
971 DUMP_REG(SOR_DP_TPG_CONFIG);
a9a9e4fd
TR		 972 DUMP_REG(SOR_DP_LQ_CSTM0);
973 DUMP_REG(SOR_DP_LQ_CSTM1);
974 DUMP_REG(SOR_DP_LQ_CSTM2);
dab16336
TR		 975
976#undef DUMP_REG
977
850bab44
TR		 978unlock:
979 drm_modeset_unlock_all(drm);
980 return err;
dab16336
TR		 981}
982
983static const struct drm_info_list debugfs_files[] = {
530239a8 984 { "crc", tegra_sor_show_crc, 0, NULL },
dab16336
TR		 985 { "regs", tegra_sor_show_regs, 0, NULL },
986};
987
6fad8f66
TR		 988static int tegra_sor_debugfs_init(struct tegra_sor *sor,
989 struct drm_minor *minor)
6b6b6042 990{
459cc2c6 991 const char *name = sor->soc->supports_dp ? "sor1" : "sor";
dab16336 992 unsigned int i;
530239a8 993 int err;
6fad8f66 994
459cc2c6 995 sor->debugfs = debugfs_create_dir(name, minor->debugfs_root);
6fad8f66
TR		 996 if (!sor->debugfs)
997 return -ENOMEM;
998
dab16336
TR		 999 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1000 GFP_KERNEL);
1001 if (!sor->debugfs_files) {
1002 err = -ENOMEM;
1003 goto remove;
1004 }
1005
1006 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1007 sor->debugfs_files[i].data = sor;
1008
1009 err = drm_debugfs_create_files(sor->debugfs_files,
1010 ARRAY_SIZE(debugfs_files),
1011 sor->debugfs, minor);
1012 if (err < 0)
1013 goto free;
1014
3ff1f22c
TR		 1015 sor->minor = minor;
1016
530239a8 1017 return 0;
6fad8f66 1018
dab16336
TR		 1019free:
1020 kfree(sor->debugfs_files);
1021 sor->debugfs_files = NULL;
6fad8f66 1022remove:
dab16336 1023 debugfs_remove_recursive(sor->debugfs);
6fad8f66
TR		 1024 sor->debugfs = NULL;
1025 return err;
1026}
1027
4009c224 1028static void tegra_sor_debugfs_exit(struct tegra_sor *sor)
6fad8f66 1029{
dab16336
TR		 1030 drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files),
1031 sor->minor);
1032 sor->minor = NULL;
1033
1034 kfree(sor->debugfs_files);
066d30f8 1035 sor->debugfs_files = NULL;
dab16336
TR		 1036
1037 debugfs_remove_recursive(sor->debugfs);
066d30f8 1038 sor->debugfs = NULL;
6fad8f66
TR		 1039}
1040
6fad8f66
TR		 1041static enum drm_connector_status
1042tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1043{
1044 struct tegra_output *output = connector_to_output(connector);
1045 struct tegra_sor *sor = to_sor(output);
1046
1047 if (sor->dpaux)
1048 return tegra_dpaux_detect(sor->dpaux);
1049
459cc2c6 1050 return tegra_output_connector_detect(connector, force);
6fad8f66
TR		 1051}
1052
1053static const struct drm_connector_funcs tegra_sor_connector_funcs = {
850bab44 1054 .dpms = drm_atomic_helper_connector_dpms,
9d44189f 1055 .reset = drm_atomic_helper_connector_reset,
6fad8f66
TR		 1056 .detect = tegra_sor_connector_detect,
1057 .fill_modes = drm_helper_probe_single_connector_modes,
1058 .destroy = tegra_output_connector_destroy,
9d44189f 1059 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4aa3df71 1060 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6fad8f66
TR		 1061};
1062
1063static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1064{
1065 struct tegra_output *output = connector_to_output(connector);
1066 struct tegra_sor *sor = to_sor(output);
1067 int err;
1068
1069 if (sor->dpaux)
1070 tegra_dpaux_enable(sor->dpaux);
1071
1072 err = tegra_output_connector_get_modes(connector);
1073
1074 if (sor->dpaux)
1075 tegra_dpaux_disable(sor->dpaux);
1076
1077 return err;
1078}
1079
1080static enum drm_mode_status
1081tegra_sor_connector_mode_valid(struct drm_connector *connector,
1082 struct drm_display_mode *mode)
1083{
1084 return MODE_OK;
1085}
1086
1087static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1088 .get_modes = tegra_sor_connector_get_modes,
1089 .mode_valid = tegra_sor_connector_mode_valid,
1090 .best_encoder = tegra_output_connector_best_encoder,
1091};
1092
1093static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1094 .destroy = tegra_output_encoder_destroy,
1095};
1096
850bab44 1097static void tegra_sor_edp_disable(struct drm_encoder *encoder)
6fad8f66 1098{
850bab44
TR		 1099 struct tegra_output *output = encoder_to_output(encoder);
1100 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1101 struct tegra_sor *sor = to_sor(output);
1102 u32 value;
1103 int err;
6fad8f66 1104
850bab44
TR		 1105 if (output->panel)
1106 drm_panel_disable(output->panel);
6fad8f66 1107
850bab44
TR		 1108 err = tegra_sor_detach(sor);
1109 if (err < 0)
1110 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1111
1112 tegra_sor_writel(sor, 0, SOR_STATE1);
1113 tegra_sor_update(sor);
1114
1115 /*
1116 * The following accesses registers of the display controller, so make
1117 * sure it's only executed when the output is attached to one.
1118 */
1119 if (dc) {
1120 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1121 value &= ~SOR_ENABLE;
1122 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1123
1124 tegra_dc_commit(dc);
1125 }
1126
1127 err = tegra_sor_power_down(sor);
1128 if (err < 0)
1129 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1130
1131 if (sor->dpaux) {
1132 err = tegra_dpaux_disable(sor->dpaux);
1133 if (err < 0)
1134 dev_err(sor->dev, "failed to disable DP: %d\n", err);
1135 }
1136
1137 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
1138 if (err < 0)
1139 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
1140
1141 if (output->panel)
1142 drm_panel_unprepare(output->panel);
1143
1144 reset_control_assert(sor->rst);
1145 clk_disable_unprepare(sor->clk);
6fad8f66
TR		 1146}
1147
459cc2c6
TR		 1148#if 0
1149static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1150 unsigned int *value)
1151{
1152 unsigned int hfp, hsw, hbp, a = 0, b;
1153
1154 hfp = mode->hsync_start - mode->hdisplay;
1155 hsw = mode->hsync_end - mode->hsync_start;
1156 hbp = mode->htotal - mode->hsync_end;
1157
1158 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1159
1160 b = hfp - 1;
1161
1162 pr_info("a: %u, b: %u\n", a, b);
1163 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1164
1165 if (a + hsw + hbp <= 11) {
1166 a = 1 + 11 - hsw - hbp;
1167 pr_info("a: %u\n", a);
1168 }
1169
1170 if (a > b)
1171 return -EINVAL;
1172
1173 if (hsw < 1)
1174 return -EINVAL;
1175
1176 if (mode->hdisplay < 16)
1177 return -EINVAL;
1178
1179 if (value) {
1180 if (b > a && a % 2)
1181 *value = a + 1;
1182 else
1183 *value = a;
1184 }
1185
1186 return 0;
1187}
1188#endif
1189
850bab44 1190static void tegra_sor_edp_enable(struct drm_encoder *encoder)
6fad8f66 1191{
850bab44 1192 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
6fad8f66
TR		 1193 struct tegra_output *output = encoder_to_output(encoder);
1194 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
6b6b6042
TR		 1195 unsigned int vbe, vse, hbe, hse, vbs, hbs, i;
1196 struct tegra_sor *sor = to_sor(output);
34fa183b
TR		 1197 struct tegra_sor_config config;
1198 struct drm_dp_link link;
1199 struct drm_dp_aux *aux;
86f5c52d 1200 int err = 0;
28fe2076 1201 u32 value;
86f5c52d 1202
6b6b6042
TR		 1203 err = clk_prepare_enable(sor->clk);
1204 if (err < 0)
850bab44 1205 dev_err(sor->dev, "failed to enable clock: %d\n", err);
6b6b6042
TR		 1206
1207 reset_control_deassert(sor->rst);
1208
6fad8f66
TR		 1209 if (output->panel)
1210 drm_panel_prepare(output->panel);
1211
34fa183b
TR		 1212 /* FIXME: properly convert to struct drm_dp_aux */
1213 aux = (struct drm_dp_aux *)sor->dpaux;
1214
6b6b6042
TR		 1215 if (sor->dpaux) {
1216 err = tegra_dpaux_enable(sor->dpaux);
1217 if (err < 0)
1218 dev_err(sor->dev, "failed to enable DP: %d\n", err);
34fa183b
TR		 1219
1220 err = drm_dp_link_probe(aux, &link);
1221 if (err < 0) {
1222 dev_err(sor->dev, "failed to probe eDP link: %d\n",
1223 err);
850bab44 1224 return;
34fa183b 1225 }
6b6b6042
TR		 1226 }
1227
1228 err = clk_set_parent(sor->clk, sor->clk_safe);
1229 if (err < 0)
1230 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1231
34fa183b 1232 memset(&config, 0, sizeof(config));
054b1bd1 1233 config.bits_per_pixel = output->connector.display_info.bpc * 3;
34fa183b
TR		 1234
1235 err = tegra_sor_calc_config(sor, mode, &config, &link);
1236 if (err < 0)
1237 dev_err(sor->dev, "failed to compute link configuration: %d\n",
1238 err);
1239
6b6b6042
TR		 1240 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1241 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1242 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1243 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1244
a9a9e4fd
TR		 1245 value = tegra_sor_readl(sor, SOR_PLL2);
1246 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1247 tegra_sor_writel(sor, value, SOR_PLL2);
6b6b6042
TR		 1248 usleep_range(20, 100);
1249
a9a9e4fd
TR		 1250 value = tegra_sor_readl(sor, SOR_PLL3);
1251 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1252 tegra_sor_writel(sor, value, SOR_PLL3);
6b6b6042 1253
a9a9e4fd
TR		 1254 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1255 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1256 tegra_sor_writel(sor, value, SOR_PLL0);
6b6b6042 1257
a9a9e4fd
TR		 1258 value = tegra_sor_readl(sor, SOR_PLL2);
1259 value |= SOR_PLL2_SEQ_PLLCAPPD;
1260 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1261 value |= SOR_PLL2_LVDS_ENABLE;
1262 tegra_sor_writel(sor, value, SOR_PLL2);
6b6b6042 1263
a9a9e4fd
TR		 1264 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1265 tegra_sor_writel(sor, value, SOR_PLL1);
6b6b6042
TR		 1266
1267 while (true) {
a9a9e4fd
TR		 1268 value = tegra_sor_readl(sor, SOR_PLL2);
1269 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
6b6b6042
TR		 1270 break;
1271
1272 usleep_range(250, 1000);
1273 }
1274
a9a9e4fd
TR		 1275 value = tegra_sor_readl(sor, SOR_PLL2);
1276 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1277 value &= ~SOR_PLL2_PORT_POWERDOWN;
1278 tegra_sor_writel(sor, value, SOR_PLL2);
6b6b6042
TR		 1279
1280 /*
1281 * power up
1282 */
1283
1284 /* set safe link bandwidth (1.62 Gbps) */
1285 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1286 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1287 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1288 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1289
1290 /* step 1 */
a9a9e4fd
TR		 1291 value = tegra_sor_readl(sor, SOR_PLL2);
1292 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1293 SOR_PLL2_BANDGAP_POWERDOWN;
1294 tegra_sor_writel(sor, value, SOR_PLL2);
6b6b6042 1295
a9a9e4fd
TR		 1296 value = tegra_sor_readl(sor, SOR_PLL0);
1297 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1298 tegra_sor_writel(sor, value, SOR_PLL0);
6b6b6042 1299
a9a9e4fd 1300 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
6b6b6042 1301 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
a9a9e4fd 1302 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
6b6b6042
TR		 1303
1304 /* step 2 */
1305 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
850bab44 1306 if (err < 0)
6b6b6042 1307 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
6b6b6042
TR		 1308
1309 usleep_range(5, 100);
1310
1311 /* step 3 */
a9a9e4fd
TR		 1312 value = tegra_sor_readl(sor, SOR_PLL2);
1313 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1314 tegra_sor_writel(sor, value, SOR_PLL2);
6b6b6042
TR		 1315
1316 usleep_range(20, 100);
1317
1318 /* step 4 */
a9a9e4fd
TR		 1319 value = tegra_sor_readl(sor, SOR_PLL0);
1320 value &= ~SOR_PLL0_VCOPD;
1321 value &= ~SOR_PLL0_PWR;
1322 tegra_sor_writel(sor, value, SOR_PLL0);
6b6b6042 1323
a9a9e4fd
TR		 1324 value = tegra_sor_readl(sor, SOR_PLL2);
1325 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1326 tegra_sor_writel(sor, value, SOR_PLL2);
6b6b6042
TR		 1327
1328 usleep_range(200, 1000);
1329
1330 /* step 5 */
a9a9e4fd
TR		 1331 value = tegra_sor_readl(sor, SOR_PLL2);
1332 value &= ~SOR_PLL2_PORT_POWERDOWN;
1333 tegra_sor_writel(sor, value, SOR_PLL2);
6b6b6042
TR		 1334
1335 /* switch to DP clock */
1336 err = clk_set_parent(sor->clk, sor->clk_dp);
1337 if (err < 0)
1338 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
1339
899451b7 1340 /* power DP lanes */
a9a9e4fd 1341 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
899451b7
TR		 1342
1343 if (link.num_lanes <= 2)
1344 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1345 else
1346 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1347
1348 if (link.num_lanes <= 1)
1349 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1350 else
1351 value |= SOR_DP_PADCTL_PD_TXD_1;
1352
1353 if (link.num_lanes == 0)
1354 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1355 else
1356 value |= SOR_DP_PADCTL_PD_TXD_0;
1357
a9a9e4fd 1358 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
6b6b6042 1359
a9a9e4fd 1360 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
6b6b6042 1361 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
0c90a184 1362 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
a9a9e4fd 1363 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
6b6b6042
TR		 1364
1365 /* start lane sequencer */
1366 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1367 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1368 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1369
1370 while (true) {
1371 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1372 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1373 break;
1374
1375 usleep_range(250, 1000);
1376 }
1377
a4263fed 1378 /* set link bandwidth */
6b6b6042
TR		 1379 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1380 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
a4263fed 1381 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
6b6b6042
TR		 1382 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1383
1384 /* set linkctl */
a9a9e4fd 1385 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
6b6b6042
TR		 1386 value |= SOR_DP_LINKCTL_ENABLE;
1387
1388 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
34fa183b 1389 value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size);
6b6b6042
TR		 1390
1391 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
a9a9e4fd 1392 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
6b6b6042
TR		 1393
1394 for (i = 0, value = 0; i < 4; i++) {
1395 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1396 SOR_DP_TPG_SCRAMBLER_GALIOS |
1397 SOR_DP_TPG_PATTERN_NONE;
1398 value = (value << 8) | lane;
1399 }
1400
1401 tegra_sor_writel(sor, value, SOR_DP_TPG);
1402
a9a9e4fd 1403 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
6b6b6042 1404 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
34fa183b 1405 value |= SOR_DP_CONFIG_WATERMARK(config.watermark);
6b6b6042
TR		 1406
1407 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
34fa183b 1408 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count);
6b6b6042
TR		 1409
1410 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
34fa183b 1411 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac);
6b6b6042 1412
34fa183b
TR		 1413 if (config.active_polarity)
1414 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1415 else
1416 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
6b6b6042
TR		 1417
1418 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1f64ae7c 1419 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
a9a9e4fd 1420 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
6b6b6042
TR		 1421
1422 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1423 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
7890b576 1424 value |= config.hblank_symbols & 0xffff;
6b6b6042
TR		 1425 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1426
1427 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1428 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
7890b576 1429 value |= config.vblank_symbols & 0xffff;
6b6b6042
TR		 1430 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1431
1432 /* enable pad calibration logic */
a9a9e4fd 1433 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
6b6b6042 1434 value |= SOR_DP_PADCTL_PAD_CAL_PD;
a9a9e4fd 1435 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
6b6b6042
TR		 1436
1437 if (sor->dpaux) {
6b6b6042
TR		 1438 u8 rate, lanes;
1439
1440 err = drm_dp_link_probe(aux, &link);
850bab44 1441 if (err < 0)
6b6b6042
TR		 1442 dev_err(sor->dev, "failed to probe eDP link: %d\n",
1443 err);
6b6b6042
TR		 1444
1445 err = drm_dp_link_power_up(aux, &link);
850bab44 1446 if (err < 0)
6b6b6042
TR		 1447 dev_err(sor->dev, "failed to power up eDP link: %d\n",
1448 err);
6b6b6042
TR		 1449
1450 err = drm_dp_link_configure(aux, &link);
850bab44 1451 if (err < 0)
6b6b6042
TR		 1452 dev_err(sor->dev, "failed to configure eDP link: %d\n",
1453 err);
6b6b6042
TR		 1454
1455 rate = drm_dp_link_rate_to_bw_code(link.rate);
1456 lanes = link.num_lanes;
1457
1458 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1459 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1460 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1461 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1462
a9a9e4fd 1463 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
6b6b6042
TR		 1464 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1465 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1466
1467 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1468 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1469
a9a9e4fd 1470 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
6b6b6042
TR		 1471
1472 /* disable training pattern generator */
1473
1474 for (i = 0; i < link.num_lanes; i++) {
1475 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1476 SOR_DP_TPG_SCRAMBLER_GALIOS |
1477 SOR_DP_TPG_PATTERN_NONE;
1478 value = (value << 8) | lane;
1479 }
1480
1481 tegra_sor_writel(sor, value, SOR_DP_TPG);
1482
1483 err = tegra_sor_dp_train_fast(sor, &link);
1484 if (err < 0) {
1485 dev_err(sor->dev, "DP fast link training failed: %d\n",
1486 err);
6b6b6042
TR		 1487 }
1488
1489 dev_dbg(sor->dev, "fast link training succeeded\n");
1490 }
1491
1492 err = tegra_sor_power_up(sor, 250);
850bab44 1493 if (err < 0)
6b6b6042 1494 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
6b6b6042 1495
6b6b6042
TR		 1496 /*
1497 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
1498 * raster, associate with display controller)
1499 */
3f4f3b5f 1500 value = SOR_STATE_ASY_PROTOCOL_DP_A |
6b6b6042
TR		 1501 SOR_STATE_ASY_CRC_MODE_COMPLETE |
1502 SOR_STATE_ASY_OWNER(dc->pipe + 1);
34fa183b 1503
3f4f3b5f
TR		 1504 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1505 value &= ~SOR_STATE_ASY_HSYNCPOL;
1506
1507 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1508 value |= SOR_STATE_ASY_HSYNCPOL;
1509
1510 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1511 value &= ~SOR_STATE_ASY_VSYNCPOL;
1512
1513 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1514 value |= SOR_STATE_ASY_VSYNCPOL;
1515
34fa183b
TR		 1516 switch (config.bits_per_pixel) {
1517 case 24:
1518 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1519 break;
1520
1521 case 18:
1522 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1523 break;
1524
1525 default:
1526 BUG();
1527 break;
1528 }
1529
a9a9e4fd 1530 tegra_sor_writel(sor, value, SOR_STATE1);
6b6b6042
TR		 1531
1532 /*
1533 * TODO: The video timing programming below doesn't seem to match the
1534 * register definitions.
1535 */
1536
1537 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
51511d05 1538 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));
6b6b6042
TR		 1539
1540 vse = mode->vsync_end - mode->vsync_start - 1;
1541 hse = mode->hsync_end - mode->hsync_start - 1;
1542
1543 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
51511d05 1544 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));
6b6b6042
TR		 1545
1546 vbe = vse + (mode->vsync_start - mode->vdisplay);
1547 hbe = hse + (mode->hsync_start - mode->hdisplay);
1548
1549 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
51511d05 1550 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));
6b6b6042
TR		 1551
1552 vbs = vbe + mode->vdisplay;
1553 hbs = hbe + mode->hdisplay;
1554
1555 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
51511d05
TR		 1556 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));
1557
1558 tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe));
6b6b6042 1559
6fad8f66
TR		 1560 /* CSTM (LVDS, link A/B, upper) */
1561 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1562 SOR_CSTM_UPPER;
1563 tegra_sor_writel(sor, value, SOR_CSTM);
1564
1565 /* PWM setup */
1566 err = tegra_sor_setup_pwm(sor, 250);
850bab44 1567 if (err < 0)
6fad8f66 1568 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
6b6b6042 1569
666cb873
TR		 1570 tegra_sor_update(sor);
1571
6fad8f66
TR		 1572 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1573 value |= SOR_ENABLE;
1574 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
6b6b6042 1575
666cb873 1576 tegra_dc_commit(dc);
6b6b6042 1577
6fad8f66 1578 err = tegra_sor_attach(sor);
850bab44 1579 if (err < 0)
6fad8f66 1580 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
6b6b6042 1581
6fad8f66 1582 err = tegra_sor_wakeup(sor);
850bab44 1583 if (err < 0)
6fad8f66 1584 dev_err(sor->dev, "failed to enable DC: %d\n", err);
6b6b6042 1585
6fad8f66
TR		 1586 if (output->panel)
1587 drm_panel_enable(output->panel);
a82752e1
TR		 1588}
1589
82f1511c
TR		 1590static int
1591tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1592 struct drm_crtc_state *crtc_state,
1593 struct drm_connector_state *conn_state)
1594{
1595 struct tegra_output *output = encoder_to_output(encoder);
1596 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1597 unsigned long pclk = crtc_state->mode.clock * 1000;
1598 struct tegra_sor *sor = to_sor(output);
1599 int err;
1600
1601 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1602 pclk, 0);
1603 if (err < 0) {
1604 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1605 return err;
1606 }
1607
1608 return 0;
1609}
1610
459cc2c6 1611static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
850bab44
TR		 1612 .disable = tegra_sor_edp_disable,
1613 .enable = tegra_sor_edp_enable,
82f1511c 1614 .atomic_check = tegra_sor_encoder_atomic_check,
a82752e1
TR		 1615};
1616
459cc2c6
TR		 1617static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1618{
1619 u32 value = 0;
1620 size_t i;
1621
1622 for (i = size; i > 0; i--)
1623 value = (value << 8) | ptr[i - 1];
1624
1625 return value;
1626}
1627
1628static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1629 const void *data, size_t size)
1630{
1631 const u8 *ptr = data;
1632 unsigned long offset;
1633 size_t i, j;
1634 u32 value;
1635
1636 switch (ptr[0]) {
1637 case HDMI_INFOFRAME_TYPE_AVI:
1638 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1639 break;
1640
1641 case HDMI_INFOFRAME_TYPE_AUDIO:
1642 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1643 break;
1644
1645 case HDMI_INFOFRAME_TYPE_VENDOR:
1646 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1647 break;
1648
1649 default:
1650 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1651 ptr[0]);
1652 return;
1653 }
1654
1655 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1656 INFOFRAME_HEADER_VERSION(ptr[1]) |
1657 INFOFRAME_HEADER_LEN(ptr[2]);
1658 tegra_sor_writel(sor, value, offset);
1659 offset++;
1660
1661 /*
1662 * Each subpack contains 7 bytes, divided into:
1663 * - subpack_low: bytes 0 - 3
1664 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1665 */
1666 for (i = 3, j = 0; i < size; i += 7, j += 8) {
1667 size_t rem = size - i, num = min_t(size_t, rem, 4);
1668
1669 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1670 tegra_sor_writel(sor, value, offset++);
1671
1672 num = min_t(size_t, rem - num, 3);
1673
1674 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1675 tegra_sor_writel(sor, value, offset++);
1676 }
1677}
1678
1679static int
1680tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1681 const struct drm_display_mode *mode)
1682{
1683 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1684 struct hdmi_avi_infoframe frame;
1685 u32 value;
1686 int err;
1687
1688 /* disable AVI infoframe */
1689 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1690 value &= ~INFOFRAME_CTRL_SINGLE;
1691 value &= ~INFOFRAME_CTRL_OTHER;
1692 value &= ~INFOFRAME_CTRL_ENABLE;
1693 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1694
1695 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1696 if (err < 0) {
1697 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1698 return err;
1699 }
1700
1701 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1702 if (err < 0) {
1703 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1704 return err;
1705 }
1706
1707 tegra_sor_hdmi_write_infopack(sor, buffer, err);
1708
1709 /* enable AVI infoframe */
1710 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1711 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1712 value |= INFOFRAME_CTRL_ENABLE;
1713 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1714
1715 return 0;
1716}
1717
1718static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
1719{
1720 u32 value;
1721
1722 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1723 value &= ~INFOFRAME_CTRL_ENABLE;
1724 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1725}
1726
1727static struct tegra_sor_hdmi_settings *
1728tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
1729{
1730 unsigned int i;
1731
1732 for (i = 0; i < sor->num_settings; i++)
1733 if (frequency <= sor->settings[i].frequency)
1734 return &sor->settings[i];
1735
1736 return NULL;
1737}
1738
1739static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
1740{
1741 struct tegra_output *output = encoder_to_output(encoder);
1742 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1743 struct tegra_sor *sor = to_sor(output);
1744 u32 value;
1745 int err;
1746
1747 err = tegra_sor_detach(sor);
1748 if (err < 0)
1749 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1750
1751 tegra_sor_writel(sor, 0, SOR_STATE1);
1752 tegra_sor_update(sor);
1753
1754 /* disable display to SOR clock */
1755 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1756 value &= ~SOR1_TIMING_CYA;
1757 value &= ~SOR1_ENABLE;
1758 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1759
1760 tegra_dc_commit(dc);
1761
1762 err = tegra_sor_power_down(sor);
1763 if (err < 0)
1764 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1765
1766 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI);
1767 if (err < 0)
1768 dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err);
1769
1770 reset_control_assert(sor->rst);
1771 usleep_range(1000, 2000);
1772 clk_disable_unprepare(sor->clk);
1773}
1774
1775static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
1776{
1777 struct tegra_output *output = encoder_to_output(encoder);
1778 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
1779 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1780 unsigned int vbe, vse, hbe, hse, vbs, hbs, div;
1781 struct tegra_sor_hdmi_settings *settings;
1782 struct tegra_sor *sor = to_sor(output);
1783 struct drm_display_mode *mode;
1784 struct drm_display_info *info;
1785 u32 value;
1786 int err;
1787
1788 mode = &encoder->crtc->state->adjusted_mode;
1789 info = &output->connector.display_info;
1790
1791 err = clk_prepare_enable(sor->clk);
1792 if (err < 0)
1793 dev_err(sor->dev, "failed to enable clock: %d\n", err);
1794
1795 usleep_range(1000, 2000);
1796
1797 reset_control_deassert(sor->rst);
1798
1799 err = clk_set_parent(sor->clk, sor->clk_safe);
1800 if (err < 0)
1801 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1802
1803 div = clk_get_rate(sor->clk) / 1000000 * 4;
1804
1805 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI);
1806 if (err < 0)
1807 dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err);
1808
1809 usleep_range(20, 100);
1810
1811 value = tegra_sor_readl(sor, SOR_PLL2);
1812 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1813 tegra_sor_writel(sor, value, SOR_PLL2);
1814
1815 usleep_range(20, 100);
1816
1817 value = tegra_sor_readl(sor, SOR_PLL3);
1818 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
1819 tegra_sor_writel(sor, value, SOR_PLL3);
1820
1821 value = tegra_sor_readl(sor, SOR_PLL0);
1822 value &= ~SOR_PLL0_VCOPD;
1823 value &= ~SOR_PLL0_PWR;
1824 tegra_sor_writel(sor, value, SOR_PLL0);
1825
1826 value = tegra_sor_readl(sor, SOR_PLL2);
1827 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1828 tegra_sor_writel(sor, value, SOR_PLL2);
1829
1830 usleep_range(200, 400);
1831
1832 value = tegra_sor_readl(sor, SOR_PLL2);
1833 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1834 value &= ~SOR_PLL2_PORT_POWERDOWN;
1835 tegra_sor_writel(sor, value, SOR_PLL2);
1836
1837 usleep_range(20, 100);
1838
1839 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1840 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1841 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
1842 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1843
1844 while (true) {
1845 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1846 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
1847 break;
1848
1849 usleep_range(250, 1000);
1850 }
1851
1852 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1853 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
1854 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1855
1856 while (true) {
1857 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1858 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1859 break;
1860
1861 usleep_range(250, 1000);
1862 }
1863
1864 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1865 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1866 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1867
1868 if (mode->clock < 340000)
1869 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
1870 else
1871 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
1872
1873 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
1874 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1875
1876 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
1877 value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
1878 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
1879 value |= SOR_DP_SPARE_SEQ_ENABLE;
1880 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
1881
1882 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
1883 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
1884 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
1885
1886 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
1887 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
1888 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
1889 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
1890
1891 /* program the reference clock */
1892 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
1893 tegra_sor_writel(sor, value, SOR_REFCLK);
1894
1895 /* XXX don't hardcode */
1896 value = SOR_XBAR_CTRL_LINK1_XSEL(4, 4) |
1897 SOR_XBAR_CTRL_LINK1_XSEL(3, 3) |
1898 SOR_XBAR_CTRL_LINK1_XSEL(2, 2) |
1899 SOR_XBAR_CTRL_LINK1_XSEL(1, 1) |
1900 SOR_XBAR_CTRL_LINK1_XSEL(0, 0) |
1901 SOR_XBAR_CTRL_LINK0_XSEL(4, 4) |
1902 SOR_XBAR_CTRL_LINK0_XSEL(3, 3) |
1903 SOR_XBAR_CTRL_LINK0_XSEL(2, 0) |
1904 SOR_XBAR_CTRL_LINK0_XSEL(1, 1) |
1905 SOR_XBAR_CTRL_LINK0_XSEL(0, 2);
1906 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1907
1908 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1909
1910 err = clk_set_parent(sor->clk, sor->clk_parent);
1911 if (err < 0)
1912 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1913
1914 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
1915
1916 /* XXX is this the proper check? */
1917 if (mode->clock < 75000)
1918 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
1919
1920 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
1921
1922 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
1923
1924 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
1925 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
1926 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
1927
1928 /* H_PULSE2 setup */
1929 pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) +
1930 (mode->htotal - mode->hsync_end) - 10;
1931
1932 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
1933 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
1934 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1935
1936 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
1937 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1938
1939 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
1940 value |= H_PULSE2_ENABLE;
1941 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
1942
1943 /* infoframe setup */
1944 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
1945 if (err < 0)
1946 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1947
1948 /* XXX HDMI audio support not implemented yet */
1949 tegra_sor_hdmi_disable_audio_infoframe(sor);
1950
1951 /* use single TMDS protocol */
1952 value = tegra_sor_readl(sor, SOR_STATE1);
1953 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1954 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
1955 tegra_sor_writel(sor, value, SOR_STATE1);
1956
1957 /* power up pad calibration */
1958 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1959 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1960 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1961
1962 /* production settings */
1963 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
1964 if (IS_ERR(settings)) {
1965 dev_err(sor->dev, "no settings for pixel clock %d Hz: %ld\n",
1966 mode->clock * 1000, PTR_ERR(settings));
1967 return;
1968 }
1969
1970 value = tegra_sor_readl(sor, SOR_PLL0);
1971 value &= ~SOR_PLL0_ICHPMP_MASK;
1972 value &= ~SOR_PLL0_VCOCAP_MASK;
1973 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
1974 value |= SOR_PLL0_VCOCAP(settings->vcocap);
1975 tegra_sor_writel(sor, value, SOR_PLL0);
1976
1977 tegra_sor_dp_term_calibrate(sor);
1978
1979 value = tegra_sor_readl(sor, SOR_PLL1);
1980 value &= ~SOR_PLL1_LOADADJ_MASK;
1981 value |= SOR_PLL1_LOADADJ(settings->loadadj);
1982 tegra_sor_writel(sor, value, SOR_PLL1);
1983
1984 value = tegra_sor_readl(sor, SOR_PLL3);
1985 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
1986 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref);
1987 tegra_sor_writel(sor, value, SOR_PLL3);
1988
1989 value = settings->drive_current[0] << 24 |
1990 settings->drive_current[1] << 16 |
1991 settings->drive_current[2] << 8 |
1992 settings->drive_current[3] << 0;
1993 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
1994
1995 value = settings->preemphasis[0] << 24 |
1996 settings->preemphasis[1] << 16 |
1997 settings->preemphasis[2] << 8 |
1998 settings->preemphasis[3] << 0;
1999 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2000
2001 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2002 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2003 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2004 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu);
2005 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2006
2007 /* power down pad calibration */
2008 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2009 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2010 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2011
2012 /* miscellaneous display controller settings */
2013 value = VSYNC_H_POSITION(1);
2014 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2015
2016 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2017 value &= ~DITHER_CONTROL_MASK;
2018 value &= ~BASE_COLOR_SIZE_MASK;
2019
2020 switch (info->bpc) {
2021 case 6:
2022 value |= BASE_COLOR_SIZE_666;
2023 break;
2024
2025 case 8:
2026 value |= BASE_COLOR_SIZE_888;
2027 break;
2028
2029 default:
2030 WARN(1, "%u bits-per-color not supported\n", info->bpc);
2031 break;
2032 }
2033
2034 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2035
2036 err = tegra_sor_power_up(sor, 250);
2037 if (err < 0)
2038 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2039
2040 /* configure mode */
2041 value = tegra_sor_readl(sor, SOR_STATE1);
2042 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
2043 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
2044 value &= ~SOR_STATE_ASY_OWNER_MASK;
2045
2046 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
2047 SOR_STATE_ASY_OWNER(dc->pipe + 1);
2048
2049 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
2050 value &= ~SOR_STATE_ASY_HSYNCPOL;
2051
2052 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2053 value |= SOR_STATE_ASY_HSYNCPOL;
2054
2055 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
2056 value &= ~SOR_STATE_ASY_VSYNCPOL;
2057
2058 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2059 value |= SOR_STATE_ASY_VSYNCPOL;
2060
2061 switch (info->bpc) {
2062 case 8:
2063 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
2064 break;
2065
2066 case 6:
2067 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
2068 break;
2069
2070 default:
2071 BUG();
2072 break;
2073 }
2074
2075 tegra_sor_writel(sor, value, SOR_STATE1);
2076
2077 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2078 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2079 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2080 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2081
2082 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2083 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2084 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2085 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2086
2087 /*
2088 * TODO: The video timing programming below doesn't seem to match the
2089 * register definitions.
2090 */
2091
2092 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
2093 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));
2094
2095 /* sync end = sync width - 1 */
2096 vse = mode->vsync_end - mode->vsync_start - 1;
2097 hse = mode->hsync_end - mode->hsync_start - 1;
2098
2099 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
2100 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));
2101
2102 /* blank end = sync end + back porch */
2103 vbe = vse + (mode->vtotal - mode->vsync_end);
2104 hbe = hse + (mode->htotal - mode->hsync_end);
2105
2106 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
2107 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));
2108
2109 /* blank start = blank end + active */
2110 vbs = vbe + mode->vdisplay;
2111 hbs = hbe + mode->hdisplay;
2112
2113 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
2114 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));
2115
2116 tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe));
2117
2118 tegra_sor_update(sor);
2119
2120 err = tegra_sor_attach(sor);
2121 if (err < 0)
2122 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2123
2124 /* enable display to SOR clock and generate HDMI preamble */
2125 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2126 value |= SOR1_ENABLE | SOR1_TIMING_CYA;
2127 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2128
2129 tegra_dc_commit(dc);
2130
2131 err = tegra_sor_wakeup(sor);
2132 if (err < 0)
2133 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2134}
2135
2136static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2137 .disable = tegra_sor_hdmi_disable,
2138 .enable = tegra_sor_hdmi_enable,
2139 .atomic_check = tegra_sor_encoder_atomic_check,
2140};
2141
6b6b6042
TR		 2142static int tegra_sor_init(struct host1x_client *client)
2143{
9910f5c4 2144 struct drm_device *drm = dev_get_drvdata(client->parent);
459cc2c6 2145 const struct drm_encoder_helper_funcs *helpers = NULL;
6b6b6042 2146 struct tegra_sor *sor = host1x_client_to_sor(client);
459cc2c6
TR		 2147 int connector = DRM_MODE_CONNECTOR_Unknown;
2148 int encoder = DRM_MODE_ENCODER_NONE;
6b6b6042
TR		 2149 int err;
2150
459cc2c6
TR		 2151 if (!sor->dpaux) {
2152 if (sor->soc->supports_hdmi) {
2153 connector = DRM_MODE_CONNECTOR_HDMIA;
2154 encoder = DRM_MODE_ENCODER_TMDS;
2155 helpers = &tegra_sor_hdmi_helpers;
2156 } else if (sor->soc->supports_lvds) {
2157 connector = DRM_MODE_CONNECTOR_LVDS;
2158 encoder = DRM_MODE_ENCODER_LVDS;
2159 }
2160 } else {
2161 if (sor->soc->supports_edp) {
2162 connector = DRM_MODE_CONNECTOR_eDP;
2163 encoder = DRM_MODE_ENCODER_TMDS;
2164 helpers = &tegra_sor_edp_helpers;
2165 } else if (sor->soc->supports_dp) {
2166 connector = DRM_MODE_CONNECTOR_DisplayPort;
2167 encoder = DRM_MODE_ENCODER_TMDS;
2168 }
2169 }
6b6b6042 2170
6b6b6042 2171 sor->output.dev = sor->dev;
6b6b6042 2172
6fad8f66
TR		 2173 drm_connector_init(drm, &sor->output.connector,
2174 &tegra_sor_connector_funcs,
459cc2c6 2175 connector);
6fad8f66
TR		 2176 drm_connector_helper_add(&sor->output.connector,
2177 &tegra_sor_connector_helper_funcs);
2178 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2179
6fad8f66 2180 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
459cc2c6
TR		 2181 encoder);
2182 drm_encoder_helper_add(&sor->output.encoder, helpers);
6fad8f66
TR		 2183
2184 drm_mode_connector_attach_encoder(&sor->output.connector,
2185 &sor->output.encoder);
2186 drm_connector_register(&sor->output.connector);
2187
ea130b24
TR		 2188 err = tegra_output_init(drm, &sor->output);
2189 if (err < 0) {
2190 dev_err(client->dev, "failed to initialize output: %d\n", err);
2191 return err;
2192 }
6fad8f66 2193
ea130b24 2194 sor->output.encoder.possible_crtcs = 0x3;
6b6b6042 2195
a82752e1 2196 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1b0c7b48 2197 err = tegra_sor_debugfs_init(sor, drm->primary);
a82752e1
TR		 2198 if (err < 0)
2199 dev_err(sor->dev, "debugfs setup failed: %d\n", err);
2200 }
2201
6b6b6042
TR		 2202 if (sor->dpaux) {
2203 err = tegra_dpaux_attach(sor->dpaux, &sor->output);
2204 if (err < 0) {
2205 dev_err(sor->dev, "failed to attach DP: %d\n", err);
2206 return err;
2207 }
2208 }
2209
535a65db
TV		 2210 /*
2211 * XXX: Remove this reset once proper hand-over from firmware to
2212 * kernel is possible.
2213 */
2214 err = reset_control_assert(sor->rst);
2215 if (err < 0) {
2216 dev_err(sor->dev, "failed to assert SOR reset: %d\n", err);
2217 return err;
2218 }
2219
6fad8f66
TR		 2220 err = clk_prepare_enable(sor->clk);
2221 if (err < 0) {
2222 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2223 return err;
2224 }
2225
535a65db
TV		 2226 usleep_range(1000, 3000);
2227
2228 err = reset_control_deassert(sor->rst);
2229 if (err < 0) {
2230 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err);
2231 return err;
2232 }
2233
6fad8f66
TR		 2234 err = clk_prepare_enable(sor->clk_safe);
2235 if (err < 0)
2236 return err;
2237
2238 err = clk_prepare_enable(sor->clk_dp);
2239 if (err < 0)
2240 return err;
2241
6b6b6042
TR		 2242 return 0;
2243}
2244
2245static int tegra_sor_exit(struct host1x_client *client)
2246{
2247 struct tegra_sor *sor = host1x_client_to_sor(client);
2248 int err;
2249
328ec69e
TR		 2250 tegra_output_exit(&sor->output);
2251
6b6b6042
TR		 2252 if (sor->dpaux) {
2253 err = tegra_dpaux_detach(sor->dpaux);
2254 if (err < 0) {
2255 dev_err(sor->dev, "failed to detach DP: %d\n", err);
2256 return err;
2257 }
2258 }
2259
6fad8f66
TR		 2260 clk_disable_unprepare(sor->clk_safe);
2261 clk_disable_unprepare(sor->clk_dp);
2262 clk_disable_unprepare(sor->clk);
2263
4009c224
TR		 2264 if (IS_ENABLED(CONFIG_DEBUG_FS))
2265 tegra_sor_debugfs_exit(sor);
a82752e1 2266
6b6b6042
TR		 2267 return 0;
2268}
2269
2270static const struct host1x_client_ops sor_client_ops = {
2271 .init = tegra_sor_init,
2272 .exit = tegra_sor_exit,
2273};
2274
459cc2c6
TR		 2275static const struct tegra_sor_ops tegra_sor_edp_ops = {
2276 .name = "eDP",
2277};
2278
2279static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2280{
2281 int err;
2282
2283 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2284 if (IS_ERR(sor->avdd_io_supply)) {
2285 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2286 PTR_ERR(sor->avdd_io_supply));
2287 return PTR_ERR(sor->avdd_io_supply);
2288 }
2289
2290 err = regulator_enable(sor->avdd_io_supply);
2291 if (err < 0) {
2292 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2293 err);
2294 return err;
2295 }
2296
2297 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2298 if (IS_ERR(sor->vdd_pll_supply)) {
2299 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2300 PTR_ERR(sor->vdd_pll_supply));
2301 return PTR_ERR(sor->vdd_pll_supply);
2302 }
2303
2304 err = regulator_enable(sor->vdd_pll_supply);
2305 if (err < 0) {
2306 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2307 err);
2308 return err;
2309 }
2310
2311 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2312 if (IS_ERR(sor->hdmi_supply)) {
2313 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2314 PTR_ERR(sor->hdmi_supply));
2315 return PTR_ERR(sor->hdmi_supply);
2316 }
2317
2318 err = regulator_enable(sor->hdmi_supply);
2319 if (err < 0) {
2320 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2321 return err;
2322 }
2323
2324 return 0;
2325}
2326
2327static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
2328{
2329 regulator_disable(sor->hdmi_supply);
2330 regulator_disable(sor->vdd_pll_supply);
2331 regulator_disable(sor->avdd_io_supply);
2332
2333 return 0;
2334}
2335
2336static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
2337 .name = "HDMI",
2338 .probe = tegra_sor_hdmi_probe,
2339 .remove = tegra_sor_hdmi_remove,
2340};
2341
2342static const struct tegra_sor_soc tegra124_sor = {
2343 .supports_edp = true,
2344 .supports_lvds = true,
2345 .supports_hdmi = false,
2346 .supports_dp = false,
2347};
2348
2349static const struct tegra_sor_soc tegra210_sor = {
2350 .supports_edp = true,
2351 .supports_lvds = false,
2352 .supports_hdmi = false,
2353 .supports_dp = false,
2354};
2355
2356static const struct tegra_sor_soc tegra210_sor1 = {
2357 .supports_edp = false,
2358 .supports_lvds = false,
2359 .supports_hdmi = true,
2360 .supports_dp = true,
2361
2362 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
2363 .settings = tegra210_sor_hdmi_defaults,
2364};
2365
2366static const struct of_device_id tegra_sor_of_match[] = {
2367 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
2368 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
2369 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
2370 { },
2371};
2372MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
2373
6b6b6042
TR		 2374static int tegra_sor_probe(struct platform_device *pdev)
2375{
459cc2c6 2376 const struct of_device_id *match;
6b6b6042
TR		 2377 struct device_node *np;
2378 struct tegra_sor *sor;
2379 struct resource *regs;
2380 int err;
2381
459cc2c6
TR		 2382 match = of_match_device(tegra_sor_of_match, &pdev->dev);
2383
6b6b6042
TR		 2384 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
2385 if (!sor)
2386 return -ENOMEM;
2387
2388 sor->output.dev = sor->dev = &pdev->dev;
459cc2c6
TR		 2389 sor->soc = match->data;
2390
2391 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
2392 sor->soc->num_settings *
2393 sizeof(*sor->settings),
2394 GFP_KERNEL);
2395 if (!sor->settings)
2396 return -ENOMEM;
2397
2398 sor->num_settings = sor->soc->num_settings;
6b6b6042
TR		 2399
2400 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
2401 if (np) {
2402 sor->dpaux = tegra_dpaux_find_by_of_node(np);
2403 of_node_put(np);
2404
2405 if (!sor->dpaux)
2406 return -EPROBE_DEFER;
2407 }
2408
459cc2c6
TR		 2409 if (!sor->dpaux) {
2410 if (sor->soc->supports_hdmi) {
2411 sor->ops = &tegra_sor_hdmi_ops;
2412 } else if (sor->soc->supports_lvds) {
2413 dev_err(&pdev->dev, "LVDS not supported yet\n");
2414 return -ENODEV;
2415 } else {
2416 dev_err(&pdev->dev, "unknown (non-DP) support\n");
2417 return -ENODEV;
2418 }
2419 } else {
2420 if (sor->soc->supports_edp) {
2421 sor->ops = &tegra_sor_edp_ops;
2422 } else if (sor->soc->supports_dp) {
2423 dev_err(&pdev->dev, "DisplayPort not supported yet\n");
2424 return -ENODEV;
2425 } else {
2426 dev_err(&pdev->dev, "unknown (DP) support\n");
2427 return -ENODEV;
2428 }
2429 }
2430
6b6b6042 2431 err = tegra_output_probe(&sor->output);
4dbdc740
TR		 2432 if (err < 0) {
2433 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
6b6b6042 2434 return err;
4dbdc740 2435 }
6b6b6042 2436
459cc2c6
TR		 2437 if (sor->ops && sor->ops->probe) {
2438 err = sor->ops->probe(sor);
2439 if (err < 0) {
2440 dev_err(&pdev->dev, "failed to probe %s: %d\n",
2441 sor->ops->name, err);
2442 goto output;
2443 }
2444 }
2445
6b6b6042
TR		 2446 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2447 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
459cc2c6
TR		 2448 if (IS_ERR(sor->regs)) {
2449 err = PTR_ERR(sor->regs);
2450 goto remove;
2451 }
6b6b6042
TR		 2452
2453 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
4dbdc740 2454 if (IS_ERR(sor->rst)) {
459cc2c6
TR		 2455 err = PTR_ERR(sor->rst);
2456 dev_err(&pdev->dev, "failed to get reset control: %d\n", err);
2457 goto remove;
4dbdc740 2458 }
6b6b6042
TR		 2459
2460 sor->clk = devm_clk_get(&pdev->dev, NULL);
4dbdc740 2461 if (IS_ERR(sor->clk)) {
459cc2c6
TR		 2462 err = PTR_ERR(sor->clk);
2463 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
2464 goto remove;
4dbdc740 2465 }
6b6b6042
TR		 2466
2467 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
4dbdc740 2468 if (IS_ERR(sor->clk_parent)) {
459cc2c6
TR		 2469 err = PTR_ERR(sor->clk_parent);
2470 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
2471 goto remove;
4dbdc740 2472 }
6b6b6042 2473
6b6b6042 2474 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
4dbdc740 2475 if (IS_ERR(sor->clk_safe)) {
459cc2c6
TR		 2476 err = PTR_ERR(sor->clk_safe);
2477 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
2478 goto remove;
4dbdc740 2479 }
6b6b6042 2480
6b6b6042 2481 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
4dbdc740 2482 if (IS_ERR(sor->clk_dp)) {
459cc2c6
TR		 2483 err = PTR_ERR(sor->clk_dp);
2484 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
2485 goto remove;
4dbdc740 2486 }
6b6b6042 2487
6b6b6042
TR		 2488 INIT_LIST_HEAD(&sor->client.list);
2489 sor->client.ops = &sor_client_ops;
2490 sor->client.dev = &pdev->dev;
2491
2492 err = host1x_client_register(&sor->client);
2493 if (err < 0) {
2494 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2495 err);
459cc2c6 2496 goto remove;
6b6b6042
TR		 2497 }
2498
2499 platform_set_drvdata(pdev, sor);
2500
2501 return 0;
459cc2c6
TR		 2502
2503remove:
2504 if (sor->ops && sor->ops->remove)
2505 sor->ops->remove(sor);
2506output:
2507 tegra_output_remove(&sor->output);
2508 return err;
6b6b6042
TR		 2509}
2510
2511static int tegra_sor_remove(struct platform_device *pdev)
2512{
2513 struct tegra_sor *sor = platform_get_drvdata(pdev);
2514 int err;
2515
2516 err = host1x_client_unregister(&sor->client);
2517 if (err < 0) {
2518 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2519 err);
2520 return err;
2521 }
2522
459cc2c6
TR		 2523 if (sor->ops && sor->ops->remove) {
2524 err = sor->ops->remove(sor);
2525 if (err < 0)
2526 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
2527 }
2528
328ec69e 2529 tegra_output_remove(&sor->output);
6b6b6042
TR		 2530
2531 return 0;
2532}
2533
6b6b6042
TR		 2534struct platform_driver tegra_sor_driver = {
2535 .driver = {
2536 .name = "tegra-sor",
2537 .of_match_table = tegra_sor_of_match,
2538 },
2539 .probe = tegra_sor_probe,
2540 .remove = tegra_sor_remove,
2541};
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