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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / tegra / sor.c
CommitLineData
6b6b6042
TR		 1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
a82752e1 10#include <linux/debugfs.h>
6b6b6042
TR		 11#include <linux/io.h>
12#include <linux/platform_device.h>
13#include <linux/reset.h>
14#include <linux/tegra-powergate.h>
15
16#include <drm/drm_dp_helper.h>
17
18#include "dc.h"
19#include "drm.h"
20#include "sor.h"
21
22struct tegra_sor {
23 struct host1x_client client;
24 struct tegra_output output;
25 struct device *dev;
26
27 void __iomem *regs;
28
29 struct reset_control *rst;
30 struct clk *clk_parent;
31 struct clk *clk_safe;
32 struct clk *clk_dp;
33 struct clk *clk;
34
35 struct tegra_dpaux *dpaux;
36
86f5c52d 37 struct mutex lock;
6b6b6042 38 bool enabled;
a82752e1
TR		 39
40 struct dentry *debugfs;
6b6b6042
TR		 41};
42
43static inline struct tegra_sor *
44host1x_client_to_sor(struct host1x_client *client)
45{
46 return container_of(client, struct tegra_sor, client);
47}
48
49static inline struct tegra_sor *to_sor(struct tegra_output *output)
50{
51 return container_of(output, struct tegra_sor, output);
52}
53
54static inline unsigned long tegra_sor_readl(struct tegra_sor *sor,
55 unsigned long offset)
56{
57 return readl(sor->regs + (offset << 2));
58}
59
60static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value,
61 unsigned long offset)
62{
63 writel(value, sor->regs + (offset << 2));
64}
65
66static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
67 struct drm_dp_link *link)
68{
69 unsigned long value;
70 unsigned int i;
71 u8 pattern;
72 int err;
73
74 /* setup lane parameters */
75 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
76 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
77 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
78 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
79 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0);
80
81 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
82 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
83 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
84 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
85 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0);
86
87 value = SOR_LANE_POST_CURSOR_LANE3(0x00) |
88 SOR_LANE_POST_CURSOR_LANE2(0x00) |
89 SOR_LANE_POST_CURSOR_LANE1(0x00) |
90 SOR_LANE_POST_CURSOR_LANE0(0x00);
91 tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0);
92
93 /* disable LVDS mode */
94 tegra_sor_writel(sor, 0, SOR_LVDS);
95
96 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
97 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
98 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
99 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
100 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
101
102 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
103 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
104 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
105 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
106
107 usleep_range(10, 100);
108
109 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
110 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
111 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
112 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
113
114 err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B);
115 if (err < 0)
116 return err;
117
118 for (i = 0, value = 0; i < link->num_lanes; i++) {
119 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
120 SOR_DP_TPG_SCRAMBLER_NONE |
121 SOR_DP_TPG_PATTERN_TRAIN1;
122 value = (value << 8) | lane;
123 }
124
125 tegra_sor_writel(sor, value, SOR_DP_TPG);
126
127 pattern = DP_TRAINING_PATTERN_1;
128
129 err = tegra_dpaux_train(sor->dpaux, link, pattern);
130 if (err < 0)
131 return err;
132
133 value = tegra_sor_readl(sor, SOR_DP_SPARE_0);
134 value |= SOR_DP_SPARE_SEQ_ENABLE;
135 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
136 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
137 tegra_sor_writel(sor, value, SOR_DP_SPARE_0);
138
139 for (i = 0, value = 0; i < link->num_lanes; i++) {
140 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
141 SOR_DP_TPG_SCRAMBLER_NONE |
142 SOR_DP_TPG_PATTERN_TRAIN2;
143 value = (value << 8) | lane;
144 }
145
146 tegra_sor_writel(sor, value, SOR_DP_TPG);
147
148 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
149
150 err = tegra_dpaux_train(sor->dpaux, link, pattern);
151 if (err < 0)
152 return err;
153
154 for (i = 0, value = 0; i < link->num_lanes; i++) {
155 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
156 SOR_DP_TPG_SCRAMBLER_GALIOS |
157 SOR_DP_TPG_PATTERN_NONE;
158 value = (value << 8) | lane;
159 }
160
161 tegra_sor_writel(sor, value, SOR_DP_TPG);
162
163 pattern = DP_TRAINING_PATTERN_DISABLE;
164
165 err = tegra_dpaux_train(sor->dpaux, link, pattern);
166 if (err < 0)
167 return err;
168
169 return 0;
170}
171
172static void tegra_sor_super_update(struct tegra_sor *sor)
173{
174 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
175 tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0);
176 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
177}
178
179static void tegra_sor_update(struct tegra_sor *sor)
180{
181 tegra_sor_writel(sor, 0, SOR_STATE_0);
182 tegra_sor_writel(sor, 1, SOR_STATE_0);
183 tegra_sor_writel(sor, 0, SOR_STATE_0);
184}
185
186static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
187{
188 unsigned long value;
189
190 value = tegra_sor_readl(sor, SOR_PWM_DIV);
191 value &= ~SOR_PWM_DIV_MASK;
192 value |= 0x400; /* period */
193 tegra_sor_writel(sor, value, SOR_PWM_DIV);
194
195 value = tegra_sor_readl(sor, SOR_PWM_CTL);
196 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
197 value |= 0x400; /* duty cycle */
198 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
199 value |= SOR_PWM_CTL_TRIGGER;
200 tegra_sor_writel(sor, value, SOR_PWM_CTL);
201
202 timeout = jiffies + msecs_to_jiffies(timeout);
203
204 while (time_before(jiffies, timeout)) {
205 value = tegra_sor_readl(sor, SOR_PWM_CTL);
206 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
207 return 0;
208
209 usleep_range(25, 100);
210 }
211
212 return -ETIMEDOUT;
213}
214
215static int tegra_sor_attach(struct tegra_sor *sor)
216{
217 unsigned long value, timeout;
218
219 /* wake up in normal mode */
220 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
221 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
222 value |= SOR_SUPER_STATE_MODE_NORMAL;
223 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
224 tegra_sor_super_update(sor);
225
226 /* attach */
227 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
228 value |= SOR_SUPER_STATE_ATTACHED;
229 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
230 tegra_sor_super_update(sor);
231
232 timeout = jiffies + msecs_to_jiffies(250);
233
234 while (time_before(jiffies, timeout)) {
235 value = tegra_sor_readl(sor, SOR_TEST);
236 if ((value & SOR_TEST_ATTACHED) != 0)
237 return 0;
238
239 usleep_range(25, 100);
240 }
241
242 return -ETIMEDOUT;
243}
244
245static int tegra_sor_wakeup(struct tegra_sor *sor)
246{
247 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
248 unsigned long value, timeout;
249
250 /* enable display controller outputs */
251 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
252 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
253 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
254 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
255
256 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
257 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
258
259 timeout = jiffies + msecs_to_jiffies(250);
260
261 /* wait for head to wake up */
262 while (time_before(jiffies, timeout)) {
263 value = tegra_sor_readl(sor, SOR_TEST);
264 value &= SOR_TEST_HEAD_MODE_MASK;
265
266 if (value == SOR_TEST_HEAD_MODE_AWAKE)
267 return 0;
268
269 usleep_range(25, 100);
270 }
271
272 return -ETIMEDOUT;
273}
274
275static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
276{
277 unsigned long value;
278
279 value = tegra_sor_readl(sor, SOR_PWR);
280 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
281 tegra_sor_writel(sor, value, SOR_PWR);
282
283 timeout = jiffies + msecs_to_jiffies(timeout);
284
285 while (time_before(jiffies, timeout)) {
286 value = tegra_sor_readl(sor, SOR_PWR);
287 if ((value & SOR_PWR_TRIGGER) == 0)
288 return 0;
289
290 usleep_range(25, 100);
291 }
292
293 return -ETIMEDOUT;
294}
295
296static int tegra_output_sor_enable(struct tegra_output *output)
297{
298 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
299 struct drm_display_mode *mode = &dc->base.mode;
300 unsigned int vbe, vse, hbe, hse, vbs, hbs, i;
301 struct tegra_sor *sor = to_sor(output);
302 unsigned long value;
86f5c52d
TR		 303 int err = 0;
304
305 mutex_lock(&sor->lock);
6b6b6042
TR		 306
307 if (sor->enabled)
86f5c52d 308 goto unlock;
6b6b6042
TR		 309
310 err = clk_prepare_enable(sor->clk);
311 if (err < 0)
86f5c52d 312 goto unlock;
6b6b6042
TR		 313
314 reset_control_deassert(sor->rst);
315
316 if (sor->dpaux) {
317 err = tegra_dpaux_enable(sor->dpaux);
318 if (err < 0)
319 dev_err(sor->dev, "failed to enable DP: %d\n", err);
320 }
321
322 err = clk_set_parent(sor->clk, sor->clk_safe);
323 if (err < 0)
324 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
325
326 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
327 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
328 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
329 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
330
331 value = tegra_sor_readl(sor, SOR_PLL_2);
332 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
333 tegra_sor_writel(sor, value, SOR_PLL_2);
334 usleep_range(20, 100);
335
336 value = tegra_sor_readl(sor, SOR_PLL_3);
337 value |= SOR_PLL_3_PLL_VDD_MODE_V3_3;
338 tegra_sor_writel(sor, value, SOR_PLL_3);
339
340 value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST |
341 SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT;
342 tegra_sor_writel(sor, value, SOR_PLL_0);
343
344 value = tegra_sor_readl(sor, SOR_PLL_2);
345 value |= SOR_PLL_2_SEQ_PLLCAPPD;
346 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
347 value |= SOR_PLL_2_LVDS_ENABLE;
348 tegra_sor_writel(sor, value, SOR_PLL_2);
349
350 value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM;
351 tegra_sor_writel(sor, value, SOR_PLL_1);
352
353 while (true) {
354 value = tegra_sor_readl(sor, SOR_PLL_2);
355 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0)
356 break;
357
358 usleep_range(250, 1000);
359 }
360
361 value = tegra_sor_readl(sor, SOR_PLL_2);
362 value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE;
363 value &= ~SOR_PLL_2_PORT_POWERDOWN;
364 tegra_sor_writel(sor, value, SOR_PLL_2);
365
366 /*
367 * power up
368 */
369
370 /* set safe link bandwidth (1.62 Gbps) */
371 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
372 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
373 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
374 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
375
376 /* step 1 */
377 value = tegra_sor_readl(sor, SOR_PLL_2);
378 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN |
379 SOR_PLL_2_BANDGAP_POWERDOWN;
380 tegra_sor_writel(sor, value, SOR_PLL_2);
381
382 value = tegra_sor_readl(sor, SOR_PLL_0);
383 value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF;
384 tegra_sor_writel(sor, value, SOR_PLL_0);
385
386 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
387 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
388 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
389
390 /* step 2 */
391 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
392 if (err < 0) {
393 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
86f5c52d 394 goto unlock;
6b6b6042
TR		 395 }
396
397 usleep_range(5, 100);
398
399 /* step 3 */
400 value = tegra_sor_readl(sor, SOR_PLL_2);
401 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
402 tegra_sor_writel(sor, value, SOR_PLL_2);
403
404 usleep_range(20, 100);
405
406 /* step 4 */
407 value = tegra_sor_readl(sor, SOR_PLL_0);
408 value &= ~SOR_PLL_0_POWER_OFF;
409 value &= ~SOR_PLL_0_VCOPD;
410 tegra_sor_writel(sor, value, SOR_PLL_0);
411
412 value = tegra_sor_readl(sor, SOR_PLL_2);
413 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
414 tegra_sor_writel(sor, value, SOR_PLL_2);
415
416 usleep_range(200, 1000);
417
418 /* step 5 */
419 value = tegra_sor_readl(sor, SOR_PLL_2);
420 value &= ~SOR_PLL_2_PORT_POWERDOWN;
421 tegra_sor_writel(sor, value, SOR_PLL_2);
422
423 /* switch to DP clock */
424 err = clk_set_parent(sor->clk, sor->clk_dp);
425 if (err < 0)
426 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
427
428 /* power dplanes (XXX parameterize based on link?) */
429 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
430 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
431 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
432 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
433
434 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
435 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
436 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
437 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
438
439 /* start lane sequencer */
440 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
441 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
442 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
443
444 while (true) {
445 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
446 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
447 break;
448
449 usleep_range(250, 1000);
450 }
451
452 /* set link bandwidth (2.7 GHz, XXX: parameterize based on link?) */
453 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
454 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
455 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
456 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
457
458 /* set linkctl */
459 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
460 value |= SOR_DP_LINKCTL_ENABLE;
461
462 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
463 value |= SOR_DP_LINKCTL_TU_SIZE(59); /* XXX: don't hardcode? */
464
465 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
466 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
467
468 for (i = 0, value = 0; i < 4; i++) {
469 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
470 SOR_DP_TPG_SCRAMBLER_GALIOS |
471 SOR_DP_TPG_PATTERN_NONE;
472 value = (value << 8) | lane;
473 }
474
475 tegra_sor_writel(sor, value, SOR_DP_TPG);
476
477 value = tegra_sor_readl(sor, SOR_DP_CONFIG_0);
478 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
479 value |= SOR_DP_CONFIG_WATERMARK(14); /* XXX: don't hardcode? */
480
481 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
482 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(47); /* XXX: don't hardcode? */
483
484 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
485 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(9); /* XXX: don't hardcode? */
486
487 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; /* XXX: don't hardcode? */
488
489 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
490 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; /* XXX: don't hardcode? */
491 tegra_sor_writel(sor, value, SOR_DP_CONFIG_0);
492
493 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
494 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
495 value |= 137; /* XXX: don't hardcode? */
496 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
497
498 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
499 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
500 value |= 2368; /* XXX: don't hardcode? */
501 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
502
503 /* enable pad calibration logic */
504 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
505 value |= SOR_DP_PADCTL_PAD_CAL_PD;
506 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
507
508 if (sor->dpaux) {
509 /* FIXME: properly convert to struct drm_dp_aux */
510 struct drm_dp_aux *aux = (struct drm_dp_aux *)sor->dpaux;
511 struct drm_dp_link link;
512 u8 rate, lanes;
513
514 err = drm_dp_link_probe(aux, &link);
515 if (err < 0) {
516 dev_err(sor->dev, "failed to probe eDP link: %d\n",
517 err);
86f5c52d 518 goto unlock;
6b6b6042
TR		 519 }
520
521 err = drm_dp_link_power_up(aux, &link);
522 if (err < 0) {
523 dev_err(sor->dev, "failed to power up eDP link: %d\n",
524 err);
86f5c52d 525 goto unlock;
6b6b6042
TR		 526 }
527
528 err = drm_dp_link_configure(aux, &link);
529 if (err < 0) {
530 dev_err(sor->dev, "failed to configure eDP link: %d\n",
531 err);
86f5c52d 532 goto unlock;
6b6b6042
TR		 533 }
534
535 rate = drm_dp_link_rate_to_bw_code(link.rate);
536 lanes = link.num_lanes;
537
538 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
539 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
540 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
541 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
542
543 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
544 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
545 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
546
547 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
548 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
549
550 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
551
552 /* disable training pattern generator */
553
554 for (i = 0; i < link.num_lanes; i++) {
555 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
556 SOR_DP_TPG_SCRAMBLER_GALIOS |
557 SOR_DP_TPG_PATTERN_NONE;
558 value = (value << 8) | lane;
559 }
560
561 tegra_sor_writel(sor, value, SOR_DP_TPG);
562
563 err = tegra_sor_dp_train_fast(sor, &link);
564 if (err < 0) {
565 dev_err(sor->dev, "DP fast link training failed: %d\n",
566 err);
86f5c52d 567 goto unlock;
6b6b6042
TR		 568 }
569
570 dev_dbg(sor->dev, "fast link training succeeded\n");
571 }
572
573 err = tegra_sor_power_up(sor, 250);
574 if (err < 0) {
575 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
86f5c52d 576 goto unlock;
6b6b6042
TR		 577 }
578
579 /* start display controller in continuous mode */
580 value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
581 value |= WRITE_MUX;
582 tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
583
584 tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
585 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
586
587 value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
588 value &= ~WRITE_MUX;
589 tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
590
591 /*
592 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
593 * raster, associate with display controller)
594 */
595 value = SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 |
596 SOR_STATE_ASY_VSYNCPOL |
597 SOR_STATE_ASY_HSYNCPOL |
598 SOR_STATE_ASY_PROTOCOL_DP_A |
599 SOR_STATE_ASY_CRC_MODE_COMPLETE |
600 SOR_STATE_ASY_OWNER(dc->pipe + 1);
601 tegra_sor_writel(sor, value, SOR_STATE_1);
602
603 /*
604 * TODO: The video timing programming below doesn't seem to match the
605 * register definitions.
606 */
607
608 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
609 tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0));
610
611 vse = mode->vsync_end - mode->vsync_start - 1;
612 hse = mode->hsync_end - mode->hsync_start - 1;
613
614 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
615 tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0));
616
617 vbe = vse + (mode->vsync_start - mode->vdisplay);
618 hbe = hse + (mode->hsync_start - mode->hdisplay);
619
620 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
621 tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0));
622
623 vbs = vbe + mode->vdisplay;
624 hbs = hbe + mode->hdisplay;
625
626 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
627 tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));
628
629 /* XXX interlaced mode */
630 tegra_sor_writel(sor, 0x00000001, SOR_HEAD_STATE_5(0));
631
632 /* CSTM (LVDS, link A/B, upper) */
633 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_B | SOR_CSTM_LINK_ACT_B |
634 SOR_CSTM_UPPER;
635 tegra_sor_writel(sor, value, SOR_CSTM);
636
637 /* PWM setup */
638 err = tegra_sor_setup_pwm(sor, 250);
639 if (err < 0) {
640 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
86f5c52d 641 goto unlock;
6b6b6042
TR		 642 }
643
644 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
645 value |= SOR_ENABLE;
646 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
647
648 tegra_sor_update(sor);
649
650 err = tegra_sor_attach(sor);
651 if (err < 0) {
652 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
86f5c52d 653 goto unlock;
6b6b6042
TR		 654 }
655
656 err = tegra_sor_wakeup(sor);
657 if (err < 0) {
658 dev_err(sor->dev, "failed to enable DC: %d\n", err);
86f5c52d 659 goto unlock;
6b6b6042
TR		 660 }
661
662 sor->enabled = true;
663
86f5c52d
TR		 664unlock:
665 mutex_unlock(&sor->lock);
666 return err;
6b6b6042
TR		 667}
668
669static int tegra_sor_detach(struct tegra_sor *sor)
670{
671 unsigned long value, timeout;
672
673 /* switch to safe mode */
674 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
675 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
676 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
677 tegra_sor_super_update(sor);
678
679 timeout = jiffies + msecs_to_jiffies(250);
680
681 while (time_before(jiffies, timeout)) {
682 value = tegra_sor_readl(sor, SOR_PWR);
683 if (value & SOR_PWR_MODE_SAFE)
684 break;
685 }
686
687 if ((value & SOR_PWR_MODE_SAFE) == 0)
688 return -ETIMEDOUT;
689
690 /* go to sleep */
691 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
692 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
693 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
694 tegra_sor_super_update(sor);
695
696 /* detach */
697 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
698 value &= ~SOR_SUPER_STATE_ATTACHED;
699 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
700 tegra_sor_super_update(sor);
701
702 timeout = jiffies + msecs_to_jiffies(250);
703
704 while (time_before(jiffies, timeout)) {
705 value = tegra_sor_readl(sor, SOR_TEST);
706 if ((value & SOR_TEST_ATTACHED) == 0)
707 break;
708
709 usleep_range(25, 100);
710 }
711
712 if ((value & SOR_TEST_ATTACHED) != 0)
713 return -ETIMEDOUT;
714
715 return 0;
716}
717
718static int tegra_sor_power_down(struct tegra_sor *sor)
719{
720 unsigned long value, timeout;
721 int err;
722
723 value = tegra_sor_readl(sor, SOR_PWR);
724 value &= ~SOR_PWR_NORMAL_STATE_PU;
725 value |= SOR_PWR_TRIGGER;
726 tegra_sor_writel(sor, value, SOR_PWR);
727
728 timeout = jiffies + msecs_to_jiffies(250);
729
730 while (time_before(jiffies, timeout)) {
731 value = tegra_sor_readl(sor, SOR_PWR);
732 if ((value & SOR_PWR_TRIGGER) == 0)
733 return 0;
734
735 usleep_range(25, 100);
736 }
737
738 if ((value & SOR_PWR_TRIGGER) != 0)
739 return -ETIMEDOUT;
740
741 err = clk_set_parent(sor->clk, sor->clk_safe);
742 if (err < 0)
743 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
744
745 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
746 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
747 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
748 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
749
750 /* stop lane sequencer */
751 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
752 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
753 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
754
755 timeout = jiffies + msecs_to_jiffies(250);
756
757 while (time_before(jiffies, timeout)) {
758 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
759 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
760 break;
761
762 usleep_range(25, 100);
763 }
764
765 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
766 return -ETIMEDOUT;
767
768 value = tegra_sor_readl(sor, SOR_PLL_2);
769 value |= SOR_PLL_2_PORT_POWERDOWN;
770 tegra_sor_writel(sor, value, SOR_PLL_2);
771
772 usleep_range(20, 100);
773
774 value = tegra_sor_readl(sor, SOR_PLL_0);
775 value |= SOR_PLL_0_POWER_OFF;
776 value |= SOR_PLL_0_VCOPD;
777 tegra_sor_writel(sor, value, SOR_PLL_0);
778
779 value = tegra_sor_readl(sor, SOR_PLL_2);
780 value |= SOR_PLL_2_SEQ_PLLCAPPD;
781 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
782 tegra_sor_writel(sor, value, SOR_PLL_2);
783
784 usleep_range(20, 100);
785
786 return 0;
787}
788
789static int tegra_output_sor_disable(struct tegra_output *output)
790{
791 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
792 struct tegra_sor *sor = to_sor(output);
793 unsigned long value;
86f5c52d
TR		 794 int err = 0;
795
796 mutex_lock(&sor->lock);
6b6b6042
TR		 797
798 if (!sor->enabled)
86f5c52d 799 goto unlock;
6b6b6042
TR		 800
801 err = tegra_sor_detach(sor);
802 if (err < 0) {
803 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
86f5c52d 804 goto unlock;
6b6b6042
TR		 805 }
806
807 tegra_sor_writel(sor, 0, SOR_STATE_1);
808 tegra_sor_update(sor);
809
810 /*
811 * The following accesses registers of the display controller, so make
812 * sure it's only executed when the output is attached to one.
813 */
814 if (dc) {
815 /*
816 * XXX: We can't do this here because it causes the SOR to go
817 * into an erroneous state and the output will look scrambled
818 * the next time it is enabled. Presumably this is because we
819 * should be doing this only on the next VBLANK. A possible
820 * solution would be to queue a "power-off" event to trigger
821 * this code to be run during the next VBLANK.
822 */
823 /*
824 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
825 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
826 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
827 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
828 */
829
830 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
831 value &= ~DISP_CTRL_MODE_MASK;
832 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
833
834 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
835 value &= ~SOR_ENABLE;
836 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
837
838 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
839 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
840 }
841
842 err = tegra_sor_power_down(sor);
843 if (err < 0) {
844 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
86f5c52d 845 goto unlock;
6b6b6042
TR		 846 }
847
848 if (sor->dpaux) {
849 err = tegra_dpaux_disable(sor->dpaux);
850 if (err < 0) {
851 dev_err(sor->dev, "failed to disable DP: %d\n", err);
86f5c52d 852 goto unlock;
6b6b6042
TR		 853 }
854 }
855
856 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
857 if (err < 0) {
858 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
86f5c52d 859 goto unlock;
6b6b6042
TR		 860 }
861
862 reset_control_assert(sor->rst);
863 clk_disable_unprepare(sor->clk);
864
865 sor->enabled = false;
866
86f5c52d
TR		 867unlock:
868 mutex_unlock(&sor->lock);
869 return err;
6b6b6042
TR		 870}
871
872static int tegra_output_sor_setup_clock(struct tegra_output *output,
91eded9b
TR		 873 struct clk *clk, unsigned long pclk,
874 unsigned int *div)
6b6b6042
TR		 875{
876 struct tegra_sor *sor = to_sor(output);
877 int err;
878
879 /* round to next MHz */
91eded9b 880 pclk = DIV_ROUND_UP(pclk, 1000000) * 1000000;
6b6b6042
TR		 881
882 err = clk_set_parent(clk, sor->clk_parent);
883 if (err < 0) {
884 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
885 return err;
886 }
887
888 err = clk_set_rate(sor->clk_parent, pclk);
889 if (err < 0) {
91eded9b 890 dev_err(sor->dev, "failed to set clock rate to %lu Hz\n", pclk);
6b6b6042
TR		 891 return err;
892 }
893
91eded9b
TR		 894 *div = 0;
895
6b6b6042
TR		 896 return 0;
897}
898
899static int tegra_output_sor_check_mode(struct tegra_output *output,
900 struct drm_display_mode *mode,
901 enum drm_mode_status *status)
902{
903 /*
904 * FIXME: For now, always assume that the mode is okay.
905 */
906
907 *status = MODE_OK;
908
909 return 0;
910}
911
912static enum drm_connector_status
913tegra_output_sor_detect(struct tegra_output *output)
914{
915 struct tegra_sor *sor = to_sor(output);
916
917 if (sor->dpaux)
918 return tegra_dpaux_detect(sor->dpaux);
919
920 return connector_status_unknown;
921}
922
923static const struct tegra_output_ops sor_ops = {
924 .enable = tegra_output_sor_enable,
925 .disable = tegra_output_sor_disable,
926 .setup_clock = tegra_output_sor_setup_clock,
927 .check_mode = tegra_output_sor_check_mode,
928 .detect = tegra_output_sor_detect,
929};
930
a82752e1
TR		 931static int tegra_sor_crc_open(struct inode *inode, struct file *file)
932{
933 file->private_data = inode->i_private;
934
935 return 0;
936}
937
938static int tegra_sor_crc_release(struct inode *inode, struct file *file)
939{
940 return 0;
941}
942
943static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
944{
945 u32 value;
946
947 timeout = jiffies + msecs_to_jiffies(timeout);
948
949 while (time_before(jiffies, timeout)) {
950 value = tegra_sor_readl(sor, SOR_CRC_A);
951 if (value & SOR_CRC_A_VALID)
952 return 0;
953
954 usleep_range(100, 200);
955 }
956
957 return -ETIMEDOUT;
958}
959
960static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer,
961 size_t size, loff_t *ppos)
962{
963 struct tegra_sor *sor = file->private_data;
86f5c52d 964 ssize_t num, err;
a82752e1 965 char buf[10];
a82752e1 966 u32 value;
86f5c52d
TR		 967
968 mutex_lock(&sor->lock);
969
970 if (!sor->enabled) {
971 err = -EAGAIN;
972 goto unlock;
973 }
a82752e1
TR		 974
975 value = tegra_sor_readl(sor, SOR_STATE_1);
976 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
977 tegra_sor_writel(sor, value, SOR_STATE_1);
978
979 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
980 value |= SOR_CRC_CNTRL_ENABLE;
981 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
982
983 value = tegra_sor_readl(sor, SOR_TEST);
984 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
985 tegra_sor_writel(sor, value, SOR_TEST);
986
987 err = tegra_sor_crc_wait(sor, 100);
988 if (err < 0)
86f5c52d 989 goto unlock;
a82752e1
TR		 990
991 tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A);
992 value = tegra_sor_readl(sor, SOR_CRC_B);
993
994 num = scnprintf(buf, sizeof(buf), "%08x\n", value);
995
86f5c52d
TR		 996 err = simple_read_from_buffer(buffer, size, ppos, buf, num);
997
998unlock:
999 mutex_unlock(&sor->lock);
1000 return err;
a82752e1
TR		 1001}
1002
1003static const struct file_operations tegra_sor_crc_fops = {
1004 .owner = THIS_MODULE,
1005 .open = tegra_sor_crc_open,
1006 .read = tegra_sor_crc_read,
1007 .release = tegra_sor_crc_release,
1008};
1009
1010static int tegra_sor_debugfs_init(struct tegra_sor *sor, struct dentry *root)
1011{
1012 struct dentry *entry;
1013 int err = 0;
1014
1015 sor->debugfs = debugfs_create_dir("sor", root);
1016 if (!sor->debugfs)
1017 return -ENOMEM;
1018
1019 entry = debugfs_create_file("crc", 0644, sor->debugfs, sor,
1020 &tegra_sor_crc_fops);
1021 if (!entry) {
1022 dev_err(sor->dev,
1023 "cannot create /sys/kernel/debug/dri/%s/sor/crc\n",
1024 root->d_name.name);
1025 err = -ENOMEM;
1026 goto remove;
1027 }
1028
1029 return err;
1030
1031remove:
1032 debugfs_remove(sor->debugfs);
1033 sor->debugfs = NULL;
1034 return err;
1035}
1036
1037static int tegra_sor_debugfs_exit(struct tegra_sor *sor)
1038{
9578184e 1039 debugfs_remove_recursive(sor->debugfs);
a82752e1
TR		 1040 sor->debugfs = NULL;
1041
1042 return 0;
1043}
1044
6b6b6042
TR		 1045static int tegra_sor_init(struct host1x_client *client)
1046{
9910f5c4 1047 struct drm_device *drm = dev_get_drvdata(client->parent);
6b6b6042
TR		 1048 struct tegra_sor *sor = host1x_client_to_sor(client);
1049 int err;
1050
1051 if (!sor->dpaux)
1052 return -ENODEV;
1053
1054 sor->output.type = TEGRA_OUTPUT_EDP;
1055
1056 sor->output.dev = sor->dev;
1057 sor->output.ops = &sor_ops;
1058
9910f5c4 1059 err = tegra_output_init(drm, &sor->output);
6b6b6042
TR		 1060 if (err < 0) {
1061 dev_err(sor->dev, "output setup failed: %d\n", err);
1062 return err;
1063 }
1064
a82752e1 1065 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1066 struct dentry *root = drm->primary->debugfs_root;
a82752e1
TR		 1067
1068 err = tegra_sor_debugfs_init(sor, root);
1069 if (err < 0)
1070 dev_err(sor->dev, "debugfs setup failed: %d\n", err);
1071 }
1072
6b6b6042
TR		 1073 if (sor->dpaux) {
1074 err = tegra_dpaux_attach(sor->dpaux, &sor->output);
1075 if (err < 0) {
1076 dev_err(sor->dev, "failed to attach DP: %d\n", err);
1077 return err;
1078 }
1079 }
1080
1081 return 0;
1082}
1083
1084static int tegra_sor_exit(struct host1x_client *client)
1085{
1086 struct tegra_sor *sor = host1x_client_to_sor(client);
1087 int err;
1088
1089 err = tegra_output_disable(&sor->output);
1090 if (err < 0) {
1091 dev_err(sor->dev, "output failed to disable: %d\n", err);
1092 return err;
1093 }
1094
1095 if (sor->dpaux) {
1096 err = tegra_dpaux_detach(sor->dpaux);
1097 if (err < 0) {
1098 dev_err(sor->dev, "failed to detach DP: %d\n", err);
1099 return err;
1100 }
1101 }
1102
a82752e1
TR		 1103 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1104 err = tegra_sor_debugfs_exit(sor);
1105 if (err < 0)
1106 dev_err(sor->dev, "debugfs cleanup failed: %d\n", err);
1107 }
1108
6b6b6042
TR		 1109 err = tegra_output_exit(&sor->output);
1110 if (err < 0) {
1111 dev_err(sor->dev, "output cleanup failed: %d\n", err);
1112 return err;
1113 }
1114
1115 return 0;
1116}
1117
1118static const struct host1x_client_ops sor_client_ops = {
1119 .init = tegra_sor_init,
1120 .exit = tegra_sor_exit,
1121};
1122
1123static int tegra_sor_probe(struct platform_device *pdev)
1124{
1125 struct device_node *np;
1126 struct tegra_sor *sor;
1127 struct resource *regs;
1128 int err;
1129
1130 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
1131 if (!sor)
1132 return -ENOMEM;
1133
1134 sor->output.dev = sor->dev = &pdev->dev;
1135
1136 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
1137 if (np) {
1138 sor->dpaux = tegra_dpaux_find_by_of_node(np);
1139 of_node_put(np);
1140
1141 if (!sor->dpaux)
1142 return -EPROBE_DEFER;
1143 }
1144
1145 err = tegra_output_probe(&sor->output);
1146 if (err < 0)
1147 return err;
1148
1149 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
1151 if (IS_ERR(sor->regs))
1152 return PTR_ERR(sor->regs);
1153
1154 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
1155 if (IS_ERR(sor->rst))
1156 return PTR_ERR(sor->rst);
1157
1158 sor->clk = devm_clk_get(&pdev->dev, NULL);
1159 if (IS_ERR(sor->clk))
1160 return PTR_ERR(sor->clk);
1161
1162 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
1163 if (IS_ERR(sor->clk_parent))
1164 return PTR_ERR(sor->clk_parent);
1165
1166 err = clk_prepare_enable(sor->clk_parent);
1167 if (err < 0)
1168 return err;
1169
1170 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
1171 if (IS_ERR(sor->clk_safe))
1172 return PTR_ERR(sor->clk_safe);
1173
1174 err = clk_prepare_enable(sor->clk_safe);
1175 if (err < 0)
1176 return err;
1177
1178 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
1179 if (IS_ERR(sor->clk_dp))
1180 return PTR_ERR(sor->clk_dp);
1181
1182 err = clk_prepare_enable(sor->clk_dp);
1183 if (err < 0)
1184 return err;
1185
1186 INIT_LIST_HEAD(&sor->client.list);
1187 sor->client.ops = &sor_client_ops;
1188 sor->client.dev = &pdev->dev;
1189
86f5c52d
TR		 1190 mutex_init(&sor->lock);
1191
6b6b6042
TR		 1192 err = host1x_client_register(&sor->client);
1193 if (err < 0) {
1194 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1195 err);
1196 return err;
1197 }
1198
1199 platform_set_drvdata(pdev, sor);
1200
1201 return 0;
1202}
1203
1204static int tegra_sor_remove(struct platform_device *pdev)
1205{
1206 struct tegra_sor *sor = platform_get_drvdata(pdev);
1207 int err;
1208
1209 err = host1x_client_unregister(&sor->client);
1210 if (err < 0) {
1211 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1212 err);
1213 return err;
1214 }
1215
1216 clk_disable_unprepare(sor->clk_parent);
1217 clk_disable_unprepare(sor->clk_safe);
1218 clk_disable_unprepare(sor->clk_dp);
1219 clk_disable_unprepare(sor->clk);
1220
1221 return 0;
1222}
1223
1224static const struct of_device_id tegra_sor_of_match[] = {
1225 { .compatible = "nvidia,tegra124-sor", },
1226 { },
1227};
1228
1229struct platform_driver tegra_sor_driver = {
1230 .driver = {
1231 .name = "tegra-sor",
1232 .of_match_table = tegra_sor_of_match,
1233 },
1234 .probe = tegra_sor_probe,
1235 .remove = tegra_sor_remove,
1236};
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